root / hw / arm_gic.c @ d537cf6c
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/*
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* ARM AMBA Generic/Distributed Interrupt Controller
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*
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* Copyright (c) 2006 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licenced under the GPL.
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*/
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/* TODO: Some variants of this controller can handle multiple CPUs.
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Currently only single CPU operation is implemented. */
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#include "vl.h" |
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#include "arm_pic.h" |
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//#define DEBUG_GIC
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#ifdef DEBUG_GIC
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#define DPRINTF(fmt, args...) \
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do { printf("arm_gic: " fmt , ##args); } while (0) |
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#else
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#define DPRINTF(fmt, args...) do {} while(0) |
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#endif
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/* Distributed interrupt controller. */
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|
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static const uint8_t gic_id[] = |
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{ 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
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|
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#define GIC_NIRQ 96 |
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|
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typedef struct gic_irq_state |
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{
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unsigned enabled:1; |
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unsigned pending:1; |
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unsigned active:1; |
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unsigned level:1; |
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unsigned model:1; /* 0 = 1:N, 1 = N:N */ |
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unsigned trigger:1; /* nonzero = edge triggered. */ |
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} gic_irq_state; |
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|
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#define GIC_SET_ENABLED(irq) s->irq_state[irq].enabled = 1 |
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#define GIC_CLEAR_ENABLED(irq) s->irq_state[irq].enabled = 0 |
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#define GIC_TEST_ENABLED(irq) s->irq_state[irq].enabled
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#define GIC_SET_PENDING(irq) s->irq_state[irq].pending = 1 |
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#define GIC_CLEAR_PENDING(irq) s->irq_state[irq].pending = 0 |
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#define GIC_TEST_PENDING(irq) s->irq_state[irq].pending
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#define GIC_SET_ACTIVE(irq) s->irq_state[irq].active = 1 |
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#define GIC_CLEAR_ACTIVE(irq) s->irq_state[irq].active = 0 |
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#define GIC_TEST_ACTIVE(irq) s->irq_state[irq].active
|
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#define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1 |
| 52 |
#define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0 |
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#define GIC_TEST_MODEL(irq) s->irq_state[irq].model
|
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#define GIC_SET_LEVEL(irq) s->irq_state[irq].level = 1 |
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#define GIC_CLEAR_LEVEL(irq) s->irq_state[irq].level = 0 |
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#define GIC_TEST_LEVEL(irq) s->irq_state[irq].level
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#define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1 |
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#define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0 |
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#define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
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|
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typedef struct gic_state |
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{
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uint32_t base; |
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qemu_irq parent_irq; |
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int enabled;
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int cpu_enabled;
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|
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gic_irq_state irq_state[GIC_NIRQ]; |
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int irq_target[GIC_NIRQ];
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int priority[GIC_NIRQ];
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int last_active[GIC_NIRQ];
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|
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int priority_mask;
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int running_irq;
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int running_priority;
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int current_pending;
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} gic_state; |
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|
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/* TODO: Many places that call this routine could be optimized. */
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/* Update interrupt status after enabled or pending bits have been changed. */
|
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static void gic_update(gic_state *s) |
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{
|
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int best_irq;
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int best_prio;
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int irq;
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|
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s->current_pending = 1023;
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if (!s->enabled || !s->cpu_enabled) {
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qemu_irq_lower(s->parent_irq); |
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return;
|
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} |
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best_prio = 0x100;
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best_irq = 1023;
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for (irq = 0; irq < 96; irq++) { |
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if (GIC_TEST_ENABLED(irq) && GIC_TEST_PENDING(irq)) {
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if (s->priority[irq] < best_prio) {
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best_prio = s->priority[irq]; |
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best_irq = irq; |
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} |
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} |
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} |
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if (best_prio > s->priority_mask) {
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qemu_irq_lower(s->parent_irq); |
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} else {
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s->current_pending = best_irq; |
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if (best_prio < s->running_priority) {
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DPRINTF("Raised pending IRQ %d\n", best_irq);
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qemu_irq_raise(s->parent_irq); |
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} |
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} |
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} |
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|
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static void gic_set_irq(void *opaque, int irq, int level) |
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{
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gic_state *s = (gic_state *)opaque; |
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/* The first external input line is internal interrupt 32. */
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irq += 32;
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if (level == GIC_TEST_LEVEL(irq))
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return;
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|
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if (level) {
|
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GIC_SET_LEVEL(irq); |
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if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq)) {
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DPRINTF("Set %d pending\n", irq);
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GIC_SET_PENDING(irq); |
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} |
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} else {
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GIC_CLEAR_LEVEL(irq); |
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} |
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gic_update(s); |
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} |
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|
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static void gic_set_running_irq(gic_state *s, int irq) |
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{
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s->running_irq = irq; |
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if (irq == 1023) |
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s->running_priority = 0x100;
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else
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s->running_priority = s->priority[irq]; |
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gic_update(s); |
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} |
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|
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static uint32_t gic_acknowledge_irq(gic_state *s)
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{
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int new_irq;
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new_irq = s->current_pending; |
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if (new_irq == 1023 || s->priority[new_irq] >= s->running_priority) { |
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DPRINTF("ACK no pending IRQ\n");
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return 1023; |
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} |
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qemu_irq_lower(s->parent_irq); |
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s->last_active[new_irq] = s->running_irq; |
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/* For level triggered interrupts we clear the pending bit while
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the interrupt is active. */
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GIC_CLEAR_PENDING(new_irq); |
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gic_set_running_irq(s, new_irq); |
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DPRINTF("ACK %d\n", new_irq);
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return new_irq;
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} |
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|
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static void gic_complete_irq(gic_state * s, int irq) |
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{
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int update = 0; |
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DPRINTF("EOI %d\n", irq);
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if (s->running_irq == 1023) |
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return; /* No active IRQ. */ |
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if (irq != 1023) { |
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/* Mark level triggered interrupts as pending if they are still
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raised. */
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if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq)
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&& GIC_TEST_LEVEL(irq)) {
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GIC_SET_PENDING(irq); |
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update = 1;
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} |
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} |
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if (irq != s->running_irq) {
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/* Complete an IRQ that is not currently running. */
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int tmp = s->running_irq;
|
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while (s->last_active[tmp] != 1023) { |
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if (s->last_active[tmp] == irq) {
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s->last_active[tmp] = s->last_active[irq]; |
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break;
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} |
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tmp = s->last_active[tmp]; |
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} |
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if (update) {
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gic_update(s); |
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} |
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} else {
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/* Complete the current running IRQ. */
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gic_set_running_irq(s, s->last_active[s->running_irq]); |
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} |
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} |
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|
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static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) |
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{
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gic_state *s = (gic_state *)opaque; |
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uint32_t res; |
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int irq;
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int i;
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|
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offset -= s->base + 0x1000;
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if (offset < 0x100) { |
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if (offset == 0) |
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return s->enabled;
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if (offset == 4) |
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return (GIC_NIRQ / 32) - 1; |
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if (offset < 0x08) |
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return 0; |
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goto bad_reg;
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} else if (offset < 0x200) { |
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/* Interrupt Set/Clear Enable. */
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if (offset < 0x180) |
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irq = (offset - 0x100) * 8; |
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else
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irq = (offset - 0x180) * 8; |
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if (irq >= GIC_NIRQ)
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goto bad_reg;
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res = 0;
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for (i = 0; i < 8; i++) { |
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if (GIC_TEST_ENABLED(irq + i)) {
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res |= (1 << i);
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} |
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} |
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} else if (offset < 0x300) { |
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/* Interrupt Set/Clear Pending. */
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if (offset < 0x280) |
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irq = (offset - 0x200) * 8; |
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else
|
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irq = (offset - 0x280) * 8; |
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if (irq >= GIC_NIRQ)
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goto bad_reg;
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res = 0;
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for (i = 0; i < 8; i++) { |
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if (GIC_TEST_PENDING(irq + i)) {
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res |= (1 << i);
|
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} |
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} |
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} else if (offset < 0x400) { |
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/* Interrupt Active. */
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irq = (offset - 0x300) * 8; |
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if (irq >= GIC_NIRQ)
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goto bad_reg;
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res = 0;
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for (i = 0; i < 8; i++) { |
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if (GIC_TEST_ACTIVE(irq + i)) {
|
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res |= (1 << i);
|
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} |
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} |
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} else if (offset < 0x800) { |
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/* Interrupt Priority. */
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irq = offset - 0x400;
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if (irq >= GIC_NIRQ)
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goto bad_reg;
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res = s->priority[irq]; |
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} else if (offset < 0xc00) { |
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/* Interrupt CPU Target. */
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irq = offset - 0x800;
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if (irq >= GIC_NIRQ)
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goto bad_reg;
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res = s->irq_target[irq]; |
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} else if (offset < 0xf00) { |
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/* Interrupt Configuration. */
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irq = (offset - 0xc00) * 2; |
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if (irq >= GIC_NIRQ)
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goto bad_reg;
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res = 0;
|
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for (i = 0; i < 4; i++) { |
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if (GIC_TEST_MODEL(irq + i))
|
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res |= (1 << (i * 2)); |
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if (GIC_TEST_TRIGGER(irq + i))
|
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res |= (2 << (i * 2)); |
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} |
| 274 |
} else if (offset < 0xfe0) { |
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goto bad_reg;
|
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} else /* offset >= 0xfe0 */ { |
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if (offset & 3) { |
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res = 0;
|
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} else {
|
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res = gic_id[(offset - 0xfe0) >> 2]; |
| 281 |
} |
| 282 |
} |
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return res;
|
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bad_reg:
|
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cpu_abort (cpu_single_env, "gic_dist_readb: Bad offset %x\n", offset);
|
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return 0; |
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} |
| 288 |
|
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static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset) |
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{
|
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uint32_t val; |
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val = gic_dist_readb(opaque, offset); |
| 293 |
val |= gic_dist_readb(opaque, offset + 1) << 8; |
| 294 |
return val;
|
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} |
| 296 |
|
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static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset) |
| 298 |
{
|
| 299 |
uint32_t val; |
| 300 |
val = gic_dist_readw(opaque, offset); |
| 301 |
val |= gic_dist_readw(opaque, offset + 2) << 16; |
| 302 |
return val;
|
| 303 |
} |
| 304 |
|
| 305 |
static void gic_dist_writeb(void *opaque, target_phys_addr_t offset, |
| 306 |
uint32_t value) |
| 307 |
{
|
| 308 |
gic_state *s = (gic_state *)opaque; |
| 309 |
int irq;
|
| 310 |
int i;
|
| 311 |
|
| 312 |
offset -= s->base + 0x1000;
|
| 313 |
if (offset < 0x100) { |
| 314 |
if (offset == 0) { |
| 315 |
s->enabled = (value & 1);
|
| 316 |
DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis"); |
| 317 |
} else if (offset < 4) { |
| 318 |
/* ignored. */
|
| 319 |
} else {
|
| 320 |
goto bad_reg;
|
| 321 |
} |
| 322 |
} else if (offset < 0x180) { |
| 323 |
/* Interrupt Set Enable. */
|
| 324 |
irq = (offset - 0x100) * 8; |
| 325 |
if (irq >= GIC_NIRQ)
|
| 326 |
goto bad_reg;
|
| 327 |
for (i = 0; i < 8; i++) { |
| 328 |
if (value & (1 << i)) { |
| 329 |
if (!GIC_TEST_ENABLED(irq + i))
|
| 330 |
DPRINTF("Enabled IRQ %d\n", irq + i);
|
| 331 |
GIC_SET_ENABLED(irq + i); |
| 332 |
/* If a raised level triggered IRQ enabled then mark
|
| 333 |
is as pending. */
|
| 334 |
if (GIC_TEST_LEVEL(irq + i) && !GIC_TEST_TRIGGER(irq + i))
|
| 335 |
GIC_SET_PENDING(irq + i); |
| 336 |
} |
| 337 |
} |
| 338 |
} else if (offset < 0x200) { |
| 339 |
/* Interrupt Clear Enable. */
|
| 340 |
irq = (offset - 0x180) * 8; |
| 341 |
if (irq >= GIC_NIRQ)
|
| 342 |
goto bad_reg;
|
| 343 |
for (i = 0; i < 8; i++) { |
| 344 |
if (value & (1 << i)) { |
| 345 |
if (GIC_TEST_ENABLED(irq + i))
|
| 346 |
DPRINTF("Disabled IRQ %d\n", irq + i);
|
| 347 |
GIC_CLEAR_ENABLED(irq + i); |
| 348 |
} |
| 349 |
} |
| 350 |
} else if (offset < 0x280) { |
| 351 |
/* Interrupt Set Pending. */
|
| 352 |
irq = (offset - 0x200) * 8; |
| 353 |
if (irq >= GIC_NIRQ)
|
| 354 |
goto bad_reg;
|
| 355 |
for (i = 0; i < 8; i++) { |
| 356 |
if (value & (1 << i)) { |
| 357 |
GIC_SET_PENDING(irq + i); |
| 358 |
} |
| 359 |
} |
| 360 |
} else if (offset < 0x300) { |
| 361 |
/* Interrupt Clear Pending. */
|
| 362 |
irq = (offset - 0x280) * 8; |
| 363 |
if (irq >= GIC_NIRQ)
|
| 364 |
goto bad_reg;
|
| 365 |
for (i = 0; i < 8; i++) { |
| 366 |
if (value & (1 << i)) { |
| 367 |
GIC_CLEAR_PENDING(irq + i); |
| 368 |
} |
| 369 |
} |
| 370 |
} else if (offset < 0x400) { |
| 371 |
/* Interrupt Active. */
|
| 372 |
goto bad_reg;
|
| 373 |
} else if (offset < 0x800) { |
| 374 |
/* Interrupt Priority. */
|
| 375 |
irq = offset - 0x400;
|
| 376 |
if (irq >= GIC_NIRQ)
|
| 377 |
goto bad_reg;
|
| 378 |
s->priority[irq] = value; |
| 379 |
} else if (offset < 0xc00) { |
| 380 |
/* Interrupt CPU Target. */
|
| 381 |
irq = offset - 0x800;
|
| 382 |
if (irq >= GIC_NIRQ)
|
| 383 |
goto bad_reg;
|
| 384 |
s->irq_target[irq] = value; |
| 385 |
} else if (offset < 0xf00) { |
| 386 |
/* Interrupt Configuration. */
|
| 387 |
irq = (offset - 0xc00) * 4; |
| 388 |
if (irq >= GIC_NIRQ)
|
| 389 |
goto bad_reg;
|
| 390 |
for (i = 0; i < 4; i++) { |
| 391 |
if (value & (1 << (i * 2))) { |
| 392 |
GIC_SET_MODEL(irq + i); |
| 393 |
} else {
|
| 394 |
GIC_CLEAR_MODEL(irq + i); |
| 395 |
} |
| 396 |
if (value & (2 << (i * 2))) { |
| 397 |
GIC_SET_TRIGGER(irq + i); |
| 398 |
} else {
|
| 399 |
GIC_CLEAR_TRIGGER(irq + i); |
| 400 |
} |
| 401 |
} |
| 402 |
} else {
|
| 403 |
/* 0xf00 is only handled for word writes. */
|
| 404 |
goto bad_reg;
|
| 405 |
} |
| 406 |
gic_update(s); |
| 407 |
return;
|
| 408 |
bad_reg:
|
| 409 |
cpu_abort (cpu_single_env, "gic_dist_writeb: Bad offset %x\n", offset);
|
| 410 |
} |
| 411 |
|
| 412 |
static void gic_dist_writew(void *opaque, target_phys_addr_t offset, |
| 413 |
uint32_t value) |
| 414 |
{
|
| 415 |
gic_state *s = (gic_state *)opaque; |
| 416 |
if (offset - s->base == 0xf00) { |
| 417 |
GIC_SET_PENDING(value & 0x3ff);
|
| 418 |
gic_update(s); |
| 419 |
return;
|
| 420 |
} |
| 421 |
gic_dist_writeb(opaque, offset, value & 0xff);
|
| 422 |
gic_dist_writeb(opaque, offset + 1, value >> 8); |
| 423 |
} |
| 424 |
|
| 425 |
static void gic_dist_writel(void *opaque, target_phys_addr_t offset, |
| 426 |
uint32_t value) |
| 427 |
{
|
| 428 |
gic_dist_writew(opaque, offset, value & 0xffff);
|
| 429 |
gic_dist_writew(opaque, offset + 2, value >> 16); |
| 430 |
} |
| 431 |
|
| 432 |
static CPUReadMemoryFunc *gic_dist_readfn[] = {
|
| 433 |
gic_dist_readb, |
| 434 |
gic_dist_readw, |
| 435 |
gic_dist_readl |
| 436 |
}; |
| 437 |
|
| 438 |
static CPUWriteMemoryFunc *gic_dist_writefn[] = {
|
| 439 |
gic_dist_writeb, |
| 440 |
gic_dist_writew, |
| 441 |
gic_dist_writel |
| 442 |
}; |
| 443 |
|
| 444 |
static uint32_t gic_cpu_read(void *opaque, target_phys_addr_t offset) |
| 445 |
{
|
| 446 |
gic_state *s = (gic_state *)opaque; |
| 447 |
offset -= s->base; |
| 448 |
switch (offset) {
|
| 449 |
case 0x00: /* Control */ |
| 450 |
return s->cpu_enabled;
|
| 451 |
case 0x04: /* Priority mask */ |
| 452 |
return s->priority_mask;
|
| 453 |
case 0x08: /* Binary Point */ |
| 454 |
/* ??? Not implemented. */
|
| 455 |
return 0; |
| 456 |
case 0x0c: /* Acknowledge */ |
| 457 |
return gic_acknowledge_irq(s);
|
| 458 |
case 0x14: /* Runing Priority */ |
| 459 |
return s->running_priority;
|
| 460 |
case 0x18: /* Highest Pending Interrupt */ |
| 461 |
return s->current_pending;
|
| 462 |
default:
|
| 463 |
cpu_abort (cpu_single_env, "gic_cpu_writeb: Bad offset %x\n", offset);
|
| 464 |
return 0; |
| 465 |
} |
| 466 |
} |
| 467 |
|
| 468 |
static void gic_cpu_write(void *opaque, target_phys_addr_t offset, |
| 469 |
uint32_t value) |
| 470 |
{
|
| 471 |
gic_state *s = (gic_state *)opaque; |
| 472 |
offset -= s->base; |
| 473 |
switch (offset) {
|
| 474 |
case 0x00: /* Control */ |
| 475 |
s->cpu_enabled = (value & 1);
|
| 476 |
DPRINTF("CPU %sabled\n", s->cpu_enabled ? "En" : "Dis"); |
| 477 |
break;
|
| 478 |
case 0x04: /* Priority mask */ |
| 479 |
s->priority_mask = (value & 0x3ff);
|
| 480 |
break;
|
| 481 |
case 0x08: /* Binary Point */ |
| 482 |
/* ??? Not implemented. */
|
| 483 |
break;
|
| 484 |
case 0x10: /* End Of Interrupt */ |
| 485 |
return gic_complete_irq(s, value & 0x3ff); |
| 486 |
default:
|
| 487 |
cpu_abort (cpu_single_env, "gic_cpu_writeb: Bad offset %x\n", offset);
|
| 488 |
return;
|
| 489 |
} |
| 490 |
gic_update(s); |
| 491 |
} |
| 492 |
|
| 493 |
static CPUReadMemoryFunc *gic_cpu_readfn[] = {
|
| 494 |
gic_cpu_read, |
| 495 |
gic_cpu_read, |
| 496 |
gic_cpu_read |
| 497 |
}; |
| 498 |
|
| 499 |
static CPUWriteMemoryFunc *gic_cpu_writefn[] = {
|
| 500 |
gic_cpu_write, |
| 501 |
gic_cpu_write, |
| 502 |
gic_cpu_write |
| 503 |
}; |
| 504 |
|
| 505 |
static void gic_reset(gic_state *s) |
| 506 |
{
|
| 507 |
int i;
|
| 508 |
memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state)); |
| 509 |
s->priority_mask = 0xf0;
|
| 510 |
s->current_pending = 1023;
|
| 511 |
s->running_irq = 1023;
|
| 512 |
s->running_priority = 0x100;
|
| 513 |
for (i = 0; i < 15; i++) { |
| 514 |
GIC_SET_ENABLED(i); |
| 515 |
GIC_SET_TRIGGER(i); |
| 516 |
} |
| 517 |
s->enabled = 0;
|
| 518 |
s->cpu_enabled = 0;
|
| 519 |
} |
| 520 |
|
| 521 |
qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq) |
| 522 |
{
|
| 523 |
gic_state *s; |
| 524 |
qemu_irq *qi; |
| 525 |
int iomemtype;
|
| 526 |
|
| 527 |
s = (gic_state *)qemu_mallocz(sizeof(gic_state));
|
| 528 |
if (!s)
|
| 529 |
return NULL; |
| 530 |
qi = qemu_allocate_irqs(gic_set_irq, s, GIC_NIRQ); |
| 531 |
s->parent_irq = parent_irq; |
| 532 |
if (base != 0xffffffff) { |
| 533 |
iomemtype = cpu_register_io_memory(0, gic_cpu_readfn,
|
| 534 |
gic_cpu_writefn, s); |
| 535 |
cpu_register_physical_memory(base, 0x00000fff, iomemtype);
|
| 536 |
iomemtype = cpu_register_io_memory(0, gic_dist_readfn,
|
| 537 |
gic_dist_writefn, s); |
| 538 |
cpu_register_physical_memory(base + 0x1000, 0x00000fff, iomemtype); |
| 539 |
s->base = base; |
| 540 |
} else {
|
| 541 |
s->base = 0;
|
| 542 |
} |
| 543 |
gic_reset(s); |
| 544 |
return qi;
|
| 545 |
} |