Revision d57c4e01 translate-i386.c
b/translate-i386.c | ||
---|---|---|
394 | 394 |
}, |
395 | 395 |
}; |
396 | 396 |
|
397 |
static GenOpFunc1 *gen_op_shiftd_T0_T1_im_cc[2][2] = { |
|
398 |
[0] = { |
|
399 |
gen_op_shldw_T0_T1_im_cc, |
|
400 |
gen_op_shrdw_T0_T1_im_cc, |
|
401 |
}, |
|
402 |
[1] = { |
|
403 |
gen_op_shldl_T0_T1_im_cc, |
|
404 |
gen_op_shrdl_T0_T1_im_cc, |
|
405 |
}, |
|
406 |
}; |
|
407 |
|
|
408 |
static GenOpFunc *gen_op_shiftd_T0_T1_ECX_cc[2][2] = { |
|
409 |
[0] = { |
|
410 |
gen_op_shldw_T0_T1_ECX_cc, |
|
411 |
gen_op_shrdw_T0_T1_ECX_cc, |
|
412 |
}, |
|
413 |
[1] = { |
|
414 |
gen_op_shldl_T0_T1_ECX_cc, |
|
415 |
gen_op_shrdl_T0_T1_ECX_cc, |
|
416 |
}, |
|
417 |
}; |
|
418 |
|
|
397 | 419 |
static GenOpFunc *gen_op_btx_T0_T1_cc[2][4] = { |
398 | 420 |
[0] = { |
399 | 421 |
gen_op_btw_T0_T1_cc, |
... | ... | |
1689 | 1711 |
shift = 0; |
1690 | 1712 |
goto grp2; |
1691 | 1713 |
|
1714 |
case 0x1a4: /* shld imm */ |
|
1715 |
op = 0; |
|
1716 |
shift = 1; |
|
1717 |
goto do_shiftd; |
|
1718 |
case 0x1a5: /* shld cl */ |
|
1719 |
op = 0; |
|
1720 |
shift = 0; |
|
1721 |
goto do_shiftd; |
|
1722 |
case 0x1ac: /* shrd imm */ |
|
1723 |
op = 1; |
|
1724 |
shift = 1; |
|
1725 |
goto do_shiftd; |
|
1726 |
case 0x1ad: /* shrd cl */ |
|
1727 |
op = 1; |
|
1728 |
shift = 0; |
|
1729 |
do_shiftd: |
|
1730 |
ot = dflag ? OT_LONG : OT_WORD; |
|
1731 |
modrm = ldub(s->pc++); |
|
1732 |
mod = (modrm >> 6) & 3; |
|
1733 |
rm = modrm & 7; |
|
1734 |
reg = (modrm >> 3) & 7; |
|
1735 |
|
|
1736 |
if (mod != 3) { |
|
1737 |
gen_lea_modrm(s, modrm, ®_addr, &offset_addr); |
|
1738 |
gen_op_ld_T0_A0[ot](); |
|
1739 |
} else { |
|
1740 |
gen_op_mov_TN_reg[ot][0][rm](); |
|
1741 |
} |
|
1742 |
gen_op_mov_TN_reg[ot][1][reg](); |
|
1743 |
|
|
1744 |
if (shift) { |
|
1745 |
val = ldub(s->pc++); |
|
1746 |
val &= 0x1f; |
|
1747 |
if (val) { |
|
1748 |
gen_op_shiftd_T0_T1_im_cc[ot - OT_WORD][op](val); |
|
1749 |
if (op == 0 && ot != OT_WORD) |
|
1750 |
s->cc_op = CC_OP_SHLB + ot; |
|
1751 |
else |
|
1752 |
s->cc_op = CC_OP_SARB + ot; |
|
1753 |
} |
|
1754 |
} else { |
|
1755 |
if (s->cc_op != CC_OP_DYNAMIC) |
|
1756 |
gen_op_set_cc_op(s->cc_op); |
|
1757 |
gen_op_shiftd_T0_T1_ECX_cc[ot - OT_WORD][op](); |
|
1758 |
s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ |
|
1759 |
} |
|
1760 |
if (mod != 3) { |
|
1761 |
gen_op_st_T0_A0[ot](); |
|
1762 |
} else { |
|
1763 |
gen_op_mov_reg_T0[ot][rm](); |
|
1764 |
} |
|
1765 |
break; |
|
1766 |
|
|
1692 | 1767 |
/************************/ |
1693 | 1768 |
/* floats */ |
1694 | 1769 |
case 0xd8 ... 0xdf: |
... | ... | |
2002 | 2077 |
break; |
2003 | 2078 |
#endif |
2004 | 2079 |
default: |
2080 |
error("unhandled FP df/4\n"); |
|
2005 | 2081 |
return -1; |
2006 | 2082 |
} |
2007 | 2083 |
break; |
... | ... | |
2291 | 2367 |
return -1; |
2292 | 2368 |
op -= 4; |
2293 | 2369 |
gen_op_btx_T0_T1_cc[ot - OT_WORD][op](); |
2294 |
s->cc_op = CC_OP_SHLB + ot;
|
|
2370 |
s->cc_op = CC_OP_SARB + ot;
|
|
2295 | 2371 |
if (op != 0) { |
2296 | 2372 |
if (mod != 3) |
2297 | 2373 |
gen_op_st_T0_A0[ot](); |
... | ... | |
2329 | 2405 |
gen_op_mov_TN_reg[ot][0][rm](); |
2330 | 2406 |
} |
2331 | 2407 |
gen_op_btx_T0_T1_cc[ot - OT_WORD][op](); |
2332 |
s->cc_op = CC_OP_SHLB + ot;
|
|
2408 |
s->cc_op = CC_OP_SARB + ot;
|
|
2333 | 2409 |
if (op != 0) { |
2334 | 2410 |
if (mod != 3) |
2335 | 2411 |
gen_op_st_T0_A0[ot](); |
... | ... | |
2417 | 2493 |
is_jmp = 0; |
2418 | 2494 |
ret = disas_insn(dc, pc_start, &is_jmp); |
2419 | 2495 |
if (ret == -1) |
2420 |
error("unknown instruction at PC=0x%x", pc_start); |
|
2496 |
error("unknown instruction at PC=0x%x B=%02x %02x", |
|
2497 |
pc_start, pc_start[0], pc_start[1]); |
|
2421 | 2498 |
/* we must store the eflags state if it is not already done */ |
2422 | 2499 |
if (dc->cc_op != CC_OP_DYNAMIC) |
2423 | 2500 |
gen_op_set_cc_op(dc->cc_op); |
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