Revision d61a4ce8
| b/Makefile.objs | ||
|---|---|---|
| 253 | 253 |
sound-obj-$(CONFIG_ADLIB) += fmopl.o adlib.o |
| 254 | 254 |
sound-obj-$(CONFIG_GUS) += gus.o gusemu_hal.o gusemu_mixer.o |
| 255 | 255 |
sound-obj-$(CONFIG_CS4231A) += cs4231a.o |
| 256 |
sound-obj-$(CONFIG_HDA) += intel-hda.o hda-audio.o |
|
| 256 | 257 |
|
| 257 | 258 |
adlib.o fmopl.o: QEMU_CFLAGS += -DBUILD_Y8950=0 |
| 258 | 259 |
hw-obj-$(CONFIG_SOUND) += $(sound-obj-y) |
| b/arch_init.c | ||
|---|---|---|
| 499 | 499 |
}, |
| 500 | 500 |
#endif |
| 501 | 501 |
|
| 502 |
#ifdef CONFIG_HDA |
|
| 503 |
{
|
|
| 504 |
"hda", |
|
| 505 |
"Intel HD Audio", |
|
| 506 |
0, |
|
| 507 |
0, |
|
| 508 |
{ .init_pci = intel_hda_and_codec_init }
|
|
| 509 |
}, |
|
| 510 |
#endif |
|
| 511 |
|
|
| 502 | 512 |
#endif /* HAS_AUDIO_CHOICE */ |
| 503 | 513 |
|
| 504 | 514 |
{ NULL, NULL, 0, 0, { NULL } }
|
| b/configure | ||
|---|---|---|
| 76 | 76 |
cross_prefix="" |
| 77 | 77 |
cc="gcc" |
| 78 | 78 |
audio_drv_list="" |
| 79 |
audio_card_list="ac97 es1370 sb16" |
|
| 80 |
audio_possible_cards="ac97 es1370 sb16 cs4231a adlib gus" |
|
| 79 |
audio_card_list="ac97 es1370 sb16 hda"
|
|
| 80 |
audio_possible_cards="ac97 es1370 sb16 cs4231a adlib gus hda"
|
|
| 81 | 81 |
block_drv_whitelist="" |
| 82 | 82 |
host_cc="gcc" |
| 83 | 83 |
ar="ar" |
| b/hw/audiodev.h | ||
|---|---|---|
| 15 | 15 |
|
| 16 | 16 |
/* cs4231a.c */ |
| 17 | 17 |
int cs4231a_init(qemu_irq *pic); |
| 18 |
|
|
| 19 |
/* intel-hda.c + hda-audio.c */ |
|
| 20 |
int intel_hda_and_codec_init(PCIBus *bus); |
|
| b/hw/hda-audio.c | ||
|---|---|---|
| 1 |
/* |
|
| 2 |
* Copyright (C) 2010 Red Hat, Inc. |
|
| 3 |
* |
|
| 4 |
* written by Gerd Hoffmann <kraxel@redhat.com> |
|
| 5 |
* |
|
| 6 |
* This program is free software; you can redistribute it and/or |
|
| 7 |
* modify it under the terms of the GNU General Public License as |
|
| 8 |
* published by the Free Software Foundation; either version 2 or |
|
| 9 |
* (at your option) version 3 of the License. |
|
| 10 |
* |
|
| 11 |
* This program is distributed in the hope that it will be useful, |
|
| 12 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
| 13 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
| 14 |
* GNU General Public License for more details. |
|
| 15 |
* |
|
| 16 |
* You should have received a copy of the GNU General Public License |
|
| 17 |
* along with this program; if not, see <http://www.gnu.org/licenses/>. |
|
| 18 |
*/ |
|
| 19 |
|
|
| 20 |
#include "hw.h" |
|
| 21 |
#include "pci.h" |
|
| 22 |
#include "intel-hda.h" |
|
| 23 |
#include "intel-hda-defs.h" |
|
| 24 |
#include "audio/audio.h" |
|
| 25 |
|
|
| 26 |
/* -------------------------------------------------------------------------- */ |
|
| 27 |
|
|
| 28 |
typedef struct desc_param {
|
|
| 29 |
uint32_t id; |
|
| 30 |
uint32_t val; |
|
| 31 |
} desc_param; |
|
| 32 |
|
|
| 33 |
typedef struct desc_node {
|
|
| 34 |
uint32_t nid; |
|
| 35 |
const char *name; |
|
| 36 |
const desc_param *params; |
|
| 37 |
uint32_t nparams; |
|
| 38 |
uint32_t config; |
|
| 39 |
uint32_t pinctl; |
|
| 40 |
uint32_t *conn; |
|
| 41 |
uint32_t stindex; |
|
| 42 |
} desc_node; |
|
| 43 |
|
|
| 44 |
typedef struct desc_codec {
|
|
| 45 |
const char *name; |
|
| 46 |
uint32_t iid; |
|
| 47 |
const desc_node *nodes; |
|
| 48 |
uint32_t nnodes; |
|
| 49 |
} desc_codec; |
|
| 50 |
|
|
| 51 |
static const desc_param* hda_codec_find_param(const desc_node *node, uint32_t id) |
|
| 52 |
{
|
|
| 53 |
int i; |
|
| 54 |
|
|
| 55 |
for (i = 0; i < node->nparams; i++) {
|
|
| 56 |
if (node->params[i].id == id) {
|
|
| 57 |
return &node->params[i]; |
|
| 58 |
} |
|
| 59 |
} |
|
| 60 |
return NULL; |
|
| 61 |
} |
|
| 62 |
|
|
| 63 |
static const desc_node* hda_codec_find_node(const desc_codec *codec, uint32_t nid) |
|
| 64 |
{
|
|
| 65 |
int i; |
|
| 66 |
|
|
| 67 |
for (i = 0; i < codec->nnodes; i++) {
|
|
| 68 |
if (codec->nodes[i].nid == nid) {
|
|
| 69 |
return &codec->nodes[i]; |
|
| 70 |
} |
|
| 71 |
} |
|
| 72 |
return NULL; |
|
| 73 |
} |
|
| 74 |
|
|
| 75 |
static void hda_codec_parse_fmt(uint32_t format, struct audsettings *as) |
|
| 76 |
{
|
|
| 77 |
if (format & AC_FMT_TYPE_NON_PCM) {
|
|
| 78 |
return; |
|
| 79 |
} |
|
| 80 |
|
|
| 81 |
as->freq = (format & AC_FMT_BASE_44K) ? 44100 : 48000; |
|
| 82 |
|
|
| 83 |
switch ((format & AC_FMT_MULT_MASK) >> AC_FMT_MULT_SHIFT) {
|
|
| 84 |
case 1: as->freq *= 2; break; |
|
| 85 |
case 2: as->freq *= 3; break; |
|
| 86 |
case 3: as->freq *= 4; break; |
|
| 87 |
} |
|
| 88 |
|
|
| 89 |
switch ((format & AC_FMT_DIV_MASK) >> AC_FMT_DIV_SHIFT) {
|
|
| 90 |
case 1: as->freq /= 2; break; |
|
| 91 |
case 2: as->freq /= 3; break; |
|
| 92 |
case 3: as->freq /= 4; break; |
|
| 93 |
case 4: as->freq /= 5; break; |
|
| 94 |
case 5: as->freq /= 6; break; |
|
| 95 |
case 6: as->freq /= 7; break; |
|
| 96 |
case 7: as->freq /= 8; break; |
|
| 97 |
} |
|
| 98 |
|
|
| 99 |
switch (format & AC_FMT_BITS_MASK) {
|
|
| 100 |
case AC_FMT_BITS_8: as->fmt = AUD_FMT_S8; break; |
|
| 101 |
case AC_FMT_BITS_16: as->fmt = AUD_FMT_S16; break; |
|
| 102 |
case AC_FMT_BITS_32: as->fmt = AUD_FMT_S32; break; |
|
| 103 |
} |
|
| 104 |
|
|
| 105 |
as->nchannels = ((format & AC_FMT_CHAN_MASK) >> AC_FMT_CHAN_SHIFT) + 1; |
|
| 106 |
} |
|
| 107 |
|
|
| 108 |
/* -------------------------------------------------------------------------- */ |
|
| 109 |
/* |
|
| 110 |
* HDA codec descriptions |
|
| 111 |
*/ |
|
| 112 |
|
|
| 113 |
/* some defines */ |
|
| 114 |
|
|
| 115 |
#define QEMU_HDA_ID_VENDOR 0x1af4 |
|
| 116 |
#define QEMU_HDA_ID_OUTPUT ((QEMU_HDA_ID_VENDOR << 16) | 0x10) |
|
| 117 |
#define QEMU_HDA_ID_DUPLEX ((QEMU_HDA_ID_VENDOR << 16) | 0x20) |
|
| 118 |
|
|
| 119 |
#define QEMU_HDA_PCM_FORMATS (AC_SUPPCM_BITS_16 | \ |
|
| 120 |
0x1fc /* 16 -> 96 kHz */) |
|
| 121 |
#define QEMU_HDA_AMP_NONE (0) |
|
| 122 |
#define QEMU_HDA_AMP_STEPS 0x4a |
|
| 123 |
|
|
| 124 |
#ifdef CONFIG_MIXEMU |
|
| 125 |
#define QEMU_HDA_AMP_CAPS \ |
|
| 126 |
(AC_AMPCAP_MUTE | \ |
|
| 127 |
(QEMU_HDA_AMP_STEPS << AC_AMPCAP_OFFSET_SHIFT) | \ |
|
| 128 |
(QEMU_HDA_AMP_STEPS << AC_AMPCAP_NUM_STEPS_SHIFT) | \ |
|
| 129 |
(3 << AC_AMPCAP_STEP_SIZE_SHIFT)) |
|
| 130 |
#else |
|
| 131 |
#define QEMU_HDA_AMP_CAPS QEMU_HDA_AMP_NONE |
|
| 132 |
#endif |
|
| 133 |
|
|
| 134 |
/* common: audio output widget */ |
|
| 135 |
static const desc_param common_params_audio_dac[] = {
|
|
| 136 |
{
|
|
| 137 |
.id = AC_PAR_AUDIO_WIDGET_CAP, |
|
| 138 |
.val = ((AC_WID_AUD_OUT << AC_WCAP_TYPE_SHIFT) | |
|
| 139 |
AC_WCAP_FORMAT_OVRD | |
|
| 140 |
AC_WCAP_AMP_OVRD | |
|
| 141 |
AC_WCAP_OUT_AMP | |
|
| 142 |
AC_WCAP_STEREO), |
|
| 143 |
},{
|
|
| 144 |
.id = AC_PAR_PCM, |
|
| 145 |
.val = QEMU_HDA_PCM_FORMATS, |
|
| 146 |
},{
|
|
| 147 |
.id = AC_PAR_STREAM, |
|
| 148 |
.val = AC_SUPFMT_PCM, |
|
| 149 |
},{
|
|
| 150 |
.id = AC_PAR_AMP_IN_CAP, |
|
| 151 |
.val = QEMU_HDA_AMP_NONE, |
|
| 152 |
},{
|
|
| 153 |
.id = AC_PAR_AMP_OUT_CAP, |
|
| 154 |
.val = QEMU_HDA_AMP_CAPS, |
|
| 155 |
}, |
|
| 156 |
}; |
|
| 157 |
|
|
| 158 |
/* common: pin widget (line-out) */ |
|
| 159 |
static const desc_param common_params_audio_lineout[] = {
|
|
| 160 |
{
|
|
| 161 |
.id = AC_PAR_AUDIO_WIDGET_CAP, |
|
| 162 |
.val = ((AC_WID_PIN << AC_WCAP_TYPE_SHIFT) | |
|
| 163 |
AC_WCAP_CONN_LIST | |
|
| 164 |
AC_WCAP_STEREO), |
|
| 165 |
},{
|
|
| 166 |
.id = AC_PAR_PIN_CAP, |
|
| 167 |
.val = AC_PINCAP_OUT, |
|
| 168 |
},{
|
|
| 169 |
.id = AC_PAR_CONNLIST_LEN, |
|
| 170 |
.val = 1, |
|
| 171 |
},{
|
|
| 172 |
.id = AC_PAR_AMP_IN_CAP, |
|
| 173 |
.val = QEMU_HDA_AMP_NONE, |
|
| 174 |
},{
|
|
| 175 |
.id = AC_PAR_AMP_OUT_CAP, |
|
| 176 |
.val = QEMU_HDA_AMP_NONE, |
|
| 177 |
}, |
|
| 178 |
}; |
|
| 179 |
|
|
| 180 |
/* output: root node */ |
|
| 181 |
static const desc_param output_params_root[] = {
|
|
| 182 |
{
|
|
| 183 |
.id = AC_PAR_VENDOR_ID, |
|
| 184 |
.val = QEMU_HDA_ID_OUTPUT, |
|
| 185 |
},{
|
|
| 186 |
.id = AC_PAR_SUBSYSTEM_ID, |
|
| 187 |
.val = QEMU_HDA_ID_OUTPUT, |
|
| 188 |
},{
|
|
| 189 |
.id = AC_PAR_REV_ID, |
|
| 190 |
.val = 0x00100101, |
|
| 191 |
},{
|
|
| 192 |
.id = AC_PAR_NODE_COUNT, |
|
| 193 |
.val = 0x00010001, |
|
| 194 |
}, |
|
| 195 |
}; |
|
| 196 |
|
|
| 197 |
/* output: audio function */ |
|
| 198 |
static const desc_param output_params_audio_func[] = {
|
|
| 199 |
{
|
|
| 200 |
.id = AC_PAR_FUNCTION_TYPE, |
|
| 201 |
.val = AC_GRP_AUDIO_FUNCTION, |
|
| 202 |
},{
|
|
| 203 |
.id = AC_PAR_SUBSYSTEM_ID, |
|
| 204 |
.val = QEMU_HDA_ID_OUTPUT, |
|
| 205 |
},{
|
|
| 206 |
.id = AC_PAR_NODE_COUNT, |
|
| 207 |
.val = 0x00020002, |
|
| 208 |
},{
|
|
| 209 |
.id = AC_PAR_PCM, |
|
| 210 |
.val = QEMU_HDA_PCM_FORMATS, |
|
| 211 |
},{
|
|
| 212 |
.id = AC_PAR_STREAM, |
|
| 213 |
.val = AC_SUPFMT_PCM, |
|
| 214 |
},{
|
|
| 215 |
.id = AC_PAR_AMP_IN_CAP, |
|
| 216 |
.val = QEMU_HDA_AMP_NONE, |
|
| 217 |
},{
|
|
| 218 |
.id = AC_PAR_AMP_OUT_CAP, |
|
| 219 |
.val = QEMU_HDA_AMP_NONE, |
|
| 220 |
},{
|
|
| 221 |
.id = AC_PAR_GPIO_CAP, |
|
| 222 |
.val = 0, |
|
| 223 |
},{
|
|
| 224 |
.id = AC_PAR_AUDIO_FG_CAP, |
|
| 225 |
.val = 0x00000808, |
|
| 226 |
},{
|
|
| 227 |
.id = AC_PAR_POWER_STATE, |
|
| 228 |
.val = 0, |
|
| 229 |
}, |
|
| 230 |
}; |
|
| 231 |
|
|
| 232 |
/* output: nodes */ |
|
| 233 |
static const desc_node output_nodes[] = {
|
|
| 234 |
{
|
|
| 235 |
.nid = AC_NODE_ROOT, |
|
| 236 |
.name = "root", |
|
| 237 |
.params = output_params_root, |
|
| 238 |
.nparams = ARRAY_SIZE(output_params_root), |
|
| 239 |
},{
|
|
| 240 |
.nid = 1, |
|
| 241 |
.name = "func", |
|
| 242 |
.params = output_params_audio_func, |
|
| 243 |
.nparams = ARRAY_SIZE(output_params_audio_func), |
|
| 244 |
},{
|
|
| 245 |
.nid = 2, |
|
| 246 |
.name = "dac", |
|
| 247 |
.params = common_params_audio_dac, |
|
| 248 |
.nparams = ARRAY_SIZE(common_params_audio_dac), |
|
| 249 |
.stindex = 0, |
|
| 250 |
},{
|
|
| 251 |
.nid = 3, |
|
| 252 |
.name = "out", |
|
| 253 |
.params = common_params_audio_lineout, |
|
| 254 |
.nparams = ARRAY_SIZE(common_params_audio_lineout), |
|
| 255 |
.config = ((AC_JACK_PORT_COMPLEX << AC_DEFCFG_PORT_CONN_SHIFT) | |
|
| 256 |
(AC_JACK_LINE_OUT << AC_DEFCFG_DEVICE_SHIFT) | |
|
| 257 |
(AC_JACK_CONN_UNKNOWN << AC_DEFCFG_CONN_TYPE_SHIFT) | |
|
| 258 |
(AC_JACK_COLOR_GREEN << AC_DEFCFG_COLOR_SHIFT) | |
|
| 259 |
0x10), |
|
| 260 |
.pinctl = AC_PINCTL_OUT_EN, |
|
| 261 |
.conn = (uint32_t[]) { 2 },
|
|
| 262 |
} |
|
| 263 |
}; |
|
| 264 |
|
|
| 265 |
/* output: codec */ |
|
| 266 |
static const desc_codec output = {
|
|
| 267 |
.name = "output", |
|
| 268 |
.iid = QEMU_HDA_ID_OUTPUT, |
|
| 269 |
.nodes = output_nodes, |
|
| 270 |
.nnodes = ARRAY_SIZE(output_nodes), |
|
| 271 |
}; |
|
| 272 |
|
|
| 273 |
/* duplex: root node */ |
|
| 274 |
static const desc_param duplex_params_root[] = {
|
|
| 275 |
{
|
|
| 276 |
.id = AC_PAR_VENDOR_ID, |
|
| 277 |
.val = QEMU_HDA_ID_DUPLEX, |
|
| 278 |
},{
|
|
| 279 |
.id = AC_PAR_SUBSYSTEM_ID, |
|
| 280 |
.val = QEMU_HDA_ID_DUPLEX, |
|
| 281 |
},{
|
|
| 282 |
.id = AC_PAR_REV_ID, |
|
| 283 |
.val = 0x00100101, |
|
| 284 |
},{
|
|
| 285 |
.id = AC_PAR_NODE_COUNT, |
|
| 286 |
.val = 0x00010001, |
|
| 287 |
}, |
|
| 288 |
}; |
|
| 289 |
|
|
| 290 |
/* duplex: audio input widget */ |
|
| 291 |
static const desc_param duplex_params_audio_adc[] = {
|
|
| 292 |
{
|
|
| 293 |
.id = AC_PAR_AUDIO_WIDGET_CAP, |
|
| 294 |
.val = ((AC_WID_AUD_IN << AC_WCAP_TYPE_SHIFT) | |
|
| 295 |
AC_WCAP_CONN_LIST | |
|
| 296 |
AC_WCAP_FORMAT_OVRD | |
|
| 297 |
AC_WCAP_AMP_OVRD | |
|
| 298 |
AC_WCAP_IN_AMP | |
|
| 299 |
AC_WCAP_STEREO), |
|
| 300 |
},{
|
|
| 301 |
.id = AC_PAR_CONNLIST_LEN, |
|
| 302 |
.val = 1, |
|
| 303 |
},{
|
|
| 304 |
.id = AC_PAR_PCM, |
|
| 305 |
.val = QEMU_HDA_PCM_FORMATS, |
|
| 306 |
},{
|
|
| 307 |
.id = AC_PAR_STREAM, |
|
| 308 |
.val = AC_SUPFMT_PCM, |
|
| 309 |
},{
|
|
| 310 |
.id = AC_PAR_AMP_IN_CAP, |
|
| 311 |
.val = QEMU_HDA_AMP_CAPS, |
|
| 312 |
},{
|
|
| 313 |
.id = AC_PAR_AMP_OUT_CAP, |
|
| 314 |
.val = QEMU_HDA_AMP_NONE, |
|
| 315 |
}, |
|
| 316 |
}; |
|
| 317 |
|
|
| 318 |
/* duplex: pin widget (line-in) */ |
|
| 319 |
static const desc_param duplex_params_audio_linein[] = {
|
|
| 320 |
{
|
|
| 321 |
.id = AC_PAR_AUDIO_WIDGET_CAP, |
|
| 322 |
.val = ((AC_WID_PIN << AC_WCAP_TYPE_SHIFT) | |
|
| 323 |
AC_WCAP_STEREO), |
|
| 324 |
},{
|
|
| 325 |
.id = AC_PAR_PIN_CAP, |
|
| 326 |
.val = AC_PINCAP_IN, |
|
| 327 |
},{
|
|
| 328 |
.id = AC_PAR_AMP_IN_CAP, |
|
| 329 |
.val = QEMU_HDA_AMP_NONE, |
|
| 330 |
},{
|
|
| 331 |
.id = AC_PAR_AMP_OUT_CAP, |
|
| 332 |
.val = QEMU_HDA_AMP_NONE, |
|
| 333 |
}, |
|
| 334 |
}; |
|
| 335 |
|
|
| 336 |
/* duplex: audio function */ |
|
| 337 |
static const desc_param duplex_params_audio_func[] = {
|
|
| 338 |
{
|
|
| 339 |
.id = AC_PAR_FUNCTION_TYPE, |
|
| 340 |
.val = AC_GRP_AUDIO_FUNCTION, |
|
| 341 |
},{
|
|
| 342 |
.id = AC_PAR_SUBSYSTEM_ID, |
|
| 343 |
.val = QEMU_HDA_ID_DUPLEX, |
|
| 344 |
},{
|
|
| 345 |
.id = AC_PAR_NODE_COUNT, |
|
| 346 |
.val = 0x00020004, |
|
| 347 |
},{
|
|
| 348 |
.id = AC_PAR_PCM, |
|
| 349 |
.val = QEMU_HDA_PCM_FORMATS, |
|
| 350 |
},{
|
|
| 351 |
.id = AC_PAR_STREAM, |
|
| 352 |
.val = AC_SUPFMT_PCM, |
|
| 353 |
},{
|
|
| 354 |
.id = AC_PAR_AMP_IN_CAP, |
|
| 355 |
.val = QEMU_HDA_AMP_NONE, |
|
| 356 |
},{
|
|
| 357 |
.id = AC_PAR_AMP_OUT_CAP, |
|
| 358 |
.val = QEMU_HDA_AMP_NONE, |
|
| 359 |
},{
|
|
| 360 |
.id = AC_PAR_GPIO_CAP, |
|
| 361 |
.val = 0, |
|
| 362 |
},{
|
|
| 363 |
.id = AC_PAR_AUDIO_FG_CAP, |
|
| 364 |
.val = 0x00000808, |
|
| 365 |
},{
|
|
| 366 |
.id = AC_PAR_POWER_STATE, |
|
| 367 |
.val = 0, |
|
| 368 |
}, |
|
| 369 |
}; |
|
| 370 |
|
|
| 371 |
/* duplex: nodes */ |
|
| 372 |
static const desc_node duplex_nodes[] = {
|
|
| 373 |
{
|
|
| 374 |
.nid = AC_NODE_ROOT, |
|
| 375 |
.name = "root", |
|
| 376 |
.params = duplex_params_root, |
|
| 377 |
.nparams = ARRAY_SIZE(duplex_params_root), |
|
| 378 |
},{
|
|
| 379 |
.nid = 1, |
|
| 380 |
.name = "func", |
|
| 381 |
.params = duplex_params_audio_func, |
|
| 382 |
.nparams = ARRAY_SIZE(duplex_params_audio_func), |
|
| 383 |
},{
|
|
| 384 |
.nid = 2, |
|
| 385 |
.name = "dac", |
|
| 386 |
.params = common_params_audio_dac, |
|
| 387 |
.nparams = ARRAY_SIZE(common_params_audio_dac), |
|
| 388 |
.stindex = 0, |
|
| 389 |
},{
|
|
| 390 |
.nid = 3, |
|
| 391 |
.name = "out", |
|
| 392 |
.params = common_params_audio_lineout, |
|
| 393 |
.nparams = ARRAY_SIZE(common_params_audio_lineout), |
|
| 394 |
.config = ((AC_JACK_PORT_COMPLEX << AC_DEFCFG_PORT_CONN_SHIFT) | |
|
| 395 |
(AC_JACK_LINE_OUT << AC_DEFCFG_DEVICE_SHIFT) | |
|
| 396 |
(AC_JACK_CONN_UNKNOWN << AC_DEFCFG_CONN_TYPE_SHIFT) | |
|
| 397 |
(AC_JACK_COLOR_GREEN << AC_DEFCFG_COLOR_SHIFT) | |
|
| 398 |
0x10), |
|
| 399 |
.pinctl = AC_PINCTL_OUT_EN, |
|
| 400 |
.conn = (uint32_t[]) { 2 },
|
|
| 401 |
},{
|
|
| 402 |
.nid = 4, |
|
| 403 |
.name = "adc", |
|
| 404 |
.params = duplex_params_audio_adc, |
|
| 405 |
.nparams = ARRAY_SIZE(duplex_params_audio_adc), |
|
| 406 |
.stindex = 1, |
|
| 407 |
.conn = (uint32_t[]) { 5 },
|
|
| 408 |
},{
|
|
| 409 |
.nid = 5, |
|
| 410 |
.name = "in", |
|
| 411 |
.params = duplex_params_audio_linein, |
|
| 412 |
.nparams = ARRAY_SIZE(duplex_params_audio_linein), |
|
| 413 |
.config = ((AC_JACK_PORT_COMPLEX << AC_DEFCFG_PORT_CONN_SHIFT) | |
|
| 414 |
(AC_JACK_LINE_IN << AC_DEFCFG_DEVICE_SHIFT) | |
|
| 415 |
(AC_JACK_CONN_UNKNOWN << AC_DEFCFG_CONN_TYPE_SHIFT) | |
|
| 416 |
(AC_JACK_COLOR_RED << AC_DEFCFG_COLOR_SHIFT) | |
|
| 417 |
0x20), |
|
| 418 |
.pinctl = AC_PINCTL_IN_EN, |
|
| 419 |
} |
|
| 420 |
}; |
|
| 421 |
|
|
| 422 |
/* duplex: codec */ |
|
| 423 |
static const desc_codec duplex = {
|
|
| 424 |
.name = "duplex", |
|
| 425 |
.iid = QEMU_HDA_ID_DUPLEX, |
|
| 426 |
.nodes = duplex_nodes, |
|
| 427 |
.nnodes = ARRAY_SIZE(duplex_nodes), |
|
| 428 |
}; |
|
| 429 |
|
|
| 430 |
/* -------------------------------------------------------------------------- */ |
|
| 431 |
|
|
| 432 |
static const char *fmt2name[] = {
|
|
| 433 |
[ AUD_FMT_U8 ] = "PCM-U8", |
|
| 434 |
[ AUD_FMT_S8 ] = "PCM-S8", |
|
| 435 |
[ AUD_FMT_U16 ] = "PCM-U16", |
|
| 436 |
[ AUD_FMT_S16 ] = "PCM-S16", |
|
| 437 |
[ AUD_FMT_U32 ] = "PCM-U32", |
|
| 438 |
[ AUD_FMT_S32 ] = "PCM-S32", |
|
| 439 |
}; |
|
| 440 |
|
|
| 441 |
typedef struct HDAAudioState HDAAudioState; |
|
| 442 |
typedef struct HDAAudioStream HDAAudioStream; |
|
| 443 |
|
|
| 444 |
struct HDAAudioStream {
|
|
| 445 |
HDAAudioState *state; |
|
| 446 |
const desc_node *node; |
|
| 447 |
bool output, running; |
|
| 448 |
uint32_t stream; |
|
| 449 |
uint32_t channel; |
|
| 450 |
uint32_t format; |
|
| 451 |
uint32_t gain_left, gain_right; |
|
| 452 |
bool mute_left, mute_right; |
|
| 453 |
struct audsettings as; |
|
| 454 |
union {
|
|
| 455 |
SWVoiceIn *in; |
|
| 456 |
SWVoiceOut *out; |
|
| 457 |
} voice; |
|
| 458 |
uint8_t buf[HDA_BUFFER_SIZE]; |
|
| 459 |
uint32_t bpos; |
|
| 460 |
}; |
|
| 461 |
|
|
| 462 |
struct HDAAudioState {
|
|
| 463 |
HDACodecDevice hda; |
|
| 464 |
const char *name; |
|
| 465 |
|
|
| 466 |
QEMUSoundCard card; |
|
| 467 |
const desc_codec *desc; |
|
| 468 |
HDAAudioStream st[4]; |
|
| 469 |
bool running[16]; |
|
| 470 |
|
|
| 471 |
/* properties */ |
|
| 472 |
uint32_t debug; |
|
| 473 |
}; |
|
| 474 |
|
|
| 475 |
static void hda_audio_input_cb(void *opaque, int avail) |
|
| 476 |
{
|
|
| 477 |
HDAAudioStream *st = opaque; |
|
| 478 |
int recv = 0; |
|
| 479 |
int len; |
|
| 480 |
bool rc; |
|
| 481 |
|
|
| 482 |
while (avail - recv >= sizeof(st->buf)) {
|
|
| 483 |
if (st->bpos != sizeof(st->buf)) {
|
|
| 484 |
len = AUD_read(st->voice.in, st->buf + st->bpos, |
|
| 485 |
sizeof(st->buf) - st->bpos); |
|
| 486 |
st->bpos += len; |
|
| 487 |
recv += len; |
|
| 488 |
if (st->bpos != sizeof(st->buf)) {
|
|
| 489 |
break; |
|
| 490 |
} |
|
| 491 |
} |
|
| 492 |
rc = hda_codec_xfer(&st->state->hda, st->stream, false, |
|
| 493 |
st->buf, sizeof(st->buf)); |
|
| 494 |
if (!rc) {
|
|
| 495 |
break; |
|
| 496 |
} |
|
| 497 |
st->bpos = 0; |
|
| 498 |
} |
|
| 499 |
} |
|
| 500 |
|
|
| 501 |
static void hda_audio_output_cb(void *opaque, int avail) |
|
| 502 |
{
|
|
| 503 |
HDAAudioStream *st = opaque; |
|
| 504 |
int sent = 0; |
|
| 505 |
int len; |
|
| 506 |
bool rc; |
|
| 507 |
|
|
| 508 |
while (avail - sent >= sizeof(st->buf)) {
|
|
| 509 |
if (st->bpos == sizeof(st->buf)) {
|
|
| 510 |
rc = hda_codec_xfer(&st->state->hda, st->stream, true, |
|
| 511 |
st->buf, sizeof(st->buf)); |
|
| 512 |
if (!rc) {
|
|
| 513 |
break; |
|
| 514 |
} |
|
| 515 |
st->bpos = 0; |
|
| 516 |
} |
|
| 517 |
len = AUD_write(st->voice.out, st->buf + st->bpos, |
|
| 518 |
sizeof(st->buf) - st->bpos); |
|
| 519 |
st->bpos += len; |
|
| 520 |
sent += len; |
|
| 521 |
if (st->bpos != sizeof(st->buf)) {
|
|
| 522 |
break; |
|
| 523 |
} |
|
| 524 |
} |
|
| 525 |
} |
|
| 526 |
|
|
| 527 |
static void hda_audio_set_running(HDAAudioStream *st, bool running) |
|
| 528 |
{
|
|
| 529 |
if (st->node == NULL) {
|
|
| 530 |
return; |
|
| 531 |
} |
|
| 532 |
if (st->running == running) {
|
|
| 533 |
return; |
|
| 534 |
} |
|
| 535 |
st->running = running; |
|
| 536 |
dprint(st->state, 1, "%s: %s (stream %d)\n", st->node->name, |
|
| 537 |
st->running ? "on" : "off", st->stream); |
|
| 538 |
if (st->output) {
|
|
| 539 |
AUD_set_active_out(st->voice.out, st->running); |
|
| 540 |
} else {
|
|
| 541 |
AUD_set_active_in(st->voice.in, st->running); |
|
| 542 |
} |
|
| 543 |
} |
|
| 544 |
|
|
| 545 |
static void hda_audio_set_amp(HDAAudioStream *st) |
|
| 546 |
{
|
|
| 547 |
bool muted; |
|
| 548 |
uint32_t left, right; |
|
| 549 |
|
|
| 550 |
if (st->node == NULL) {
|
|
| 551 |
return; |
|
| 552 |
} |
|
| 553 |
|
|
| 554 |
muted = st->mute_left && st->mute_right; |
|
| 555 |
left = st->mute_left ? 0 : st->gain_left; |
|
| 556 |
right = st->mute_right ? 0 : st->gain_right; |
|
| 557 |
|
|
| 558 |
left = left * 255 / QEMU_HDA_AMP_STEPS; |
|
| 559 |
right = right * 255 / QEMU_HDA_AMP_STEPS; |
|
| 560 |
|
|
| 561 |
if (st->output) {
|
|
| 562 |
AUD_set_volume_out(st->voice.out, muted, left, right); |
|
| 563 |
} else {
|
|
| 564 |
AUD_set_volume_in(st->voice.in, muted, left, right); |
|
| 565 |
} |
|
| 566 |
} |
|
| 567 |
|
|
| 568 |
static void hda_audio_setup(HDAAudioStream *st) |
|
| 569 |
{
|
|
| 570 |
if (st->node == NULL) {
|
|
| 571 |
return; |
|
| 572 |
} |
|
| 573 |
|
|
| 574 |
dprint(st->state, 1, "%s: format: %d x %s @ %d Hz\n", |
|
| 575 |
st->node->name, st->as.nchannels, |
|
| 576 |
fmt2name[st->as.fmt], st->as.freq); |
|
| 577 |
|
|
| 578 |
if (st->output) {
|
|
| 579 |
st->voice.out = AUD_open_out(&st->state->card, st->voice.out, |
|
| 580 |
st->node->name, st, |
|
| 581 |
hda_audio_output_cb, &st->as); |
|
| 582 |
} else {
|
|
| 583 |
st->voice.in = AUD_open_in(&st->state->card, st->voice.in, |
|
| 584 |
st->node->name, st, |
|
| 585 |
hda_audio_input_cb, &st->as); |
|
| 586 |
} |
|
| 587 |
} |
|
| 588 |
|
|
| 589 |
static void hda_audio_command(HDACodecDevice *hda, uint32_t nid, uint32_t data) |
|
| 590 |
{
|
|
| 591 |
HDAAudioState *a = DO_UPCAST(HDAAudioState, hda, hda); |
|
| 592 |
HDAAudioStream *st; |
|
| 593 |
const desc_node *node = NULL; |
|
| 594 |
const desc_param *param; |
|
| 595 |
uint32_t verb, payload, response, count, shift; |
|
| 596 |
|
|
| 597 |
if ((data & 0x70000) == 0x70000) {
|
|
| 598 |
/* 12/8 id/payload */ |
|
| 599 |
verb = (data >> 8) & 0xfff; |
|
| 600 |
payload = data & 0x00ff; |
|
| 601 |
} else {
|
|
| 602 |
/* 4/16 id/payload */ |
|
| 603 |
verb = (data >> 8) & 0xf00; |
|
| 604 |
payload = data & 0xffff; |
|
| 605 |
} |
|
| 606 |
|
|
| 607 |
node = hda_codec_find_node(a->desc, nid); |
|
| 608 |
if (node == NULL) {
|
|
| 609 |
goto fail; |
|
| 610 |
} |
|
| 611 |
dprint(a, 2, "%s: nid %d (%s), verb 0x%x, payload 0x%x\n", |
|
| 612 |
__FUNCTION__, nid, node->name, verb, payload); |
|
| 613 |
|
|
| 614 |
switch (verb) {
|
|
| 615 |
/* all nodes */ |
|
| 616 |
case AC_VERB_PARAMETERS: |
|
| 617 |
param = hda_codec_find_param(node, payload); |
|
| 618 |
if (param == NULL) {
|
|
| 619 |
goto fail; |
|
| 620 |
} |
|
| 621 |
hda_codec_response(hda, true, param->val); |
|
| 622 |
break; |
|
| 623 |
case AC_VERB_GET_SUBSYSTEM_ID: |
|
| 624 |
hda_codec_response(hda, true, a->desc->iid); |
|
| 625 |
break; |
|
| 626 |
|
|
| 627 |
/* all functions */ |
|
| 628 |
case AC_VERB_GET_CONNECT_LIST: |
|
| 629 |
param = hda_codec_find_param(node, AC_PAR_CONNLIST_LEN); |
|
| 630 |
count = param ? param->val : 0; |
|
| 631 |
response = 0; |
|
| 632 |
shift = 0; |
|
| 633 |
while (payload < count && shift < 32) {
|
|
| 634 |
response |= node->conn[payload] << shift; |
|
| 635 |
payload++; |
|
| 636 |
shift += 8; |
|
| 637 |
} |
|
| 638 |
hda_codec_response(hda, true, response); |
|
| 639 |
break; |
|
| 640 |
|
|
| 641 |
/* pin widget */ |
|
| 642 |
case AC_VERB_GET_CONFIG_DEFAULT: |
|
| 643 |
hda_codec_response(hda, true, node->config); |
|
| 644 |
break; |
|
| 645 |
case AC_VERB_GET_PIN_WIDGET_CONTROL: |
|
| 646 |
hda_codec_response(hda, true, node->pinctl); |
|
| 647 |
break; |
|
| 648 |
case AC_VERB_SET_PIN_WIDGET_CONTROL: |
|
| 649 |
if (node->pinctl != payload) {
|
|
| 650 |
dprint(a, 1, "unhandled pin control bit\n"); |
|
| 651 |
} |
|
| 652 |
hda_codec_response(hda, true, 0); |
|
| 653 |
break; |
|
| 654 |
|
|
| 655 |
/* audio in/out widget */ |
|
| 656 |
case AC_VERB_SET_CHANNEL_STREAMID: |
|
| 657 |
st = a->st + node->stindex; |
|
| 658 |
if (st->node == NULL) {
|
|
| 659 |
goto fail; |
|
| 660 |
} |
|
| 661 |
hda_audio_set_running(st, false); |
|
| 662 |
st->stream = (payload >> 4) & 0x0f; |
|
| 663 |
st->channel = payload & 0x0f; |
|
| 664 |
dprint(a, 2, "%s: stream %d, channel %d\n", |
|
| 665 |
st->node->name, st->stream, st->channel); |
|
| 666 |
hda_audio_set_running(st, a->running[st->stream]); |
|
| 667 |
hda_codec_response(hda, true, 0); |
|
| 668 |
break; |
|
| 669 |
case AC_VERB_GET_CONV: |
|
| 670 |
st = a->st + node->stindex; |
|
| 671 |
if (st->node == NULL) {
|
|
| 672 |
goto fail; |
|
| 673 |
} |
|
| 674 |
response = st->stream << 4 | st->channel; |
|
| 675 |
hda_codec_response(hda, true, response); |
|
| 676 |
break; |
|
| 677 |
case AC_VERB_SET_STREAM_FORMAT: |
|
| 678 |
st = a->st + node->stindex; |
|
| 679 |
if (st->node == NULL) {
|
|
| 680 |
goto fail; |
|
| 681 |
} |
|
| 682 |
st->format = payload; |
|
| 683 |
hda_codec_parse_fmt(st->format, &st->as); |
|
| 684 |
hda_audio_setup(st); |
|
| 685 |
hda_codec_response(hda, true, 0); |
|
| 686 |
break; |
|
| 687 |
case AC_VERB_GET_STREAM_FORMAT: |
|
| 688 |
st = a->st + node->stindex; |
|
| 689 |
if (st->node == NULL) {
|
|
| 690 |
goto fail; |
|
| 691 |
} |
|
| 692 |
hda_codec_response(hda, true, st->format); |
|
| 693 |
break; |
|
| 694 |
case AC_VERB_GET_AMP_GAIN_MUTE: |
|
| 695 |
st = a->st + node->stindex; |
|
| 696 |
if (st->node == NULL) {
|
|
| 697 |
goto fail; |
|
| 698 |
} |
|
| 699 |
if (payload & AC_AMP_GET_LEFT) {
|
|
| 700 |
response = st->gain_left | (st->mute_left ? AC_AMP_MUTE : 0); |
|
| 701 |
} else {
|
|
| 702 |
response = st->gain_right | (st->mute_right ? AC_AMP_MUTE : 0); |
|
| 703 |
} |
|
| 704 |
hda_codec_response(hda, true, response); |
|
| 705 |
break; |
|
| 706 |
case AC_VERB_SET_AMP_GAIN_MUTE: |
|
| 707 |
st = a->st + node->stindex; |
|
| 708 |
if (st->node == NULL) {
|
|
| 709 |
goto fail; |
|
| 710 |
} |
|
| 711 |
dprint(a, 1, "amp (%s): %s%s%s%s index %d gain %3d %s\n", |
|
| 712 |
st->node->name, |
|
| 713 |
(payload & AC_AMP_SET_OUTPUT) ? "o" : "-", |
|
| 714 |
(payload & AC_AMP_SET_INPUT) ? "i" : "-", |
|
| 715 |
(payload & AC_AMP_SET_LEFT) ? "l" : "-", |
|
| 716 |
(payload & AC_AMP_SET_RIGHT) ? "r" : "-", |
|
| 717 |
(payload & AC_AMP_SET_INDEX) >> AC_AMP_SET_INDEX_SHIFT, |
|
| 718 |
(payload & AC_AMP_GAIN), |
|
| 719 |
(payload & AC_AMP_MUTE) ? "muted" : ""); |
|
| 720 |
if (payload & AC_AMP_SET_LEFT) {
|
|
| 721 |
st->gain_left = payload & AC_AMP_GAIN; |
|
| 722 |
st->mute_left = payload & AC_AMP_MUTE; |
|
| 723 |
} |
|
| 724 |
if (payload & AC_AMP_SET_RIGHT) {
|
|
| 725 |
st->gain_right = payload & AC_AMP_GAIN; |
|
| 726 |
st->mute_right = payload & AC_AMP_MUTE; |
|
| 727 |
} |
|
| 728 |
hda_audio_set_amp(st); |
|
| 729 |
hda_codec_response(hda, true, 0); |
|
| 730 |
break; |
|
| 731 |
|
|
| 732 |
/* not supported */ |
|
| 733 |
case AC_VERB_SET_POWER_STATE: |
|
| 734 |
case AC_VERB_GET_POWER_STATE: |
|
| 735 |
case AC_VERB_GET_SDI_SELECT: |
|
| 736 |
hda_codec_response(hda, true, 0); |
|
| 737 |
break; |
|
| 738 |
default: |
|
| 739 |
goto fail; |
|
| 740 |
} |
|
| 741 |
return; |
|
| 742 |
|
|
| 743 |
fail: |
|
| 744 |
dprint(a, 1, "%s: not handled: nid %d (%s), verb 0x%x, payload 0x%x\n", |
|
| 745 |
__FUNCTION__, nid, node ? node->name : "?", verb, payload); |
|
| 746 |
hda_codec_response(hda, true, 0); |
|
| 747 |
} |
|
| 748 |
|
|
| 749 |
static void hda_audio_stream(HDACodecDevice *hda, uint32_t stnr, bool running) |
|
| 750 |
{
|
|
| 751 |
HDAAudioState *a = DO_UPCAST(HDAAudioState, hda, hda); |
|
| 752 |
int s; |
|
| 753 |
|
|
| 754 |
a->running[stnr] = running; |
|
| 755 |
for (s = 0; s < ARRAY_SIZE(a->st); s++) {
|
|
| 756 |
if (a->st[s].node == NULL) {
|
|
| 757 |
continue; |
|
| 758 |
} |
|
| 759 |
if (a->st[s].stream != stnr) {
|
|
| 760 |
continue; |
|
| 761 |
} |
|
| 762 |
hda_audio_set_running(&a->st[s], running); |
|
| 763 |
} |
|
| 764 |
} |
|
| 765 |
|
|
| 766 |
static int hda_audio_init(HDACodecDevice *hda, const struct desc_codec *desc) |
|
| 767 |
{
|
|
| 768 |
HDAAudioState *a = DO_UPCAST(HDAAudioState, hda, hda); |
|
| 769 |
HDAAudioStream *st; |
|
| 770 |
const desc_node *node; |
|
| 771 |
const desc_param *param; |
|
| 772 |
uint32_t i, type; |
|
| 773 |
|
|
| 774 |
a->desc = desc; |
|
| 775 |
a->name = a->hda.qdev.info->name; |
|
| 776 |
dprint(a, 1, "%s: cad %d\n", __FUNCTION__, a->hda.cad); |
|
| 777 |
|
|
| 778 |
AUD_register_card("hda", &a->card);
|
|
| 779 |
for (i = 0; i < a->desc->nnodes; i++) {
|
|
| 780 |
node = a->desc->nodes + i; |
|
| 781 |
param = hda_codec_find_param(node, AC_PAR_AUDIO_WIDGET_CAP); |
|
| 782 |
if (NULL == param) |
|
| 783 |
continue; |
|
| 784 |
type = (param->val & AC_WCAP_TYPE) >> AC_WCAP_TYPE_SHIFT; |
|
| 785 |
switch (type) {
|
|
| 786 |
case AC_WID_AUD_OUT: |
|
| 787 |
case AC_WID_AUD_IN: |
|
| 788 |
assert(node->stindex < ARRAY_SIZE(a->st)); |
|
| 789 |
st = a->st + node->stindex; |
|
| 790 |
st->state = a; |
|
| 791 |
st->node = node; |
|
| 792 |
if (type == AC_WID_AUD_OUT) {
|
|
| 793 |
/* unmute output by default */ |
|
| 794 |
st->gain_left = QEMU_HDA_AMP_STEPS; |
|
| 795 |
st->gain_right = QEMU_HDA_AMP_STEPS; |
|
| 796 |
st->bpos = sizeof(st->buf); |
|
| 797 |
st->output = true; |
|
| 798 |
} else {
|
|
| 799 |
st->output = false; |
|
| 800 |
} |
|
| 801 |
st->format = AC_FMT_TYPE_PCM | AC_FMT_BITS_16 | |
|
| 802 |
(1 << AC_FMT_CHAN_SHIFT); |
|
| 803 |
hda_codec_parse_fmt(st->format, &st->as); |
|
| 804 |
hda_audio_setup(st); |
|
| 805 |
break; |
|
| 806 |
} |
|
| 807 |
} |
|
| 808 |
return 0; |
|
| 809 |
} |
|
| 810 |
|
|
| 811 |
static int hda_audio_post_load(void *opaque, int version) |
|
| 812 |
{
|
|
| 813 |
HDAAudioState *a = opaque; |
|
| 814 |
HDAAudioStream *st; |
|
| 815 |
int i; |
|
| 816 |
|
|
| 817 |
dprint(a, 1, "%s\n", __FUNCTION__); |
|
| 818 |
for (i = 0; i < ARRAY_SIZE(a->st); i++) {
|
|
| 819 |
st = a->st + i; |
|
| 820 |
if (st->node == NULL) |
|
| 821 |
continue; |
|
| 822 |
hda_codec_parse_fmt(st->format, &st->as); |
|
| 823 |
hda_audio_setup(st); |
|
| 824 |
hda_audio_set_amp(st); |
|
| 825 |
hda_audio_set_running(st, a->running[st->stream]); |
|
| 826 |
} |
|
| 827 |
return 0; |
|
| 828 |
} |
|
| 829 |
|
|
| 830 |
static const VMStateDescription vmstate_hda_audio_stream = {
|
|
| 831 |
.name = "hda-audio-stream", |
|
| 832 |
.version_id = 1, |
|
| 833 |
.fields = (VMStateField []) {
|
|
| 834 |
VMSTATE_UINT32(stream, HDAAudioStream), |
|
| 835 |
VMSTATE_UINT32(channel, HDAAudioStream), |
|
| 836 |
VMSTATE_UINT32(format, HDAAudioStream), |
|
| 837 |
VMSTATE_UINT32(gain_left, HDAAudioStream), |
|
| 838 |
VMSTATE_UINT32(gain_right, HDAAudioStream), |
|
| 839 |
VMSTATE_BOOL(mute_left, HDAAudioStream), |
|
| 840 |
VMSTATE_BOOL(mute_right, HDAAudioStream), |
|
| 841 |
VMSTATE_UINT32(bpos, HDAAudioStream), |
|
| 842 |
VMSTATE_BUFFER(buf, HDAAudioStream), |
|
| 843 |
VMSTATE_END_OF_LIST() |
|
| 844 |
} |
|
| 845 |
}; |
|
| 846 |
|
|
| 847 |
static const VMStateDescription vmstate_hda_audio = {
|
|
| 848 |
.name = "hda-audio", |
|
| 849 |
.version_id = 1, |
|
| 850 |
.post_load = hda_audio_post_load, |
|
| 851 |
.fields = (VMStateField []) {
|
|
| 852 |
VMSTATE_STRUCT_ARRAY(st, HDAAudioState, 4, 0, |
|
| 853 |
vmstate_hda_audio_stream, |
|
| 854 |
HDAAudioStream), |
|
| 855 |
VMSTATE_BOOL_ARRAY(running, HDAAudioState, 16), |
|
| 856 |
VMSTATE_END_OF_LIST() |
|
| 857 |
} |
|
| 858 |
}; |
|
| 859 |
|
|
| 860 |
static Property hda_audio_properties[] = {
|
|
| 861 |
DEFINE_PROP_UINT32("debug", HDAAudioState, debug, 0),
|
|
| 862 |
DEFINE_PROP_END_OF_LIST(), |
|
| 863 |
}; |
|
| 864 |
|
|
| 865 |
static int hda_audio_init_output(HDACodecDevice *hda) |
|
| 866 |
{
|
|
| 867 |
return hda_audio_init(hda, &output); |
|
| 868 |
} |
|
| 869 |
|
|
| 870 |
static int hda_audio_init_duplex(HDACodecDevice *hda) |
|
| 871 |
{
|
|
| 872 |
return hda_audio_init(hda, &duplex); |
|
| 873 |
} |
|
| 874 |
|
|
| 875 |
static HDACodecDeviceInfo hda_audio_info_output = {
|
|
| 876 |
.qdev.name = "hda-output", |
|
| 877 |
.qdev.desc = "HDA Audio Codec, output-only", |
|
| 878 |
.qdev.size = sizeof(HDAAudioState), |
|
| 879 |
.qdev.vmsd = &vmstate_hda_audio, |
|
| 880 |
.qdev.props = hda_audio_properties, |
|
| 881 |
.init = hda_audio_init_output, |
|
| 882 |
.command = hda_audio_command, |
|
| 883 |
.stream = hda_audio_stream, |
|
| 884 |
}; |
|
| 885 |
|
|
| 886 |
static HDACodecDeviceInfo hda_audio_info_duplex = {
|
|
| 887 |
.qdev.name = "hda-duplex", |
|
| 888 |
.qdev.desc = "HDA Audio Codec, duplex", |
|
| 889 |
.qdev.size = sizeof(HDAAudioState), |
|
| 890 |
.qdev.vmsd = &vmstate_hda_audio, |
|
| 891 |
.qdev.props = hda_audio_properties, |
|
| 892 |
.init = hda_audio_init_duplex, |
|
| 893 |
.command = hda_audio_command, |
|
| 894 |
.stream = hda_audio_stream, |
|
| 895 |
}; |
|
| 896 |
|
|
| 897 |
static void hda_audio_register(void) |
|
| 898 |
{
|
|
| 899 |
hda_codec_register(&hda_audio_info_output); |
|
| 900 |
hda_codec_register(&hda_audio_info_duplex); |
|
| 901 |
} |
|
| 902 |
device_init(hda_audio_register); |
|
| b/hw/intel-hda-defs.h | ||
|---|---|---|
| 1 |
#ifndef HW_INTEL_HDA_DEFS_H |
|
| 2 |
#define HW_INTEL_HDA_DEFS_H |
|
| 3 |
|
|
| 4 |
/* qemu */ |
|
| 5 |
#define HDA_BUFFER_SIZE 256 |
|
| 6 |
|
|
| 7 |
/* --------------------------------------------------------------------- */ |
|
| 8 |
/* from linux/sound/pci/hda/hda_intel.c */ |
|
| 9 |
|
|
| 10 |
/* |
|
| 11 |
* registers |
|
| 12 |
*/ |
|
| 13 |
#define ICH6_REG_GCAP 0x00 |
|
| 14 |
#define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */ |
|
| 15 |
#define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */ |
|
| 16 |
#define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */ |
|
| 17 |
#define ICH6_GCAP_ISS (15 << 8) /* # of input streams */ |
|
| 18 |
#define ICH6_GCAP_OSS (15 << 12) /* # of output streams */ |
|
| 19 |
#define ICH6_REG_VMIN 0x02 |
|
| 20 |
#define ICH6_REG_VMAJ 0x03 |
|
| 21 |
#define ICH6_REG_OUTPAY 0x04 |
|
| 22 |
#define ICH6_REG_INPAY 0x06 |
|
| 23 |
#define ICH6_REG_GCTL 0x08 |
|
| 24 |
#define ICH6_GCTL_RESET (1 << 0) /* controller reset */ |
|
| 25 |
#define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */ |
|
| 26 |
#define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */ |
|
| 27 |
#define ICH6_REG_WAKEEN 0x0c |
|
| 28 |
#define ICH6_REG_STATESTS 0x0e |
|
| 29 |
#define ICH6_REG_GSTS 0x10 |
|
| 30 |
#define ICH6_GSTS_FSTS (1 << 1) /* flush status */ |
|
| 31 |
#define ICH6_REG_INTCTL 0x20 |
|
| 32 |
#define ICH6_REG_INTSTS 0x24 |
|
| 33 |
#define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */ |
|
| 34 |
#define ICH6_REG_SYNC 0x34 |
|
| 35 |
#define ICH6_REG_CORBLBASE 0x40 |
|
| 36 |
#define ICH6_REG_CORBUBASE 0x44 |
|
| 37 |
#define ICH6_REG_CORBWP 0x48 |
|
| 38 |
#define ICH6_REG_CORBRP 0x4a |
|
| 39 |
#define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */ |
|
| 40 |
#define ICH6_REG_CORBCTL 0x4c |
|
| 41 |
#define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */ |
|
| 42 |
#define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */ |
|
| 43 |
#define ICH6_REG_CORBSTS 0x4d |
|
| 44 |
#define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */ |
|
| 45 |
#define ICH6_REG_CORBSIZE 0x4e |
|
| 46 |
|
|
| 47 |
#define ICH6_REG_RIRBLBASE 0x50 |
|
| 48 |
#define ICH6_REG_RIRBUBASE 0x54 |
|
| 49 |
#define ICH6_REG_RIRBWP 0x58 |
|
| 50 |
#define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */ |
|
| 51 |
#define ICH6_REG_RINTCNT 0x5a |
|
| 52 |
#define ICH6_REG_RIRBCTL 0x5c |
|
| 53 |
#define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */ |
|
| 54 |
#define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */ |
|
| 55 |
#define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */ |
|
| 56 |
#define ICH6_REG_RIRBSTS 0x5d |
|
| 57 |
#define ICH6_RBSTS_IRQ (1 << 0) /* response irq */ |
|
| 58 |
#define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */ |
|
| 59 |
#define ICH6_REG_RIRBSIZE 0x5e |
|
| 60 |
|
|
| 61 |
#define ICH6_REG_IC 0x60 |
|
| 62 |
#define ICH6_REG_IR 0x64 |
|
| 63 |
#define ICH6_REG_IRS 0x68 |
|
| 64 |
#define ICH6_IRS_VALID (1<<1) |
|
| 65 |
#define ICH6_IRS_BUSY (1<<0) |
|
| 66 |
|
|
| 67 |
#define ICH6_REG_DPLBASE 0x70 |
|
| 68 |
#define ICH6_REG_DPUBASE 0x74 |
|
| 69 |
#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */ |
|
| 70 |
|
|
| 71 |
/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ |
|
| 72 |
enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
|
|
| 73 |
|
|
| 74 |
/* stream register offsets from stream base */ |
|
| 75 |
#define ICH6_REG_SD_CTL 0x00 |
|
| 76 |
#define ICH6_REG_SD_STS 0x03 |
|
| 77 |
#define ICH6_REG_SD_LPIB 0x04 |
|
| 78 |
#define ICH6_REG_SD_CBL 0x08 |
|
| 79 |
#define ICH6_REG_SD_LVI 0x0c |
|
| 80 |
#define ICH6_REG_SD_FIFOW 0x0e |
|
| 81 |
#define ICH6_REG_SD_FIFOSIZE 0x10 |
|
| 82 |
#define ICH6_REG_SD_FORMAT 0x12 |
|
| 83 |
#define ICH6_REG_SD_BDLPL 0x18 |
|
| 84 |
#define ICH6_REG_SD_BDLPU 0x1c |
|
| 85 |
|
|
| 86 |
/* PCI space */ |
|
| 87 |
#define ICH6_PCIREG_TCSEL 0x44 |
|
| 88 |
|
|
| 89 |
/* |
|
| 90 |
* other constants |
|
| 91 |
*/ |
|
| 92 |
|
|
| 93 |
/* max number of SDs */ |
|
| 94 |
/* ICH, ATI and VIA have 4 playback and 4 capture */ |
|
| 95 |
#define ICH6_NUM_CAPTURE 4 |
|
| 96 |
#define ICH6_NUM_PLAYBACK 4 |
|
| 97 |
|
|
| 98 |
/* ULI has 6 playback and 5 capture */ |
|
| 99 |
#define ULI_NUM_CAPTURE 5 |
|
| 100 |
#define ULI_NUM_PLAYBACK 6 |
|
| 101 |
|
|
| 102 |
/* ATI HDMI has 1 playback and 0 capture */ |
|
| 103 |
#define ATIHDMI_NUM_CAPTURE 0 |
|
| 104 |
#define ATIHDMI_NUM_PLAYBACK 1 |
|
| 105 |
|
|
| 106 |
/* TERA has 4 playback and 3 capture */ |
|
| 107 |
#define TERA_NUM_CAPTURE 3 |
|
| 108 |
#define TERA_NUM_PLAYBACK 4 |
|
| 109 |
|
|
| 110 |
/* this number is statically defined for simplicity */ |
|
| 111 |
#define MAX_AZX_DEV 16 |
|
| 112 |
|
|
| 113 |
/* max number of fragments - we may use more if allocating more pages for BDL */ |
|
| 114 |
#define BDL_SIZE 4096 |
|
| 115 |
#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16) |
|
| 116 |
#define AZX_MAX_FRAG 32 |
|
| 117 |
/* max buffer size - no h/w limit, you can increase as you like */ |
|
| 118 |
#define AZX_MAX_BUF_SIZE (1024*1024*1024) |
|
| 119 |
|
|
| 120 |
/* RIRB int mask: overrun[2], response[0] */ |
|
| 121 |
#define RIRB_INT_RESPONSE 0x01 |
|
| 122 |
#define RIRB_INT_OVERRUN 0x04 |
|
| 123 |
#define RIRB_INT_MASK 0x05 |
|
| 124 |
|
|
| 125 |
/* STATESTS int mask: S3,SD2,SD1,SD0 */ |
|
| 126 |
#define AZX_MAX_CODECS 8 |
|
| 127 |
#define AZX_DEFAULT_CODECS 4 |
|
| 128 |
#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1) |
|
| 129 |
|
|
| 130 |
/* SD_CTL bits */ |
|
| 131 |
#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ |
|
| 132 |
#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ |
|
| 133 |
#define SD_CTL_STRIPE (3 << 16) /* stripe control */ |
|
| 134 |
#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */ |
|
| 135 |
#define SD_CTL_DIR (1 << 19) /* bi-directional stream */ |
|
| 136 |
#define SD_CTL_STREAM_TAG_MASK (0xf << 20) |
|
| 137 |
#define SD_CTL_STREAM_TAG_SHIFT 20 |
|
| 138 |
|
|
| 139 |
/* SD_CTL and SD_STS */ |
|
| 140 |
#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ |
|
| 141 |
#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ |
|
| 142 |
#define SD_INT_COMPLETE 0x04 /* completion interrupt */ |
|
| 143 |
#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ |
|
| 144 |
SD_INT_COMPLETE) |
|
| 145 |
|
|
| 146 |
/* SD_STS */ |
|
| 147 |
#define SD_STS_FIFO_READY 0x20 /* FIFO ready */ |
|
| 148 |
|
|
| 149 |
/* INTCTL and INTSTS */ |
|
| 150 |
#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */ |
|
| 151 |
#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ |
|
| 152 |
#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ |
|
| 153 |
|
|
| 154 |
/* below are so far hardcoded - should read registers in future */ |
|
| 155 |
#define ICH6_MAX_CORB_ENTRIES 256 |
|
| 156 |
#define ICH6_MAX_RIRB_ENTRIES 256 |
|
| 157 |
|
|
| 158 |
/* position fix mode */ |
|
| 159 |
enum {
|
|
| 160 |
POS_FIX_AUTO, |
|
| 161 |
POS_FIX_LPIB, |
|
| 162 |
POS_FIX_POSBUF, |
|
| 163 |
}; |
|
| 164 |
|
|
| 165 |
/* Defines for ATI HD Audio support in SB450 south bridge */ |
|
| 166 |
#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 |
|
| 167 |
#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 |
|
| 168 |
|
|
| 169 |
/* Defines for Nvidia HDA support */ |
|
| 170 |
#define NVIDIA_HDA_TRANSREG_ADDR 0x4e |
|
| 171 |
#define NVIDIA_HDA_ENABLE_COHBITS 0x0f |
|
| 172 |
#define NVIDIA_HDA_ISTRM_COH 0x4d |
|
| 173 |
#define NVIDIA_HDA_OSTRM_COH 0x4c |
|
| 174 |
#define NVIDIA_HDA_ENABLE_COHBIT 0x01 |
|
| 175 |
|
|
| 176 |
/* Defines for Intel SCH HDA snoop control */ |
|
| 177 |
#define INTEL_SCH_HDA_DEVC 0x78 |
|
| 178 |
#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) |
|
| 179 |
|
|
| 180 |
/* Define IN stream 0 FIFO size offset in VIA controller */ |
|
| 181 |
#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90 |
|
| 182 |
/* Define VIA HD Audio Device ID*/ |
|
| 183 |
#define VIA_HDAC_DEVICE_ID 0x3288 |
|
| 184 |
|
|
| 185 |
/* HD Audio class code */ |
|
| 186 |
#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 |
|
| 187 |
|
|
| 188 |
/* --------------------------------------------------------------------- */ |
|
| 189 |
/* from linux/sound/pci/hda/hda_codec.h */ |
|
| 190 |
|
|
| 191 |
/* |
|
| 192 |
* nodes |
|
| 193 |
*/ |
|
| 194 |
#define AC_NODE_ROOT 0x00 |
|
| 195 |
|
|
| 196 |
/* |
|
| 197 |
* function group types |
|
| 198 |
*/ |
|
| 199 |
enum {
|
|
| 200 |
AC_GRP_AUDIO_FUNCTION = 0x01, |
|
| 201 |
AC_GRP_MODEM_FUNCTION = 0x02, |
|
| 202 |
}; |
|
| 203 |
|
|
| 204 |
/* |
|
| 205 |
* widget types |
|
| 206 |
*/ |
|
| 207 |
enum {
|
|
| 208 |
AC_WID_AUD_OUT, /* Audio Out */ |
|
| 209 |
AC_WID_AUD_IN, /* Audio In */ |
|
| 210 |
AC_WID_AUD_MIX, /* Audio Mixer */ |
|
| 211 |
AC_WID_AUD_SEL, /* Audio Selector */ |
|
| 212 |
AC_WID_PIN, /* Pin Complex */ |
|
| 213 |
AC_WID_POWER, /* Power */ |
|
| 214 |
AC_WID_VOL_KNB, /* Volume Knob */ |
|
| 215 |
AC_WID_BEEP, /* Beep Generator */ |
|
| 216 |
AC_WID_VENDOR = 0x0f /* Vendor specific */ |
|
| 217 |
}; |
|
| 218 |
|
|
| 219 |
/* |
|
| 220 |
* GET verbs |
|
| 221 |
*/ |
|
| 222 |
#define AC_VERB_GET_STREAM_FORMAT 0x0a00 |
|
| 223 |
#define AC_VERB_GET_AMP_GAIN_MUTE 0x0b00 |
|
| 224 |
#define AC_VERB_GET_PROC_COEF 0x0c00 |
|
| 225 |
#define AC_VERB_GET_COEF_INDEX 0x0d00 |
|
| 226 |
#define AC_VERB_PARAMETERS 0x0f00 |
|
| 227 |
#define AC_VERB_GET_CONNECT_SEL 0x0f01 |
|
| 228 |
#define AC_VERB_GET_CONNECT_LIST 0x0f02 |
|
| 229 |
#define AC_VERB_GET_PROC_STATE 0x0f03 |
|
| 230 |
#define AC_VERB_GET_SDI_SELECT 0x0f04 |
|
| 231 |
#define AC_VERB_GET_POWER_STATE 0x0f05 |
|
| 232 |
#define AC_VERB_GET_CONV 0x0f06 |
|
| 233 |
#define AC_VERB_GET_PIN_WIDGET_CONTROL 0x0f07 |
|
| 234 |
#define AC_VERB_GET_UNSOLICITED_RESPONSE 0x0f08 |
|
| 235 |
#define AC_VERB_GET_PIN_SENSE 0x0f09 |
|
| 236 |
#define AC_VERB_GET_BEEP_CONTROL 0x0f0a |
|
| 237 |
#define AC_VERB_GET_EAPD_BTLENABLE 0x0f0c |
|
| 238 |
#define AC_VERB_GET_DIGI_CONVERT_1 0x0f0d |
|
| 239 |
#define AC_VERB_GET_DIGI_CONVERT_2 0x0f0e /* unused */ |
|
| 240 |
#define AC_VERB_GET_VOLUME_KNOB_CONTROL 0x0f0f |
|
| 241 |
/* f10-f1a: GPIO */ |
|
| 242 |
#define AC_VERB_GET_GPIO_DATA 0x0f15 |
|
| 243 |
#define AC_VERB_GET_GPIO_MASK 0x0f16 |
|
| 244 |
#define AC_VERB_GET_GPIO_DIRECTION 0x0f17 |
|
| 245 |
#define AC_VERB_GET_GPIO_WAKE_MASK 0x0f18 |
|
| 246 |
#define AC_VERB_GET_GPIO_UNSOLICITED_RSP_MASK 0x0f19 |
|
| 247 |
#define AC_VERB_GET_GPIO_STICKY_MASK 0x0f1a |
|
| 248 |
#define AC_VERB_GET_CONFIG_DEFAULT 0x0f1c |
|
| 249 |
/* f20: AFG/MFG */ |
|
| 250 |
#define AC_VERB_GET_SUBSYSTEM_ID 0x0f20 |
|
| 251 |
#define AC_VERB_GET_CVT_CHAN_COUNT 0x0f2d |
|
| 252 |
#define AC_VERB_GET_HDMI_DIP_SIZE 0x0f2e |
|
| 253 |
#define AC_VERB_GET_HDMI_ELDD 0x0f2f |
|
| 254 |
#define AC_VERB_GET_HDMI_DIP_INDEX 0x0f30 |
|
| 255 |
#define AC_VERB_GET_HDMI_DIP_DATA 0x0f31 |
|
| 256 |
#define AC_VERB_GET_HDMI_DIP_XMIT 0x0f32 |
|
| 257 |
#define AC_VERB_GET_HDMI_CP_CTRL 0x0f33 |
|
| 258 |
#define AC_VERB_GET_HDMI_CHAN_SLOT 0x0f34 |
|
| 259 |
|
|
| 260 |
/* |
|
| 261 |
* SET verbs |
|
| 262 |
*/ |
|
| 263 |
#define AC_VERB_SET_STREAM_FORMAT 0x200 |
|
| 264 |
#define AC_VERB_SET_AMP_GAIN_MUTE 0x300 |
|
| 265 |
#define AC_VERB_SET_PROC_COEF 0x400 |
|
| 266 |
#define AC_VERB_SET_COEF_INDEX 0x500 |
|
| 267 |
#define AC_VERB_SET_CONNECT_SEL 0x701 |
|
| 268 |
#define AC_VERB_SET_PROC_STATE 0x703 |
|
| 269 |
#define AC_VERB_SET_SDI_SELECT 0x704 |
|
| 270 |
#define AC_VERB_SET_POWER_STATE 0x705 |
|
| 271 |
#define AC_VERB_SET_CHANNEL_STREAMID 0x706 |
|
| 272 |
#define AC_VERB_SET_PIN_WIDGET_CONTROL 0x707 |
|
| 273 |
#define AC_VERB_SET_UNSOLICITED_ENABLE 0x708 |
|
| 274 |
#define AC_VERB_SET_PIN_SENSE 0x709 |
|
| 275 |
#define AC_VERB_SET_BEEP_CONTROL 0x70a |
|
| 276 |
#define AC_VERB_SET_EAPD_BTLENABLE 0x70c |
|
| 277 |
#define AC_VERB_SET_DIGI_CONVERT_1 0x70d |
|
| 278 |
#define AC_VERB_SET_DIGI_CONVERT_2 0x70e |
|
| 279 |
#define AC_VERB_SET_VOLUME_KNOB_CONTROL 0x70f |
|
| 280 |
#define AC_VERB_SET_GPIO_DATA 0x715 |
|
| 281 |
#define AC_VERB_SET_GPIO_MASK 0x716 |
|
| 282 |
#define AC_VERB_SET_GPIO_DIRECTION 0x717 |
|
| 283 |
#define AC_VERB_SET_GPIO_WAKE_MASK 0x718 |
|
| 284 |
#define AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK 0x719 |
|
| 285 |
#define AC_VERB_SET_GPIO_STICKY_MASK 0x71a |
|
| 286 |
#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_0 0x71c |
|
| 287 |
#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_1 0x71d |
|
| 288 |
#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_2 0x71e |
|
| 289 |
#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_3 0x71f |
|
| 290 |
#define AC_VERB_SET_EAPD 0x788 |
|
| 291 |
#define AC_VERB_SET_CODEC_RESET 0x7ff |
|
| 292 |
#define AC_VERB_SET_CVT_CHAN_COUNT 0x72d |
|
| 293 |
#define AC_VERB_SET_HDMI_DIP_INDEX 0x730 |
|
| 294 |
#define AC_VERB_SET_HDMI_DIP_DATA 0x731 |
|
| 295 |
#define AC_VERB_SET_HDMI_DIP_XMIT 0x732 |
|
| 296 |
#define AC_VERB_SET_HDMI_CP_CTRL 0x733 |
|
| 297 |
#define AC_VERB_SET_HDMI_CHAN_SLOT 0x734 |
|
| 298 |
|
|
| 299 |
/* |
|
| 300 |
* Parameter IDs |
|
| 301 |
*/ |
|
| 302 |
#define AC_PAR_VENDOR_ID 0x00 |
|
| 303 |
#define AC_PAR_SUBSYSTEM_ID 0x01 |
|
| 304 |
#define AC_PAR_REV_ID 0x02 |
|
| 305 |
#define AC_PAR_NODE_COUNT 0x04 |
|
| 306 |
#define AC_PAR_FUNCTION_TYPE 0x05 |
|
| 307 |
#define AC_PAR_AUDIO_FG_CAP 0x08 |
|
| 308 |
#define AC_PAR_AUDIO_WIDGET_CAP 0x09 |
|
| 309 |
#define AC_PAR_PCM 0x0a |
|
| 310 |
#define AC_PAR_STREAM 0x0b |
|
| 311 |
#define AC_PAR_PIN_CAP 0x0c |
|
| 312 |
#define AC_PAR_AMP_IN_CAP 0x0d |
|
| 313 |
#define AC_PAR_CONNLIST_LEN 0x0e |
|
| 314 |
#define AC_PAR_POWER_STATE 0x0f |
|
| 315 |
#define AC_PAR_PROC_CAP 0x10 |
|
| 316 |
#define AC_PAR_GPIO_CAP 0x11 |
|
| 317 |
#define AC_PAR_AMP_OUT_CAP 0x12 |
|
| 318 |
#define AC_PAR_VOL_KNB_CAP 0x13 |
|
| 319 |
#define AC_PAR_HDMI_LPCM_CAP 0x20 |
|
| 320 |
|
|
| 321 |
/* |
|
| 322 |
* AC_VERB_PARAMETERS results (32bit) |
|
| 323 |
*/ |
|
| 324 |
|
|
| 325 |
/* Function Group Type */ |
|
| 326 |
#define AC_FGT_TYPE (0xff<<0) |
|
| 327 |
#define AC_FGT_TYPE_SHIFT 0 |
|
| 328 |
#define AC_FGT_UNSOL_CAP (1<<8) |
|
| 329 |
|
|
| 330 |
/* Audio Function Group Capabilities */ |
|
| 331 |
#define AC_AFG_OUT_DELAY (0xf<<0) |
|
| 332 |
#define AC_AFG_IN_DELAY (0xf<<8) |
|
| 333 |
#define AC_AFG_BEEP_GEN (1<<16) |
|
| 334 |
|
|
| 335 |
/* Audio Widget Capabilities */ |
|
| 336 |
#define AC_WCAP_STEREO (1<<0) /* stereo I/O */ |
|
| 337 |
#define AC_WCAP_IN_AMP (1<<1) /* AMP-in present */ |
|
| 338 |
#define AC_WCAP_OUT_AMP (1<<2) /* AMP-out present */ |
|
| 339 |
#define AC_WCAP_AMP_OVRD (1<<3) /* AMP-parameter override */ |
|
| 340 |
#define AC_WCAP_FORMAT_OVRD (1<<4) /* format override */ |
|
| 341 |
#define AC_WCAP_STRIPE (1<<5) /* stripe */ |
|
| 342 |
#define AC_WCAP_PROC_WID (1<<6) /* Proc Widget */ |
|
| 343 |
#define AC_WCAP_UNSOL_CAP (1<<7) /* Unsol capable */ |
|
| 344 |
#define AC_WCAP_CONN_LIST (1<<8) /* connection list */ |
|
| 345 |
#define AC_WCAP_DIGITAL (1<<9) /* digital I/O */ |
|
| 346 |
#define AC_WCAP_POWER (1<<10) /* power control */ |
|
| 347 |
#define AC_WCAP_LR_SWAP (1<<11) /* L/R swap */ |
|
| 348 |
#define AC_WCAP_CP_CAPS (1<<12) /* content protection */ |
|
| 349 |
#define AC_WCAP_CHAN_CNT_EXT (7<<13) /* channel count ext */ |
|
| 350 |
#define AC_WCAP_DELAY (0xf<<16) |
|
| 351 |
#define AC_WCAP_DELAY_SHIFT 16 |
|
| 352 |
#define AC_WCAP_TYPE (0xf<<20) |
|
| 353 |
#define AC_WCAP_TYPE_SHIFT 20 |
|
| 354 |
|
|
| 355 |
/* supported PCM rates and bits */ |
|
| 356 |
#define AC_SUPPCM_RATES (0xfff << 0) |
|
| 357 |
#define AC_SUPPCM_BITS_8 (1<<16) |
|
| 358 |
#define AC_SUPPCM_BITS_16 (1<<17) |
|
| 359 |
#define AC_SUPPCM_BITS_20 (1<<18) |
|
| 360 |
#define AC_SUPPCM_BITS_24 (1<<19) |
|
| 361 |
#define AC_SUPPCM_BITS_32 (1<<20) |
|
| 362 |
|
|
| 363 |
/* supported PCM stream format */ |
|
| 364 |
#define AC_SUPFMT_PCM (1<<0) |
|
| 365 |
#define AC_SUPFMT_FLOAT32 (1<<1) |
|
| 366 |
#define AC_SUPFMT_AC3 (1<<2) |
|
| 367 |
|
|
| 368 |
/* GP I/O count */ |
|
| 369 |
#define AC_GPIO_IO_COUNT (0xff<<0) |
|
| 370 |
#define AC_GPIO_O_COUNT (0xff<<8) |
|
| 371 |
#define AC_GPIO_O_COUNT_SHIFT 8 |
|
| 372 |
#define AC_GPIO_I_COUNT (0xff<<16) |
|
| 373 |
#define AC_GPIO_I_COUNT_SHIFT 16 |
|
| 374 |
#define AC_GPIO_UNSOLICITED (1<<30) |
|
| 375 |
#define AC_GPIO_WAKE (1<<31) |
|
| 376 |
|
|
| 377 |
/* Converter stream, channel */ |
|
| 378 |
#define AC_CONV_CHANNEL (0xf<<0) |
|
| 379 |
#define AC_CONV_STREAM (0xf<<4) |
|
| 380 |
#define AC_CONV_STREAM_SHIFT 4 |
|
| 381 |
|
|
| 382 |
/* Input converter SDI select */ |
|
| 383 |
#define AC_SDI_SELECT (0xf<<0) |
|
| 384 |
|
|
| 385 |
/* stream format id */ |
|
| 386 |
#define AC_FMT_CHAN_SHIFT 0 |
|
| 387 |
#define AC_FMT_CHAN_MASK (0x0f << 0) |
|
| 388 |
#define AC_FMT_BITS_SHIFT 4 |
|
| 389 |
#define AC_FMT_BITS_MASK (7 << 4) |
|
| 390 |
#define AC_FMT_BITS_8 (0 << 4) |
|
| 391 |
#define AC_FMT_BITS_16 (1 << 4) |
|
| 392 |
#define AC_FMT_BITS_20 (2 << 4) |
|
| 393 |
#define AC_FMT_BITS_24 (3 << 4) |
|
| 394 |
#define AC_FMT_BITS_32 (4 << 4) |
|
| 395 |
#define AC_FMT_DIV_SHIFT 8 |
|
| 396 |
#define AC_FMT_DIV_MASK (7 << 8) |
|
| 397 |
#define AC_FMT_MULT_SHIFT 11 |
|
| 398 |
#define AC_FMT_MULT_MASK (7 << 11) |
|
| 399 |
#define AC_FMT_BASE_SHIFT 14 |
|
| 400 |
#define AC_FMT_BASE_48K (0 << 14) |
|
| 401 |
#define AC_FMT_BASE_44K (1 << 14) |
|
| 402 |
#define AC_FMT_TYPE_SHIFT 15 |
|
| 403 |
#define AC_FMT_TYPE_PCM (0 << 15) |
|
| 404 |
#define AC_FMT_TYPE_NON_PCM (1 << 15) |
|
| 405 |
|
|
| 406 |
/* Unsolicited response control */ |
|
| 407 |
#define AC_UNSOL_TAG (0x3f<<0) |
|
| 408 |
#define AC_UNSOL_ENABLED (1<<7) |
|
| 409 |
#define AC_USRSP_EN AC_UNSOL_ENABLED |
|
| 410 |
|
|
| 411 |
/* Unsolicited responses */ |
|
| 412 |
#define AC_UNSOL_RES_TAG (0x3f<<26) |
|
| 413 |
#define AC_UNSOL_RES_TAG_SHIFT 26 |
|
| 414 |
#define AC_UNSOL_RES_SUBTAG (0x1f<<21) |
|
| 415 |
#define AC_UNSOL_RES_SUBTAG_SHIFT 21 |
|
| 416 |
#define AC_UNSOL_RES_ELDV (1<<1) /* ELD Data valid (for HDMI) */ |
|
| 417 |
#define AC_UNSOL_RES_PD (1<<0) /* pinsense detect */ |
|
| 418 |
#define AC_UNSOL_RES_CP_STATE (1<<1) /* content protection */ |
|
| 419 |
#define AC_UNSOL_RES_CP_READY (1<<0) /* content protection */ |
|
| 420 |
|
|
| 421 |
/* Pin widget capabilies */ |
|
| 422 |
#define AC_PINCAP_IMP_SENSE (1<<0) /* impedance sense capable */ |
|
| 423 |
#define AC_PINCAP_TRIG_REQ (1<<1) /* trigger required */ |
|
| 424 |
#define AC_PINCAP_PRES_DETECT (1<<2) /* presence detect capable */ |
|
| 425 |
#define AC_PINCAP_HP_DRV (1<<3) /* headphone drive capable */ |
|
| 426 |
#define AC_PINCAP_OUT (1<<4) /* output capable */ |
|
| 427 |
#define AC_PINCAP_IN (1<<5) /* input capable */ |
|
| 428 |
#define AC_PINCAP_BALANCE (1<<6) /* balanced I/O capable */ |
|
| 429 |
/* Note: This LR_SWAP pincap is defined in the Realtek ALC883 specification, |
|
| 430 |
* but is marked reserved in the Intel HDA specification. |
|
| 431 |
*/ |
|
| 432 |
#define AC_PINCAP_LR_SWAP (1<<7) /* L/R swap */ |
|
| 433 |
/* Note: The same bit as LR_SWAP is newly defined as HDMI capability |
|
| 434 |
* in HD-audio specification |
|
| 435 |
*/ |
|
| 436 |
#define AC_PINCAP_HDMI (1<<7) /* HDMI pin */ |
|
| 437 |
#define AC_PINCAP_DP (1<<24) /* DisplayPort pin, can |
|
| 438 |
* coexist with AC_PINCAP_HDMI |
|
| 439 |
*/ |
|
| 440 |
#define AC_PINCAP_VREF (0x37<<8) |
|
| 441 |
#define AC_PINCAP_VREF_SHIFT 8 |
|
| 442 |
#define AC_PINCAP_EAPD (1<<16) /* EAPD capable */ |
|
| 443 |
#define AC_PINCAP_HBR (1<<27) /* High Bit Rate */ |
|
| 444 |
/* Vref status (used in pin cap) */ |
|
| 445 |
#define AC_PINCAP_VREF_HIZ (1<<0) /* Hi-Z */ |
|
| 446 |
#define AC_PINCAP_VREF_50 (1<<1) /* 50% */ |
|
| 447 |
#define AC_PINCAP_VREF_GRD (1<<2) /* ground */ |
|
| 448 |
#define AC_PINCAP_VREF_80 (1<<4) /* 80% */ |
|
| 449 |
#define AC_PINCAP_VREF_100 (1<<5) /* 100% */ |
|
| 450 |
|
|
| 451 |
/* Amplifier capabilities */ |
|
| 452 |
#define AC_AMPCAP_OFFSET (0x7f<<0) /* 0dB offset */ |
|
| 453 |
#define AC_AMPCAP_OFFSET_SHIFT 0 |
|
| 454 |
#define AC_AMPCAP_NUM_STEPS (0x7f<<8) /* number of steps */ |
|
| 455 |
#define AC_AMPCAP_NUM_STEPS_SHIFT 8 |
|
| 456 |
#define AC_AMPCAP_STEP_SIZE (0x7f<<16) /* step size 0-32dB |
|
| 457 |
* in 0.25dB |
|
| 458 |
*/ |
|
| 459 |
#define AC_AMPCAP_STEP_SIZE_SHIFT 16 |
|
| 460 |
#define AC_AMPCAP_MUTE (1<<31) /* mute capable */ |
|
| 461 |
#define AC_AMPCAP_MUTE_SHIFT 31 |
|
| 462 |
|
|
| 463 |
/* Connection list */ |
|
| 464 |
#define AC_CLIST_LENGTH (0x7f<<0) |
|
| 465 |
#define AC_CLIST_LONG (1<<7) |
|
| 466 |
|
|
| 467 |
/* Supported power status */ |
|
| 468 |
#define AC_PWRST_D0SUP (1<<0) |
|
| 469 |
#define AC_PWRST_D1SUP (1<<1) |
|
| 470 |
#define AC_PWRST_D2SUP (1<<2) |
|
| 471 |
#define AC_PWRST_D3SUP (1<<3) |
|
| 472 |
#define AC_PWRST_D3COLDSUP (1<<4) |
|
| 473 |
#define AC_PWRST_S3D3COLDSUP (1<<29) |
|
| 474 |
#define AC_PWRST_CLKSTOP (1<<30) |
|
| 475 |
#define AC_PWRST_EPSS (1U<<31) |
|
| 476 |
|
|
| 477 |
/* Power state values */ |
|
| 478 |
#define AC_PWRST_SETTING (0xf<<0) |
|
| 479 |
#define AC_PWRST_ACTUAL (0xf<<4) |
|
| 480 |
#define AC_PWRST_ACTUAL_SHIFT 4 |
|
| 481 |
#define AC_PWRST_D0 0x00 |
|
| 482 |
#define AC_PWRST_D1 0x01 |
|
Also available in: Unified diff