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1 | ab93bbe2 | bellard | /*
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2 | ab93bbe2 | bellard | * common defines for all CPUs
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3 | 5fafdf24 | ths | *
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4 | ab93bbe2 | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | ab93bbe2 | bellard | *
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6 | ab93bbe2 | bellard | * This library is free software; you can redistribute it and/or
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7 | ab93bbe2 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | ab93bbe2 | bellard | * License as published by the Free Software Foundation; either
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9 | ab93bbe2 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | ab93bbe2 | bellard | *
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11 | ab93bbe2 | bellard | * This library is distributed in the hope that it will be useful,
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12 | ab93bbe2 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | ab93bbe2 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | ab93bbe2 | bellard | * Lesser General Public License for more details.
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15 | ab93bbe2 | bellard | *
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16 | ab93bbe2 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | ab93bbe2 | bellard | * License along with this library; if not, write to the Free Software
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18 | ab93bbe2 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | ab93bbe2 | bellard | */
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20 | ab93bbe2 | bellard | #ifndef CPU_DEFS_H
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21 | ab93bbe2 | bellard | #define CPU_DEFS_H
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22 | ab93bbe2 | bellard | |
23 | 87ecb68b | pbrook | #ifndef NEED_CPU_H
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24 | 87ecb68b | pbrook | #error cpu.h included from common code
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25 | 87ecb68b | pbrook | #endif
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26 | 87ecb68b | pbrook | |
27 | ab93bbe2 | bellard | #include "config.h" |
28 | ab93bbe2 | bellard | #include <setjmp.h> |
29 | ed1c0bcb | bellard | #include <inttypes.h> |
30 | ed1c0bcb | bellard | #include "osdep.h" |
31 | ab93bbe2 | bellard | |
32 | 35b66fc4 | bellard | #ifndef TARGET_LONG_BITS
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33 | 35b66fc4 | bellard | #error TARGET_LONG_BITS must be defined before including this header
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34 | 35b66fc4 | bellard | #endif
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35 | 35b66fc4 | bellard | |
36 | 5fafdf24 | ths | #ifndef TARGET_PHYS_ADDR_BITS
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37 | 4f2ac237 | bellard | #if TARGET_LONG_BITS >= HOST_LONG_BITS
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38 | ab6d960f | bellard | #define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS
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39 | 4f2ac237 | bellard | #else
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40 | 4f2ac237 | bellard | #define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS
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41 | 4f2ac237 | bellard | #endif
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42 | ab6d960f | bellard | #endif
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43 | ab6d960f | bellard | |
44 | 35b66fc4 | bellard | #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) |
45 | 35b66fc4 | bellard | |
46 | ab6d960f | bellard | /* target_ulong is the type of a virtual address */
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47 | 35b66fc4 | bellard | #if TARGET_LONG_SIZE == 4 |
48 | 35b66fc4 | bellard | typedef int32_t target_long;
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49 | 35b66fc4 | bellard | typedef uint32_t target_ulong;
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50 | c27004ec | bellard | #define TARGET_FMT_lx "%08x" |
51 | b62b461b | j_mayer | #define TARGET_FMT_ld "%d" |
52 | 71c8b8fd | j_mayer | #define TARGET_FMT_lu "%u" |
53 | 35b66fc4 | bellard | #elif TARGET_LONG_SIZE == 8 |
54 | 35b66fc4 | bellard | typedef int64_t target_long;
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55 | 35b66fc4 | bellard | typedef uint64_t target_ulong;
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56 | 26a76461 | bellard | #define TARGET_FMT_lx "%016" PRIx64 |
57 | b62b461b | j_mayer | #define TARGET_FMT_ld "%" PRId64 |
58 | 71c8b8fd | j_mayer | #define TARGET_FMT_lu "%" PRIu64 |
59 | 35b66fc4 | bellard | #else
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60 | 35b66fc4 | bellard | #error TARGET_LONG_SIZE undefined
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61 | 35b66fc4 | bellard | #endif
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62 | 35b66fc4 | bellard | |
63 | ab6d960f | bellard | /* target_phys_addr_t is the type of a physical address (its size can
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64 | 4f2ac237 | bellard | be different from 'target_ulong'). We have sizeof(target_phys_addr)
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65 | 4f2ac237 | bellard | = max(sizeof(unsigned long),
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66 | 4f2ac237 | bellard | sizeof(size_of_target_physical_address)) because we must pass a
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67 | 4f2ac237 | bellard | host pointer to memory operations in some cases */
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68 | 4f2ac237 | bellard | |
69 | ab6d960f | bellard | #if TARGET_PHYS_ADDR_BITS == 32 |
70 | ab6d960f | bellard | typedef uint32_t target_phys_addr_t;
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71 | ba13c432 | j_mayer | #define TARGET_FMT_plx "%08x" |
72 | ab6d960f | bellard | #elif TARGET_PHYS_ADDR_BITS == 64 |
73 | ab6d960f | bellard | typedef uint64_t target_phys_addr_t;
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74 | ba13c432 | j_mayer | #define TARGET_FMT_plx "%016" PRIx64 |
75 | ab6d960f | bellard | #else
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76 | ab6d960f | bellard | #error TARGET_PHYS_ADDR_BITS undefined
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77 | ab6d960f | bellard | #endif
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78 | ab6d960f | bellard | |
79 | ff7b8f5b | bellard | /* address in the RAM (different from a physical address) */
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80 | ff7b8f5b | bellard | typedef unsigned long ram_addr_t; |
81 | ff7b8f5b | bellard | |
82 | f193c797 | bellard | #define HOST_LONG_SIZE (HOST_LONG_BITS / 8) |
83 | f193c797 | bellard | |
84 | 2be0071f | bellard | #define EXCP_INTERRUPT 0x10000 /* async interruption */ |
85 | 2be0071f | bellard | #define EXCP_HLT 0x10001 /* hlt instruction reached */ |
86 | 2be0071f | bellard | #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ |
87 | 5a1e3cfc | bellard | #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ |
88 | ab93bbe2 | bellard | #define MAX_BREAKPOINTS 32 |
89 | 6658ffb8 | pbrook | #define MAX_WATCHPOINTS 32 |
90 | ab93bbe2 | bellard | |
91 | a316d335 | bellard | #define TB_JMP_CACHE_BITS 12 |
92 | a316d335 | bellard | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) |
93 | a316d335 | bellard | |
94 | b362e5e0 | pbrook | /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
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95 | b362e5e0 | pbrook | addresses on the same page. The top bits are the same. This allows
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96 | b362e5e0 | pbrook | TLB invalidation to quickly clear a subset of the hash table. */
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97 | b362e5e0 | pbrook | #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2) |
98 | b362e5e0 | pbrook | #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS) |
99 | b362e5e0 | pbrook | #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1) |
100 | b362e5e0 | pbrook | #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
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101 | b362e5e0 | pbrook | |
102 | 84b7b8e7 | bellard | #define CPU_TLB_BITS 8 |
103 | 84b7b8e7 | bellard | #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) |
104 | ab93bbe2 | bellard | |
105 | d656469f | bellard | #if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32 |
106 | d656469f | bellard | #define CPU_TLB_ENTRY_BITS 4 |
107 | d656469f | bellard | #else
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108 | d656469f | bellard | #define CPU_TLB_ENTRY_BITS 5 |
109 | d656469f | bellard | #endif
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110 | d656469f | bellard | |
111 | ab93bbe2 | bellard | typedef struct CPUTLBEntry { |
112 | 5fafdf24 | ths | /* bit 31 to TARGET_PAGE_BITS : virtual address
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113 | db8d7466 | bellard | bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io
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114 | db8d7466 | bellard | zone number
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115 | db8d7466 | bellard | bit 3 : indicates that the entry is invalid
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116 | db8d7466 | bellard | bit 2..0 : zero
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117 | db8d7466 | bellard | */
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118 | 5fafdf24 | ths | target_ulong addr_read; |
119 | 5fafdf24 | ths | target_ulong addr_write; |
120 | 5fafdf24 | ths | target_ulong addr_code; |
121 | db8d7466 | bellard | /* addend to virtual address to get physical address */
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122 | d656469f | bellard | #if TARGET_PHYS_ADDR_BITS == 64 |
123 | d656469f | bellard | /* on i386 Linux make sure it is aligned */
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124 | d656469f | bellard | target_phys_addr_t addend __attribute__((aligned(8)));
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125 | d656469f | bellard | #else
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126 | 5fafdf24 | ths | target_phys_addr_t addend; |
127 | d656469f | bellard | #endif
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128 | d656469f | bellard | /* padding to get a power of two size */
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129 | d656469f | bellard | uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
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130 | d656469f | bellard | (sizeof(target_ulong) * 3 + |
131 | d656469f | bellard | ((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) + |
132 | d656469f | bellard | sizeof(target_phys_addr_t))];
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133 | ab93bbe2 | bellard | } CPUTLBEntry; |
134 | ab93bbe2 | bellard | |
135 | a316d335 | bellard | #define CPU_COMMON \
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136 | a316d335 | bellard | struct TranslationBlock *current_tb; /* currently executing TB */ \ |
137 | a316d335 | bellard | /* soft mmu support */ \
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138 | a316d335 | bellard | /* in order to avoid passing too many arguments to the memory \
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139 | a316d335 | bellard | write helpers, we store some rarely used information in the CPU \
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140 | a316d335 | bellard | context) */ \
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141 | a316d335 | bellard | unsigned long mem_write_pc; /* host pc at which the memory was \ |
142 | a316d335 | bellard | written */ \
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143 | a316d335 | bellard | target_ulong mem_write_vaddr; /* target virtual addr at which the \
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144 | a316d335 | bellard | memory was written */ \
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145 | 623a930e | ths | /* The meaning of the MMU modes is defined in the target code. */ \
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146 | 6fa4cea9 | j_mayer | CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ |
147 | a316d335 | bellard | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
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148 | a316d335 | bellard | \ |
149 | a316d335 | bellard | /* from this point: preserved by CPU reset */ \
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150 | a316d335 | bellard | /* ice debug support */ \
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151 | a316d335 | bellard | target_ulong breakpoints[MAX_BREAKPOINTS]; \ |
152 | a316d335 | bellard | int nb_breakpoints; \
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153 | a316d335 | bellard | int singlestep_enabled; \
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154 | a316d335 | bellard | \ |
155 | 6658ffb8 | pbrook | struct { \
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156 | 6658ffb8 | pbrook | target_ulong vaddr; \ |
157 | d79acba4 | balrog | target_phys_addr_t addend; \ |
158 | 6658ffb8 | pbrook | } watchpoint[MAX_WATCHPOINTS]; \ |
159 | 6658ffb8 | pbrook | int nb_watchpoints; \
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160 | 6658ffb8 | pbrook | int watchpoint_hit; \
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161 | 6658ffb8 | pbrook | \ |
162 | 6a00d601 | bellard | void *next_cpu; /* next CPU sharing TB cache */ \ |
163 | 6a00d601 | bellard | int cpu_index; /* CPU index (informative) */ \ |
164 | a316d335 | bellard | /* user data */ \
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165 | 01ba9816 | ths | void *opaque; \
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166 | 01ba9816 | ths | \ |
167 | 01ba9816 | ths | const char *cpu_model_str; |
168 | a316d335 | bellard | |
169 | ab93bbe2 | bellard | #endif |