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/*
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 * common defines for all CPUs
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 *
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 * Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#ifndef CPU_DEFS_H
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#define CPU_DEFS_H
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#ifndef NEED_CPU_H
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#error cpu.h included from common code
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#endif
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#include "config.h"
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#include <setjmp.h>
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#include <inttypes.h>
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#include "osdep.h"
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#ifndef TARGET_LONG_BITS
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#error TARGET_LONG_BITS must be defined before including this header
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#endif
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#ifndef TARGET_PHYS_ADDR_BITS
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#if TARGET_LONG_BITS >= HOST_LONG_BITS
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#define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS
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#else
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#define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS
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#endif
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#endif
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#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
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/* target_ulong is the type of a virtual address */
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#if TARGET_LONG_SIZE == 4
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typedef int32_t target_long;
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typedef uint32_t target_ulong;
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#define TARGET_FMT_lx "%08x"
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#define TARGET_FMT_ld "%d"
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#define TARGET_FMT_lu "%u"
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#elif TARGET_LONG_SIZE == 8
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typedef int64_t target_long;
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typedef uint64_t target_ulong;
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#define TARGET_FMT_lx "%016" PRIx64
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#define TARGET_FMT_ld "%" PRId64
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#define TARGET_FMT_lu "%" PRIu64
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#else
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#error TARGET_LONG_SIZE undefined
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#endif
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/* target_phys_addr_t is the type of a physical address (its size can
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   be different from 'target_ulong'). We have sizeof(target_phys_addr)
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   = max(sizeof(unsigned long),
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   sizeof(size_of_target_physical_address)) because we must pass a
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   host pointer to memory operations in some cases */
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#if TARGET_PHYS_ADDR_BITS == 32
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typedef uint32_t target_phys_addr_t;
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#define TARGET_FMT_plx "%08x"
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#elif TARGET_PHYS_ADDR_BITS == 64
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typedef uint64_t target_phys_addr_t;
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#define TARGET_FMT_plx "%016" PRIx64
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#else
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#error TARGET_PHYS_ADDR_BITS undefined
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#endif
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/* address in the RAM (different from a physical address) */
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typedef unsigned long ram_addr_t;
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#define HOST_LONG_SIZE (HOST_LONG_BITS / 8)
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#define EXCP_INTERRUPT         0x10000 /* async interruption */
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#define EXCP_HLT        0x10001 /* hlt instruction reached */
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#define EXCP_DEBUG      0x10002 /* cpu stopped after a breakpoint or singlestep */
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#define EXCP_HALTED     0x10003 /* cpu is halted (waiting for external event) */
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#define MAX_BREAKPOINTS 32
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#define MAX_WATCHPOINTS 32
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#define TB_JMP_CACHE_BITS 12
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#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
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/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
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   addresses on the same page.  The top bits are the same.  This allows
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   TLB invalidation to quickly clear a subset of the hash table.  */
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#define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
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#define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
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#define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
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#define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
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#define CPU_TLB_BITS 8
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#define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
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#if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32
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#define CPU_TLB_ENTRY_BITS 4
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#else
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#define CPU_TLB_ENTRY_BITS 5
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#endif
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typedef struct CPUTLBEntry {
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    /* bit 31 to TARGET_PAGE_BITS : virtual address
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       bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io
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                                              zone number
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       bit 3                      : indicates that the entry is invalid
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       bit 2..0                   : zero
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    */
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    target_ulong addr_read;
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    target_ulong addr_write;
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    target_ulong addr_code;
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    /* addend to virtual address to get physical address */
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#if TARGET_PHYS_ADDR_BITS == 64
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    /* on i386 Linux make sure it is aligned */
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    target_phys_addr_t addend __attribute__((aligned(8)));
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#else
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    target_phys_addr_t addend;
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#endif
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    /* padding to get a power of two size */
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    uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - 
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                  (sizeof(target_ulong) * 3 + 
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                   ((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) + 
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                   sizeof(target_phys_addr_t))];
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} CPUTLBEntry;
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#define CPU_COMMON                                                      \
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    struct TranslationBlock *current_tb; /* currently executing TB  */  \
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    /* soft mmu support */                                              \
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    /* in order to avoid passing too many arguments to the memory       \
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       write helpers, we store some rarely used information in the CPU  \
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       context) */                                                      \
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    unsigned long mem_write_pc; /* host pc at which the memory was      \
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                                   written */                           \
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    target_ulong mem_write_vaddr; /* target virtual addr at which the   \
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                                     memory was written */              \
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    /* The meaning of the MMU modes is defined in the target code. */   \
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    CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE];                  \
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    struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];           \
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                                                                        \
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    /* from this point: preserved by CPU reset */                       \
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    /* ice debug support */                                             \
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    target_ulong breakpoints[MAX_BREAKPOINTS];                          \
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    int nb_breakpoints;                                                 \
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    int singlestep_enabled;                                             \
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                                                                        \
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    struct {                                                            \
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        target_ulong vaddr;                                             \
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        target_phys_addr_t addend;                                      \
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    } watchpoint[MAX_WATCHPOINTS];                                      \
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    int nb_watchpoints;                                                 \
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    int watchpoint_hit;                                                 \
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                                                                        \
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    void *next_cpu; /* next CPU sharing TB cache */                     \
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    int cpu_index; /* CPU index (informative) */                        \
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    /* user data */                                                     \
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    void *opaque;                                                       \
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                                                                        \
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    const char *cpu_model_str;
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#endif