Revision d720b93d target-i386/cpu.h

b/target-i386/cpu.h
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#define TARGET_LONG_BITS 32
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/* target supports implicit self modifying code */
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#define TARGET_HAS_SMC
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/* support for self modifying code even if the modified instruction is
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   close to the modifying instruction */
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#define TARGET_HAS_PRECISE_SMC
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#include "cpu-defs.h"
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#if defined(__i386__) && !defined(CONFIG_SOFTMMU)
......
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    int interrupt_request; 
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    int user_mode_only; /* user mode only simulation */
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    /* soft mmu support */
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    uint32_t a20_mask;
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    /* soft mmu support */
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    /* in order to avoid passing too many arguments to the memory
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       write helpers, we store some rarely used information in the CPU
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       context) */
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    unsigned long mem_write_pc; /* host pc at which the memory was
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                                   written */
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    unsigned long mem_write_vaddr; /* target virtual addr at which the
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                                      memory was written */
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    /* 0 = kernel, 1 = user */
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    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
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    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
......
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CPUX86State *cpu_x86_init(void);
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int cpu_x86_exec(CPUX86State *s);
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void cpu_x86_close(CPUX86State *s);
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int cpu_x86_get_pic_interrupt(CPUX86State *s);
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int cpu_get_pic_interrupt(CPUX86State *s);
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/* this function must always be used to load data in the segment
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   cache: it synchronizes the hflags with the segment cache values */

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