Revision d7585251 hw/mips_malta.c
b/hw/mips_malta.c | ||
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521 | 521 |
a3 - RAM size in bytes |
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*/ |
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static void write_bootloader (CPUState *env, unsigned long bios_offset, int64_t kernel_entry) |
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static void write_bootloader (CPUState *env, uint8_t *base, |
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int64_t kernel_entry) |
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{ |
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uint32_t *p; |
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/* Small bootloader */ |
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p = (uint32_t *) (phys_ram_base + bios_offset);
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p = (uint32_t *)base;
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stl_raw(p++, 0x0bf00160); /* j 0x1fc00580 */ |
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stl_raw(p++, 0x00000000); /* nop */ |
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/* YAMON service vector */ |
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stl_raw(phys_ram_base + bios_offset + 0x500, 0xbfc00580); /* start: */
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stl_raw(phys_ram_base + bios_offset + 0x504, 0xbfc0083c); /* print_count: */
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stl_raw(phys_ram_base + bios_offset + 0x520, 0xbfc00580); /* start: */
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stl_raw(phys_ram_base + bios_offset + 0x52c, 0xbfc00800); /* flush_cache: */
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stl_raw(phys_ram_base + bios_offset + 0x534, 0xbfc00808); /* print: */
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stl_raw(phys_ram_base + bios_offset + 0x538, 0xbfc00800); /* reg_cpu_isr: */
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stl_raw(phys_ram_base + bios_offset + 0x53c, 0xbfc00800); /* unred_cpu_isr: */
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stl_raw(phys_ram_base + bios_offset + 0x540, 0xbfc00800); /* reg_ic_isr: */
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stl_raw(phys_ram_base + bios_offset + 0x544, 0xbfc00800); /* unred_ic_isr: */
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stl_raw(phys_ram_base + bios_offset + 0x548, 0xbfc00800); /* reg_esr: */
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stl_raw(phys_ram_base + bios_offset + 0x54c, 0xbfc00800); /* unreg_esr: */
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stl_raw(phys_ram_base + bios_offset + 0x550, 0xbfc00800); /* getchar: */
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stl_raw(phys_ram_base + bios_offset + 0x554, 0xbfc00800); /* syscon_read: */
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stl_raw(base + 0x500, 0xbfc00580); /* start: */
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stl_raw(base + 0x504, 0xbfc0083c); /* print_count: */
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stl_raw(base + 0x520, 0xbfc00580); /* start: */
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stl_raw(base + 0x52c, 0xbfc00800); /* flush_cache: */
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stl_raw(base + 0x534, 0xbfc00808); /* print: */
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stl_raw(base + 0x538, 0xbfc00800); /* reg_cpu_isr: */
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stl_raw(base + 0x53c, 0xbfc00800); /* unred_cpu_isr: */
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stl_raw(base + 0x540, 0xbfc00800); /* reg_ic_isr: */
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stl_raw(base + 0x544, 0xbfc00800); /* unred_ic_isr: */
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stl_raw(base + 0x548, 0xbfc00800); /* reg_esr: */
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stl_raw(base + 0x54c, 0xbfc00800); /* unreg_esr: */
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stl_raw(base + 0x550, 0xbfc00800); /* getchar: */
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stl_raw(base + 0x554, 0xbfc00800); /* syscon_read: */
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547 | 548 |
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548 | 549 |
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549 | 550 |
/* Second part of the bootloader */ |
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p = (uint32_t *) (phys_ram_base + bios_offset + 0x580);
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p = (uint32_t *) (base + 0x580);
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stl_raw(p++, 0x24040002); /* addiu a0, zero, 2 */ |
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stl_raw(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */ |
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stl_raw(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */ |
... | ... | |
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stl_raw(p++, 0x00000000); /* nop */ |
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/* YAMON subroutines */ |
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p = (uint32_t *) (phys_ram_base + bios_offset + 0x800);
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p = (uint32_t *) (base + 0x800);
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stl_raw(p++, 0x03e00008); /* jr ra */ |
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stl_raw(p++, 0x24020000); /* li v0,0 */ |
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/* 808 YAMON print */ |
... | ... | |
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static void prom_set(int index, const char *string, ...) |
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{ |
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char buf[ENVP_ENTRY_SIZE]; |
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target_phys_addr_t p; |
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va_list ap; |
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int32_t *p; |
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int32_t table_addr; |
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char *s; |
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if (index >= ENVP_NB_ENTRIES) |
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return; |
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p = (int32_t *) (phys_ram_base + ENVP_ADDR + VIRT_TO_PHYS_ADDEND); |
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p += index; |
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p = ENVP_ADDR + VIRT_TO_PHYS_ADDEND + index * 4; |
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if (string == NULL) { |
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stl_raw(p, 0);
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stl_phys(p, 0);
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return; |
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} |
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table_addr = ENVP_ADDR + sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE; |
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s = (char *) (phys_ram_base + VIRT_TO_PHYS_ADDEND + table_addr); |
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table_addr = ENVP_ADDR + sizeof(int32_t) * ENVP_NB_ENTRIES |
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+ index * ENVP_ENTRY_SIZE + VIRT_TO_PHYS_ADDEND; |
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stl_raw(p, table_addr); |
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va_start(ap, string); |
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vsnprintf (s, ENVP_ENTRY_SIZE, string, ap);
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vsnprintf(buf, ENVP_ENTRY_SIZE, string, ap);
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va_end(ap); |
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pstrcpy_targphys(table_addr, ENVP_ENTRY_SIZE, buf); |
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} |
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/* Kernel */ |
... | ... | |
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loaderparams.initrd_filename = initrd_filename; |
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kernel_entry = load_kernel(env); |
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env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL)); |
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write_bootloader(env, bios_offset, kernel_entry);
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write_bootloader(env, qemu_get_ram_ptr(bios_offset), kernel_entry);
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} else { |
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index = drive_get_index(IF_PFLASH, 0, fl_idx); |
840 | 840 |
if (index != -1) { |
... | ... | |
868 | 868 |
a neat trick which allows bi-endian firmware. */ |
869 | 869 |
#ifndef TARGET_WORDS_BIGENDIAN |
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{ |
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uint32_t *addr; |
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for (addr = (uint32_t *)(phys_ram_base + bios_offset); |
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addr < (uint32_t *)(phys_ram_base + bios_offset + bios_size); |
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addr++) { |
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*addr = bswap32(*addr); |
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uint32_t *addr = qemu_get_ram_ptr(bios_offset);; |
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uint32_t *end = addr + bios_size; |
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while (addr < end) { |
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bswap32s(addr); |
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} |
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} |
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#endif |
... | ... | |
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/* Board ID = 0x420 (Malta Board with CoreLV) |
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XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should |
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map to the board ID. */ |
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stl_raw(phys_ram_base + bios_offset + 0x10, 0x00000420);
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stl_phys(0x1fc00010LL, 0x00000420);
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885 | 884 |
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886 | 885 |
/* Init internal devices */ |
887 | 886 |
cpu_mips_irq_init_cpu(env); |
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