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/*
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* QEMU i8255x (PRO100) emulation
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*
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* Copyright (c) 2006-2007 Stefan Weil
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*
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* Portions of the code are copies from grub / etherboot eepro100.c
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* and linux e100.c.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* Tested features (i82559):
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* PXE boot (i386) no valid link
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* Linux networking (i386) ok
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*
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* Untested:
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* non-i386 platforms
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* Windows networking
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*
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* References:
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*
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* Intel 8255x 10/100 Mbps Ethernet Controller Family
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* Open Source Software Developer Manual
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*/
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#if defined(TARGET_I386)
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# warning "PXE boot still not working!" |
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#endif
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#include <assert.h> |
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#include <stddef.h> /* offsetof */ |
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#include "hw.h" |
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#include "pci.h" |
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#include "net.h" |
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#include "eeprom93xx.h" |
| 47 |
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/* Common declarations for all PCI devices. */
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#define PCI_DEVICE_ID 0x02 /* 16 bits */ |
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#define PCI_COMMAND 0x04 /* 16 bits */ |
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#define PCI_STATUS 0x06 /* 16 bits */ |
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#define PCI_REVISION_ID 0x08 /* 8 bits */ |
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#define PCI_CONFIG_8(offset, value) \
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(pci_conf[offset] = (value)) |
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#define PCI_CONFIG_16(offset, value) \
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(*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value)) |
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#define PCI_CONFIG_32(offset, value) \
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(*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value)) |
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#define KiB 1024 |
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/* debug EEPRO100 card */
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//~ #define DEBUG_EEPRO100
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#ifdef DEBUG_EEPRO100
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#define logout(fmt, args...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ##args) |
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#else
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#define logout(fmt, args...) ((void)0) |
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#endif
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/* Set flags to 0 to disable debug output. */
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#define MDI 0 |
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#define TRACE(flag, command) ((flag) ? (command) : (void)0) |
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#define missing(text) assert(!"feature is missing in this emulation: " text) |
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#define MAX_ETH_FRAME_SIZE 1514 |
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/* This driver supports several different devices which are declared here. */
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#define i82551 0x82551 |
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#define i82557B 0x82557b |
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#define i82557C 0x82557c |
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#define i82558B 0x82558b |
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#define i82559C 0x82559c |
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#define i82559ER 0x82559e |
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#define i82562 0x82562 |
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#define EEPROM_SIZE 64 |
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#define PCI_MEM_SIZE (4 * KiB) |
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#define PCI_IO_SIZE 64 |
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#define PCI_FLASH_SIZE (128 * KiB) |
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#define BIT(n) (1 << (n)) |
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#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) |
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/* The SCB accepts the following controls for the Tx and Rx units: */
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#define CU_NOP 0x0000 /* No operation. */ |
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#define CU_START 0x0010 /* CU start. */ |
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#define CU_RESUME 0x0020 /* CU resume. */ |
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#define CU_STATSADDR 0x0040 /* Load dump counters address. */ |
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#define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */ |
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#define CU_CMD_BASE 0x0060 /* Load CU base address. */ |
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#define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */ |
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#define CU_SRESUME 0x00a0 /* CU static resume. */ |
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#define RU_NOP 0x0000 |
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#define RX_START 0x0001 |
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#define RX_RESUME 0x0002 |
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#define RX_ABORT 0x0004 |
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#define RX_ADDR_LOAD 0x0006 |
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#define RX_RESUMENR 0x0007 |
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#define INT_MASK 0x0100 |
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#define DRVR_INT 0x0200 /* Driver generated interrupt. */ |
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typedef unsigned char bool; |
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/* Offsets to the various registers.
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All accesses need not be longword aligned. */
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enum speedo_offsets {
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SCBStatus = 0,
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SCBAck = 1,
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SCBCmd = 2, /* Rx/Command Unit command and status. */ |
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SCBIntmask = 3,
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SCBPointer = 4, /* General purpose pointer. */ |
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SCBPort = 8, /* Misc. commands and operands. */ |
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SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */ |
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SCBCtrlMDI = 16, /* MDI interface control. */ |
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SCBEarlyRx = 20, /* Early receive byte count. */ |
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SCBFlow = 24,
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}; |
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/* A speedo3 transmit buffer descriptor with two buffers... */
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typedef struct { |
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uint16_t status; |
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uint16_t command; |
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uint32_t link; /* void * */
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uint32_t tx_desc_addr; /* transmit buffer decsriptor array address. */
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uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
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uint8_t tx_threshold; /* transmit threshold */
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uint8_t tbd_count; /* TBD number */
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//~ /* This constitutes two "TBD" entries: hdr and data */
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//~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
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//~ int32_t tx_buf_size0; /* Length of Tx hdr. */
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//~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
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//~ int32_t tx_buf_size1; /* Length of Tx data. */
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} eepro100_tx_t; |
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/* Receive frame descriptor. */
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typedef struct { |
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int16_t status; |
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uint16_t command; |
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uint32_t link; /* struct RxFD * */
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uint32_t rx_buf_addr; /* void * */
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uint16_t count; |
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uint16_t size; |
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char packet[MAX_ETH_FRAME_SIZE + 4]; |
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} eepro100_rx_t; |
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typedef struct { |
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uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions, |
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tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions, |
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tx_multiple_collisions, tx_total_collisions; |
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uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors, |
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rx_resource_errors, rx_overrun_errors, rx_cdt_errors, |
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rx_short_frame_errors; |
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uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported; |
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uint16_t xmt_tco_frames, rcv_tco_frames; |
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uint32_t complete; |
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} eepro100_stats_t; |
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typedef enum { |
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cu_idle = 0,
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cu_suspended = 1,
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cu_active = 2,
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cu_lpq_active = 2,
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cu_hqp_active = 3
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} cu_state_t; |
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typedef enum { |
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ru_idle = 0,
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ru_suspended = 1,
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ru_no_resources = 2,
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ru_ready = 4
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} ru_state_t; |
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typedef struct { |
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#if 1 |
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uint8_t cmd; |
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uint32_t start; |
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uint32_t stop; |
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uint8_t boundary; |
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uint8_t tsr; |
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uint8_t tpsr; |
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uint16_t tcnt; |
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uint16_t rcnt; |
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uint32_t rsar; |
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uint8_t rsr; |
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uint8_t rxcr; |
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uint8_t isr; |
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uint8_t dcfg; |
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uint8_t imr; |
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uint8_t phys[6]; /* mac address */ |
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uint8_t curpag; |
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uint8_t mult[8]; /* multicast mask array */ |
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int mmio_index;
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PCIDevice *pci_dev; |
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VLANClientState *vc; |
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#endif
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uint8_t scb_stat; /* SCB stat/ack byte */
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uint8_t int_stat; /* PCI interrupt status */
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uint32_t region[3]; /* PCI region addresses */ |
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uint8_t macaddr[6];
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uint32_t statcounter[19];
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uint16_t mdimem[32];
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eeprom_t *eeprom; |
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uint32_t device; /* device variant */
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uint32_t pointer; |
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/* (cu_base + cu_offset) address the next command block in the command block list. */
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uint32_t cu_base; /* CU base address */
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uint32_t cu_offset; /* CU address offset */
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/* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
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uint32_t ru_base; /* RU base address */
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uint32_t ru_offset; /* RU address offset */
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uint32_t statsaddr; /* pointer to eepro100_stats_t */
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eepro100_stats_t statistics; /* statistical counters */
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#if 0
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uint16_t status;
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#endif
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/* Configuration bytes. */
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uint8_t configuration[22];
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/* Data in mem is always in the byte order of the controller (le). */
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uint8_t mem[PCI_MEM_SIZE]; |
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} EEPRO100State; |
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/* Default values for MDI (PHY) registers */
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static const uint16_t eepro100_mdi_default[] = { |
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/* MDI Registers 0 - 6, 7 */
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0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000, |
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/* MDI Registers 8 - 15 */
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0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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/* MDI Registers 16 - 31 */
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0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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}; |
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/* Readonly mask for MDI (PHY) registers */
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static const uint16_t eepro100_mdi_mask[] = { |
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0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000, |
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0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, |
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0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, |
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}; |
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#define POLYNOMIAL 0x04c11db6 |
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/* From FreeBSD */
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/* XXX: optimize */
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static int compute_mcast_idx(const uint8_t * ep) |
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{
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uint32_t crc; |
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int carry, i, j;
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uint8_t b; |
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crc = 0xffffffff;
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for (i = 0; i < 6; i++) { |
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b = *ep++; |
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for (j = 0; j < 8; j++) { |
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carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); |
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crc <<= 1;
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b >>= 1;
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if (carry)
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crc = ((crc ^ POLYNOMIAL) | carry); |
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} |
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} |
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return (crc >> 26); |
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} |
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#if defined(DEBUG_EEPRO100)
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static const char *nic_dump(const uint8_t * buf, unsigned size) |
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{
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static char dump[3 * 16 + 1]; |
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char *p = &dump[0]; |
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if (size > 16) |
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size = 16;
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while (size-- > 0) { |
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p += sprintf(p, " %02x", *buf++);
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} |
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return dump;
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} |
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#endif /* DEBUG_EEPRO100 */ |
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enum scb_stat_ack {
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stat_ack_not_ours = 0x00,
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stat_ack_sw_gen = 0x04,
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stat_ack_rnr = 0x10,
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stat_ack_cu_idle = 0x20,
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stat_ack_frame_rx = 0x40,
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stat_ack_cu_cmd_done = 0x80,
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stat_ack_not_present = 0xFF,
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stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx), |
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stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done), |
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}; |
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static void disable_interrupt(EEPRO100State * s) |
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{
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if (s->int_stat) {
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logout("interrupt disabled\n");
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qemu_irq_lower(s->pci_dev->irq[0]);
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s->int_stat = 0;
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} |
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} |
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static void enable_interrupt(EEPRO100State * s) |
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{
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if (!s->int_stat) {
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logout("interrupt enabled\n");
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qemu_irq_raise(s->pci_dev->irq[0]);
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s->int_stat = 1;
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} |
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} |
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|
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static void eepro100_acknowledge(EEPRO100State * s) |
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{
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s->scb_stat &= ~s->mem[SCBAck]; |
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s->mem[SCBAck] = s->scb_stat; |
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if (s->scb_stat == 0) { |
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disable_interrupt(s); |
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} |
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} |
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|
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static void eepro100_interrupt(EEPRO100State * s, uint8_t stat) |
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{
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uint8_t mask = ~s->mem[SCBIntmask]; |
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s->mem[SCBAck] |= stat; |
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stat = s->scb_stat = s->mem[SCBAck]; |
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stat &= (mask | 0x0f);
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//~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
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if (stat && (mask & 0x01)) { |
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/* SCB mask and SCB Bit M do not disable interrupt. */
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enable_interrupt(s); |
| 348 |
} else if (s->int_stat) { |
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disable_interrupt(s); |
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} |
| 351 |
} |
| 352 |
|
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static void eepro100_cx_interrupt(EEPRO100State * s) |
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{
|
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/* CU completed action command. */
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/* Transmit not ok (82557 only, not in emulation). */
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eepro100_interrupt(s, 0x80);
|
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} |
| 359 |
|
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static void eepro100_cna_interrupt(EEPRO100State * s) |
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{
|
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/* CU left the active state. */
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eepro100_interrupt(s, 0x20);
|
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} |
| 365 |
|
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static void eepro100_fr_interrupt(EEPRO100State * s) |
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{
|
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/* RU received a complete frame. */
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eepro100_interrupt(s, 0x40);
|
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} |
| 371 |
|
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#if 0
|
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static void eepro100_rnr_interrupt(EEPRO100State * s)
|
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{
|
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/* RU is not ready. */
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eepro100_interrupt(s, 0x10);
|
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}
|
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#endif
|
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|
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static void eepro100_mdi_interrupt(EEPRO100State * s) |
| 381 |
{
|
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/* MDI completed read or write cycle. */
|
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eepro100_interrupt(s, 0x08);
|
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} |
| 385 |
|
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static void eepro100_swi_interrupt(EEPRO100State * s) |
| 387 |
{
|
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/* Software has requested an interrupt. */
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eepro100_interrupt(s, 0x04);
|
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} |
| 391 |
|
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#if 0
|
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static void eepro100_fcp_interrupt(EEPRO100State * s)
|
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{
|
| 395 |
/* Flow control pause interrupt (82558 and later). */
|
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eepro100_interrupt(s, 0x01);
|
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}
|
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#endif
|
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|
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static void pci_reset(EEPRO100State * s) |
| 401 |
{
|
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uint32_t device = s->device; |
| 403 |
uint8_t *pci_conf = s->pci_dev->config; |
| 404 |
|
| 405 |
logout("%p\n", s);
|
| 406 |
|
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/* PCI Vendor ID */
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
| 409 |
/* PCI Device ID */
|
| 410 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT); |
| 411 |
/* PCI Command */
|
| 412 |
PCI_CONFIG_16(PCI_COMMAND, 0x0000);
|
| 413 |
/* PCI Status */
|
| 414 |
PCI_CONFIG_16(PCI_STATUS, 0x2800);
|
| 415 |
/* PCI Revision ID */
|
| 416 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
|
| 417 |
/* PCI Class Code */
|
| 418 |
PCI_CONFIG_8(0x09, 0x00); |
| 419 |
pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
| 420 |
/* PCI Cache Line Size */
|
| 421 |
/* check cache line size!!! */
|
| 422 |
//~ PCI_CONFIG_8(0x0c, 0x00);
|
| 423 |
/* PCI Latency Timer */
|
| 424 |
PCI_CONFIG_8(0x0d, 0x20); // latency timer = 32 clocks |
| 425 |
/* PCI Header Type */
|
| 426 |
/* BIST (built-in self test) */
|
| 427 |
#if defined(TARGET_I386)
|
| 428 |
// !!! workaround for buggy bios
|
| 429 |
//~ #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0
|
| 430 |
#endif
|
| 431 |
#if 0
|
| 432 |
/* PCI Base Address Registers */
|
| 433 |
/* CSR Memory Mapped Base Address */
|
| 434 |
PCI_CONFIG_32(PCI_BASE_ADDRESS_0,
|
| 435 |
PCI_ADDRESS_SPACE_MEM | PCI_ADDRESS_SPACE_MEM_PREFETCH);
|
| 436 |
/* CSR I/O Mapped Base Address */
|
| 437 |
PCI_CONFIG_32(PCI_BASE_ADDRESS_1, PCI_ADDRESS_SPACE_IO);
|
| 438 |
#if 0
|
| 439 |
/* Flash Memory Mapped Base Address */
|
| 440 |
PCI_CONFIG_32(PCI_BASE_ADDRESS_2, 0xfffe0000 | PCI_ADDRESS_SPACE_MEM);
|
| 441 |
#endif
|
| 442 |
#endif
|
| 443 |
/* Expansion ROM Base Address (depends on boot disable!!!) */
|
| 444 |
PCI_CONFIG_32(0x30, 0x00000000); |
| 445 |
/* Capability Pointer */
|
| 446 |
PCI_CONFIG_8(0x34, 0xdc); |
| 447 |
/* Interrupt Pin */
|
| 448 |
PCI_CONFIG_8(0x3d, 1); // interrupt pin 0 |
| 449 |
/* Minimum Grant */
|
| 450 |
PCI_CONFIG_8(0x3e, 0x08); |
| 451 |
/* Maximum Latency */
|
| 452 |
PCI_CONFIG_8(0x3f, 0x18); |
| 453 |
/* Power Management Capabilities / Next Item Pointer / Capability ID */
|
| 454 |
PCI_CONFIG_32(0xdc, 0x7e210001); |
| 455 |
|
| 456 |
switch (device) {
|
| 457 |
case i82551:
|
| 458 |
//~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1209);
|
| 459 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
|
| 460 |
break;
|
| 461 |
case i82557B:
|
| 462 |
PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
|
| 463 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
|
| 464 |
break;
|
| 465 |
case i82557C:
|
| 466 |
PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
|
| 467 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
|
| 468 |
break;
|
| 469 |
case i82558B:
|
| 470 |
PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
|
| 471 |
PCI_CONFIG_16(PCI_STATUS, 0x2810);
|
| 472 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
|
| 473 |
break;
|
| 474 |
case i82559C:
|
| 475 |
PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
|
| 476 |
PCI_CONFIG_16(PCI_STATUS, 0x2810);
|
| 477 |
//~ PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
|
| 478 |
break;
|
| 479 |
case i82559ER:
|
| 480 |
//~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1209);
|
| 481 |
PCI_CONFIG_16(PCI_STATUS, 0x2810);
|
| 482 |
PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
|
| 483 |
break;
|
| 484 |
//~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1029);
|
| 485 |
//~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1030); /* 82559 InBusiness 10/100 */
|
| 486 |
default:
|
| 487 |
logout("Device %X is undefined!\n", device);
|
| 488 |
} |
| 489 |
|
| 490 |
if (device == i82557C || device == i82558B || device == i82559C) {
|
| 491 |
logout("Get device id and revision from EEPROM!!!\n");
|
| 492 |
} |
| 493 |
} |
| 494 |
|
| 495 |
static void nic_selective_reset(EEPRO100State * s) |
| 496 |
{
|
| 497 |
size_t i; |
| 498 |
uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom); |
| 499 |
//~ eeprom93xx_reset(s->eeprom);
|
| 500 |
memcpy(eeprom_contents, s->macaddr, 6);
|
| 501 |
eeprom_contents[0xa] = 0x4000; |
| 502 |
uint16_t sum = 0;
|
| 503 |
for (i = 0; i < EEPROM_SIZE - 1; i++) { |
| 504 |
sum += eeprom_contents[i]; |
| 505 |
} |
| 506 |
eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum; |
| 507 |
|
| 508 |
memset(s->mem, 0, sizeof(s->mem)); |
| 509 |
uint32_t val = BIT(21);
|
| 510 |
memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
|
| 511 |
|
| 512 |
assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default)); |
| 513 |
memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem)); |
| 514 |
} |
| 515 |
|
| 516 |
static void nic_reset(void *opaque) |
| 517 |
{
|
| 518 |
EEPRO100State *s = (EEPRO100State *) opaque; |
| 519 |
logout("%p\n", s);
|
| 520 |
static int first; |
| 521 |
if (!first) {
|
| 522 |
first = 1;
|
| 523 |
} |
| 524 |
nic_selective_reset(s); |
| 525 |
} |
| 526 |
|
| 527 |
#if defined(DEBUG_EEPRO100)
|
| 528 |
static const char *reg[PCI_IO_SIZE / 4] = { |
| 529 |
"Command/Status",
|
| 530 |
"General Pointer",
|
| 531 |
"Port",
|
| 532 |
"EEPROM/Flash Control",
|
| 533 |
"MDI Control",
|
| 534 |
"Receive DMA Byte Count",
|
| 535 |
"Flow control register",
|
| 536 |
"General Status/Control"
|
| 537 |
}; |
| 538 |
|
| 539 |
static char *regname(uint32_t addr) |
| 540 |
{
|
| 541 |
static char buf[16]; |
| 542 |
if (addr < PCI_IO_SIZE) {
|
| 543 |
const char *r = reg[addr / 4]; |
| 544 |
if (r != 0) { |
| 545 |
sprintf(buf, "%s+%u", r, addr % 4); |
| 546 |
} else {
|
| 547 |
sprintf(buf, "0x%02x", addr);
|
| 548 |
} |
| 549 |
} else {
|
| 550 |
sprintf(buf, "??? 0x%08x", addr);
|
| 551 |
} |
| 552 |
return buf;
|
| 553 |
} |
| 554 |
#endif /* DEBUG_EEPRO100 */ |
| 555 |
|
| 556 |
#if 0
|
| 557 |
static uint16_t eepro100_read_status(EEPRO100State * s)
|
| 558 |
{
|
| 559 |
uint16_t val = s->status;
|
| 560 |
logout("val=0x%04x\n", val);
|
| 561 |
return val;
|
| 562 |
}
|
| 563 |
|
| 564 |
static void eepro100_write_status(EEPRO100State * s, uint16_t val)
|
| 565 |
{
|
| 566 |
logout("val=0x%04x\n", val);
|
| 567 |
s->status = val;
|
| 568 |
}
|
| 569 |
#endif
|
| 570 |
|
| 571 |
/*****************************************************************************
|
| 572 |
*
|
| 573 |
* Command emulation.
|
| 574 |
*
|
| 575 |
****************************************************************************/
|
| 576 |
|
| 577 |
#if 0
|
| 578 |
static uint16_t eepro100_read_command(EEPRO100State * s)
|
| 579 |
{
|
| 580 |
uint16_t val = 0xffff;
|
| 581 |
//~ logout("val=0x%04x\n", val);
|
| 582 |
return val;
|
| 583 |
}
|
| 584 |
#endif
|
| 585 |
|
| 586 |
/* Commands that can be put in a command list entry. */
|
| 587 |
enum commands {
|
| 588 |
CmdNOp = 0,
|
| 589 |
CmdIASetup = 1,
|
| 590 |
CmdConfigure = 2,
|
| 591 |
CmdMulticastList = 3,
|
| 592 |
CmdTx = 4,
|
| 593 |
CmdTDR = 5, /* load microcode */ |
| 594 |
CmdDump = 6,
|
| 595 |
CmdDiagnose = 7,
|
| 596 |
|
| 597 |
/* And some extra flags: */
|
| 598 |
CmdSuspend = 0x4000, /* Suspend after completion. */ |
| 599 |
CmdIntr = 0x2000, /* Interrupt after completion. */ |
| 600 |
CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */ |
| 601 |
}; |
| 602 |
|
| 603 |
static cu_state_t get_cu_state(EEPRO100State * s)
|
| 604 |
{
|
| 605 |
return ((s->mem[SCBStatus] >> 6) & 0x03); |
| 606 |
} |
| 607 |
|
| 608 |
static void set_cu_state(EEPRO100State * s, cu_state_t state) |
| 609 |
{
|
| 610 |
s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6); |
| 611 |
} |
| 612 |
|
| 613 |
static ru_state_t get_ru_state(EEPRO100State * s)
|
| 614 |
{
|
| 615 |
return ((s->mem[SCBStatus] >> 2) & 0x0f); |
| 616 |
} |
| 617 |
|
| 618 |
static void set_ru_state(EEPRO100State * s, ru_state_t state) |
| 619 |
{
|
| 620 |
s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2); |
| 621 |
} |
| 622 |
|
| 623 |
static void dump_statistics(EEPRO100State * s) |
| 624 |
{
|
| 625 |
/* Dump statistical data. Most data is never changed by the emulation
|
| 626 |
* and always 0, so we first just copy the whole block and then those
|
| 627 |
* values which really matter.
|
| 628 |
* Number of data should check configuration!!!
|
| 629 |
*/
|
| 630 |
cpu_physical_memory_write(s->statsaddr, (uint8_t *) & s->statistics, 64);
|
| 631 |
stl_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
|
| 632 |
stl_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
|
| 633 |
stl_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
|
| 634 |
stl_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
|
| 635 |
//~ stw_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
|
| 636 |
//~ stw_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
|
| 637 |
//~ missing("CU dump statistical counters");
|
| 638 |
} |
| 639 |
|
| 640 |
static void eepro100_cu_command(EEPRO100State * s, uint8_t val) |
| 641 |
{
|
| 642 |
eepro100_tx_t tx; |
| 643 |
uint32_t cb_address; |
| 644 |
switch (val) {
|
| 645 |
case CU_NOP:
|
| 646 |
/* No operation. */
|
| 647 |
break;
|
| 648 |
case CU_START:
|
| 649 |
if (get_cu_state(s) != cu_idle) {
|
| 650 |
/* Intel documentation says that CU must be idle for the CU
|
| 651 |
* start command. Intel driver for Linux also starts the CU
|
| 652 |
* from suspended state. */
|
| 653 |
logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle);
|
| 654 |
//~ assert(!"wrong CU state");
|
| 655 |
} |
| 656 |
set_cu_state(s, cu_active); |
| 657 |
s->cu_offset = s->pointer; |
| 658 |
next_command:
|
| 659 |
cb_address = s->cu_base + s->cu_offset; |
| 660 |
cpu_physical_memory_read(cb_address, (uint8_t *) & tx, sizeof(tx));
|
| 661 |
uint16_t status = le16_to_cpu(tx.status); |
| 662 |
uint16_t command = le16_to_cpu(tx.command); |
| 663 |
logout |
| 664 |
("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
|
| 665 |
val, status, command, tx.link); |
| 666 |
bool bit_el = ((command & 0x8000) != 0); |
| 667 |
bool bit_s = ((command & 0x4000) != 0); |
| 668 |
bool bit_i = ((command & 0x2000) != 0); |
| 669 |
bool bit_nc = ((command & 0x0010) != 0); |
| 670 |
//~ bool bit_sf = ((command & 0x0008) != 0);
|
| 671 |
uint16_t cmd = command & 0x0007;
|
| 672 |
s->cu_offset = le32_to_cpu(tx.link); |
| 673 |
switch (cmd) {
|
| 674 |
case CmdNOp:
|
| 675 |
/* Do nothing. */
|
| 676 |
break;
|
| 677 |
case CmdIASetup:
|
| 678 |
cpu_physical_memory_read(cb_address + 8, &s->macaddr[0], 6); |
| 679 |
logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6)); |
| 680 |
break;
|
| 681 |
case CmdConfigure:
|
| 682 |
cpu_physical_memory_read(cb_address + 8, &s->configuration[0], |
| 683 |
sizeof(s->configuration));
|
| 684 |
logout("configuration: %s\n", nic_dump(&s->configuration[0], 16)); |
| 685 |
break;
|
| 686 |
case CmdMulticastList:
|
| 687 |
//~ missing("multicast list");
|
| 688 |
break;
|
| 689 |
case CmdTx:
|
| 690 |
(void)0; |
| 691 |
uint32_t tbd_array = le32_to_cpu(tx.tx_desc_addr); |
| 692 |
uint16_t tcb_bytes = (le16_to_cpu(tx.tcb_bytes) & 0x3fff);
|
| 693 |
logout |
| 694 |
("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
|
| 695 |
tbd_array, tcb_bytes, tx.tbd_count); |
| 696 |
assert(!bit_nc); |
| 697 |
//~ assert(!bit_sf);
|
| 698 |
assert(tcb_bytes <= 2600);
|
| 699 |
/* Next assertion fails for local configuration. */
|
| 700 |
//~ assert((tcb_bytes > 0) || (tbd_array != 0xffffffff));
|
| 701 |
if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) { |
| 702 |
logout |
| 703 |
("illegal values of TBD array address and TCB byte count!\n");
|
| 704 |
} |
| 705 |
uint8_t buf[MAX_ETH_FRAME_SIZE + 4];
|
| 706 |
uint16_t size = 0;
|
| 707 |
uint32_t tbd_address = cb_address + 0x10;
|
| 708 |
assert(tcb_bytes <= sizeof(buf));
|
| 709 |
while (size < tcb_bytes) {
|
| 710 |
uint32_t tx_buffer_address = ldl_phys(tbd_address); |
| 711 |
uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
|
| 712 |
//~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
|
| 713 |
tbd_address += 8;
|
| 714 |
logout |
| 715 |
("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
|
| 716 |
tx_buffer_address, tx_buffer_size); |
| 717 |
cpu_physical_memory_read(tx_buffer_address, &buf[size], |
| 718 |
tx_buffer_size); |
| 719 |
size += tx_buffer_size; |
| 720 |
} |
| 721 |
if (tbd_array == 0xffffffff) { |
| 722 |
/* Simplified mode. Was already handled by code above. */
|
| 723 |
} else {
|
| 724 |
/* Flexible mode. */
|
| 725 |
uint8_t tbd_count = 0;
|
| 726 |
if (!(s->configuration[6] & BIT(4))) { |
| 727 |
/* Extended TCB. */
|
| 728 |
assert(tcb_bytes == 0);
|
| 729 |
for (; tbd_count < 2; tbd_count++) { |
| 730 |
uint32_t tx_buffer_address = ldl_phys(tbd_address); |
| 731 |
uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
|
| 732 |
uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
|
| 733 |
tbd_address += 8;
|
| 734 |
logout |
| 735 |
("TBD (extended mode): buffer address 0x%08x, size 0x%04x\n",
|
| 736 |
tx_buffer_address, tx_buffer_size); |
| 737 |
cpu_physical_memory_read(tx_buffer_address, &buf[size], |
| 738 |
tx_buffer_size); |
| 739 |
size += tx_buffer_size; |
| 740 |
if (tx_buffer_el & 1) { |
| 741 |
break;
|
| 742 |
} |
| 743 |
} |
| 744 |
} |
| 745 |
tbd_address = tbd_array; |
| 746 |
for (; tbd_count < tx.tbd_count; tbd_count++) {
|
| 747 |
uint32_t tx_buffer_address = ldl_phys(tbd_address); |
| 748 |
uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
|
| 749 |
uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
|
| 750 |
tbd_address += 8;
|
| 751 |
logout |
| 752 |
("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
|
| 753 |
tx_buffer_address, tx_buffer_size); |
| 754 |
cpu_physical_memory_read(tx_buffer_address, &buf[size], |
| 755 |
tx_buffer_size); |
| 756 |
size += tx_buffer_size; |
| 757 |
if (tx_buffer_el & 1) { |
| 758 |
break;
|
| 759 |
} |
| 760 |
} |
| 761 |
} |
| 762 |
qemu_send_packet(s->vc, buf, size); |
| 763 |
s->statistics.tx_good_frames++; |
| 764 |
/* Transmit with bad status would raise an CX/TNO interrupt.
|
| 765 |
* (82557 only). Emulation never has bad status. */
|
| 766 |
//~ eepro100_cx_interrupt(s);
|
| 767 |
break;
|
| 768 |
case CmdTDR:
|
| 769 |
logout("load microcode\n");
|
| 770 |
/* Starting with offset 8, the command contains
|
| 771 |
* 64 dwords microcode which we just ignore here. */
|
| 772 |
break;
|
| 773 |
default:
|
| 774 |
missing("undefined command");
|
| 775 |
} |
| 776 |
/* Write new status (success). */
|
| 777 |
stw_phys(cb_address, status | 0x8000 | 0x2000); |
| 778 |
if (bit_i) {
|
| 779 |
/* CU completed action. */
|
| 780 |
eepro100_cx_interrupt(s); |
| 781 |
} |
| 782 |
if (bit_el) {
|
| 783 |
/* CU becomes idle. */
|
| 784 |
set_cu_state(s, cu_idle); |
| 785 |
eepro100_cna_interrupt(s); |
| 786 |
} else if (bit_s) { |
| 787 |
/* CU becomes suspended. */
|
| 788 |
set_cu_state(s, cu_suspended); |
| 789 |
eepro100_cna_interrupt(s); |
| 790 |
} else {
|
| 791 |
/* More entries in list. */
|
| 792 |
logout("CU list with at least one more entry\n");
|
| 793 |
goto next_command;
|
| 794 |
} |
| 795 |
logout("CU list empty\n");
|
| 796 |
/* List is empty. Now CU is idle or suspended. */
|
| 797 |
break;
|
| 798 |
case CU_RESUME:
|
| 799 |
if (get_cu_state(s) != cu_suspended) {
|
| 800 |
logout("bad CU resume from CU state %u\n", get_cu_state(s));
|
| 801 |
/* Workaround for bad Linux eepro100 driver which resumes
|
| 802 |
* from idle state. */
|
| 803 |
//~ missing("cu resume");
|
| 804 |
set_cu_state(s, cu_suspended); |
| 805 |
} |
| 806 |
if (get_cu_state(s) == cu_suspended) {
|
| 807 |
logout("CU resuming\n");
|
| 808 |
set_cu_state(s, cu_active); |
| 809 |
goto next_command;
|
| 810 |
} |
| 811 |
break;
|
| 812 |
case CU_STATSADDR:
|
| 813 |
/* Load dump counters address. */
|
| 814 |
s->statsaddr = s->pointer; |
| 815 |
logout("val=0x%02x (status address)\n", val);
|
| 816 |
break;
|
| 817 |
case CU_SHOWSTATS:
|
| 818 |
/* Dump statistical counters. */
|
| 819 |
dump_statistics(s); |
| 820 |
break;
|
| 821 |
case CU_CMD_BASE:
|
| 822 |
/* Load CU base. */
|
| 823 |
logout("val=0x%02x (CU base address)\n", val);
|
| 824 |
s->cu_base = s->pointer; |
| 825 |
break;
|
| 826 |
case CU_DUMPSTATS:
|
| 827 |
/* Dump and reset statistical counters. */
|
| 828 |
dump_statistics(s); |
| 829 |
memset(&s->statistics, 0, sizeof(s->statistics)); |
| 830 |
break;
|
| 831 |
case CU_SRESUME:
|
| 832 |
/* CU static resume. */
|
| 833 |
missing("CU static resume");
|
| 834 |
break;
|
| 835 |
default:
|
| 836 |
missing("Undefined CU command");
|
| 837 |
} |
| 838 |
} |
| 839 |
|
| 840 |
static void eepro100_ru_command(EEPRO100State * s, uint8_t val) |
| 841 |
{
|
| 842 |
switch (val) {
|
| 843 |
case RU_NOP:
|
| 844 |
/* No operation. */
|
| 845 |
break;
|
| 846 |
case RX_START:
|
| 847 |
/* RU start. */
|
| 848 |
if (get_ru_state(s) != ru_idle) {
|
| 849 |
logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
|
| 850 |
//~ assert(!"wrong RU state");
|
| 851 |
} |
| 852 |
set_ru_state(s, ru_ready); |
| 853 |
s->ru_offset = s->pointer; |
| 854 |
logout("val=0x%02x (rx start)\n", val);
|
| 855 |
break;
|
| 856 |
case RX_RESUME:
|
| 857 |
/* Restart RU. */
|
| 858 |
if (get_ru_state(s) != ru_suspended) {
|
| 859 |
logout("RU state is %u, should be %u\n", get_ru_state(s),
|
| 860 |
ru_suspended); |
| 861 |
//~ assert(!"wrong RU state");
|
| 862 |
} |
| 863 |
set_ru_state(s, ru_ready); |
| 864 |
break;
|
| 865 |
case RX_ADDR_LOAD:
|
| 866 |
/* Load RU base. */
|
| 867 |
logout("val=0x%02x (RU base address)\n", val);
|
| 868 |
s->ru_base = s->pointer; |
| 869 |
break;
|
| 870 |
default:
|
| 871 |
logout("val=0x%02x (undefined RU command)\n", val);
|
| 872 |
missing("Undefined SU command");
|
| 873 |
} |
| 874 |
} |
| 875 |
|
| 876 |
static void eepro100_write_command(EEPRO100State * s, uint8_t val) |
| 877 |
{
|
| 878 |
eepro100_ru_command(s, val & 0x0f);
|
| 879 |
eepro100_cu_command(s, val & 0xf0);
|
| 880 |
if ((val) == 0) { |
| 881 |
logout("val=0x%02x\n", val);
|
| 882 |
} |
| 883 |
/* Clear command byte after command was accepted. */
|
| 884 |
s->mem[SCBCmd] = 0;
|
| 885 |
} |
| 886 |
|
| 887 |
/*****************************************************************************
|
| 888 |
*
|
| 889 |
* EEPROM emulation.
|
| 890 |
*
|
| 891 |
****************************************************************************/
|
| 892 |
|
| 893 |
#define EEPROM_CS 0x02 |
| 894 |
#define EEPROM_SK 0x01 |
| 895 |
#define EEPROM_DI 0x04 |
| 896 |
#define EEPROM_DO 0x08 |
| 897 |
|
| 898 |
static uint16_t eepro100_read_eeprom(EEPRO100State * s)
|
| 899 |
{
|
| 900 |
uint16_t val; |
| 901 |
memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
|
| 902 |
if (eeprom93xx_read(s->eeprom)) {
|
| 903 |
val |= EEPROM_DO; |
| 904 |
} else {
|
| 905 |
val &= ~EEPROM_DO; |
| 906 |
} |
| 907 |
return val;
|
| 908 |
} |
| 909 |
|
| 910 |
static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val) |
| 911 |
{
|
| 912 |
logout("write val=0x%02x\n", val);
|
| 913 |
|
| 914 |
/* mask unwriteable bits */
|
| 915 |
//~ val = SET_MASKED(val, 0x31, eeprom->value);
|
| 916 |
|
| 917 |
int eecs = ((val & EEPROM_CS) != 0); |
| 918 |
int eesk = ((val & EEPROM_SK) != 0); |
| 919 |
int eedi = ((val & EEPROM_DI) != 0); |
| 920 |
eeprom93xx_write(eeprom, eecs, eesk, eedi); |
| 921 |
} |
| 922 |
|
| 923 |
static void eepro100_write_pointer(EEPRO100State * s, uint32_t val) |
| 924 |
{
|
| 925 |
s->pointer = le32_to_cpu(val); |
| 926 |
logout("val=0x%08x\n", val);
|
| 927 |
} |
| 928 |
|
| 929 |
/*****************************************************************************
|
| 930 |
*
|
| 931 |
* MDI emulation.
|
| 932 |
*
|
| 933 |
****************************************************************************/
|
| 934 |
|
| 935 |
#if defined(DEBUG_EEPRO100)
|
| 936 |
static const char *mdi_op_name[] = { |
| 937 |
"opcode 0",
|
| 938 |
"write",
|
| 939 |
"read",
|
| 940 |
"opcode 3"
|
| 941 |
}; |
| 942 |
|
| 943 |
static const char *mdi_reg_name[] = { |
| 944 |
"Control",
|
| 945 |
"Status",
|
| 946 |
"PHY Identification (Word 1)",
|
| 947 |
"PHY Identification (Word 2)",
|
| 948 |
"Auto-Negotiation Advertisement",
|
| 949 |
"Auto-Negotiation Link Partner Ability",
|
| 950 |
"Auto-Negotiation Expansion"
|
| 951 |
}; |
| 952 |
#endif /* DEBUG_EEPRO100 */ |
| 953 |
|
| 954 |
static uint32_t eepro100_read_mdi(EEPRO100State * s)
|
| 955 |
{
|
| 956 |
uint32_t val; |
| 957 |
memcpy(&val, &s->mem[0x10], sizeof(val)); |
| 958 |
|
| 959 |
#ifdef DEBUG_EEPRO100
|
| 960 |
uint8_t raiseint = (val & BIT(29)) >> 29; |
| 961 |
uint8_t opcode = (val & BITS(27, 26)) >> 26; |
| 962 |
uint8_t phy = (val & BITS(25, 21)) >> 21; |
| 963 |
uint8_t reg = (val & BITS(20, 16)) >> 16; |
| 964 |
uint16_t data = (val & BITS(15, 0)); |
| 965 |
#endif
|
| 966 |
/* Emulation takes no time to finish MDI transaction. */
|
| 967 |
val |= BIT(28);
|
| 968 |
TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
|
| 969 |
val, raiseint, mdi_op_name[opcode], phy, |
| 970 |
mdi_reg_name[reg], data)); |
| 971 |
return val;
|
| 972 |
} |
| 973 |
|
| 974 |
//~ #define BITS(val, upper, lower) (val & ???)
|
| 975 |
static void eepro100_write_mdi(EEPRO100State * s, uint32_t val) |
| 976 |
{
|
| 977 |
uint8_t raiseint = (val & BIT(29)) >> 29; |
| 978 |
uint8_t opcode = (val & BITS(27, 26)) >> 26; |
| 979 |
uint8_t phy = (val & BITS(25, 21)) >> 21; |
| 980 |
uint8_t reg = (val & BITS(20, 16)) >> 16; |
| 981 |
uint16_t data = (val & BITS(15, 0)); |
| 982 |
if (phy != 1) { |
| 983 |
/* Unsupported PHY address. */
|
| 984 |
//~ logout("phy must be 1 but is %u\n", phy);
|
| 985 |
data = 0;
|
| 986 |
} else if (opcode != 1 && opcode != 2) { |
| 987 |
/* Unsupported opcode. */
|
| 988 |
logout("opcode must be 1 or 2 but is %u\n", opcode);
|
| 989 |
data = 0;
|
| 990 |
} else if (reg > 6) { |
| 991 |
/* Unsupported register. */
|
| 992 |
logout("register must be 0...6 but is %u\n", reg);
|
| 993 |
data = 0;
|
| 994 |
} else {
|
| 995 |
TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
|
| 996 |
val, raiseint, mdi_op_name[opcode], phy, |
| 997 |
mdi_reg_name[reg], data)); |
| 998 |
if (opcode == 1) { |
| 999 |
/* MDI write */
|
| 1000 |
switch (reg) {
|
| 1001 |
case 0: /* Control Register */ |
| 1002 |
if (data & 0x8000) { |
| 1003 |
/* Reset status and control registers to default. */
|
| 1004 |
s->mdimem[0] = eepro100_mdi_default[0]; |
| 1005 |
s->mdimem[1] = eepro100_mdi_default[1]; |
| 1006 |
data = s->mdimem[reg]; |
| 1007 |
} else {
|
| 1008 |
/* Restart Auto Configuration = Normal Operation */
|
| 1009 |
data &= ~0x0200;
|
| 1010 |
} |
| 1011 |
break;
|
| 1012 |
case 1: /* Status Register */ |
| 1013 |
missing("not writable");
|
| 1014 |
data = s->mdimem[reg]; |
| 1015 |
break;
|
| 1016 |
case 2: /* PHY Identification Register (Word 1) */ |
| 1017 |
case 3: /* PHY Identification Register (Word 2) */ |
| 1018 |
missing("not implemented");
|
| 1019 |
break;
|
| 1020 |
case 4: /* Auto-Negotiation Advertisement Register */ |
| 1021 |
case 5: /* Auto-Negotiation Link Partner Ability Register */ |
| 1022 |
break;
|
| 1023 |
case 6: /* Auto-Negotiation Expansion Register */ |
| 1024 |
default:
|
| 1025 |
missing("not implemented");
|
| 1026 |
} |
| 1027 |
s->mdimem[reg] = data; |
| 1028 |
} else if (opcode == 2) { |
| 1029 |
/* MDI read */
|
| 1030 |
switch (reg) {
|
| 1031 |
case 0: /* Control Register */ |
| 1032 |
if (data & 0x8000) { |
| 1033 |
/* Reset status and control registers to default. */
|
| 1034 |
s->mdimem[0] = eepro100_mdi_default[0]; |
| 1035 |
s->mdimem[1] = eepro100_mdi_default[1]; |
| 1036 |
} |
| 1037 |
break;
|
| 1038 |
case 1: /* Status Register */ |
| 1039 |
s->mdimem[reg] |= 0x0020;
|
| 1040 |
break;
|
| 1041 |
case 2: /* PHY Identification Register (Word 1) */ |
| 1042 |
case 3: /* PHY Identification Register (Word 2) */ |
| 1043 |
case 4: /* Auto-Negotiation Advertisement Register */ |
| 1044 |
break;
|
| 1045 |
case 5: /* Auto-Negotiation Link Partner Ability Register */ |
| 1046 |
s->mdimem[reg] = 0x41fe;
|
| 1047 |
break;
|
| 1048 |
case 6: /* Auto-Negotiation Expansion Register */ |
| 1049 |
s->mdimem[reg] = 0x0001;
|
| 1050 |
break;
|
| 1051 |
} |
| 1052 |
data = s->mdimem[reg]; |
| 1053 |
} |
| 1054 |
/* Emulation takes no time to finish MDI transaction.
|
| 1055 |
* Set MDI bit in SCB status register. */
|
| 1056 |
s->mem[SCBAck] |= 0x08;
|
| 1057 |
val |= BIT(28);
|
| 1058 |
if (raiseint) {
|
| 1059 |
eepro100_mdi_interrupt(s); |
| 1060 |
} |
| 1061 |
} |
| 1062 |
val = (val & 0xffff0000) + data;
|
| 1063 |
memcpy(&s->mem[0x10], &val, sizeof(val)); |
| 1064 |
} |
| 1065 |
|
| 1066 |
/*****************************************************************************
|
| 1067 |
*
|
| 1068 |
* Port emulation.
|
| 1069 |
*
|
| 1070 |
****************************************************************************/
|
| 1071 |
|
| 1072 |
#define PORT_SOFTWARE_RESET 0 |
| 1073 |
#define PORT_SELFTEST 1 |
| 1074 |
#define PORT_SELECTIVE_RESET 2 |
| 1075 |
#define PORT_DUMP 3 |
| 1076 |
#define PORT_SELECTION_MASK 3 |
| 1077 |
|
| 1078 |
typedef struct { |
| 1079 |
uint32_t st_sign; /* Self Test Signature */
|
| 1080 |
uint32_t st_result; /* Self Test Results */
|
| 1081 |
} eepro100_selftest_t; |
| 1082 |
|
| 1083 |
static uint32_t eepro100_read_port(EEPRO100State * s)
|
| 1084 |
{
|
| 1085 |
return 0; |
| 1086 |
} |
| 1087 |
|
| 1088 |
static void eepro100_write_port(EEPRO100State * s, uint32_t val) |
| 1089 |
{
|
| 1090 |
val = le32_to_cpu(val); |
| 1091 |
uint32_t address = (val & ~PORT_SELECTION_MASK); |
| 1092 |
uint8_t selection = (val & PORT_SELECTION_MASK); |
| 1093 |
switch (selection) {
|
| 1094 |
case PORT_SOFTWARE_RESET:
|
| 1095 |
nic_reset(s); |
| 1096 |
break;
|
| 1097 |
case PORT_SELFTEST:
|
| 1098 |
logout("selftest address=0x%08x\n", address);
|
| 1099 |
eepro100_selftest_t data; |
| 1100 |
cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
|
| 1101 |
data.st_sign = 0xffffffff;
|
| 1102 |
data.st_result = 0;
|
| 1103 |
cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
|
| 1104 |
break;
|
| 1105 |
case PORT_SELECTIVE_RESET:
|
| 1106 |
logout("selective reset, selftest address=0x%08x\n", address);
|
| 1107 |
nic_selective_reset(s); |
| 1108 |
break;
|
| 1109 |
default:
|
| 1110 |
logout("val=0x%08x\n", val);
|
| 1111 |
missing("unknown port selection");
|
| 1112 |
} |
| 1113 |
} |
| 1114 |
|
| 1115 |
/*****************************************************************************
|
| 1116 |
*
|
| 1117 |
* General hardware emulation.
|
| 1118 |
*
|
| 1119 |
****************************************************************************/
|
| 1120 |
|
| 1121 |
static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
|
| 1122 |
{
|
| 1123 |
uint8_t val; |
| 1124 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
| 1125 |
memcpy(&val, &s->mem[addr], sizeof(val));
|
| 1126 |
} |
| 1127 |
|
| 1128 |
switch (addr) {
|
| 1129 |
case SCBStatus:
|
| 1130 |
//~ val = eepro100_read_status(s);
|
| 1131 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1132 |
break;
|
| 1133 |
case SCBAck:
|
| 1134 |
//~ val = eepro100_read_status(s);
|
| 1135 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1136 |
break;
|
| 1137 |
case SCBCmd:
|
| 1138 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1139 |
//~ val = eepro100_read_command(s);
|
| 1140 |
break;
|
| 1141 |
case SCBIntmask:
|
| 1142 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1143 |
break;
|
| 1144 |
case SCBPort + 3: |
| 1145 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1146 |
break;
|
| 1147 |
case SCBeeprom:
|
| 1148 |
val = eepro100_read_eeprom(s); |
| 1149 |
break;
|
| 1150 |
case 0x1b: /* PMDR (power management driver register) */ |
| 1151 |
val = 0;
|
| 1152 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1153 |
break;
|
| 1154 |
case 0x1d: /* general status register */ |
| 1155 |
/* 100 Mbps full duplex, valid link */
|
| 1156 |
val = 0x07;
|
| 1157 |
logout("addr=General Status val=%02x\n", val);
|
| 1158 |
break;
|
| 1159 |
default:
|
| 1160 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1161 |
missing("unknown byte read");
|
| 1162 |
} |
| 1163 |
return val;
|
| 1164 |
} |
| 1165 |
|
| 1166 |
static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
|
| 1167 |
{
|
| 1168 |
uint16_t val; |
| 1169 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
| 1170 |
memcpy(&val, &s->mem[addr], sizeof(val));
|
| 1171 |
} |
| 1172 |
|
| 1173 |
logout("addr=%s val=0x%04x\n", regname(addr), val);
|
| 1174 |
|
| 1175 |
switch (addr) {
|
| 1176 |
case SCBStatus:
|
| 1177 |
//~ val = eepro100_read_status(s);
|
| 1178 |
break;
|
| 1179 |
case SCBeeprom:
|
| 1180 |
val = eepro100_read_eeprom(s); |
| 1181 |
break;
|
| 1182 |
default:
|
| 1183 |
logout("addr=%s val=0x%04x\n", regname(addr), val);
|
| 1184 |
missing("unknown word read");
|
| 1185 |
} |
| 1186 |
return val;
|
| 1187 |
} |
| 1188 |
|
| 1189 |
static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
|
| 1190 |
{
|
| 1191 |
uint32_t val; |
| 1192 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
| 1193 |
memcpy(&val, &s->mem[addr], sizeof(val));
|
| 1194 |
} |
| 1195 |
|
| 1196 |
switch (addr) {
|
| 1197 |
case SCBStatus:
|
| 1198 |
//~ val = eepro100_read_status(s);
|
| 1199 |
logout("addr=%s val=0x%08x\n", regname(addr), val);
|
| 1200 |
break;
|
| 1201 |
case SCBPointer:
|
| 1202 |
//~ val = eepro100_read_pointer(s);
|
| 1203 |
logout("addr=%s val=0x%08x\n", regname(addr), val);
|
| 1204 |
break;
|
| 1205 |
case SCBPort:
|
| 1206 |
val = eepro100_read_port(s); |
| 1207 |
logout("addr=%s val=0x%08x\n", regname(addr), val);
|
| 1208 |
break;
|
| 1209 |
case SCBCtrlMDI:
|
| 1210 |
val = eepro100_read_mdi(s); |
| 1211 |
break;
|
| 1212 |
default:
|
| 1213 |
logout("addr=%s val=0x%08x\n", regname(addr), val);
|
| 1214 |
missing("unknown longword read");
|
| 1215 |
} |
| 1216 |
return val;
|
| 1217 |
} |
| 1218 |
|
| 1219 |
static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val) |
| 1220 |
{
|
| 1221 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
| 1222 |
memcpy(&s->mem[addr], &val, sizeof(val));
|
| 1223 |
} |
| 1224 |
|
| 1225 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1226 |
|
| 1227 |
switch (addr) {
|
| 1228 |
case SCBStatus:
|
| 1229 |
//~ eepro100_write_status(s, val);
|
| 1230 |
break;
|
| 1231 |
case SCBAck:
|
| 1232 |
eepro100_acknowledge(s); |
| 1233 |
break;
|
| 1234 |
case SCBCmd:
|
| 1235 |
eepro100_write_command(s, val); |
| 1236 |
break;
|
| 1237 |
case SCBIntmask:
|
| 1238 |
if (val & BIT(1)) { |
| 1239 |
eepro100_swi_interrupt(s); |
| 1240 |
} |
| 1241 |
eepro100_interrupt(s, 0);
|
| 1242 |
break;
|
| 1243 |
case SCBPort + 3: |
| 1244 |
case SCBFlow:
|
| 1245 |
case SCBFlow + 1: |
| 1246 |
case SCBFlow + 2: |
| 1247 |
case SCBFlow + 3: |
| 1248 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1249 |
break;
|
| 1250 |
case SCBeeprom:
|
| 1251 |
eepro100_write_eeprom(s->eeprom, val); |
| 1252 |
break;
|
| 1253 |
default:
|
| 1254 |
logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1255 |
missing("unknown byte write");
|
| 1256 |
} |
| 1257 |
} |
| 1258 |
|
| 1259 |
static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val) |
| 1260 |
{
|
| 1261 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
| 1262 |
memcpy(&s->mem[addr], &val, sizeof(val));
|
| 1263 |
} |
| 1264 |
|
| 1265 |
logout("addr=%s val=0x%04x\n", regname(addr), val);
|
| 1266 |
|
| 1267 |
switch (addr) {
|
| 1268 |
case SCBStatus:
|
| 1269 |
//~ eepro100_write_status(s, val);
|
| 1270 |
eepro100_acknowledge(s); |
| 1271 |
break;
|
| 1272 |
case SCBCmd:
|
| 1273 |
eepro100_write_command(s, val); |
| 1274 |
eepro100_write1(s, SCBIntmask, val >> 8);
|
| 1275 |
break;
|
| 1276 |
case SCBeeprom:
|
| 1277 |
eepro100_write_eeprom(s->eeprom, val); |
| 1278 |
break;
|
| 1279 |
default:
|
| 1280 |
logout("addr=%s val=0x%04x\n", regname(addr), val);
|
| 1281 |
missing("unknown word write");
|
| 1282 |
} |
| 1283 |
} |
| 1284 |
|
| 1285 |
static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val) |
| 1286 |
{
|
| 1287 |
if (addr <= sizeof(s->mem) - sizeof(val)) { |
| 1288 |
memcpy(&s->mem[addr], &val, sizeof(val));
|
| 1289 |
} |
| 1290 |
|
| 1291 |
switch (addr) {
|
| 1292 |
case SCBPointer:
|
| 1293 |
eepro100_write_pointer(s, val); |
| 1294 |
break;
|
| 1295 |
case SCBPort:
|
| 1296 |
logout("addr=%s val=0x%08x\n", regname(addr), val);
|
| 1297 |
eepro100_write_port(s, val); |
| 1298 |
break;
|
| 1299 |
case SCBCtrlMDI:
|
| 1300 |
eepro100_write_mdi(s, val); |
| 1301 |
break;
|
| 1302 |
default:
|
| 1303 |
logout("addr=%s val=0x%08x\n", regname(addr), val);
|
| 1304 |
missing("unknown longword write");
|
| 1305 |
} |
| 1306 |
} |
| 1307 |
|
| 1308 |
static uint32_t ioport_read1(void *opaque, uint32_t addr) |
| 1309 |
{
|
| 1310 |
EEPRO100State *s = opaque; |
| 1311 |
//~ logout("addr=%s\n", regname(addr));
|
| 1312 |
return eepro100_read1(s, addr - s->region[1]); |
| 1313 |
} |
| 1314 |
|
| 1315 |
static uint32_t ioport_read2(void *opaque, uint32_t addr) |
| 1316 |
{
|
| 1317 |
EEPRO100State *s = opaque; |
| 1318 |
return eepro100_read2(s, addr - s->region[1]); |
| 1319 |
} |
| 1320 |
|
| 1321 |
static uint32_t ioport_read4(void *opaque, uint32_t addr) |
| 1322 |
{
|
| 1323 |
EEPRO100State *s = opaque; |
| 1324 |
return eepro100_read4(s, addr - s->region[1]); |
| 1325 |
} |
| 1326 |
|
| 1327 |
static void ioport_write1(void *opaque, uint32_t addr, uint32_t val) |
| 1328 |
{
|
| 1329 |
EEPRO100State *s = opaque; |
| 1330 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1331 |
eepro100_write1(s, addr - s->region[1], val);
|
| 1332 |
} |
| 1333 |
|
| 1334 |
static void ioport_write2(void *opaque, uint32_t addr, uint32_t val) |
| 1335 |
{
|
| 1336 |
EEPRO100State *s = opaque; |
| 1337 |
eepro100_write2(s, addr - s->region[1], val);
|
| 1338 |
} |
| 1339 |
|
| 1340 |
static void ioport_write4(void *opaque, uint32_t addr, uint32_t val) |
| 1341 |
{
|
| 1342 |
EEPRO100State *s = opaque; |
| 1343 |
eepro100_write4(s, addr - s->region[1], val);
|
| 1344 |
} |
| 1345 |
|
| 1346 |
/***********************************************************/
|
| 1347 |
/* PCI EEPRO100 definitions */
|
| 1348 |
|
| 1349 |
typedef struct PCIEEPRO100State { |
| 1350 |
PCIDevice dev; |
| 1351 |
EEPRO100State eepro100; |
| 1352 |
} PCIEEPRO100State; |
| 1353 |
|
| 1354 |
static void pci_map(PCIDevice * pci_dev, int region_num, |
| 1355 |
uint32_t addr, uint32_t size, int type)
|
| 1356 |
{
|
| 1357 |
PCIEEPRO100State *d = (PCIEEPRO100State *) pci_dev; |
| 1358 |
EEPRO100State *s = &d->eepro100; |
| 1359 |
|
| 1360 |
logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
|
| 1361 |
region_num, addr, size, type); |
| 1362 |
|
| 1363 |
assert(region_num == 1);
|
| 1364 |
register_ioport_write(addr, size, 1, ioport_write1, s);
|
| 1365 |
register_ioport_read(addr, size, 1, ioport_read1, s);
|
| 1366 |
register_ioport_write(addr, size, 2, ioport_write2, s);
|
| 1367 |
register_ioport_read(addr, size, 2, ioport_read2, s);
|
| 1368 |
register_ioport_write(addr, size, 4, ioport_write4, s);
|
| 1369 |
register_ioport_read(addr, size, 4, ioport_read4, s);
|
| 1370 |
|
| 1371 |
s->region[region_num] = addr; |
| 1372 |
} |
| 1373 |
|
| 1374 |
static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1375 |
{
|
| 1376 |
EEPRO100State *s = opaque; |
| 1377 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1378 |
eepro100_write1(s, addr, val); |
| 1379 |
} |
| 1380 |
|
| 1381 |
static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1382 |
{
|
| 1383 |
EEPRO100State *s = opaque; |
| 1384 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1385 |
eepro100_write2(s, addr, val); |
| 1386 |
} |
| 1387 |
|
| 1388 |
static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1389 |
{
|
| 1390 |
EEPRO100State *s = opaque; |
| 1391 |
//~ logout("addr=%s val=0x%02x\n", regname(addr), val);
|
| 1392 |
eepro100_write4(s, addr, val); |
| 1393 |
} |
| 1394 |
|
| 1395 |
static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr) |
| 1396 |
{
|
| 1397 |
EEPRO100State *s = opaque; |
| 1398 |
//~ logout("addr=%s\n", regname(addr));
|
| 1399 |
return eepro100_read1(s, addr);
|
| 1400 |
} |
| 1401 |
|
| 1402 |
static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr) |
| 1403 |
{
|
| 1404 |
EEPRO100State *s = opaque; |
| 1405 |
//~ logout("addr=%s\n", regname(addr));
|
| 1406 |
return eepro100_read2(s, addr);
|
| 1407 |
} |
| 1408 |
|
| 1409 |
static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr) |
| 1410 |
{
|
| 1411 |
EEPRO100State *s = opaque; |
| 1412 |
//~ logout("addr=%s\n", regname(addr));
|
| 1413 |
return eepro100_read4(s, addr);
|
| 1414 |
} |
| 1415 |
|
| 1416 |
static CPUWriteMemoryFunc *pci_mmio_write[] = {
|
| 1417 |
pci_mmio_writeb, |
| 1418 |
pci_mmio_writew, |
| 1419 |
pci_mmio_writel |
| 1420 |
}; |
| 1421 |
|
| 1422 |
static CPUReadMemoryFunc *pci_mmio_read[] = {
|
| 1423 |
pci_mmio_readb, |
| 1424 |
pci_mmio_readw, |
| 1425 |
pci_mmio_readl |
| 1426 |
}; |
| 1427 |
|
| 1428 |
static void pci_mmio_map(PCIDevice * pci_dev, int region_num, |
| 1429 |
uint32_t addr, uint32_t size, int type)
|
| 1430 |
{
|
| 1431 |
PCIEEPRO100State *d = (PCIEEPRO100State *) pci_dev; |
| 1432 |
|
| 1433 |
logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
|
| 1434 |
region_num, addr, size, type); |
| 1435 |
|
| 1436 |
if (region_num == 0) { |
| 1437 |
/* Map control / status registers. */
|
| 1438 |
cpu_register_physical_memory(addr, size, d->eepro100.mmio_index); |
| 1439 |
d->eepro100.region[region_num] = addr; |
| 1440 |
} |
| 1441 |
} |
| 1442 |
|
| 1443 |
static int nic_can_receive(void *opaque) |
| 1444 |
{
|
| 1445 |
EEPRO100State *s = opaque; |
| 1446 |
logout("%p\n", s);
|
| 1447 |
return get_ru_state(s) == ru_ready;
|
| 1448 |
//~ return !eepro100_buffer_full(s);
|
| 1449 |
} |
| 1450 |
|
| 1451 |
static void nic_receive(void *opaque, const uint8_t * buf, int size) |
| 1452 |
{
|
| 1453 |
/* TODO:
|
| 1454 |
* - Magic packets should set bit 30 in power management driver register.
|
| 1455 |
* - Interesting packets should set bit 29 in power management driver register.
|
| 1456 |
*/
|
| 1457 |
EEPRO100State *s = opaque; |
| 1458 |
uint16_t rfd_status = 0xa000;
|
| 1459 |
static const uint8_t broadcast_macaddr[6] = |
| 1460 |
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
|
| 1461 |
|
| 1462 |
/* TODO: check multiple IA bit. */
|
| 1463 |
assert(!(s->configuration[20] & BIT(6))); |
| 1464 |
|
| 1465 |
if (s->configuration[8] & 0x80) { |
| 1466 |
/* CSMA is disabled. */
|
| 1467 |
logout("%p received while CSMA is disabled\n", s);
|
| 1468 |
return;
|
| 1469 |
} else if (size < 64 && (s->configuration[7] & 1)) { |
| 1470 |
/* Short frame and configuration byte 7/0 (discard short receive) set:
|
| 1471 |
* Short frame is discarded */
|
| 1472 |
logout("%p received short frame (%d byte)\n", s, size);
|
| 1473 |
s->statistics.rx_short_frame_errors++; |
| 1474 |
//~ return;
|
| 1475 |
} else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & 8)) { |
| 1476 |
/* Long frame and configuration byte 18/3 (long receive ok) not set:
|
| 1477 |
* Long frames are discarded. */
|
| 1478 |
logout("%p received long frame (%d byte), ignored\n", s, size);
|
| 1479 |
return;
|
| 1480 |
} else if (memcmp(buf, s->macaddr, 6) == 0) { // !!! |
| 1481 |
/* Frame matches individual address. */
|
| 1482 |
/* TODO: check configuration byte 15/4 (ignore U/L). */
|
| 1483 |
logout("%p received frame for me, len=%d\n", s, size);
|
| 1484 |
} else if (memcmp(buf, broadcast_macaddr, 6) == 0) { |
| 1485 |
/* Broadcast frame. */
|
| 1486 |
logout("%p received broadcast, len=%d\n", s, size);
|
| 1487 |
rfd_status |= 0x0002;
|
| 1488 |
} else if (buf[0] & 0x01) { // !!! |
| 1489 |
/* Multicast frame. */
|
| 1490 |
logout("%p received multicast, len=%d\n", s, size);
|
| 1491 |
/* TODO: check multicast all bit. */
|
| 1492 |
assert(!(s->configuration[21] & BIT(3))); |
| 1493 |
int mcast_idx = compute_mcast_idx(buf);
|
| 1494 |
if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) { |
| 1495 |
return;
|
| 1496 |
} |
| 1497 |
rfd_status |= 0x0002;
|
| 1498 |
} else if (s->configuration[15] & 1) { |
| 1499 |
/* Promiscuous: receive all. */
|
| 1500 |
logout("%p received frame in promiscuous mode, len=%d\n", s, size);
|
| 1501 |
rfd_status |= 0x0004;
|
| 1502 |
} else {
|
| 1503 |
logout("%p received frame, ignored, len=%d,%s\n", s, size,
|
| 1504 |
nic_dump(buf, size)); |
| 1505 |
return;
|
| 1506 |
} |
| 1507 |
|
| 1508 |
if (get_ru_state(s) != ru_ready) {
|
| 1509 |
/* No ressources available. */
|
| 1510 |
logout("no ressources, state=%u\n", get_ru_state(s));
|
| 1511 |
s->statistics.rx_resource_errors++; |
| 1512 |
//~ assert(!"no ressources");
|
| 1513 |
return;
|
| 1514 |
} |
| 1515 |
//~ !!!
|
| 1516 |
//~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
|
| 1517 |
eepro100_rx_t rx; |
| 1518 |
cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx, |
| 1519 |
offsetof(eepro100_rx_t, packet)); |
| 1520 |
uint16_t rfd_command = le16_to_cpu(rx.command); |
| 1521 |
uint16_t rfd_size = le16_to_cpu(rx.size); |
| 1522 |
assert(size <= rfd_size); |
| 1523 |
if (size < 64) { |
| 1524 |
rfd_status |= 0x0080;
|
| 1525 |
} |
| 1526 |
logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n", rfd_command,
|
| 1527 |
rx.link, rx.rx_buf_addr, rfd_size); |
| 1528 |
stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status), |
| 1529 |
rfd_status); |
| 1530 |
stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size); |
| 1531 |
/* Early receive interrupt not supported. */
|
| 1532 |
//~ eepro100_er_interrupt(s);
|
| 1533 |
/* Receive CRC Transfer not supported. */
|
| 1534 |
assert(!(s->configuration[18] & 4)); |
| 1535 |
/* TODO: check stripping enable bit. */
|
| 1536 |
//~ assert(!(s->configuration[17] & 1));
|
| 1537 |
cpu_physical_memory_write(s->ru_base + s->ru_offset + |
| 1538 |
offsetof(eepro100_rx_t, packet), buf, size); |
| 1539 |
s->statistics.rx_good_frames++; |
| 1540 |
eepro100_fr_interrupt(s); |
| 1541 |
s->ru_offset = le32_to_cpu(rx.link); |
| 1542 |
if (rfd_command & 0x8000) { |
| 1543 |
/* EL bit is set, so this was the last frame. */
|
| 1544 |
assert(0);
|
| 1545 |
} |
| 1546 |
if (rfd_command & 0x4000) { |
| 1547 |
/* S bit is set. */
|
| 1548 |
set_ru_state(s, ru_suspended); |
| 1549 |
} |
| 1550 |
} |
| 1551 |
|
| 1552 |
static int nic_load(QEMUFile * f, void *opaque, int version_id) |
| 1553 |
{
|
| 1554 |
EEPRO100State *s = (EEPRO100State *) opaque; |
| 1555 |
int i;
|
| 1556 |
int ret;
|
| 1557 |
|
| 1558 |
if (version_id > 3) |
| 1559 |
return -EINVAL;
|
| 1560 |
|
| 1561 |
if (s->pci_dev && version_id >= 3) { |
| 1562 |
ret = pci_device_load(s->pci_dev, f); |
| 1563 |
if (ret < 0) |
| 1564 |
return ret;
|
| 1565 |
} |
| 1566 |
|
| 1567 |
if (version_id >= 2) { |
| 1568 |
qemu_get_8s(f, &s->rxcr); |
| 1569 |
} else {
|
| 1570 |
s->rxcr = 0x0c;
|
| 1571 |
} |
| 1572 |
|
| 1573 |
qemu_get_8s(f, &s->cmd); |
| 1574 |
qemu_get_be32s(f, &s->start); |
| 1575 |
qemu_get_be32s(f, &s->stop); |
| 1576 |
qemu_get_8s(f, &s->boundary); |
| 1577 |
qemu_get_8s(f, &s->tsr); |
| 1578 |
qemu_get_8s(f, &s->tpsr); |
| 1579 |
qemu_get_be16s(f, &s->tcnt); |
| 1580 |
qemu_get_be16s(f, &s->rcnt); |
| 1581 |
qemu_get_be32s(f, &s->rsar); |
| 1582 |
qemu_get_8s(f, &s->rsr); |
| 1583 |
qemu_get_8s(f, &s->isr); |
| 1584 |
qemu_get_8s(f, &s->dcfg); |
| 1585 |
qemu_get_8s(f, &s->imr); |
| 1586 |
qemu_get_buffer(f, s->phys, 6);
|
| 1587 |
qemu_get_8s(f, &s->curpag); |
| 1588 |
qemu_get_buffer(f, s->mult, 8);
|
| 1589 |
qemu_get_buffer(f, s->mem, sizeof(s->mem));
|
| 1590 |
|
| 1591 |
/* Restore all members of struct between scv_stat and mem */
|
| 1592 |
qemu_get_8s(f, &s->scb_stat); |
| 1593 |
qemu_get_8s(f, &s->int_stat); |
| 1594 |
for (i = 0; i < 3; i++) |
| 1595 |
qemu_get_be32s(f, &s->region[i]); |
| 1596 |
qemu_get_buffer(f, s->macaddr, 6);
|
| 1597 |
for (i = 0; i < 19; i++) |
| 1598 |
qemu_get_be32s(f, &s->statcounter[i]); |
| 1599 |
for (i = 0; i < 32; i++) |
| 1600 |
qemu_get_be16s(f, &s->mdimem[i]); |
| 1601 |
/* The eeprom should be saved and restored by its own routines */
|
| 1602 |
qemu_get_be32s(f, &s->device); |
| 1603 |
qemu_get_be32s(f, &s->pointer); |
| 1604 |
qemu_get_be32s(f, &s->cu_base); |
| 1605 |
qemu_get_be32s(f, &s->cu_offset); |
| 1606 |
qemu_get_be32s(f, &s->ru_base); |
| 1607 |
qemu_get_be32s(f, &s->ru_offset); |
| 1608 |
qemu_get_be32s(f, &s->statsaddr); |
| 1609 |
/* Restore epro100_stats_t statistics */
|
| 1610 |
qemu_get_be32s(f, &s->statistics.tx_good_frames); |
| 1611 |
qemu_get_be32s(f, &s->statistics.tx_max_collisions); |
| 1612 |
qemu_get_be32s(f, &s->statistics.tx_late_collisions); |
| 1613 |
qemu_get_be32s(f, &s->statistics.tx_underruns); |
| 1614 |
qemu_get_be32s(f, &s->statistics.tx_lost_crs); |
| 1615 |
qemu_get_be32s(f, &s->statistics.tx_deferred); |
| 1616 |
qemu_get_be32s(f, &s->statistics.tx_single_collisions); |
| 1617 |
qemu_get_be32s(f, &s->statistics.tx_multiple_collisions); |
| 1618 |
qemu_get_be32s(f, &s->statistics.tx_total_collisions); |
| 1619 |
qemu_get_be32s(f, &s->statistics.rx_good_frames); |
| 1620 |
qemu_get_be32s(f, &s->statistics.rx_crc_errors); |
| 1621 |
qemu_get_be32s(f, &s->statistics.rx_alignment_errors); |
| 1622 |
qemu_get_be32s(f, &s->statistics.rx_resource_errors); |
| 1623 |
qemu_get_be32s(f, &s->statistics.rx_overrun_errors); |
| 1624 |
qemu_get_be32s(f, &s->statistics.rx_cdt_errors); |
| 1625 |
qemu_get_be32s(f, &s->statistics.rx_short_frame_errors); |
| 1626 |
qemu_get_be32s(f, &s->statistics.fc_xmt_pause); |
| 1627 |
qemu_get_be32s(f, &s->statistics.fc_rcv_pause); |
| 1628 |
qemu_get_be32s(f, &s->statistics.fc_rcv_unsupported); |
| 1629 |
qemu_get_be16s(f, &s->statistics.xmt_tco_frames); |
| 1630 |
qemu_get_be16s(f, &s->statistics.rcv_tco_frames); |
| 1631 |
qemu_get_be32s(f, &s->statistics.complete); |
| 1632 |
#if 0
|
| 1633 |
qemu_get_be16s(f, &s->status);
|
| 1634 |
#endif
|
| 1635 |
|
| 1636 |
/* Configuration bytes. */
|
| 1637 |
qemu_get_buffer(f, s->configuration, sizeof(s->configuration));
|
| 1638 |
|
| 1639 |
return 0; |
| 1640 |
} |
| 1641 |
|
| 1642 |
static void nic_save(QEMUFile * f, void *opaque) |
| 1643 |
{
|
| 1644 |
EEPRO100State *s = (EEPRO100State *) opaque; |
| 1645 |
int i;
|
| 1646 |
|
| 1647 |
if (s->pci_dev)
|
| 1648 |
pci_device_save(s->pci_dev, f); |
| 1649 |
|
| 1650 |
qemu_put_8s(f, &s->rxcr); |
| 1651 |
|
| 1652 |
qemu_put_8s(f, &s->cmd); |
| 1653 |
qemu_put_be32s(f, &s->start); |
| 1654 |
qemu_put_be32s(f, &s->stop); |
| 1655 |
qemu_put_8s(f, &s->boundary); |
| 1656 |
qemu_put_8s(f, &s->tsr); |
| 1657 |
qemu_put_8s(f, &s->tpsr); |
| 1658 |
qemu_put_be16s(f, &s->tcnt); |
| 1659 |
qemu_put_be16s(f, &s->rcnt); |
| 1660 |
qemu_put_be32s(f, &s->rsar); |
| 1661 |
qemu_put_8s(f, &s->rsr); |
| 1662 |
qemu_put_8s(f, &s->isr); |
| 1663 |
qemu_put_8s(f, &s->dcfg); |
| 1664 |
qemu_put_8s(f, &s->imr); |
| 1665 |
qemu_put_buffer(f, s->phys, 6);
|
| 1666 |
qemu_put_8s(f, &s->curpag); |
| 1667 |
qemu_put_buffer(f, s->mult, 8);
|
| 1668 |
qemu_put_buffer(f, s->mem, sizeof(s->mem));
|
| 1669 |
|
| 1670 |
/* Save all members of struct between scv_stat and mem */
|
| 1671 |
qemu_put_8s(f, &s->scb_stat); |
| 1672 |
qemu_put_8s(f, &s->int_stat); |
| 1673 |
for (i = 0; i < 3; i++) |
| 1674 |
qemu_put_be32s(f, &s->region[i]); |
| 1675 |
qemu_put_buffer(f, s->macaddr, 6);
|
| 1676 |
for (i = 0; i < 19; i++) |
| 1677 |
qemu_put_be32s(f, &s->statcounter[i]); |
| 1678 |
for (i = 0; i < 32; i++) |
| 1679 |
qemu_put_be16s(f, &s->mdimem[i]); |
| 1680 |
/* The eeprom should be saved and restored by its own routines */
|
| 1681 |
qemu_put_be32s(f, &s->device); |
| 1682 |
qemu_put_be32s(f, &s->pointer); |
| 1683 |
qemu_put_be32s(f, &s->cu_base); |
| 1684 |
qemu_put_be32s(f, &s->cu_offset); |
| 1685 |
qemu_put_be32s(f, &s->ru_base); |
| 1686 |
qemu_put_be32s(f, &s->ru_offset); |
| 1687 |
qemu_put_be32s(f, &s->statsaddr); |
| 1688 |
/* Save epro100_stats_t statistics */
|
| 1689 |
qemu_put_be32s(f, &s->statistics.tx_good_frames); |
| 1690 |
qemu_put_be32s(f, &s->statistics.tx_max_collisions); |
| 1691 |
qemu_put_be32s(f, &s->statistics.tx_late_collisions); |
| 1692 |
qemu_put_be32s(f, &s->statistics.tx_underruns); |
| 1693 |
qemu_put_be32s(f, &s->statistics.tx_lost_crs); |
| 1694 |
qemu_put_be32s(f, &s->statistics.tx_deferred); |
| 1695 |
qemu_put_be32s(f, &s->statistics.tx_single_collisions); |
| 1696 |
qemu_put_be32s(f, &s->statistics.tx_multiple_collisions); |
| 1697 |
qemu_put_be32s(f, &s->statistics.tx_total_collisions); |
| 1698 |
qemu_put_be32s(f, &s->statistics.rx_good_frames); |
| 1699 |
qemu_put_be32s(f, &s->statistics.rx_crc_errors); |
| 1700 |
qemu_put_be32s(f, &s->statistics.rx_alignment_errors); |
| 1701 |
qemu_put_be32s(f, &s->statistics.rx_resource_errors); |
| 1702 |
qemu_put_be32s(f, &s->statistics.rx_overrun_errors); |
| 1703 |
qemu_put_be32s(f, &s->statistics.rx_cdt_errors); |
| 1704 |
qemu_put_be32s(f, &s->statistics.rx_short_frame_errors); |
| 1705 |
qemu_put_be32s(f, &s->statistics.fc_xmt_pause); |
| 1706 |
qemu_put_be32s(f, &s->statistics.fc_rcv_pause); |
| 1707 |
qemu_put_be32s(f, &s->statistics.fc_rcv_unsupported); |
| 1708 |
qemu_put_be16s(f, &s->statistics.xmt_tco_frames); |
| 1709 |
qemu_put_be16s(f, &s->statistics.rcv_tco_frames); |
| 1710 |
qemu_put_be32s(f, &s->statistics.complete); |
| 1711 |
#if 0
|
| 1712 |
qemu_put_be16s(f, &s->status);
|
| 1713 |
#endif
|
| 1714 |
|
| 1715 |
/* Configuration bytes. */
|
| 1716 |
qemu_put_buffer(f, s->configuration, sizeof(s->configuration));
|
| 1717 |
} |
| 1718 |
|
| 1719 |
static PCIDevice *nic_init(PCIBus * bus, NICInfo * nd,
|
| 1720 |
const char *name, uint32_t device) |
| 1721 |
{
|
| 1722 |
PCIEEPRO100State *d; |
| 1723 |
EEPRO100State *s; |
| 1724 |
|
| 1725 |
logout("\n");
|
| 1726 |
|
| 1727 |
d = (PCIEEPRO100State *) pci_register_device(bus, name, |
| 1728 |
sizeof(PCIEEPRO100State), -1, |
| 1729 |
NULL, NULL); |
| 1730 |
|
| 1731 |
s = &d->eepro100; |
| 1732 |
s->device = device; |
| 1733 |
s->pci_dev = &d->dev; |
| 1734 |
|
| 1735 |
pci_reset(s); |
| 1736 |
|
| 1737 |
/* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
|
| 1738 |
* i82559 and later support 64 or 256 word EEPROM. */
|
| 1739 |
s->eeprom = eeprom93xx_new(EEPROM_SIZE); |
| 1740 |
|
| 1741 |
/* Handler for memory-mapped I/O */
|
| 1742 |
d->eepro100.mmio_index = |
| 1743 |
cpu_register_io_memory(0, pci_mmio_read, pci_mmio_write, s);
|
| 1744 |
|
| 1745 |
pci_register_io_region(&d->dev, 0, PCI_MEM_SIZE,
|
| 1746 |
PCI_ADDRESS_SPACE_MEM | |
| 1747 |
PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_mmio_map); |
| 1748 |
pci_register_io_region(&d->dev, 1, PCI_IO_SIZE, PCI_ADDRESS_SPACE_IO,
|
| 1749 |
pci_map); |
| 1750 |
pci_register_io_region(&d->dev, 2, PCI_FLASH_SIZE, PCI_ADDRESS_SPACE_MEM,
|
| 1751 |
pci_mmio_map); |
| 1752 |
|
| 1753 |
memcpy(s->macaddr, nd->macaddr, 6);
|
| 1754 |
logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6)); |
| 1755 |
assert(s->region[1] == 0); |
| 1756 |
|
| 1757 |
nic_reset(s); |
| 1758 |
|
| 1759 |
s->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name, |
| 1760 |
nic_receive, nic_can_receive, s); |
| 1761 |
|
| 1762 |
qemu_format_nic_info_str(s->vc, s->macaddr); |
| 1763 |
|
| 1764 |
qemu_register_reset(nic_reset, s); |
| 1765 |
|
| 1766 |
register_savevm(name, -1, 3, nic_save, nic_load, s); |
| 1767 |
return (PCIDevice *)d;
|
| 1768 |
} |
| 1769 |
|
| 1770 |
PCIDevice *pci_i82551_init(PCIBus * bus, NICInfo * nd, int devfn)
|
| 1771 |
{
|
| 1772 |
return nic_init(bus, nd, "i82551", i82551); |
| 1773 |
//~ uint8_t *pci_conf = d->dev.config;
|
| 1774 |
} |
| 1775 |
|
| 1776 |
PCIDevice *pci_i82557b_init(PCIBus * bus, NICInfo * nd, int devfn)
|
| 1777 |
{
|
| 1778 |
return nic_init(bus, nd, "i82557b", i82557B); |
| 1779 |
} |
| 1780 |
|
| 1781 |
PCIDevice *pci_i82559er_init(PCIBus * bus, NICInfo * nd, int devfn)
|
| 1782 |
{
|
| 1783 |
return nic_init(bus, nd, "i82559er", i82559ER); |
| 1784 |
} |
| 1785 |
|
| 1786 |
/* eof */
|