Revision d7d02e3c

b/hw/dma.c
355 355
    cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
356 356
}
357 357

  
358
static void dma_reset(void *opaque)
359
{
360
    struct dma_cont *d = opaque;
361
    write_cont (d, (0x0d << d->dshift), 0);
362
}
363

  
358 364
/* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
359 365
static void dma_init2(struct dma_cont *d, int base, int dshift, int page_base)
360 366
{
......
378 384
        register_ioport_read (base + ((i + 8) << dshift), 1, 1, 
379 385
                              read_cont, d);
380 386
    }
381
    write_cont (d, base + (0x0d << dshift), 0);
387
    qemu_register_reset(dma_reset, d);
388
    dma_reset(d);
382 389
}
383 390

  
384 391
void DMA_init (void)
b/hw/i8254.c
434 434
    return 0;
435 435
}
436 436

  
437
PITState *pit_init(int base, int irq)
437
static void pit_reset(void *opaque)
438 438
{
439
    PITState *pit = &pit_state;
439
    PITState *pit = opaque;
440 440
    PITChannelState *s;
441 441
    int i;
442 442

  
443 443
    for(i = 0;i < 3; i++) {
444 444
        s = &pit->channels[i];
445
        if (i == 0) {
446
            /* the timer 0 is connected to an IRQ */
447
            s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
448
            s->irq = irq;
449
        }
450 445
        s->mode = 3;
451 446
        s->gate = (i != 2);
452 447
        pit_load_count(s, 0);
453 448
    }
449
}
450

  
451
PITState *pit_init(int base, int irq)
452
{
453
    PITState *pit = &pit_state;
454
    PITChannelState *s;
455

  
456
    s = &pit->channels[0];
457
    /* the timer 0 is connected to an IRQ */
458
    s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
459
    s->irq = irq;
454 460

  
455 461
    register_savevm("i8254", base, 1, pit_save, pit_load, pit);
456 462

  
463
    qemu_register_reset(pit_reset, pit);
457 464
    register_ioport_write(base, 4, 1, pit_ioport_write, pit);
458 465
    register_ioport_read(base, 3, 1, pit_ioport_read, pit);
466

  
467
    pit_reset(pit);
468

  
459 469
    return pit;
460 470
}
b/hw/i8259.c
231 231
    return intno;
232 232
}
233 233

  
234
static void pic_reset(void *opaque)
235
{
236
    PicState *s = opaque;
237
    int tmp;
238

  
239
    tmp = s->elcr_mask;
240
    memset(s, 0, sizeof(PicState));
241
    s->elcr_mask = tmp;
242
}
243

  
234 244
static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
235 245
{
236 246
    PicState *s = opaque;
237
    int priority, cmd, irq, tmp;
247
    int priority, cmd, irq;
238 248

  
239 249
#ifdef DEBUG_PIC
240 250
    printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
......
243 253
    if (addr == 0) {
244 254
        if (val & 0x10) {
245 255
            /* init */
246
            tmp = s->elcr_mask;
247
            memset(s, 0, sizeof(PicState));
248
            s->elcr_mask = tmp;
256
            pic_reset(s);
249 257
            /* deassert a pending interrupt */
250 258
            cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
251 259

  
......
458 466
        register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
459 467
    }
460 468
    register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
469
    qemu_register_reset(pic_reset, s);
461 470
}
462 471

  
463 472
void pic_info(void)
b/hw/m48t59.c
162 162
	NVRAM->buffer[0x1FF7] = 0x00;
163 163
	NVRAM->buffer[0x1FFC] &= ~0x40;
164 164
        /* May it be a hw CPU Reset instead ? */
165
        reset_requested = 1;
166
        printf("Watchdog reset...\n");
167
        cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
165
        qemu_system_reset_request();
168 166
    } else {
169 167
	pic_set_irq(NVRAM->IRQ, 1);
170 168
	pic_set_irq(NVRAM->IRQ, 0);
b/hw/pckbd.c
139 139
} KBDState;
140 140

  
141 141
KBDState kbd_state;
142
int reset_requested;
143 142

  
144 143
/* update irq and KBD_STAT_[MOUSE_]OBF */
145 144
/* XXX: not generating the irqs if KBD_MODE_DISABLE_KBD is set may be
......
274 273
        break;
275 274
#endif
276 275
    case KBD_CCMD_RESET:
277
        reset_requested = 1;
278
        cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
276
        qemu_system_reset_request();
279 277
        break;
280 278
    case 0xff:
281 279
        /* ignore that - I don't know what is its use */
......
617 615
        cpu_x86_set_a20(cpu_single_env, (val >> 1) & 1);
618 616
#endif
619 617
        if (!(val & 1)) {
620
            reset_requested = 1;
621
            cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
618
            qemu_system_reset_request();
622 619
        }
623 620
        break;
624 621
    case KBD_CCMD_WRITE_MOUSE:
......
630 627
    s->write_cmd = 0;
631 628
}
632 629

  
633
void kbd_reset(KBDState *s)
630
static void kbd_reset(void *opaque)
634 631
{
632
    KBDState *s = opaque;
635 633
    KBDQueue *q;
636 634

  
637 635
    s->kbd_write_cmd = -1;
......
656 654

  
657 655
    qemu_add_kbd_event_handler(pc_kbd_put_keycode, s);
658 656
    qemu_add_mouse_event_handler(pc_kbd_mouse_event, s);
657
    qemu_register_reset(kbd_reset, s);
659 658
}

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