Revision d7d02e3c hw/dma.c

b/hw/dma.c
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    cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
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}
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static void dma_reset(void *opaque)
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{
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    struct dma_cont *d = opaque;
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    write_cont (d, (0x0d << d->dshift), 0);
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}
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/* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
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static void dma_init2(struct dma_cont *d, int base, int dshift, int page_base)
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{
......
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        register_ioport_read (base + ((i + 8) << dshift), 1, 1, 
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                              read_cont, d);
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    }
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    write_cont (d, base + (0x0d << dshift), 0);
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    qemu_register_reset(dma_reset, d);
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    dma_reset(d);
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}
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void DMA_init (void)

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