Revision d7d02e3c hw/i8254.c
| b/hw/i8254.c | ||
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| 434 | 434 |
return 0; |
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} |
| 436 | 436 |
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PITState *pit_init(int base, int irq)
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static void pit_reset(void *opaque)
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{
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PITState *pit = &pit_state;
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PITState *pit = opaque;
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PITChannelState *s; |
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int i; |
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for(i = 0;i < 3; i++) {
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| 444 | 444 |
s = &pit->channels[i]; |
| 445 |
if (i == 0) {
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/* the timer 0 is connected to an IRQ */ |
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s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s); |
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s->irq = irq; |
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} |
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| 450 | 445 |
s->mode = 3; |
| 451 | 446 |
s->gate = (i != 2); |
| 452 | 447 |
pit_load_count(s, 0); |
| 453 | 448 |
} |
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} |
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PITState *pit_init(int base, int irq) |
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{
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PITState *pit = &pit_state; |
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PITChannelState *s; |
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s = &pit->channels[0]; |
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/* the timer 0 is connected to an IRQ */ |
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s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s); |
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s->irq = irq; |
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| 454 | 460 |
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register_savevm("i8254", base, 1, pit_save, pit_load, pit);
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| 456 | 462 |
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qemu_register_reset(pit_reset, pit); |
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| 457 | 464 |
register_ioport_write(base, 4, 1, pit_ioport_write, pit); |
| 458 | 465 |
register_ioport_read(base, 3, 1, pit_ioport_read, pit); |
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pit_reset(pit); |
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| 459 | 469 |
return pit; |
| 460 | 470 |
} |
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