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1
/*
2
 *  APIC support
3
 *
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 *  Copyright (c) 2004-2005 Fabrice Bellard
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
10
 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>
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 */
19
#include "hw.h"
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#include "apic.h"
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#include "qemu-timer.h"
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#include "host-utils.h"
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#include "sysbus.h"
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#include "trace.h"
25

    
26
/* APIC Local Vector Table */
27
#define APIC_LVT_TIMER   0
28
#define APIC_LVT_THERMAL 1
29
#define APIC_LVT_PERFORM 2
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#define APIC_LVT_LINT0   3
31
#define APIC_LVT_LINT1   4
32
#define APIC_LVT_ERROR   5
33
#define APIC_LVT_NB      6
34

    
35
/* APIC delivery modes */
36
#define APIC_DM_FIXED        0
37
#define APIC_DM_LOWPRI        1
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#define APIC_DM_SMI        2
39
#define APIC_DM_NMI        4
40
#define APIC_DM_INIT        5
41
#define APIC_DM_SIPI        6
42
#define APIC_DM_EXTINT        7
43

    
44
/* APIC destination mode */
45
#define APIC_DESTMODE_FLAT        0xf
46
#define APIC_DESTMODE_CLUSTER        1
47

    
48
#define APIC_TRIGGER_EDGE  0
49
#define APIC_TRIGGER_LEVEL 1
50

    
51
#define        APIC_LVT_TIMER_PERIODIC                (1<<17)
52
#define        APIC_LVT_MASKED                        (1<<16)
53
#define        APIC_LVT_LEVEL_TRIGGER                (1<<15)
54
#define        APIC_LVT_REMOTE_IRR                (1<<14)
55
#define        APIC_INPUT_POLARITY                (1<<13)
56
#define        APIC_SEND_PENDING                (1<<12)
57

    
58
#define ESR_ILLEGAL_ADDRESS (1 << 7)
59

    
60
#define APIC_SV_ENABLE (1 << 8)
61

    
62
#define MAX_APICS 255
63
#define MAX_APIC_WORDS 8
64

    
65
/* Intel APIC constants: from include/asm/msidef.h */
66
#define MSI_DATA_VECTOR_SHIFT                0
67
#define MSI_DATA_VECTOR_MASK                0x000000ff
68
#define MSI_DATA_DELIVERY_MODE_SHIFT        8
69
#define MSI_DATA_TRIGGER_SHIFT                15
70
#define MSI_DATA_LEVEL_SHIFT                14
71
#define MSI_ADDR_DEST_MODE_SHIFT        2
72
#define MSI_ADDR_DEST_ID_SHIFT                12
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#define        MSI_ADDR_DEST_ID_MASK                0x00ffff0
74

    
75
#define MSI_ADDR_SIZE                   0x100000
76

    
77
typedef struct APICState APICState;
78

    
79
struct APICState {
80
    SysBusDevice busdev;
81
    void *cpu_env;
82
    uint32_t apicbase;
83
    uint8_t id;
84
    uint8_t arb_id;
85
    uint8_t tpr;
86
    uint32_t spurious_vec;
87
    uint8_t log_dest;
88
    uint8_t dest_mode;
89
    uint32_t isr[8];  /* in service register */
90
    uint32_t tmr[8];  /* trigger mode register */
91
    uint32_t irr[8]; /* interrupt request register */
92
    uint32_t lvt[APIC_LVT_NB];
93
    uint32_t esr; /* error register */
94
    uint32_t icr[2];
95

    
96
    uint32_t divide_conf;
97
    int count_shift;
98
    uint32_t initial_count;
99
    int64_t initial_count_load_time, next_time;
100
    uint32_t idx;
101
    QEMUTimer *timer;
102
    int sipi_vector;
103
    int wait_for_sipi;
104
};
105

    
106
static APICState *local_apics[MAX_APICS + 1];
107
static int apic_irq_delivered;
108

    
109
static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
110
static void apic_update_irq(APICState *s);
111
static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
112
                                      uint8_t dest, uint8_t dest_mode);
113

    
114
/* Find first bit starting from msb */
115
static int fls_bit(uint32_t value)
116
{
117
    return 31 - clz32(value);
118
}
119

    
120
/* Find first bit starting from lsb */
121
static int ffs_bit(uint32_t value)
122
{
123
    return ctz32(value);
124
}
125

    
126
static inline void set_bit(uint32_t *tab, int index)
127
{
128
    int i, mask;
129
    i = index >> 5;
130
    mask = 1 << (index & 0x1f);
131
    tab[i] |= mask;
132
}
133

    
134
static inline void reset_bit(uint32_t *tab, int index)
135
{
136
    int i, mask;
137
    i = index >> 5;
138
    mask = 1 << (index & 0x1f);
139
    tab[i] &= ~mask;
140
}
141

    
142
static inline int get_bit(uint32_t *tab, int index)
143
{
144
    int i, mask;
145
    i = index >> 5;
146
    mask = 1 << (index & 0x1f);
147
    return !!(tab[i] & mask);
148
}
149

    
150
static void apic_local_deliver(APICState *s, int vector)
151
{
152
    uint32_t lvt = s->lvt[vector];
153
    int trigger_mode;
154

    
155
    trace_apic_local_deliver(vector, (lvt >> 8) & 7);
156

    
157
    if (lvt & APIC_LVT_MASKED)
158
        return;
159

    
160
    switch ((lvt >> 8) & 7) {
161
    case APIC_DM_SMI:
162
        cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI);
163
        break;
164

    
165
    case APIC_DM_NMI:
166
        cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI);
167
        break;
168

    
169
    case APIC_DM_EXTINT:
170
        cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
171
        break;
172

    
173
    case APIC_DM_FIXED:
174
        trigger_mode = APIC_TRIGGER_EDGE;
175
        if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
176
            (lvt & APIC_LVT_LEVEL_TRIGGER))
177
            trigger_mode = APIC_TRIGGER_LEVEL;
178
        apic_set_irq(s, lvt & 0xff, trigger_mode);
179
    }
180
}
181

    
182
void apic_deliver_pic_intr(DeviceState *d, int level)
183
{
184
    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
185

    
186
    if (level) {
187
        apic_local_deliver(s, APIC_LVT_LINT0);
188
    } else {
189
        uint32_t lvt = s->lvt[APIC_LVT_LINT0];
190

    
191
        switch ((lvt >> 8) & 7) {
192
        case APIC_DM_FIXED:
193
            if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
194
                break;
195
            reset_bit(s->irr, lvt & 0xff);
196
            /* fall through */
197
        case APIC_DM_EXTINT:
198
            cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
199
            break;
200
        }
201
    }
202
}
203

    
204
#define foreach_apic(apic, deliver_bitmask, code) \
205
{\
206
    int __i, __j, __mask;\
207
    for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
208
        __mask = deliver_bitmask[__i];\
209
        if (__mask) {\
210
            for(__j = 0; __j < 32; __j++) {\
211
                if (__mask & (1 << __j)) {\
212
                    apic = local_apics[__i * 32 + __j];\
213
                    if (apic) {\
214
                        code;\
215
                    }\
216
                }\
217
            }\
218
        }\
219
    }\
220
}
221

    
222
static void apic_bus_deliver(const uint32_t *deliver_bitmask,
223
                             uint8_t delivery_mode,
224
                             uint8_t vector_num, uint8_t polarity,
225
                             uint8_t trigger_mode)
226
{
227
    APICState *apic_iter;
228

    
229
    switch (delivery_mode) {
230
        case APIC_DM_LOWPRI:
231
            /* XXX: search for focus processor, arbitration */
232
            {
233
                int i, d;
234
                d = -1;
235
                for(i = 0; i < MAX_APIC_WORDS; i++) {
236
                    if (deliver_bitmask[i]) {
237
                        d = i * 32 + ffs_bit(deliver_bitmask[i]);
238
                        break;
239
                    }
240
                }
241
                if (d >= 0) {
242
                    apic_iter = local_apics[d];
243
                    if (apic_iter) {
244
                        apic_set_irq(apic_iter, vector_num, trigger_mode);
245
                    }
246
                }
247
            }
248
            return;
249

    
250
        case APIC_DM_FIXED:
251
            break;
252

    
253
        case APIC_DM_SMI:
254
            foreach_apic(apic_iter, deliver_bitmask,
255
                cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
256
            return;
257

    
258
        case APIC_DM_NMI:
259
            foreach_apic(apic_iter, deliver_bitmask,
260
                cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
261
            return;
262

    
263
        case APIC_DM_INIT:
264
            /* normal INIT IPI sent to processors */
265
            foreach_apic(apic_iter, deliver_bitmask,
266
                         cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
267
            return;
268

    
269
        case APIC_DM_EXTINT:
270
            /* handled in I/O APIC code */
271
            break;
272

    
273
        default:
274
            return;
275
    }
276

    
277
    foreach_apic(apic_iter, deliver_bitmask,
278
                 apic_set_irq(apic_iter, vector_num, trigger_mode) );
279
}
280

    
281
void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
282
                      uint8_t delivery_mode, uint8_t vector_num,
283
                      uint8_t polarity, uint8_t trigger_mode)
284
{
285
    uint32_t deliver_bitmask[MAX_APIC_WORDS];
286

    
287
    trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
288
                           polarity, trigger_mode);
289

    
290
    apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
291
    apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
292
                     trigger_mode);
293
}
294

    
295
void cpu_set_apic_base(DeviceState *d, uint64_t val)
296
{
297
    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
298

    
299
    trace_cpu_set_apic_base(val);
300

    
301
    if (!s)
302
        return;
303
    s->apicbase = (val & 0xfffff000) |
304
        (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
305
    /* if disabled, cannot be enabled again */
306
    if (!(val & MSR_IA32_APICBASE_ENABLE)) {
307
        s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
308
        cpu_clear_apic_feature(s->cpu_env);
309
        s->spurious_vec &= ~APIC_SV_ENABLE;
310
    }
311
}
312

    
313
uint64_t cpu_get_apic_base(DeviceState *d)
314
{
315
    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
316

    
317
    trace_cpu_get_apic_base(s ? (uint64_t)s->apicbase: 0);
318

    
319
    return s ? s->apicbase : 0;
320
}
321

    
322
void cpu_set_apic_tpr(DeviceState *d, uint8_t val)
323
{
324
    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
325

    
326
    if (!s)
327
        return;
328
    s->tpr = (val & 0x0f) << 4;
329
    apic_update_irq(s);
330
}
331

    
332
uint8_t cpu_get_apic_tpr(DeviceState *d)
333
{
334
    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
335

    
336
    return s ? s->tpr >> 4 : 0;
337
}
338

    
339
/* return -1 if no bit is set */
340
static int get_highest_priority_int(uint32_t *tab)
341
{
342
    int i;
343
    for(i = 7; i >= 0; i--) {
344
        if (tab[i] != 0) {
345
            return i * 32 + fls_bit(tab[i]);
346
        }
347
    }
348
    return -1;
349
}
350

    
351
static int apic_get_ppr(APICState *s)
352
{
353
    int tpr, isrv, ppr;
354

    
355
    tpr = (s->tpr >> 4);
356
    isrv = get_highest_priority_int(s->isr);
357
    if (isrv < 0)
358
        isrv = 0;
359
    isrv >>= 4;
360
    if (tpr >= isrv)
361
        ppr = s->tpr;
362
    else
363
        ppr = isrv << 4;
364
    return ppr;
365
}
366

    
367
static int apic_get_arb_pri(APICState *s)
368
{
369
    /* XXX: arbitration */
370
    return 0;
371
}
372

    
373
/* signal the CPU if an irq is pending */
374
static void apic_update_irq(APICState *s)
375
{
376
    int irrv, ppr;
377
    if (!(s->spurious_vec & APIC_SV_ENABLE))
378
        return;
379
    irrv = get_highest_priority_int(s->irr);
380
    if (irrv < 0)
381
        return;
382
    ppr = apic_get_ppr(s);
383
    if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
384
        return;
385
    cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
386
}
387

    
388
void apic_reset_irq_delivered(void)
389
{
390
    trace_apic_reset_irq_delivered(apic_irq_delivered);
391

    
392
    apic_irq_delivered = 0;
393
}
394

    
395
int apic_get_irq_delivered(void)
396
{
397
    trace_apic_get_irq_delivered(apic_irq_delivered);
398

    
399
    return apic_irq_delivered;
400
}
401

    
402
static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
403
{
404
    apic_irq_delivered += !get_bit(s->irr, vector_num);
405

    
406
    trace_apic_set_irq(apic_irq_delivered);
407

    
408
    set_bit(s->irr, vector_num);
409
    if (trigger_mode)
410
        set_bit(s->tmr, vector_num);
411
    else
412
        reset_bit(s->tmr, vector_num);
413
    apic_update_irq(s);
414
}
415

    
416
static void apic_eoi(APICState *s)
417
{
418
    int isrv;
419
    isrv = get_highest_priority_int(s->isr);
420
    if (isrv < 0)
421
        return;
422
    reset_bit(s->isr, isrv);
423
    /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
424
            set the remote IRR bit for level triggered interrupts. */
425
    apic_update_irq(s);
426
}
427

    
428
static int apic_find_dest(uint8_t dest)
429
{
430
    APICState *apic = local_apics[dest];
431
    int i;
432

    
433
    if (apic && apic->id == dest)
434
        return dest;  /* shortcut in case apic->id == apic->idx */
435

    
436
    for (i = 0; i < MAX_APICS; i++) {
437
        apic = local_apics[i];
438
        if (apic && apic->id == dest)
439
            return i;
440
    }
441

    
442
    return -1;
443
}
444

    
445
static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
446
                                      uint8_t dest, uint8_t dest_mode)
447
{
448
    APICState *apic_iter;
449
    int i;
450

    
451
    if (dest_mode == 0) {
452
        if (dest == 0xff) {
453
            memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
454
        } else {
455
            int idx = apic_find_dest(dest);
456
            memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
457
            if (idx >= 0)
458
                set_bit(deliver_bitmask, idx);
459
        }
460
    } else {
461
        /* XXX: cluster mode */
462
        memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
463
        for(i = 0; i < MAX_APICS; i++) {
464
            apic_iter = local_apics[i];
465
            if (apic_iter) {
466
                if (apic_iter->dest_mode == 0xf) {
467
                    if (dest & apic_iter->log_dest)
468
                        set_bit(deliver_bitmask, i);
469
                } else if (apic_iter->dest_mode == 0x0) {
470
                    if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
471
                        (dest & apic_iter->log_dest & 0x0f)) {
472
                        set_bit(deliver_bitmask, i);
473
                    }
474
                }
475
            }
476
        }
477
    }
478
}
479

    
480
void apic_init_reset(DeviceState *d)
481
{
482
    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
483
    int i;
484

    
485
    if (!s)
486
        return;
487

    
488
    s->tpr = 0;
489
    s->spurious_vec = 0xff;
490
    s->log_dest = 0;
491
    s->dest_mode = 0xf;
492
    memset(s->isr, 0, sizeof(s->isr));
493
    memset(s->tmr, 0, sizeof(s->tmr));
494
    memset(s->irr, 0, sizeof(s->irr));
495
    for(i = 0; i < APIC_LVT_NB; i++)
496
        s->lvt[i] = 1 << 16; /* mask LVT */
497
    s->esr = 0;
498
    memset(s->icr, 0, sizeof(s->icr));
499
    s->divide_conf = 0;
500
    s->count_shift = 0;
501
    s->initial_count = 0;
502
    s->initial_count_load_time = 0;
503
    s->next_time = 0;
504
    s->wait_for_sipi = 1;
505
}
506

    
507
static void apic_startup(APICState *s, int vector_num)
508
{
509
    s->sipi_vector = vector_num;
510
    cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
511
}
512

    
513
void apic_sipi(DeviceState *d)
514
{
515
    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
516

    
517
    cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
518

    
519
    if (!s->wait_for_sipi)
520
        return;
521
    cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector);
522
    s->wait_for_sipi = 0;
523
}
524

    
525
static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode,
526
                         uint8_t delivery_mode, uint8_t vector_num,
527
                         uint8_t polarity, uint8_t trigger_mode)
528
{
529
    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
530
    uint32_t deliver_bitmask[MAX_APIC_WORDS];
531
    int dest_shorthand = (s->icr[0] >> 18) & 3;
532
    APICState *apic_iter;
533

    
534
    switch (dest_shorthand) {
535
    case 0:
536
        apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
537
        break;
538
    case 1:
539
        memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
540
        set_bit(deliver_bitmask, s->idx);
541
        break;
542
    case 2:
543
        memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
544
        break;
545
    case 3:
546
        memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
547
        reset_bit(deliver_bitmask, s->idx);
548
        break;
549
    }
550

    
551
    switch (delivery_mode) {
552
        case APIC_DM_INIT:
553
            {
554
                int trig_mode = (s->icr[0] >> 15) & 1;
555
                int level = (s->icr[0] >> 14) & 1;
556
                if (level == 0 && trig_mode == 1) {
557
                    foreach_apic(apic_iter, deliver_bitmask,
558
                                 apic_iter->arb_id = apic_iter->id );
559
                    return;
560
                }
561
            }
562
            break;
563

    
564
        case APIC_DM_SIPI:
565
            foreach_apic(apic_iter, deliver_bitmask,
566
                         apic_startup(apic_iter, vector_num) );
567
            return;
568
    }
569

    
570
    apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
571
                     trigger_mode);
572
}
573

    
574
int apic_get_interrupt(DeviceState *d)
575
{
576
    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
577
    int intno;
578

    
579
    /* if the APIC is installed or enabled, we let the 8259 handle the
580
       IRQs */
581
    if (!s)
582
        return -1;
583
    if (!(s->spurious_vec & APIC_SV_ENABLE))
584
        return -1;
585

    
586
    /* XXX: spurious IRQ handling */
587
    intno = get_highest_priority_int(s->irr);
588
    if (intno < 0)
589
        return -1;
590
    if (s->tpr && intno <= s->tpr)
591
        return s->spurious_vec & 0xff;
592
    reset_bit(s->irr, intno);
593
    set_bit(s->isr, intno);
594
    apic_update_irq(s);
595
    return intno;
596
}
597

    
598
int apic_accept_pic_intr(DeviceState *d)
599
{
600
    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
601
    uint32_t lvt0;
602

    
603
    if (!s)
604
        return -1;
605

    
606
    lvt0 = s->lvt[APIC_LVT_LINT0];
607

    
608
    if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
609
        (lvt0 & APIC_LVT_MASKED) == 0)
610
        return 1;
611

    
612
    return 0;
613
}
614

    
615
static uint32_t apic_get_current_count(APICState *s)
616
{
617
    int64_t d;
618
    uint32_t val;
619
    d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
620
        s->count_shift;
621
    if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
622
        /* periodic */
623
        val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
624
    } else {
625
        if (d >= s->initial_count)
626
            val = 0;
627
        else
628
            val = s->initial_count - d;
629
    }
630
    return val;
631
}
632

    
633
static void apic_timer_update(APICState *s, int64_t current_time)
634
{
635
    int64_t next_time, d;
636

    
637
    if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
638
        d = (current_time - s->initial_count_load_time) >>
639
            s->count_shift;
640
        if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
641
            if (!s->initial_count)
642
                goto no_timer;
643
            d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
644
        } else {
645
            if (d >= s->initial_count)
646
                goto no_timer;
647
            d = (uint64_t)s->initial_count + 1;
648
        }
649
        next_time = s->initial_count_load_time + (d << s->count_shift);
650
        qemu_mod_timer(s->timer, next_time);
651
        s->next_time = next_time;
652
    } else {
653
    no_timer:
654
        qemu_del_timer(s->timer);
655
    }
656
}
657

    
658
static void apic_timer(void *opaque)
659
{
660
    APICState *s = opaque;
661

    
662
    apic_local_deliver(s, APIC_LVT_TIMER);
663
    apic_timer_update(s, s->next_time);
664
}
665

    
666
static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
667
{
668
    return 0;
669
}
670

    
671
static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
672
{
673
    return 0;
674
}
675

    
676
static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
677
{
678
}
679

    
680
static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
681
{
682
}
683

    
684
static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
685
{
686
    DeviceState *d;
687
    APICState *s;
688
    uint32_t val;
689
    int index;
690

    
691
    d = cpu_get_current_apic();
692
    if (!d) {
693
        return 0;
694
    }
695
    s = DO_UPCAST(APICState, busdev.qdev, d);
696

    
697
    index = (addr >> 4) & 0xff;
698
    switch(index) {
699
    case 0x02: /* id */
700
        val = s->id << 24;
701
        break;
702
    case 0x03: /* version */
703
        val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
704
        break;
705
    case 0x08:
706
        val = s->tpr;
707
        break;
708
    case 0x09:
709
        val = apic_get_arb_pri(s);
710
        break;
711
    case 0x0a:
712
        /* ppr */
713
        val = apic_get_ppr(s);
714
        break;
715
    case 0x0b:
716
        val = 0;
717
        break;
718
    case 0x0d:
719
        val = s->log_dest << 24;
720
        break;
721
    case 0x0e:
722
        val = s->dest_mode << 28;
723
        break;
724
    case 0x0f:
725
        val = s->spurious_vec;
726
        break;
727
    case 0x10 ... 0x17:
728
        val = s->isr[index & 7];
729
        break;
730
    case 0x18 ... 0x1f:
731
        val = s->tmr[index & 7];
732
        break;
733
    case 0x20 ... 0x27:
734
        val = s->irr[index & 7];
735
        break;
736
    case 0x28:
737
        val = s->esr;
738
        break;
739
    case 0x30:
740
    case 0x31:
741
        val = s->icr[index & 1];
742
        break;
743
    case 0x32 ... 0x37:
744
        val = s->lvt[index - 0x32];
745
        break;
746
    case 0x38:
747
        val = s->initial_count;
748
        break;
749
    case 0x39:
750
        val = apic_get_current_count(s);
751
        break;
752
    case 0x3e:
753
        val = s->divide_conf;
754
        break;
755
    default:
756
        s->esr |= ESR_ILLEGAL_ADDRESS;
757
        val = 0;
758
        break;
759
    }
760
    trace_apic_mem_readl(addr, val);
761
    return val;
762
}
763

    
764
static void apic_send_msi(target_phys_addr_t addr, uint32 data)
765
{
766
    uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
767
    uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
768
    uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
769
    uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
770
    uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
771
    /* XXX: Ignore redirection hint. */
772
    apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
773
}
774

    
775
static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
776
{
777
    DeviceState *d;
778
    APICState *s;
779
    int index = (addr >> 4) & 0xff;
780
    if (addr > 0xfff || !index) {
781
        /* MSI and MMIO APIC are at the same memory location,
782
         * but actually not on the global bus: MSI is on PCI bus
783
         * APIC is connected directly to the CPU.
784
         * Mapping them on the global bus happens to work because
785
         * MSI registers are reserved in APIC MMIO and vice versa. */
786
        apic_send_msi(addr, val);
787
        return;
788
    }
789

    
790
    d = cpu_get_current_apic();
791
    if (!d) {
792
        return;
793
    }
794
    s = DO_UPCAST(APICState, busdev.qdev, d);
795

    
796
    trace_apic_mem_writel(addr, val);
797

    
798
    switch(index) {
799
    case 0x02:
800
        s->id = (val >> 24);
801
        break;
802
    case 0x03:
803
        break;
804
    case 0x08:
805
        s->tpr = val;
806
        apic_update_irq(s);
807
        break;
808
    case 0x09:
809
    case 0x0a:
810
        break;
811
    case 0x0b: /* EOI */
812
        apic_eoi(s);
813
        break;
814
    case 0x0d:
815
        s->log_dest = val >> 24;
816
        break;
817
    case 0x0e:
818
        s->dest_mode = val >> 28;
819
        break;
820
    case 0x0f:
821
        s->spurious_vec = val & 0x1ff;
822
        apic_update_irq(s);
823
        break;
824
    case 0x10 ... 0x17:
825
    case 0x18 ... 0x1f:
826
    case 0x20 ... 0x27:
827
    case 0x28:
828
        break;
829
    case 0x30:
830
        s->icr[0] = val;
831
        apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
832
                     (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
833
                     (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
834
        break;
835
    case 0x31:
836
        s->icr[1] = val;
837
        break;
838
    case 0x32 ... 0x37:
839
        {
840
            int n = index - 0x32;
841
            s->lvt[n] = val;
842
            if (n == APIC_LVT_TIMER)
843
                apic_timer_update(s, qemu_get_clock(vm_clock));
844
        }
845
        break;
846
    case 0x38:
847
        s->initial_count = val;
848
        s->initial_count_load_time = qemu_get_clock(vm_clock);
849
        apic_timer_update(s, s->initial_count_load_time);
850
        break;
851
    case 0x39:
852
        break;
853
    case 0x3e:
854
        {
855
            int v;
856
            s->divide_conf = val & 0xb;
857
            v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
858
            s->count_shift = (v + 1) & 7;
859
        }
860
        break;
861
    default:
862
        s->esr |= ESR_ILLEGAL_ADDRESS;
863
        break;
864
    }
865
}
866

    
867
/* This function is only used for old state version 1 and 2 */
868
static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
869
{
870
    APICState *s = opaque;
871
    int i;
872

    
873
    if (version_id > 2)
874
        return -EINVAL;
875

    
876
    /* XXX: what if the base changes? (registered memory regions) */
877
    qemu_get_be32s(f, &s->apicbase);
878
    qemu_get_8s(f, &s->id);
879
    qemu_get_8s(f, &s->arb_id);
880
    qemu_get_8s(f, &s->tpr);
881
    qemu_get_be32s(f, &s->spurious_vec);
882
    qemu_get_8s(f, &s->log_dest);
883
    qemu_get_8s(f, &s->dest_mode);
884
    for (i = 0; i < 8; i++) {
885
        qemu_get_be32s(f, &s->isr[i]);
886
        qemu_get_be32s(f, &s->tmr[i]);
887
        qemu_get_be32s(f, &s->irr[i]);
888
    }
889
    for (i = 0; i < APIC_LVT_NB; i++) {
890
        qemu_get_be32s(f, &s->lvt[i]);
891
    }
892
    qemu_get_be32s(f, &s->esr);
893
    qemu_get_be32s(f, &s->icr[0]);
894
    qemu_get_be32s(f, &s->icr[1]);
895
    qemu_get_be32s(f, &s->divide_conf);
896
    s->count_shift=qemu_get_be32(f);
897
    qemu_get_be32s(f, &s->initial_count);
898
    s->initial_count_load_time=qemu_get_be64(f);
899
    s->next_time=qemu_get_be64(f);
900

    
901
    if (version_id >= 2)
902
        qemu_get_timer(f, s->timer);
903
    return 0;
904
}
905

    
906
static const VMStateDescription vmstate_apic = {
907
    .name = "apic",
908
    .version_id = 3,
909
    .minimum_version_id = 3,
910
    .minimum_version_id_old = 1,
911
    .load_state_old = apic_load_old,
912
    .fields      = (VMStateField []) {
913
        VMSTATE_UINT32(apicbase, APICState),
914
        VMSTATE_UINT8(id, APICState),
915
        VMSTATE_UINT8(arb_id, APICState),
916
        VMSTATE_UINT8(tpr, APICState),
917
        VMSTATE_UINT32(spurious_vec, APICState),
918
        VMSTATE_UINT8(log_dest, APICState),
919
        VMSTATE_UINT8(dest_mode, APICState),
920
        VMSTATE_UINT32_ARRAY(isr, APICState, 8),
921
        VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
922
        VMSTATE_UINT32_ARRAY(irr, APICState, 8),
923
        VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB),
924
        VMSTATE_UINT32(esr, APICState),
925
        VMSTATE_UINT32_ARRAY(icr, APICState, 2),
926
        VMSTATE_UINT32(divide_conf, APICState),
927
        VMSTATE_INT32(count_shift, APICState),
928
        VMSTATE_UINT32(initial_count, APICState),
929
        VMSTATE_INT64(initial_count_load_time, APICState),
930
        VMSTATE_INT64(next_time, APICState),
931
        VMSTATE_TIMER(timer, APICState),
932
        VMSTATE_END_OF_LIST()
933
    }
934
};
935

    
936
static void apic_reset(DeviceState *d)
937
{
938
    APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
939
    int bsp;
940

    
941
    bsp = cpu_is_bsp(s->cpu_env);
942
    s->apicbase = 0xfee00000 |
943
        (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
944

    
945
    apic_init_reset(d);
946

    
947
    if (bsp) {
948
        /*
949
         * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
950
         * time typically by BIOS, so PIC interrupt can be delivered to the
951
         * processor when local APIC is enabled.
952
         */
953
        s->lvt[APIC_LVT_LINT0] = 0x700;
954
    }
955
}
956

    
957
static CPUReadMemoryFunc * const apic_mem_read[3] = {
958
    apic_mem_readb,
959
    apic_mem_readw,
960
    apic_mem_readl,
961
};
962

    
963
static CPUWriteMemoryFunc * const apic_mem_write[3] = {
964
    apic_mem_writeb,
965
    apic_mem_writew,
966
    apic_mem_writel,
967
};
968

    
969
static int apic_init1(SysBusDevice *dev)
970
{
971
    APICState *s = FROM_SYSBUS(APICState, dev);
972
    int apic_io_memory;
973
    static int last_apic_idx;
974

    
975
    if (last_apic_idx >= MAX_APICS) {
976
        return -1;
977
    }
978
    apic_io_memory = cpu_register_io_memory(apic_mem_read,
979
                                            apic_mem_write, NULL);
980
    sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory);
981

    
982
    s->timer = qemu_new_timer(vm_clock, apic_timer, s);
983
    s->idx = last_apic_idx++;
984
    local_apics[s->idx] = s;
985
    return 0;
986
}
987

    
988
static SysBusDeviceInfo apic_info = {
989
    .init = apic_init1,
990
    .qdev.name = "apic",
991
    .qdev.size = sizeof(APICState),
992
    .qdev.vmsd = &vmstate_apic,
993
    .qdev.reset = apic_reset,
994
    .qdev.no_user = 1,
995
    .qdev.props = (Property[]) {
996
        DEFINE_PROP_UINT8("id", APICState, id, -1),
997
        DEFINE_PROP_PTR("cpu_env", APICState, cpu_env),
998
        DEFINE_PROP_END_OF_LIST(),
999
    }
1000
};
1001

    
1002
static void apic_register_devices(void)
1003
{
1004
    sysbus_register_withprop(&apic_info);
1005
}
1006

    
1007
device_init(apic_register_devices)