Revision d82310f7 hw/omap2.c
| b/hw/omap2.c | ||
|---|---|---|
| 559 | 559 |
omap_synctimer_readfn, omap_synctimer_writefn, s)); |
| 560 | 560 |
} |
| 561 | 561 |
|
| 562 |
/* General-Purpose Interface of OMAP2 */ |
|
| 563 |
struct omap2_gpio_s {
|
|
| 564 |
qemu_irq irq[2]; |
|
| 565 |
qemu_irq wkup; |
|
| 566 |
qemu_irq *in; |
|
| 567 |
qemu_irq handler[32]; |
|
| 568 |
|
|
| 569 |
uint8_t config[2]; |
|
| 570 |
uint32_t inputs; |
|
| 571 |
uint32_t outputs; |
|
| 572 |
uint32_t dir; |
|
| 573 |
uint32_t level[2]; |
|
| 574 |
uint32_t edge[2]; |
|
| 575 |
uint32_t mask[2]; |
|
| 576 |
uint32_t wumask; |
|
| 577 |
uint32_t ints[2]; |
|
| 578 |
uint32_t debounce; |
|
| 579 |
uint8_t delay; |
|
| 580 |
}; |
|
| 581 |
|
|
| 582 |
static inline void omap_gpio_module_int_update(struct omap2_gpio_s *s, |
|
| 583 |
int line) |
|
| 584 |
{
|
|
| 585 |
qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]); |
|
| 586 |
} |
|
| 587 |
|
|
| 588 |
static void omap_gpio_module_wake(struct omap2_gpio_s *s, int line) |
|
| 589 |
{
|
|
| 590 |
if (!(s->config[0] & (1 << 2))) /* ENAWAKEUP */ |
|
| 591 |
return; |
|
| 592 |
if (!(s->config[0] & (3 << 3))) /* Force Idle */ |
|
| 593 |
return; |
|
| 594 |
if (!(s->wumask & (1 << line))) |
|
| 595 |
return; |
|
| 596 |
|
|
| 597 |
qemu_irq_raise(s->wkup); |
|
| 598 |
} |
|
| 599 |
|
|
| 600 |
static inline void omap_gpio_module_out_update(struct omap2_gpio_s *s, |
|
| 601 |
uint32_t diff) |
|
| 602 |
{
|
|
| 603 |
int ln; |
|
| 604 |
|
|
| 605 |
s->outputs ^= diff; |
|
| 606 |
diff &= ~s->dir; |
|
| 607 |
while ((ln = ffs(diff))) {
|
|
| 608 |
ln --; |
|
| 609 |
qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1); |
|
| 610 |
diff &= ~(1 << ln); |
|
| 611 |
} |
|
| 612 |
} |
|
| 613 |
|
|
| 614 |
static void omap_gpio_module_level_update(struct omap2_gpio_s *s, int line) |
|
| 615 |
{
|
|
| 616 |
s->ints[line] |= s->dir & |
|
| 617 |
((s->inputs & s->level[1]) | (~s->inputs & s->level[0])); |
|
| 618 |
omap_gpio_module_int_update(s, line); |
|
| 619 |
} |
|
| 620 |
|
|
| 621 |
static inline void omap_gpio_module_int(struct omap2_gpio_s *s, int line) |
|
| 622 |
{
|
|
| 623 |
s->ints[0] |= 1 << line; |
|
| 624 |
omap_gpio_module_int_update(s, 0); |
|
| 625 |
s->ints[1] |= 1 << line; |
|
| 626 |
omap_gpio_module_int_update(s, 1); |
|
| 627 |
omap_gpio_module_wake(s, line); |
|
| 628 |
} |
|
| 629 |
|
|
| 630 |
static void omap_gpio_module_set(void *opaque, int line, int level) |
|
| 631 |
{
|
|
| 632 |
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; |
|
| 633 |
|
|
| 634 |
if (level) {
|
|
| 635 |
if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1])) |
|
| 636 |
omap_gpio_module_int(s, line); |
|
| 637 |
s->inputs |= 1 << line; |
|
| 638 |
} else {
|
|
| 639 |
if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0])) |
|
| 640 |
omap_gpio_module_int(s, line); |
|
| 641 |
s->inputs &= ~(1 << line); |
|
| 642 |
} |
|
| 643 |
} |
|
| 644 |
|
|
| 645 |
static void omap_gpio_module_reset(struct omap2_gpio_s *s) |
|
| 646 |
{
|
|
| 647 |
s->config[0] = 0; |
|
| 648 |
s->config[1] = 2; |
|
| 649 |
s->ints[0] = 0; |
|
| 650 |
s->ints[1] = 0; |
|
| 651 |
s->mask[0] = 0; |
|
| 652 |
s->mask[1] = 0; |
|
| 653 |
s->wumask = 0; |
|
| 654 |
s->dir = ~0; |
|
| 655 |
s->level[0] = 0; |
|
| 656 |
s->level[1] = 0; |
|
| 657 |
s->edge[0] = 0; |
|
| 658 |
s->edge[1] = 0; |
|
| 659 |
s->debounce = 0; |
|
| 660 |
s->delay = 0; |
|
| 661 |
} |
|
| 662 |
|
|
| 663 |
static uint32_t omap_gpio_module_read(void *opaque, target_phys_addr_t addr) |
|
| 664 |
{
|
|
| 665 |
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; |
|
| 666 |
|
|
| 667 |
switch (addr) {
|
|
| 668 |
case 0x00: /* GPIO_REVISION */ |
|
| 669 |
return 0x18; |
|
| 670 |
|
|
| 671 |
case 0x10: /* GPIO_SYSCONFIG */ |
|
| 672 |
return s->config[0]; |
|
| 673 |
|
|
| 674 |
case 0x14: /* GPIO_SYSSTATUS */ |
|
| 675 |
return 0x01; |
|
| 676 |
|
|
| 677 |
case 0x18: /* GPIO_IRQSTATUS1 */ |
|
| 678 |
return s->ints[0]; |
|
| 679 |
|
|
| 680 |
case 0x1c: /* GPIO_IRQENABLE1 */ |
|
| 681 |
case 0x60: /* GPIO_CLEARIRQENABLE1 */ |
|
| 682 |
case 0x64: /* GPIO_SETIRQENABLE1 */ |
|
| 683 |
return s->mask[0]; |
|
| 684 |
|
|
| 685 |
case 0x20: /* GPIO_WAKEUPENABLE */ |
|
| 686 |
case 0x80: /* GPIO_CLEARWKUENA */ |
|
| 687 |
case 0x84: /* GPIO_SETWKUENA */ |
|
| 688 |
return s->wumask; |
|
| 689 |
|
|
| 690 |
case 0x28: /* GPIO_IRQSTATUS2 */ |
|
| 691 |
return s->ints[1]; |
|
| 692 |
|
|
| 693 |
case 0x2c: /* GPIO_IRQENABLE2 */ |
|
| 694 |
case 0x70: /* GPIO_CLEARIRQENABLE2 */ |
|
| 695 |
case 0x74: /* GPIO_SETIREQNEABLE2 */ |
|
| 696 |
return s->mask[1]; |
|
| 697 |
|
|
| 698 |
case 0x30: /* GPIO_CTRL */ |
|
| 699 |
return s->config[1]; |
|
| 700 |
|
|
| 701 |
case 0x34: /* GPIO_OE */ |
|
| 702 |
return s->dir; |
|
| 703 |
|
|
| 704 |
case 0x38: /* GPIO_DATAIN */ |
|
| 705 |
return s->inputs; |
|
| 706 |
|
|
| 707 |
case 0x3c: /* GPIO_DATAOUT */ |
|
| 708 |
case 0x90: /* GPIO_CLEARDATAOUT */ |
|
| 709 |
case 0x94: /* GPIO_SETDATAOUT */ |
|
| 710 |
return s->outputs; |
|
| 711 |
|
|
| 712 |
case 0x40: /* GPIO_LEVELDETECT0 */ |
|
| 713 |
return s->level[0]; |
|
| 714 |
|
|
| 715 |
case 0x44: /* GPIO_LEVELDETECT1 */ |
|
| 716 |
return s->level[1]; |
|
| 717 |
|
|
| 718 |
case 0x48: /* GPIO_RISINGDETECT */ |
|
| 719 |
return s->edge[0]; |
|
| 720 |
|
|
| 721 |
case 0x4c: /* GPIO_FALLINGDETECT */ |
|
| 722 |
return s->edge[1]; |
|
| 723 |
|
|
| 724 |
case 0x50: /* GPIO_DEBOUNCENABLE */ |
|
| 725 |
return s->debounce; |
|
| 726 |
|
|
| 727 |
case 0x54: /* GPIO_DEBOUNCINGTIME */ |
|
| 728 |
return s->delay; |
|
| 729 |
} |
|
| 730 |
|
|
| 731 |
OMAP_BAD_REG(addr); |
|
| 732 |
return 0; |
|
| 733 |
} |
|
| 734 |
|
|
| 735 |
static void omap_gpio_module_write(void *opaque, target_phys_addr_t addr, |
|
| 736 |
uint32_t value) |
|
| 737 |
{
|
|
| 738 |
struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque; |
|
| 739 |
uint32_t diff; |
|
| 740 |
int ln; |
|
| 741 |
|
|
| 742 |
switch (addr) {
|
|
| 743 |
case 0x00: /* GPIO_REVISION */ |
|
| 744 |
case 0x14: /* GPIO_SYSSTATUS */ |
|
| 745 |
case 0x38: /* GPIO_DATAIN */ |
|
| 746 |
OMAP_RO_REG(addr); |
|
| 747 |
break; |
|
| 748 |
|
|
| 749 |
case 0x10: /* GPIO_SYSCONFIG */ |
|
| 750 |
if (((value >> 3) & 3) == 3) |
|
| 751 |
fprintf(stderr, "%s: bad IDLEMODE value\n", __FUNCTION__); |
|
| 752 |
if (value & 2) |
|
| 753 |
omap_gpio_module_reset(s); |
|
| 754 |
s->config[0] = value & 0x1d; |
|
| 755 |
break; |
|
| 756 |
|
|
| 757 |
case 0x18: /* GPIO_IRQSTATUS1 */ |
|
| 758 |
if (s->ints[0] & value) {
|
|
| 759 |
s->ints[0] &= ~value; |
|
| 760 |
omap_gpio_module_level_update(s, 0); |
|
| 761 |
} |
|
| 762 |
break; |
|
| 763 |
|
|
| 764 |
case 0x1c: /* GPIO_IRQENABLE1 */ |
|
| 765 |
s->mask[0] = value; |
|
| 766 |
omap_gpio_module_int_update(s, 0); |
|
| 767 |
break; |
|
| 768 |
|
|
| 769 |
case 0x20: /* GPIO_WAKEUPENABLE */ |
|
| 770 |
s->wumask = value; |
|
| 771 |
break; |
|
| 772 |
|
|
| 773 |
case 0x28: /* GPIO_IRQSTATUS2 */ |
|
| 774 |
if (s->ints[1] & value) {
|
|
| 775 |
s->ints[1] &= ~value; |
|
| 776 |
omap_gpio_module_level_update(s, 1); |
|
| 777 |
} |
|
| 778 |
break; |
|
| 779 |
|
|
| 780 |
case 0x2c: /* GPIO_IRQENABLE2 */ |
|
| 781 |
s->mask[1] = value; |
|
| 782 |
omap_gpio_module_int_update(s, 1); |
|
| 783 |
break; |
|
| 784 |
|
|
| 785 |
case 0x30: /* GPIO_CTRL */ |
|
| 786 |
s->config[1] = value & 7; |
|
| 787 |
break; |
|
| 788 |
|
|
| 789 |
case 0x34: /* GPIO_OE */ |
|
| 790 |
diff = s->outputs & (s->dir ^ value); |
|
| 791 |
s->dir = value; |
|
| 792 |
|
|
| 793 |
value = s->outputs & ~s->dir; |
|
| 794 |
while ((ln = ffs(diff))) {
|
|
| 795 |
diff &= ~(1 <<-- ln); |
|
| 796 |
qemu_set_irq(s->handler[ln], (value >> ln) & 1); |
|
| 797 |
} |
|
| 798 |
|
|
| 799 |
omap_gpio_module_level_update(s, 0); |
|
| 800 |
omap_gpio_module_level_update(s, 1); |
|
| 801 |
break; |
|
| 802 |
|
|
| 803 |
case 0x3c: /* GPIO_DATAOUT */ |
|
| 804 |
omap_gpio_module_out_update(s, s->outputs ^ value); |
|
| 805 |
break; |
|
| 806 |
|
|
| 807 |
case 0x40: /* GPIO_LEVELDETECT0 */ |
|
| 808 |
s->level[0] = value; |
|
| 809 |
omap_gpio_module_level_update(s, 0); |
|
| 810 |
omap_gpio_module_level_update(s, 1); |
|
| 811 |
break; |
|
| 812 |
|
|
| 813 |
case 0x44: /* GPIO_LEVELDETECT1 */ |
|
| 814 |
s->level[1] = value; |
|
| 815 |
omap_gpio_module_level_update(s, 0); |
|
| 816 |
omap_gpio_module_level_update(s, 1); |
|
| 817 |
break; |
|
| 818 |
|
|
| 819 |
case 0x48: /* GPIO_RISINGDETECT */ |
|
| 820 |
s->edge[0] = value; |
|
| 821 |
break; |
|
| 822 |
|
|
| 823 |
case 0x4c: /* GPIO_FALLINGDETECT */ |
|
| 824 |
s->edge[1] = value; |
|
| 825 |
break; |
|
| 826 |
|
|
| 827 |
case 0x50: /* GPIO_DEBOUNCENABLE */ |
|
| 828 |
s->debounce = value; |
|
| 829 |
break; |
|
| 830 |
|
|
| 831 |
case 0x54: /* GPIO_DEBOUNCINGTIME */ |
|
| 832 |
s->delay = value; |
|
| 833 |
break; |
|
| 834 |
|
|
| 835 |
case 0x60: /* GPIO_CLEARIRQENABLE1 */ |
|
| 836 |
s->mask[0] &= ~value; |
|
| 837 |
omap_gpio_module_int_update(s, 0); |
|
| 838 |
break; |
|
| 839 |
|
|
| 840 |
case 0x64: /* GPIO_SETIRQENABLE1 */ |
|
| 841 |
s->mask[0] |= value; |
|
| 842 |
omap_gpio_module_int_update(s, 0); |
|
| 843 |
break; |
|
| 844 |
|
|
| 845 |
case 0x70: /* GPIO_CLEARIRQENABLE2 */ |
|
| 846 |
s->mask[1] &= ~value; |
|
| 847 |
omap_gpio_module_int_update(s, 1); |
|
| 848 |
break; |
|
| 849 |
|
|
| 850 |
case 0x74: /* GPIO_SETIREQNEABLE2 */ |
|
| 851 |
s->mask[1] |= value; |
|
| 852 |
omap_gpio_module_int_update(s, 1); |
|
| 853 |
break; |
|
| 854 |
|
|
| 855 |
case 0x80: /* GPIO_CLEARWKUENA */ |
|
| 856 |
s->wumask &= ~value; |
|
| 857 |
break; |
|
| 858 |
|
|
| 859 |
case 0x84: /* GPIO_SETWKUENA */ |
|
| 860 |
s->wumask |= value; |
|
| 861 |
break; |
|
| 862 |
|
|
| 863 |
case 0x90: /* GPIO_CLEARDATAOUT */ |
|
| 864 |
omap_gpio_module_out_update(s, s->outputs & value); |
|
| 865 |
break; |
|
| 866 |
|
|
| 867 |
case 0x94: /* GPIO_SETDATAOUT */ |
|
| 868 |
omap_gpio_module_out_update(s, ~s->outputs & value); |
|
| 869 |
break; |
|
| 870 |
|
|
| 871 |
default: |
|
| 872 |
OMAP_BAD_REG(addr); |
|
| 873 |
return; |
|
| 874 |
} |
|
| 875 |
} |
|
| 876 |
|
|
| 877 |
static uint32_t omap_gpio_module_readp(void *opaque, target_phys_addr_t addr) |
|
| 878 |
{
|
|
| 879 |
return omap_gpio_module_readp(opaque, addr) >> ((addr & 3) << 3); |
|
| 880 |
} |
|
| 881 |
|
|
| 882 |
static void omap_gpio_module_writep(void *opaque, target_phys_addr_t addr, |
|
| 883 |
uint32_t value) |
|
| 884 |
{
|
|
| 885 |
uint32_t cur = 0; |
|
| 886 |
uint32_t mask = 0xffff; |
|
| 887 |
|
|
| 888 |
switch (addr & ~3) {
|
|
| 889 |
case 0x00: /* GPIO_REVISION */ |
|
| 890 |
case 0x14: /* GPIO_SYSSTATUS */ |
|
| 891 |
case 0x38: /* GPIO_DATAIN */ |
|
| 892 |
OMAP_RO_REG(addr); |
|
| 893 |
break; |
|
| 894 |
|
|
| 895 |
case 0x10: /* GPIO_SYSCONFIG */ |
|
| 896 |
case 0x1c: /* GPIO_IRQENABLE1 */ |
|
| 897 |
case 0x20: /* GPIO_WAKEUPENABLE */ |
|
| 898 |
case 0x2c: /* GPIO_IRQENABLE2 */ |
|
| 899 |
case 0x30: /* GPIO_CTRL */ |
|
| 900 |
case 0x34: /* GPIO_OE */ |
|
| 901 |
case 0x3c: /* GPIO_DATAOUT */ |
|
| 902 |
case 0x40: /* GPIO_LEVELDETECT0 */ |
|
| 903 |
case 0x44: /* GPIO_LEVELDETECT1 */ |
|
| 904 |
case 0x48: /* GPIO_RISINGDETECT */ |
|
| 905 |
case 0x4c: /* GPIO_FALLINGDETECT */ |
|
| 906 |
case 0x50: /* GPIO_DEBOUNCENABLE */ |
|
| 907 |
case 0x54: /* GPIO_DEBOUNCINGTIME */ |
|
| 908 |
cur = omap_gpio_module_read(opaque, addr & ~3) & |
|
| 909 |
~(mask << ((addr & 3) << 3)); |
|
| 910 |
|
|
| 911 |
/* Fall through. */ |
|
| 912 |
case 0x18: /* GPIO_IRQSTATUS1 */ |
|
| 913 |
case 0x28: /* GPIO_IRQSTATUS2 */ |
|
| 914 |
case 0x60: /* GPIO_CLEARIRQENABLE1 */ |
|
| 915 |
case 0x64: /* GPIO_SETIRQENABLE1 */ |
|
| 916 |
case 0x70: /* GPIO_CLEARIRQENABLE2 */ |
|
| 917 |
case 0x74: /* GPIO_SETIREQNEABLE2 */ |
|
| 918 |
case 0x80: /* GPIO_CLEARWKUENA */ |
|
| 919 |
case 0x84: /* GPIO_SETWKUENA */ |
|
| 920 |
case 0x90: /* GPIO_CLEARDATAOUT */ |
|
| 921 |
case 0x94: /* GPIO_SETDATAOUT */ |
|
| 922 |
value <<= (addr & 3) << 3; |
|
| 923 |
omap_gpio_module_write(opaque, addr, cur | value); |
|
| 924 |
break; |
|
| 925 |
|
|
| 926 |
default: |
|
| 927 |
OMAP_BAD_REG(addr); |
|
| 928 |
return; |
|
| 929 |
} |
|
| 930 |
} |
|
| 931 |
|
|
| 932 |
static CPUReadMemoryFunc * const omap_gpio_module_readfn[] = {
|
|
| 933 |
omap_gpio_module_readp, |
|
| 934 |
omap_gpio_module_readp, |
|
| 935 |
omap_gpio_module_read, |
|
| 936 |
}; |
|
| 937 |
|
|
| 938 |
static CPUWriteMemoryFunc * const omap_gpio_module_writefn[] = {
|
|
| 939 |
omap_gpio_module_writep, |
|
| 940 |
omap_gpio_module_writep, |
|
| 941 |
omap_gpio_module_write, |
|
| 942 |
}; |
|
| 943 |
|
|
| 944 |
static void omap_gpio_module_init(struct omap2_gpio_s *s, |
|
| 945 |
struct omap_target_agent_s *ta, int region, |
|
| 946 |
qemu_irq mpu, qemu_irq dsp, qemu_irq wkup, |
|
| 947 |
omap_clk fclk, omap_clk iclk) |
|
| 948 |
{
|
|
| 949 |
int iomemtype; |
|
| 950 |
|
|
| 951 |
s->irq[0] = mpu; |
|
| 952 |
s->irq[1] = dsp; |
|
| 953 |
s->wkup = wkup; |
|
| 954 |
s->in = qemu_allocate_irqs(omap_gpio_module_set, s, 32); |
|
| 955 |
|
|
| 956 |
iomemtype = l4_register_io_memory(omap_gpio_module_readfn, |
|
| 957 |
omap_gpio_module_writefn, s); |
|
| 958 |
omap_l4_attach(ta, region, iomemtype); |
|
| 959 |
} |
|
| 960 |
|
|
| 961 |
struct omap_gpif_s {
|
|
| 962 |
struct omap2_gpio_s module[5]; |
|
| 963 |
int modules; |
|
| 964 |
|
|
| 965 |
int autoidle; |
|
| 966 |
int gpo; |
|
| 967 |
}; |
|
| 968 |
|
|
| 969 |
static void omap_gpif_reset(struct omap_gpif_s *s) |
|
| 970 |
{
|
|
| 971 |
int i; |
|
| 972 |
|
|
| 973 |
for (i = 0; i < s->modules; i ++) |
|
| 974 |
omap_gpio_module_reset(s->module + i); |
|
| 975 |
|
|
| 976 |
s->autoidle = 0; |
|
| 977 |
s->gpo = 0; |
|
| 978 |
} |
|
| 979 |
|
|
| 980 |
static uint32_t omap_gpif_top_read(void *opaque, target_phys_addr_t addr) |
|
| 981 |
{
|
|
| 982 |
struct omap_gpif_s *s = (struct omap_gpif_s *) opaque; |
|
| 983 |
|
|
| 984 |
switch (addr) {
|
|
| 985 |
case 0x00: /* IPGENERICOCPSPL_REVISION */ |
|
| 986 |
return 0x18; |
|
| 987 |
|
|
| 988 |
case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ |
|
| 989 |
return s->autoidle; |
|
| 990 |
|
|
| 991 |
case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ |
|
| 992 |
return 0x01; |
|
| 993 |
|
|
| 994 |
case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ |
|
| 995 |
return 0x00; |
|
| 996 |
|
|
| 997 |
case 0x40: /* IPGENERICOCPSPL_GPO */ |
|
| 998 |
return s->gpo; |
|
| 999 |
|
|
| 1000 |
case 0x50: /* IPGENERICOCPSPL_GPI */ |
|
| 1001 |
return 0x00; |
|
| 1002 |
} |
|
| 1003 |
|
|
| 1004 |
OMAP_BAD_REG(addr); |
|
| 1005 |
return 0; |
|
| 1006 |
} |
|
| 1007 |
|
|
| 1008 |
static void omap_gpif_top_write(void *opaque, target_phys_addr_t addr, |
|
| 1009 |
uint32_t value) |
|
| 1010 |
{
|
|
| 1011 |
struct omap_gpif_s *s = (struct omap_gpif_s *) opaque; |
|
| 1012 |
|
|
| 1013 |
switch (addr) {
|
|
| 1014 |
case 0x00: /* IPGENERICOCPSPL_REVISION */ |
|
| 1015 |
case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */ |
|
| 1016 |
case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */ |
|
| 1017 |
case 0x50: /* IPGENERICOCPSPL_GPI */ |
|
| 1018 |
OMAP_RO_REG(addr); |
|
| 1019 |
break; |
|
| 1020 |
|
|
| 1021 |
case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */ |
|
| 1022 |
if (value & (1 << 1)) /* SOFTRESET */ |
|
| 1023 |
omap_gpif_reset(s); |
|
| 1024 |
s->autoidle = value & 1; |
|
| 1025 |
break; |
|
| 1026 |
|
|
| 1027 |
case 0x40: /* IPGENERICOCPSPL_GPO */ |
|
| 1028 |
s->gpo = value & 1; |
|
| 1029 |
break; |
|
| 1030 |
|
|
| 1031 |
default: |
|
| 1032 |
OMAP_BAD_REG(addr); |
|
| 1033 |
return; |
|
| 1034 |
} |
|
| 1035 |
} |
|
| 1036 |
|
|
| 1037 |
static CPUReadMemoryFunc * const omap_gpif_top_readfn[] = {
|
|
| 1038 |
omap_gpif_top_read, |
|
| 1039 |
omap_gpif_top_read, |
|
| 1040 |
omap_gpif_top_read, |
|
| 1041 |
}; |
|
| 1042 |
|
|
| 1043 |
static CPUWriteMemoryFunc * const omap_gpif_top_writefn[] = {
|
|
| 1044 |
omap_gpif_top_write, |
|
| 1045 |
omap_gpif_top_write, |
|
| 1046 |
omap_gpif_top_write, |
|
| 1047 |
}; |
|
| 1048 |
|
|
| 1049 |
struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta, |
|
| 1050 |
qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules) |
|
| 1051 |
{
|
|
| 1052 |
int iomemtype, i; |
|
| 1053 |
struct omap_gpif_s *s = (struct omap_gpif_s *) |
|
| 1054 |
qemu_mallocz(sizeof(struct omap_gpif_s)); |
|
| 1055 |
int region[4] = { 0, 2, 4, 5 };
|
|
| 1056 |
|
|
| 1057 |
s->modules = modules; |
|
| 1058 |
for (i = 0; i < modules; i ++) |
|
| 1059 |
omap_gpio_module_init(s->module + i, ta, region[i], |
|
| 1060 |
irq[i], NULL, NULL, fclk[i], iclk); |
|
| 1061 |
|
|
| 1062 |
omap_gpif_reset(s); |
|
| 1063 |
|
|
| 1064 |
iomemtype = l4_register_io_memory(omap_gpif_top_readfn, |
|
| 1065 |
omap_gpif_top_writefn, s); |
|
| 1066 |
omap_l4_attach(ta, 1, iomemtype); |
|
| 1067 |
|
|
| 1068 |
return s; |
|
| 1069 |
} |
|
| 1070 |
|
|
| 1071 |
qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start) |
|
| 1072 |
{
|
|
| 1073 |
if (start >= s->modules * 32 || start < 0) |
|
| 1074 |
hw_error("%s: No GPIO line %i\n", __FUNCTION__, start);
|
|
| 1075 |
return s->module[start >> 5].in + (start & 31); |
|
| 1076 |
} |
|
| 1077 |
|
|
| 1078 |
void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler) |
|
| 1079 |
{
|
|
| 1080 |
if (line >= s->modules * 32 || line < 0) |
|
| 1081 |
hw_error("%s: No GPIO line %i\n", __FUNCTION__, line);
|
|
| 1082 |
s->module[line >> 5].handler[line & 31] = handler; |
|
| 1083 |
} |
|
| 1084 |
|
|
| 1085 | 562 |
/* Multichannel SPI */ |
| 1086 | 563 |
struct omap_mcspi_s {
|
| 1087 | 564 |
qemu_irq irq; |
Also available in: Unified diff