Revision d84bda46
b/cpu-exec.c | ||
---|---|---|
416 | 416 |
#elif defined(TARGET_PPC) |
417 | 417 |
#if 0 |
418 | 418 |
if ((interrupt_request & CPU_INTERRUPT_RESET)) { |
419 |
cpu_ppc_reset(env);
|
|
419 |
cpu_reset(env); |
|
420 | 420 |
} |
421 | 421 |
#endif |
422 | 422 |
if (interrupt_request & CPU_INTERRUPT_HARD) { |
b/hw/ppc.c | ||
---|---|---|
123 | 123 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
124 | 124 |
/* XXX: TOFIX */ |
125 | 125 |
#if 0 |
126 |
cpu_ppc_reset(env);
|
|
126 |
cpu_reset(env); |
|
127 | 127 |
#else |
128 | 128 |
qemu_system_reset_request(); |
129 | 129 |
#endif |
... | ... | |
1088 | 1088 |
#if 0 |
1089 | 1089 |
/*****************************************************************************/ |
1090 | 1090 |
/* Handle system reset (for now, just stop emulation) */ |
1091 |
void cpu_ppc_reset (CPUState *env)
|
|
1091 |
void cpu_reset(CPUState *env)
|
|
1092 | 1092 |
{ |
1093 | 1093 |
printf("Reset asked... Stop emulation\n"); |
1094 | 1094 |
abort(); |
b/hw/ppc405_uc.c | ||
---|---|---|
1805 | 1805 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
1806 | 1806 |
/* XXX: TOFIX */ |
1807 | 1807 |
#if 0 |
1808 |
cpu_ppc_reset(env);
|
|
1808 |
cpu_reset(env); |
|
1809 | 1809 |
#else |
1810 | 1810 |
qemu_system_reset_request(); |
1811 | 1811 |
#endif |
... | ... | |
1823 | 1823 |
env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
1824 | 1824 |
/* XXX: TOFIX */ |
1825 | 1825 |
#if 0 |
1826 |
cpu_ppc_reset(env);
|
|
1826 |
cpu_reset(env); |
|
1827 | 1827 |
#else |
1828 | 1828 |
qemu_system_reset_request(); |
1829 | 1829 |
#endif |
b/hw/ppc4xx_devs.c | ||
---|---|---|
60 | 60 |
tb_clk->opaque = env; |
61 | 61 |
ppc_dcr_init(env, NULL, NULL); |
62 | 62 |
/* Register qemu callbacks */ |
63 |
qemu_register_reset(&cpu_ppc_reset, env);
|
|
63 |
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
|
|
64 | 64 |
|
65 | 65 |
return env; |
66 | 66 |
} |
b/hw/ppc_newworld.c | ||
---|---|---|
130 | 130 |
#if 0 |
131 | 131 |
env->osi_call = vga_osi_call; |
132 | 132 |
#endif |
133 |
qemu_register_reset(&cpu_ppc_reset, env);
|
|
133 |
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
|
|
134 | 134 |
envs[i] = env; |
135 | 135 |
} |
136 | 136 |
|
b/hw/ppc_oldworld.c | ||
---|---|---|
158 | 158 |
/* Set time-base frequency to 16.6 Mhz */ |
159 | 159 |
cpu_ppc_tb_init(env, 16600000UL); |
160 | 160 |
env->osi_call = vga_osi_call; |
161 |
qemu_register_reset(&cpu_ppc_reset, env);
|
|
161 |
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
|
|
162 | 162 |
envs[i] = env; |
163 | 163 |
} |
164 | 164 |
|
b/hw/ppc_prep.c | ||
---|---|---|
586 | 586 |
/* Set time-base frequency to 100 Mhz */ |
587 | 587 |
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
588 | 588 |
} |
589 |
qemu_register_reset(&cpu_ppc_reset, env);
|
|
589 |
qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
|
|
590 | 590 |
envs[i] = env; |
591 | 591 |
} |
592 | 592 |
|
b/target-ppc/cpu.h | ||
---|---|---|
734 | 734 |
#endif /* !defined(CONFIG_USER_ONLY) */ |
735 | 735 |
void ppc_store_msr (CPUPPCState *env, target_ulong value); |
736 | 736 |
|
737 |
void cpu_ppc_reset (void *opaque); |
|
738 |
|
|
739 | 737 |
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
740 | 738 |
|
741 | 739 |
const ppc_def_t *cpu_ppc_find_by_name (const char *name); |
b/target-ppc/helper.c | ||
---|---|---|
2748 | 2748 |
TARGET_FMT_lx "\n", RA, msr); |
2749 | 2749 |
} |
2750 | 2750 |
|
2751 |
void cpu_ppc_reset (void *opaque)
|
|
2751 |
void cpu_reset(CPUPPCState *env)
|
|
2752 | 2752 |
{ |
2753 |
CPUPPCState *env = opaque; |
|
2754 | 2753 |
target_ulong msr; |
2755 | 2754 |
|
2756 | 2755 |
if (qemu_loglevel_mask(CPU_LOG_RESET)) { |
... | ... | |
2812 | 2811 |
env->cpu_model_str = cpu_model; |
2813 | 2812 |
cpu_ppc_register_internal(env, def); |
2814 | 2813 |
#if defined(CONFIG_USER_ONLY) |
2815 |
cpu_ppc_reset(env);
|
|
2814 |
cpu_reset(env); |
|
2816 | 2815 |
#endif |
2817 | 2816 |
|
2818 | 2817 |
qemu_init_vcpu(env); |
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