Revision d8a5950a
| b/target-mips/translate.c | ||
|---|---|---|
| 749 | 749 |
generate_exception(ctx, EXCP_RI); |
| 750 | 750 |
} |
| 751 | 751 |
|
| 752 |
static always_inline void check_cp1_3d(CPUState *env, DisasContext *ctx) |
|
| 753 |
{
|
|
| 754 |
if (unlikely(!(env->fpu->fcr0 & (1 << FCR0_3D)))) |
|
| 755 |
generate_exception(ctx, EXCP_RI); |
|
| 756 |
} |
|
| 757 |
|
|
| 752 | 758 |
/* |
| 753 | 759 |
* Verify if floating point register is valid; an operation is not defined |
| 754 | 760 |
* if bit 0 of any register specification is set and the FR bit in the |
| ... | ... | |
| 6328 | 6334 |
gen_cp1(ctx, op1, rt, rd); |
| 6329 | 6335 |
break; |
| 6330 | 6336 |
#endif |
| 6331 |
case OPC_BC1: |
|
| 6332 | 6337 |
case OPC_BC1ANY2: |
| 6333 | 6338 |
case OPC_BC1ANY4: |
| 6339 |
check_cp1_3d(env, ctx); |
|
| 6340 |
/* fall through */ |
|
| 6341 |
case OPC_BC1: |
|
| 6334 | 6342 |
gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode), |
| 6335 | 6343 |
(rt >> 2) & 0x7, imm << 2); |
| 6336 | 6344 |
return; |
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