Revision d8a5950a target-mips/translate.c

b/target-mips/translate.c
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        generate_exception(ctx, EXCP_RI);
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}
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static always_inline void check_cp1_3d(CPUState *env, DisasContext *ctx)
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{
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    if (unlikely(!(env->fpu->fcr0 & (1 << FCR0_3D))))
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        generate_exception(ctx, EXCP_RI);
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}
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/*
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 * Verify if floating point register is valid; an operation is not defined
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 * if bit 0 of any register specification is set and the FR bit in the
......
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                gen_cp1(ctx, op1, rt, rd);
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                break;
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#endif
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            case OPC_BC1:
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            case OPC_BC1ANY2:
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            case OPC_BC1ANY4:
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                check_cp1_3d(env, ctx);
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                /* fall through */
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            case OPC_BC1:
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                gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode),
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                                    (rt >> 2) & 0x7, imm << 2);
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                return;

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