Revision d8f699cb hw/omap.h

b/hw/omap.h
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struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
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                qemu_irq *irq, omap_clk clk);
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struct i2s_codec_s {
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    void *opaque;
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    /* The CPU can call this if it is generating the clock signal on the
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     * i2s port.  The CODEC can ignore it if it is set up as a clock
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     * master and generates its own clock.  */
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    void (*set_rate)(void *opaque, int in, int out);
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    void (*tx_swallow)(void *opaque);
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    qemu_irq rx_swallow;
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    qemu_irq tx_start;
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    struct i2s_fifo_s {
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        uint8_t *fifo;
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        int len;
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        int start;
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        int size;
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    } in, out;
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};
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struct omap_mcbsp_s;
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struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
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                qemu_irq *irq, qemu_irq *dma, omap_clk clk);
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void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave);
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/* omap_lcdc.c */
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struct omap_lcd_panel_s;
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void omap_lcdc_reset(struct omap_lcd_panel_s *s);
......
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    struct omap_gpio_s *gpio;
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    struct omap_mcbsp_s *mcbsp1;
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    struct omap_mcbsp_s *mcbsp3;
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    /* MPU public TIPB peripherals */
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    struct omap_32khz_timer_s *os_timer;
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......
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    struct omap_rtc_s *rtc;
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    struct omap_mcbsp_s *mcbsp2;
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    /* MPU private TIPB peripherals */
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    struct omap_intr_handler_s *ih[2];
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......
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                        __FUNCTION__, paddr)
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# define TCMI_VERBOSE			1
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//# define MEM_VERBOSE			1
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# ifdef TCMI_VERBOSE
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#  define OMAP_8B_REG(paddr)		\
......
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# define OMAP_MPUI_REG_MASK		0x000007ff
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# ifdef MEM_VERBOSE
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struct io_fn {
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    CPUReadMemoryFunc **mem_read;
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    CPUWriteMemoryFunc **mem_write;
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    void *opaque;
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    int in;
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};
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static uint32_t io_readb(void *opaque, target_phys_addr_t addr)
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{
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    struct io_fn *s = opaque;
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    uint32_t ret;
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    s->in ++;
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    ret = s->mem_read[0](s->opaque, addr);
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    s->in --;
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    if (!s->in)
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        fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
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    return ret;
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}
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static uint32_t io_readh(void *opaque, target_phys_addr_t addr)
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{
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    struct io_fn *s = opaque;
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    uint32_t ret;
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    s->in ++;
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    ret = s->mem_read[1](s->opaque, addr);
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    s->in --;
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    if (!s->in)
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        fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
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    return ret;
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}
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static uint32_t io_readw(void *opaque, target_phys_addr_t addr)
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{
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    struct io_fn *s = opaque;
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    uint32_t ret;
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    s->in ++;
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    ret = s->mem_read[2](s->opaque, addr);
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    s->in --;
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    if (!s->in)
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        fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
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    return ret;
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}
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static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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    struct io_fn *s = opaque;
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    if (!s->in)
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        fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);
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    s->in ++;
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    s->mem_write[0](s->opaque, addr, value);
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    s->in --;
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}
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static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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    struct io_fn *s = opaque;
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    if (!s->in)
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        fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);
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    s->in ++;
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    s->mem_write[1](s->opaque, addr, value);
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    s->in --;
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}
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static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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    struct io_fn *s = opaque;
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    if (!s->in)
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        fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);
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    s->in ++;
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    s->mem_write[2](s->opaque, addr, value);
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    s->in --;
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}
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static CPUReadMemoryFunc *io_readfn[] = { io_readb, io_readh, io_readw, };
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static CPUWriteMemoryFunc *io_writefn[] = { io_writeb, io_writeh, io_writew, };
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inline static int debug_register_io_memory(int io_index,
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                CPUReadMemoryFunc **mem_read, CPUWriteMemoryFunc **mem_write,
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                void *opaque)
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{
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    struct io_fn *s = qemu_malloc(sizeof(struct io_fn));
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    s->mem_read = mem_read;
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    s->mem_write = mem_write;
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    s->opaque = opaque;
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    s->in = 0;
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    return cpu_register_io_memory(io_index, io_readfn, io_writefn, s);
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}
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#  define cpu_register_io_memory	debug_register_io_memory
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# endif
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#endif /* hw_omap_h */

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