root / hw / omap1_clk.c @ d8f699cb
History | View | Annotate | Download (18.7 kB)
1 |
/*
|
---|---|
2 |
* OMAP clocks.
|
3 |
*
|
4 |
* Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
|
5 |
*
|
6 |
* Clocks data comes in part from arch/arm/mach-omap1/clock.h in Linux.
|
7 |
*
|
8 |
* This program is free software; you can redistribute it and/or
|
9 |
* modify it under the terms of the GNU General Public License as
|
10 |
* published by the Free Software Foundation; either version 2 of
|
11 |
* the License, or (at your option) any later version.
|
12 |
*
|
13 |
* This program is distributed in the hope that it will be useful,
|
14 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
15 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
16 |
* GNU General Public License for more details.
|
17 |
*
|
18 |
* You should have received a copy of the GNU General Public License
|
19 |
* along with this program; if not, write to the Free Software
|
20 |
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
21 |
* MA 02111-1307 USA
|
22 |
*/
|
23 |
#include "vl.h" |
24 |
|
25 |
struct clk {
|
26 |
const char *name; |
27 |
const char *alias; |
28 |
struct clk *parent;
|
29 |
struct clk *child1;
|
30 |
struct clk *sibling;
|
31 |
#define ALWAYS_ENABLED (1 << 0) |
32 |
#define CLOCK_IN_OMAP310 (1 << 10) |
33 |
#define CLOCK_IN_OMAP730 (1 << 11) |
34 |
#define CLOCK_IN_OMAP1510 (1 << 12) |
35 |
#define CLOCK_IN_OMAP16XX (1 << 13) |
36 |
uint32_t flags; |
37 |
int id;
|
38 |
|
39 |
int running; /* Is currently ticking */ |
40 |
int enabled; /* Is enabled, regardless of its input clk */ |
41 |
unsigned long rate; /* Current rate (if .running) */ |
42 |
unsigned int divisor; /* Rate relative to input (if .enabled) */ |
43 |
unsigned int multiplier; /* Rate relative to input (if .enabled) */ |
44 |
qemu_irq users[16]; /* Who to notify on change */ |
45 |
int usecount; /* Automatically idle when unused */ |
46 |
}; |
47 |
|
48 |
static struct clk xtal_osc12m = { |
49 |
.name = "xtal_osc_12m",
|
50 |
.rate = 12000000,
|
51 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
52 |
}; |
53 |
|
54 |
static struct clk xtal_osc32k = { |
55 |
.name = "xtal_osc_32k",
|
56 |
.rate = 32768,
|
57 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
58 |
}; |
59 |
|
60 |
static struct clk ck_ref = { |
61 |
.name = "ck_ref",
|
62 |
.alias = "clkin",
|
63 |
.parent = &xtal_osc12m, |
64 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
65 |
ALWAYS_ENABLED, |
66 |
}; |
67 |
|
68 |
/* If a dpll is disabled it becomes a bypass, child clocks don't stop */
|
69 |
static struct clk dpll1 = { |
70 |
.name = "dpll1",
|
71 |
.parent = &ck_ref, |
72 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
73 |
ALWAYS_ENABLED, |
74 |
}; |
75 |
|
76 |
static struct clk dpll2 = { |
77 |
.name = "dpll2",
|
78 |
.parent = &ck_ref, |
79 |
.flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
80 |
}; |
81 |
|
82 |
static struct clk dpll3 = { |
83 |
.name = "dpll3",
|
84 |
.parent = &ck_ref, |
85 |
.flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
86 |
}; |
87 |
|
88 |
static struct clk dpll4 = { |
89 |
.name = "dpll4",
|
90 |
.parent = &ck_ref, |
91 |
.multiplier = 4,
|
92 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
93 |
}; |
94 |
|
95 |
static struct clk apll = { |
96 |
.name = "apll",
|
97 |
.parent = &ck_ref, |
98 |
.multiplier = 48,
|
99 |
.divisor = 12,
|
100 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
101 |
}; |
102 |
|
103 |
static struct clk ck_48m = { |
104 |
.name = "ck_48m",
|
105 |
.parent = &dpll4, /* either dpll4 or apll */
|
106 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
107 |
}; |
108 |
|
109 |
static struct clk ck_dpll1out = { |
110 |
.name = "ck_dpll1out",
|
111 |
.parent = &dpll1, |
112 |
.flags = CLOCK_IN_OMAP16XX, |
113 |
}; |
114 |
|
115 |
static struct clk sossi_ck = { |
116 |
.name = "ck_sossi",
|
117 |
.parent = &ck_dpll1out, |
118 |
.flags = CLOCK_IN_OMAP16XX, |
119 |
}; |
120 |
|
121 |
static struct clk clkm1 = { |
122 |
.name = "clkm1",
|
123 |
.alias = "ck_gen1",
|
124 |
.parent = &dpll1, |
125 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
126 |
ALWAYS_ENABLED, |
127 |
}; |
128 |
|
129 |
static struct clk clkm2 = { |
130 |
.name = "clkm2",
|
131 |
.alias = "ck_gen2",
|
132 |
.parent = &dpll1, |
133 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
134 |
ALWAYS_ENABLED, |
135 |
}; |
136 |
|
137 |
static struct clk clkm3 = { |
138 |
.name = "clkm3",
|
139 |
.alias = "ck_gen3",
|
140 |
.parent = &dpll1, /* either dpll1 or ck_ref */
|
141 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
142 |
ALWAYS_ENABLED, |
143 |
}; |
144 |
|
145 |
static struct clk arm_ck = { |
146 |
.name = "arm_ck",
|
147 |
.alias = "mpu_ck",
|
148 |
.parent = &clkm1, |
149 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
150 |
ALWAYS_ENABLED, |
151 |
}; |
152 |
|
153 |
static struct clk armper_ck = { |
154 |
.name = "armper_ck",
|
155 |
.alias = "mpuper_ck",
|
156 |
.parent = &clkm1, |
157 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
158 |
}; |
159 |
|
160 |
static struct clk arm_gpio_ck = { |
161 |
.name = "arm_gpio_ck",
|
162 |
.alias = "mpu_gpio_ck",
|
163 |
.parent = &clkm1, |
164 |
.divisor = 1,
|
165 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
166 |
}; |
167 |
|
168 |
static struct clk armxor_ck = { |
169 |
.name = "armxor_ck",
|
170 |
.alias = "mpuxor_ck",
|
171 |
.parent = &ck_ref, |
172 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
173 |
}; |
174 |
|
175 |
static struct clk armtim_ck = { |
176 |
.name = "armtim_ck",
|
177 |
.alias = "mputim_ck",
|
178 |
.parent = &ck_ref, /* either CLKIN or DPLL1 */
|
179 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
180 |
}; |
181 |
|
182 |
static struct clk armwdt_ck = { |
183 |
.name = "armwdt_ck",
|
184 |
.alias = "mpuwd_ck",
|
185 |
.parent = &clkm1, |
186 |
.divisor = 14,
|
187 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
188 |
ALWAYS_ENABLED, |
189 |
}; |
190 |
|
191 |
static struct clk arminth_ck16xx = { |
192 |
.name = "arminth_ck",
|
193 |
.parent = &arm_ck, |
194 |
.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, |
195 |
/* Note: On 16xx the frequency can be divided by 2 by programming
|
196 |
* ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
|
197 |
*
|
198 |
* 1510 version is in TC clocks.
|
199 |
*/
|
200 |
}; |
201 |
|
202 |
static struct clk dsp_ck = { |
203 |
.name = "dsp_ck",
|
204 |
.parent = &clkm2, |
205 |
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
206 |
}; |
207 |
|
208 |
static struct clk dspmmu_ck = { |
209 |
.name = "dspmmu_ck",
|
210 |
.parent = &clkm2, |
211 |
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
212 |
ALWAYS_ENABLED, |
213 |
}; |
214 |
|
215 |
static struct clk dspper_ck = { |
216 |
.name = "dspper_ck",
|
217 |
.parent = &clkm2, |
218 |
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
219 |
}; |
220 |
|
221 |
static struct clk dspxor_ck = { |
222 |
.name = "dspxor_ck",
|
223 |
.parent = &ck_ref, |
224 |
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
225 |
}; |
226 |
|
227 |
static struct clk dsptim_ck = { |
228 |
.name = "dsptim_ck",
|
229 |
.parent = &ck_ref, |
230 |
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
231 |
}; |
232 |
|
233 |
static struct clk tc_ck = { |
234 |
.name = "tc_ck",
|
235 |
.parent = &clkm3, |
236 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
237 |
CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 | |
238 |
ALWAYS_ENABLED, |
239 |
}; |
240 |
|
241 |
static struct clk arminth_ck15xx = { |
242 |
.name = "arminth_ck",
|
243 |
.parent = &tc_ck, |
244 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
245 |
/* Note: On 1510 the frequency follows TC_CK
|
246 |
*
|
247 |
* 16xx version is in MPU clocks.
|
248 |
*/
|
249 |
}; |
250 |
|
251 |
static struct clk tipb_ck = { |
252 |
/* No-idle controlled by "tc_ck" */
|
253 |
.name = "tipb_ck",
|
254 |
.parent = &tc_ck, |
255 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
256 |
}; |
257 |
|
258 |
static struct clk l3_ocpi_ck = { |
259 |
/* No-idle controlled by "tc_ck" */
|
260 |
.name = "l3_ocpi_ck",
|
261 |
.parent = &tc_ck, |
262 |
.flags = CLOCK_IN_OMAP16XX, |
263 |
}; |
264 |
|
265 |
static struct clk tc1_ck = { |
266 |
.name = "tc1_ck",
|
267 |
.parent = &tc_ck, |
268 |
.flags = CLOCK_IN_OMAP16XX, |
269 |
}; |
270 |
|
271 |
static struct clk tc2_ck = { |
272 |
.name = "tc2_ck",
|
273 |
.parent = &tc_ck, |
274 |
.flags = CLOCK_IN_OMAP16XX, |
275 |
}; |
276 |
|
277 |
static struct clk dma_ck = { |
278 |
/* No-idle controlled by "tc_ck" */
|
279 |
.name = "dma_ck",
|
280 |
.parent = &tc_ck, |
281 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
282 |
ALWAYS_ENABLED, |
283 |
}; |
284 |
|
285 |
static struct clk dma_lcdfree_ck = { |
286 |
.name = "dma_lcdfree_ck",
|
287 |
.parent = &tc_ck, |
288 |
.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, |
289 |
}; |
290 |
|
291 |
static struct clk api_ck = { |
292 |
.name = "api_ck",
|
293 |
.alias = "mpui_ck",
|
294 |
.parent = &tc_ck, |
295 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
296 |
}; |
297 |
|
298 |
static struct clk lb_ck = { |
299 |
.name = "lb_ck",
|
300 |
.parent = &tc_ck, |
301 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
302 |
}; |
303 |
|
304 |
static struct clk lbfree_ck = { |
305 |
.name = "lbfree_ck",
|
306 |
.parent = &tc_ck, |
307 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
308 |
}; |
309 |
|
310 |
static struct clk hsab_ck = { |
311 |
.name = "hsab_ck",
|
312 |
.parent = &tc_ck, |
313 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
314 |
}; |
315 |
|
316 |
static struct clk rhea1_ck = { |
317 |
.name = "rhea1_ck",
|
318 |
.parent = &tc_ck, |
319 |
.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, |
320 |
}; |
321 |
|
322 |
static struct clk rhea2_ck = { |
323 |
.name = "rhea2_ck",
|
324 |
.parent = &tc_ck, |
325 |
.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, |
326 |
}; |
327 |
|
328 |
static struct clk lcd_ck_16xx = { |
329 |
.name = "lcd_ck",
|
330 |
.parent = &clkm3, |
331 |
.flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730, |
332 |
}; |
333 |
|
334 |
static struct clk lcd_ck_1510 = { |
335 |
.name = "lcd_ck",
|
336 |
.parent = &clkm3, |
337 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
338 |
}; |
339 |
|
340 |
static struct clk uart1_1510 = { |
341 |
.name = "uart1_ck",
|
342 |
/* Direct from ULPD, no real parent */
|
343 |
.parent = &armper_ck, /* either armper_ck or dpll4 */
|
344 |
.rate = 12000000,
|
345 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
346 |
}; |
347 |
|
348 |
static struct clk uart1_16xx = { |
349 |
.name = "uart1_ck",
|
350 |
/* Direct from ULPD, no real parent */
|
351 |
.parent = &armper_ck, |
352 |
.rate = 48000000,
|
353 |
.flags = CLOCK_IN_OMAP16XX, |
354 |
}; |
355 |
|
356 |
static struct clk uart2_ck = { |
357 |
.name = "uart2_ck",
|
358 |
/* Direct from ULPD, no real parent */
|
359 |
.parent = &armper_ck, /* either armper_ck or dpll4 */
|
360 |
.rate = 12000000,
|
361 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 | |
362 |
ALWAYS_ENABLED, |
363 |
}; |
364 |
|
365 |
static struct clk uart3_1510 = { |
366 |
.name = "uart3_ck",
|
367 |
/* Direct from ULPD, no real parent */
|
368 |
.parent = &armper_ck, /* either armper_ck or dpll4 */
|
369 |
.rate = 12000000,
|
370 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, |
371 |
}; |
372 |
|
373 |
static struct clk uart3_16xx = { |
374 |
.name = "uart3_ck",
|
375 |
/* Direct from ULPD, no real parent */
|
376 |
.parent = &armper_ck, |
377 |
.rate = 48000000,
|
378 |
.flags = CLOCK_IN_OMAP16XX, |
379 |
}; |
380 |
|
381 |
static struct clk usb_clk0 = { /* 6 MHz output on W4_USB_CLK0 */ |
382 |
.name = "usb_clk0",
|
383 |
.alias = "usb.clko",
|
384 |
/* Direct from ULPD, no parent */
|
385 |
.rate = 6000000,
|
386 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
387 |
}; |
388 |
|
389 |
static struct clk usb_hhc_ck1510 = { |
390 |
.name = "usb_hhc_ck",
|
391 |
/* Direct from ULPD, no parent */
|
392 |
.rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ |
393 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
394 |
}; |
395 |
|
396 |
static struct clk usb_hhc_ck16xx = { |
397 |
.name = "usb_hhc_ck",
|
398 |
/* Direct from ULPD, no parent */
|
399 |
.rate = 48000000,
|
400 |
/* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
|
401 |
.flags = CLOCK_IN_OMAP16XX, |
402 |
}; |
403 |
|
404 |
static struct clk usb_w2fc_mclk = { |
405 |
.name = "usb_w2fc_mclk",
|
406 |
.alias = "usb_w2fc_ck",
|
407 |
.parent = &ck_48m, |
408 |
.rate = 48000000,
|
409 |
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
410 |
}; |
411 |
|
412 |
static struct clk mclk_1510 = { |
413 |
.name = "mclk",
|
414 |
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
415 |
.rate = 12000000,
|
416 |
.flags = CLOCK_IN_OMAP1510, |
417 |
}; |
418 |
|
419 |
static struct clk bclk_310 = { |
420 |
.name = "bt_mclk_out", /* Alias midi_mclk_out? */ |
421 |
.parent = &armper_ck, |
422 |
.flags = CLOCK_IN_OMAP310, |
423 |
}; |
424 |
|
425 |
static struct clk mclk_310 = { |
426 |
.name = "com_mclk_out",
|
427 |
.parent = &armper_ck, |
428 |
.flags = CLOCK_IN_OMAP310, |
429 |
}; |
430 |
|
431 |
static struct clk mclk_16xx = { |
432 |
.name = "mclk",
|
433 |
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
434 |
.flags = CLOCK_IN_OMAP16XX, |
435 |
}; |
436 |
|
437 |
static struct clk bclk_1510 = { |
438 |
.name = "bclk",
|
439 |
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
440 |
.rate = 12000000,
|
441 |
.flags = CLOCK_IN_OMAP1510, |
442 |
}; |
443 |
|
444 |
static struct clk bclk_16xx = { |
445 |
.name = "bclk",
|
446 |
/* Direct from ULPD, no parent. May be enabled by ext hardware. */
|
447 |
.flags = CLOCK_IN_OMAP16XX, |
448 |
}; |
449 |
|
450 |
static struct clk mmc1_ck = { |
451 |
.name = "mmc_ck",
|
452 |
.id = 1,
|
453 |
/* Functional clock is direct from ULPD, interface clock is ARMPER */
|
454 |
.parent = &armper_ck, /* either armper_ck or dpll4 */
|
455 |
.rate = 48000000,
|
456 |
.flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310, |
457 |
}; |
458 |
|
459 |
static struct clk mmc2_ck = { |
460 |
.name = "mmc_ck",
|
461 |
.id = 2,
|
462 |
/* Functional clock is direct from ULPD, interface clock is ARMPER */
|
463 |
.parent = &armper_ck, |
464 |
.rate = 48000000,
|
465 |
.flags = CLOCK_IN_OMAP16XX, |
466 |
}; |
467 |
|
468 |
static struct clk cam_mclk = { |
469 |
.name = "cam.mclk",
|
470 |
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
471 |
.rate = 12000000,
|
472 |
}; |
473 |
|
474 |
static struct clk cam_exclk = { |
475 |
.name = "cam.exclk",
|
476 |
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
477 |
/* Either 12M from cam.mclk or 48M from dpll4 */
|
478 |
.parent = &cam_mclk, |
479 |
}; |
480 |
|
481 |
static struct clk cam_lclk = { |
482 |
.name = "cam.lclk",
|
483 |
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
484 |
}; |
485 |
|
486 |
static struct clk i2c_fck = { |
487 |
.name = "i2c_fck",
|
488 |
.id = 1,
|
489 |
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
490 |
ALWAYS_ENABLED, |
491 |
.parent = &armxor_ck, |
492 |
}; |
493 |
|
494 |
static struct clk i2c_ick = { |
495 |
.name = "i2c_ick",
|
496 |
.id = 1,
|
497 |
.flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, |
498 |
.parent = &armper_ck, |
499 |
}; |
500 |
|
501 |
static struct clk clk32k = { |
502 |
.name = "clk32-kHz",
|
503 |
.flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
504 |
ALWAYS_ENABLED, |
505 |
.parent = &xtal_osc32k, |
506 |
}; |
507 |
|
508 |
static struct clk *onchip_clks[] = { |
509 |
/* non-ULPD clocks */
|
510 |
&xtal_osc12m, |
511 |
&xtal_osc32k, |
512 |
&ck_ref, |
513 |
&dpll1, |
514 |
&dpll2, |
515 |
&dpll3, |
516 |
&dpll4, |
517 |
&apll, |
518 |
&ck_48m, |
519 |
/* CK_GEN1 clocks */
|
520 |
&clkm1, |
521 |
&ck_dpll1out, |
522 |
&sossi_ck, |
523 |
&arm_ck, |
524 |
&armper_ck, |
525 |
&arm_gpio_ck, |
526 |
&armxor_ck, |
527 |
&armtim_ck, |
528 |
&armwdt_ck, |
529 |
&arminth_ck15xx, &arminth_ck16xx, |
530 |
/* CK_GEN2 clocks */
|
531 |
&clkm2, |
532 |
&dsp_ck, |
533 |
&dspmmu_ck, |
534 |
&dspper_ck, |
535 |
&dspxor_ck, |
536 |
&dsptim_ck, |
537 |
/* CK_GEN3 clocks */
|
538 |
&clkm3, |
539 |
&tc_ck, |
540 |
&tipb_ck, |
541 |
&l3_ocpi_ck, |
542 |
&tc1_ck, |
543 |
&tc2_ck, |
544 |
&dma_ck, |
545 |
&dma_lcdfree_ck, |
546 |
&api_ck, |
547 |
&lb_ck, |
548 |
&lbfree_ck, |
549 |
&hsab_ck, |
550 |
&rhea1_ck, |
551 |
&rhea2_ck, |
552 |
&lcd_ck_16xx, |
553 |
&lcd_ck_1510, |
554 |
/* ULPD clocks */
|
555 |
&uart1_1510, |
556 |
&uart1_16xx, |
557 |
&uart2_ck, |
558 |
&uart3_1510, |
559 |
&uart3_16xx, |
560 |
&usb_clk0, |
561 |
&usb_hhc_ck1510, &usb_hhc_ck16xx, |
562 |
&mclk_1510, &mclk_16xx, &mclk_310, |
563 |
&bclk_1510, &bclk_16xx, &bclk_310, |
564 |
&mmc1_ck, |
565 |
&mmc2_ck, |
566 |
&cam_mclk, |
567 |
&cam_exclk, |
568 |
&cam_lclk, |
569 |
&clk32k, |
570 |
&usb_w2fc_mclk, |
571 |
/* Virtual clocks */
|
572 |
&i2c_fck, |
573 |
&i2c_ick, |
574 |
0
|
575 |
}; |
576 |
|
577 |
void omap_clk_adduser(struct clk *clk, qemu_irq user) |
578 |
{ |
579 |
qemu_irq *i; |
580 |
|
581 |
for (i = clk->users; *i; i ++);
|
582 |
*i = user; |
583 |
} |
584 |
|
585 |
/* If a clock is allowed to idle, it is disabled automatically when
|
586 |
* all of clock domains using it are disabled. */
|
587 |
int omap_clk_is_idle(struct clk *clk) |
588 |
{ |
589 |
struct clk *chld;
|
590 |
|
591 |
if (!clk->enabled && (!clk->usecount || !(clk->flags && ALWAYS_ENABLED)))
|
592 |
return 1; |
593 |
if (clk->usecount)
|
594 |
return 0; |
595 |
|
596 |
for (chld = clk->child1; chld; chld = chld->sibling)
|
597 |
if (!omap_clk_is_idle(chld))
|
598 |
return 0; |
599 |
return 1; |
600 |
} |
601 |
|
602 |
struct clk *omap_findclk(struct omap_mpu_state_s *mpu, const char *name) |
603 |
{ |
604 |
struct clk *i;
|
605 |
|
606 |
for (i = mpu->clks; i->name; i ++)
|
607 |
if (!strcmp(i->name, name) || (i->alias && !strcmp(i->alias, name)))
|
608 |
return i;
|
609 |
cpu_abort(mpu->env, "%s: %s not found\n", __FUNCTION__, name);
|
610 |
} |
611 |
|
612 |
void omap_clk_get(struct clk *clk) |
613 |
{ |
614 |
clk->usecount ++; |
615 |
} |
616 |
|
617 |
void omap_clk_put(struct clk *clk) |
618 |
{ |
619 |
if (!(clk->usecount --))
|
620 |
cpu_abort(cpu_single_env, "%s: %s is not in use\n",
|
621 |
__FUNCTION__, clk->name); |
622 |
} |
623 |
|
624 |
static void omap_clk_update(struct clk *clk) |
625 |
{ |
626 |
int parent, running;
|
627 |
qemu_irq *user; |
628 |
struct clk *i;
|
629 |
|
630 |
if (clk->parent)
|
631 |
parent = clk->parent->running; |
632 |
else
|
633 |
parent = 1;
|
634 |
|
635 |
running = parent && (clk->enabled || |
636 |
((clk->flags & ALWAYS_ENABLED) && clk->usecount)); |
637 |
if (clk->running != running) {
|
638 |
clk->running = running; |
639 |
for (user = clk->users; *user; user ++)
|
640 |
qemu_set_irq(*user, running); |
641 |
for (i = clk->child1; i; i = i->sibling)
|
642 |
omap_clk_update(i); |
643 |
} |
644 |
} |
645 |
|
646 |
static void omap_clk_rate_update_full(struct clk *clk, unsigned long int rate, |
647 |
unsigned long int div, unsigned long int mult) |
648 |
{ |
649 |
struct clk *i;
|
650 |
qemu_irq *user; |
651 |
|
652 |
clk->rate = muldiv64(rate, mult, div); |
653 |
if (clk->running)
|
654 |
for (user = clk->users; *user; user ++)
|
655 |
qemu_irq_raise(*user); |
656 |
for (i = clk->child1; i; i = i->sibling)
|
657 |
omap_clk_rate_update_full(i, rate, |
658 |
div * i->divisor, mult * i->multiplier); |
659 |
} |
660 |
|
661 |
static void omap_clk_rate_update(struct clk *clk) |
662 |
{ |
663 |
struct clk *i;
|
664 |
unsigned long int div, mult = div = 1; |
665 |
|
666 |
for (i = clk; i->parent; i = i->parent) {
|
667 |
div *= i->divisor; |
668 |
mult *= i->multiplier; |
669 |
} |
670 |
|
671 |
omap_clk_rate_update_full(clk, i->rate, div, mult); |
672 |
} |
673 |
|
674 |
void omap_clk_reparent(struct clk *clk, struct clk *parent) |
675 |
{ |
676 |
struct clk **p;
|
677 |
|
678 |
if (clk->parent) {
|
679 |
for (p = &clk->parent->child1; *p != clk; p = &(*p)->sibling);
|
680 |
*p = clk->sibling; |
681 |
} |
682 |
|
683 |
clk->parent = parent; |
684 |
if (parent) {
|
685 |
clk->sibling = parent->child1; |
686 |
parent->child1 = clk; |
687 |
omap_clk_update(clk); |
688 |
omap_clk_rate_update(clk); |
689 |
} else
|
690 |
clk->sibling = 0;
|
691 |
} |
692 |
|
693 |
void omap_clk_onoff(struct clk *clk, int on) |
694 |
{ |
695 |
clk->enabled = on; |
696 |
omap_clk_update(clk); |
697 |
} |
698 |
|
699 |
void omap_clk_canidle(struct clk *clk, int can) |
700 |
{ |
701 |
if (can)
|
702 |
omap_clk_put(clk); |
703 |
else
|
704 |
omap_clk_get(clk); |
705 |
} |
706 |
|
707 |
void omap_clk_setrate(struct clk *clk, int divide, int multiply) |
708 |
{ |
709 |
clk->divisor = divide; |
710 |
clk->multiplier = multiply; |
711 |
omap_clk_rate_update(clk); |
712 |
} |
713 |
|
714 |
int64_t omap_clk_getrate(omap_clk clk) |
715 |
{ |
716 |
return clk->rate;
|
717 |
} |
718 |
|
719 |
void omap_clk_init(struct omap_mpu_state_s *mpu) |
720 |
{ |
721 |
struct clk **i, *j, *k;
|
722 |
int count;
|
723 |
int flag;
|
724 |
|
725 |
if (cpu_is_omap310(mpu))
|
726 |
flag = CLOCK_IN_OMAP310; |
727 |
else if (cpu_is_omap1510(mpu)) |
728 |
flag = CLOCK_IN_OMAP1510; |
729 |
else
|
730 |
return;
|
731 |
|
732 |
for (i = onchip_clks, count = 0; *i; i ++) |
733 |
if ((*i)->flags & flag)
|
734 |
count ++; |
735 |
mpu->clks = (struct clk *) qemu_mallocz(sizeof(struct clk) * (count + 1)); |
736 |
for (i = onchip_clks, j = mpu->clks; *i; i ++)
|
737 |
if ((*i)->flags & flag) {
|
738 |
memcpy(j, *i, sizeof(struct clk)); |
739 |
for (k = mpu->clks; k < j; k ++)
|
740 |
if (j->parent && !strcmp(j->parent->name, k->name)) {
|
741 |
j->parent = k; |
742 |
j->sibling = k->child1; |
743 |
k->child1 = j; |
744 |
} else if (k->parent && !strcmp(k->parent->name, j->name)) { |
745 |
k->parent = j; |
746 |
k->sibling = j->child1; |
747 |
j->child1 = k; |
748 |
} |
749 |
j->divisor = j->divisor ?: 1;
|
750 |
j->multiplier = j->multiplier ?: 1;
|
751 |
j ++; |
752 |
} |
753 |
for (j = mpu->clks; count --; j ++) {
|
754 |
omap_clk_update(j); |
755 |
omap_clk_rate_update(j); |
756 |
} |
757 |
} |