Revision d94536f4
| b/target-mips/translate.c | ||
|---|---|---|
| 643 | 643 |
} |
| 644 | 644 |
} |
| 645 | 645 |
|
| 646 |
static inline void get_fp_cond (TCGv_i32 t)
|
|
| 646 |
static inline int get_fp_bit (int cc)
|
|
| 647 | 647 |
{
|
| 648 |
TCGv_i32 r_tmp1 = tcg_temp_new_i32(); |
|
| 649 |
TCGv_i32 r_tmp2 = tcg_temp_new_i32(); |
|
| 650 |
|
|
| 651 |
tcg_gen_shri_i32(r_tmp2, fpu_fcr31, 24); |
|
| 652 |
tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xfe); |
|
| 653 |
tcg_gen_shri_i32(r_tmp1, fpu_fcr31, 23); |
|
| 654 |
tcg_gen_andi_i32(r_tmp1, r_tmp1, 0x1); |
|
| 655 |
tcg_gen_or_i32(t, r_tmp1, r_tmp2); |
|
| 656 |
tcg_temp_free_i32(r_tmp1); |
|
| 657 |
tcg_temp_free_i32(r_tmp2); |
|
| 648 |
if (cc) |
|
| 649 |
return 24 + cc; |
|
| 650 |
else |
|
| 651 |
return 23; |
|
| 658 | 652 |
} |
| 659 | 653 |
|
| 660 | 654 |
#define FOP_CONDS(type, fmt, bits) \ |
| ... | ... | |
| 5500 | 5494 |
|
| 5501 | 5495 |
switch (op) {
|
| 5502 | 5496 |
case OPC_BC1F: |
| 5503 |
{
|
|
| 5504 |
int l1 = gen_new_label(); |
|
| 5505 |
int l2 = gen_new_label(); |
|
| 5506 |
|
|
| 5507 |
get_fp_cond(t0); |
|
| 5508 |
tcg_gen_andi_i32(t0, t0, 0x1 << cc); |
|
| 5509 |
tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); |
|
| 5510 |
tcg_gen_movi_tl(bcond, 0); |
|
| 5511 |
tcg_gen_br(l2); |
|
| 5512 |
gen_set_label(l1); |
|
| 5513 |
tcg_gen_movi_tl(bcond, 1); |
|
| 5514 |
gen_set_label(l2); |
|
| 5515 |
} |
|
| 5497 |
tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); |
|
| 5498 |
tcg_gen_not_i32(t0, t0); |
|
| 5499 |
tcg_gen_andi_i32(t0, t0, 1); |
|
| 5500 |
tcg_gen_extu_i32_tl(bcond, t0); |
|
| 5516 | 5501 |
opn = "bc1f"; |
| 5517 | 5502 |
goto not_likely; |
| 5518 | 5503 |
case OPC_BC1FL: |
| 5519 |
{
|
|
| 5520 |
int l1 = gen_new_label(); |
|
| 5521 |
int l2 = gen_new_label(); |
|
| 5522 |
|
|
| 5523 |
get_fp_cond(t0); |
|
| 5524 |
tcg_gen_andi_i32(t0, t0, 0x1 << cc); |
|
| 5525 |
tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); |
|
| 5526 |
tcg_gen_movi_tl(bcond, 0); |
|
| 5527 |
tcg_gen_br(l2); |
|
| 5528 |
gen_set_label(l1); |
|
| 5529 |
tcg_gen_movi_tl(bcond, 1); |
|
| 5530 |
gen_set_label(l2); |
|
| 5531 |
} |
|
| 5504 |
tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); |
|
| 5505 |
tcg_gen_not_i32(t0, t0); |
|
| 5506 |
tcg_gen_andi_i32(t0, t0, 1); |
|
| 5507 |
tcg_gen_extu_i32_tl(bcond, t0); |
|
| 5532 | 5508 |
opn = "bc1fl"; |
| 5533 | 5509 |
goto likely; |
| 5534 | 5510 |
case OPC_BC1T: |
| 5535 |
{
|
|
| 5536 |
int l1 = gen_new_label(); |
|
| 5537 |
int l2 = gen_new_label(); |
|
| 5538 |
|
|
| 5539 |
get_fp_cond(t0); |
|
| 5540 |
tcg_gen_andi_i32(t0, t0, 0x1 << cc); |
|
| 5541 |
tcg_gen_brcondi_i32(TCG_COND_NE, t0, 0, l1); |
|
| 5542 |
tcg_gen_movi_tl(bcond, 0); |
|
| 5543 |
tcg_gen_br(l2); |
|
| 5544 |
gen_set_label(l1); |
|
| 5545 |
tcg_gen_movi_tl(bcond, 1); |
|
| 5546 |
gen_set_label(l2); |
|
| 5547 |
} |
|
| 5511 |
tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); |
|
| 5512 |
tcg_gen_andi_i32(t0, t0, 1); |
|
| 5513 |
tcg_gen_extu_i32_tl(bcond, t0); |
|
| 5548 | 5514 |
opn = "bc1t"; |
| 5549 | 5515 |
goto not_likely; |
| 5550 | 5516 |
case OPC_BC1TL: |
| 5551 |
{
|
|
| 5552 |
int l1 = gen_new_label(); |
|
| 5553 |
int l2 = gen_new_label(); |
|
| 5554 |
|
|
| 5555 |
get_fp_cond(t0); |
|
| 5556 |
tcg_gen_andi_i32(t0, t0, 0x1 << cc); |
|
| 5557 |
tcg_gen_brcondi_i32(TCG_COND_NE, t0, 0, l1); |
|
| 5558 |
tcg_gen_movi_tl(bcond, 0); |
|
| 5559 |
tcg_gen_br(l2); |
|
| 5560 |
gen_set_label(l1); |
|
| 5561 |
tcg_gen_movi_tl(bcond, 1); |
|
| 5562 |
gen_set_label(l2); |
|
| 5563 |
} |
|
| 5517 |
tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); |
|
| 5518 |
tcg_gen_andi_i32(t0, t0, 1); |
|
| 5519 |
tcg_gen_extu_i32_tl(bcond, t0); |
|
| 5564 | 5520 |
opn = "bc1tl"; |
| 5565 | 5521 |
likely: |
| 5566 | 5522 |
ctx->hflags |= MIPS_HFLAG_BL; |
| 5567 | 5523 |
break; |
| 5568 | 5524 |
case OPC_BC1FANY2: |
| 5569 | 5525 |
{
|
| 5570 |
int l1 = gen_new_label(); |
|
| 5571 |
int l2 = gen_new_label(); |
|
| 5572 |
|
|
| 5573 |
get_fp_cond(t0); |
|
| 5574 |
tcg_gen_andi_i32(t0, t0, 0x3 << cc); |
|
| 5575 |
tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); |
|
| 5576 |
tcg_gen_movi_tl(bcond, 0); |
|
| 5577 |
tcg_gen_br(l2); |
|
| 5578 |
gen_set_label(l1); |
|
| 5579 |
tcg_gen_movi_tl(bcond, 1); |
|
| 5580 |
gen_set_label(l2); |
|
| 5526 |
TCGv_i32 t1 = tcg_temp_new_i32(); |
|
| 5527 |
tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); |
|
| 5528 |
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); |
|
| 5529 |
tcg_gen_or_i32(t0, t0, t1); |
|
| 5530 |
tcg_temp_free_i32(t1); |
|
| 5531 |
tcg_gen_not_i32(t0, t0); |
|
| 5532 |
tcg_gen_andi_i32(t0, t0, 1); |
|
| 5533 |
tcg_gen_extu_i32_tl(bcond, t0); |
|
| 5581 | 5534 |
} |
| 5582 | 5535 |
opn = "bc1any2f"; |
| 5583 | 5536 |
goto not_likely; |
| 5584 | 5537 |
case OPC_BC1TANY2: |
| 5585 | 5538 |
{
|
| 5586 |
int l1 = gen_new_label(); |
|
| 5587 |
int l2 = gen_new_label(); |
|
| 5588 |
|
|
| 5589 |
get_fp_cond(t0); |
|
| 5590 |
tcg_gen_andi_i32(t0, t0, 0x3 << cc); |
|
| 5591 |
tcg_gen_brcondi_i32(TCG_COND_NE, t0, 0, l1); |
|
| 5592 |
tcg_gen_movi_tl(bcond, 0); |
|
| 5593 |
tcg_gen_br(l2); |
|
| 5594 |
gen_set_label(l1); |
|
| 5595 |
tcg_gen_movi_tl(bcond, 1); |
|
| 5596 |
gen_set_label(l2); |
|
| 5539 |
TCGv_i32 t1 = tcg_temp_new_i32(); |
|
| 5540 |
tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); |
|
| 5541 |
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); |
|
| 5542 |
tcg_gen_or_i32(t0, t0, t1); |
|
| 5543 |
tcg_temp_free_i32(t1); |
|
| 5544 |
tcg_gen_andi_i32(t0, t0, 1); |
|
| 5545 |
tcg_gen_extu_i32_tl(bcond, t0); |
|
| 5597 | 5546 |
} |
| 5598 | 5547 |
opn = "bc1any2t"; |
| 5599 | 5548 |
goto not_likely; |
| 5600 | 5549 |
case OPC_BC1FANY4: |
| 5601 | 5550 |
{
|
| 5602 |
int l1 = gen_new_label(); |
|
| 5603 |
int l2 = gen_new_label(); |
|
| 5604 |
|
|
| 5605 |
get_fp_cond(t0); |
|
| 5606 |
tcg_gen_andi_i32(t0, t0, 0xf << cc); |
|
| 5607 |
tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1); |
|
| 5608 |
tcg_gen_movi_tl(bcond, 0); |
|
| 5609 |
tcg_gen_br(l2); |
|
| 5610 |
gen_set_label(l1); |
|
| 5611 |
tcg_gen_movi_tl(bcond, 1); |
|
| 5612 |
gen_set_label(l2); |
|
| 5551 |
TCGv_i32 t1 = tcg_temp_new_i32(); |
|
| 5552 |
tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); |
|
| 5553 |
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); |
|
| 5554 |
tcg_gen_or_i32(t0, t0, t1); |
|
| 5555 |
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2)); |
|
| 5556 |
tcg_gen_or_i32(t0, t0, t1); |
|
| 5557 |
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3)); |
|
| 5558 |
tcg_gen_or_i32(t0, t0, t1); |
|
| 5559 |
tcg_temp_free_i32(t1); |
|
| 5560 |
tcg_gen_not_i32(t0, t0); |
|
| 5561 |
tcg_gen_andi_i32(t0, t0, 1); |
|
| 5562 |
tcg_gen_extu_i32_tl(bcond, t0); |
|
| 5613 | 5563 |
} |
| 5614 | 5564 |
opn = "bc1any4f"; |
| 5615 | 5565 |
goto not_likely; |
| 5616 | 5566 |
case OPC_BC1TANY4: |
| 5617 | 5567 |
{
|
| 5618 |
int l1 = gen_new_label();
|
|
| 5619 |
int l2 = gen_new_label();
|
|
| 5620 |
|
|
| 5621 |
get_fp_cond(t0);
|
|
| 5622 |
tcg_gen_andi_i32(t0, t0, 0xf << cc);
|
|
| 5623 |
tcg_gen_brcondi_i32(TCG_COND_NE, t0, 0, l1);
|
|
| 5624 |
tcg_gen_movi_tl(bcond, 0);
|
|
| 5625 |
tcg_gen_br(l2);
|
|
| 5626 |
gen_set_label(l1);
|
|
| 5627 |
tcg_gen_movi_tl(bcond, 1);
|
|
| 5628 |
gen_set_label(l2);
|
|
| 5568 |
TCGv_i32 t1 = tcg_temp_new_i32();
|
|
| 5569 |
tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc));
|
|
| 5570 |
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+1)); |
|
| 5571 |
tcg_gen_or_i32(t0, t0, t1);
|
|
| 5572 |
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+2));
|
|
| 5573 |
tcg_gen_or_i32(t0, t0, t1);
|
|
| 5574 |
tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc+3));
|
|
| 5575 |
tcg_gen_or_i32(t0, t0, t1);
|
|
| 5576 |
tcg_temp_free_i32(t1);
|
|
| 5577 |
tcg_gen_andi_i32(t0, t0, 1);
|
|
| 5578 |
tcg_gen_extu_i32_tl(bcond, t0);
|
|
| 5629 | 5579 |
} |
| 5630 | 5580 |
opn = "bc1any4t"; |
| 5631 | 5581 |
not_likely: |
Also available in: Unified diff