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1
/*
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   SPARC translation
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4
   Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
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   Copyright (C) 2003-2005 Fabrice Bellard
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7
   This library is free software; you can redistribute it and/or
8
   modify it under the terms of the GNU Lesser General Public
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   License as published by the Free Software Foundation; either
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   version 2 of the License, or (at your option) any later version.
11

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   This library is distributed in the hope that it will be useful,
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   but WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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   Lesser General Public License for more details.
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   You should have received a copy of the GNU Lesser General Public
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   License along with this library; if not, write to the Free Software
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   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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28
#include "cpu.h"
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#include "exec-all.h"
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#include "disas.h"
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#include "helper.h"
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#include "tcg-op.h"
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34
#define DEBUG_DISAS
35

    
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#define DYNAMIC_PC  1 /* dynamic pc value */
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#define JUMP_PC     2 /* dynamic pc value which takes only two values
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                         according to jump_pc[T2] */
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40
/* global register indexes */
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static TCGv cpu_env, cpu_regwptr;
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static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
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static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
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static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
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#ifdef TARGET_SPARC64
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static TCGv cpu_xcc;
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#endif
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/* local register indexes (only used inside old micro ops) */
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static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
50

    
51
typedef struct DisasContext {
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    target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
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    target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
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    target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
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    int is_br;
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    int mem_idx;
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    int fpu_enabled;
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    struct TranslationBlock *tb;
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    uint32_t features;
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} DisasContext;
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62
// This function uses non-native bit order
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#define GET_FIELD(X, FROM, TO) \
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  ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
65

    
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// This function uses the order in the manuals, i.e. bit 0 is 2^0
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#define GET_FIELD_SP(X, FROM, TO) \
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    GET_FIELD(X, 31 - (TO), 31 - (FROM))
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70
#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
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#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
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73
#ifdef TARGET_SPARC64
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#define FFPREG(r) (r)
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#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
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#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
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#else
78
#define FFPREG(r) (r)
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#define DFPREG(r) (r & 0x1e)
80
#define QFPREG(r) (r & 0x1c)
81
#endif
82

    
83
static int sign_extend(int x, int len)
84
{
85
    len = 32 - len;
86
    return (x << len) >> len;
87
}
88

    
89
#define IS_IMM (insn & (1<<13))
90

    
91
/* floating point registers moves */
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static void gen_op_load_fpr_FT0(unsigned int src)
93
{
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
95
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
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}
97

    
98
static void gen_op_load_fpr_FT1(unsigned int src)
99
{
100
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
102
}
103

    
104
static void gen_op_store_FT0_fpr(unsigned int dst)
105
{
106
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
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}
109

    
110
static void gen_op_load_fpr_DT0(unsigned int src)
111
{
112
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
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                   offsetof(CPU_DoubleU, l.upper));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
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                   offsetof(CPU_DoubleU, l.lower));
118
}
119

    
120
static void gen_op_load_fpr_DT1(unsigned int src)
121
{
122
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
124
                   offsetof(CPU_DoubleU, l.upper));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
126
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) +
127
                   offsetof(CPU_DoubleU, l.lower));
128
}
129

    
130
static void gen_op_store_DT0_fpr(unsigned int dst)
131
{
132
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
133
                   offsetof(CPU_DoubleU, l.upper));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) +
136
                   offsetof(CPU_DoubleU, l.lower));
137
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
138
}
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140
static void gen_op_load_fpr_QT0(unsigned int src)
141
{
142
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
143
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
144
                   offsetof(CPU_QuadU, l.upmost));
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    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
146
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
147
                   offsetof(CPU_QuadU, l.upper));
148
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
149
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
150
                   offsetof(CPU_QuadU, l.lower));
151
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
152
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
153
                   offsetof(CPU_QuadU, l.lowest));
154
}
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156
static void gen_op_load_fpr_QT1(unsigned int src)
157
{
158
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
159
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
160
                   offsetof(CPU_QuadU, l.upmost));
161
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
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    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
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                   offsetof(CPU_QuadU, l.upper));
164
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
165
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
166
                   offsetof(CPU_QuadU, l.lower));
167
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
168
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) +
169
                   offsetof(CPU_QuadU, l.lowest));
170
}
171

    
172
static void gen_op_store_QT0_fpr(unsigned int dst)
173
{
174
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
175
                   offsetof(CPU_QuadU, l.upmost));
176
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
177
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
178
                   offsetof(CPU_QuadU, l.upper));
179
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
180
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
181
                   offsetof(CPU_QuadU, l.lower));
182
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
183
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) +
184
                   offsetof(CPU_QuadU, l.lowest));
185
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
186
}
187

    
188
/* moves */
189
#ifdef CONFIG_USER_ONLY
190
#define supervisor(dc) 0
191
#ifdef TARGET_SPARC64
192
#define hypervisor(dc) 0
193
#endif
194
#else
195
#define supervisor(dc) (dc->mem_idx >= 1)
196
#ifdef TARGET_SPARC64
197
#define hypervisor(dc) (dc->mem_idx == 2)
198
#else
199
#endif
200
#endif
201

    
202
#ifdef TARGET_ABI32
203
#define ABI32_MASK(addr) tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
204
#else
205
#define ABI32_MASK(addr)
206
#endif
207

    
208
static inline void gen_movl_reg_TN(int reg, TCGv tn)
209
{
210
    if (reg == 0)
211
        tcg_gen_movi_tl(tn, 0);
212
    else if (reg < 8)
213
        tcg_gen_mov_tl(tn, cpu_gregs[reg]);
214
    else {
215
        tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
216
    }
217
}
218

    
219
static inline void gen_movl_TN_reg(int reg, TCGv tn)
220
{
221
    if (reg == 0)
222
        return;
223
    else if (reg < 8)
224
        tcg_gen_mov_tl(cpu_gregs[reg], tn);
225
    else {
226
        tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
227
    }
228
}
229

    
230
static inline void gen_goto_tb(DisasContext *s, int tb_num,
231
                               target_ulong pc, target_ulong npc)
232
{
233
    TranslationBlock *tb;
234

    
235
    tb = s->tb;
236
    if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
237
        (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {
238
        /* jump to same page: we can use a direct jump */
239
        tcg_gen_goto_tb(tb_num);
240
        tcg_gen_movi_tl(cpu_pc, pc);
241
        tcg_gen_movi_tl(cpu_npc, npc);
242
        tcg_gen_exit_tb((long)tb + tb_num);
243
    } else {
244
        /* jump to another page: currently not optimized */
245
        tcg_gen_movi_tl(cpu_pc, pc);
246
        tcg_gen_movi_tl(cpu_npc, npc);
247
        tcg_gen_exit_tb(0);
248
    }
249
}
250

    
251
// XXX suboptimal
252
static inline void gen_mov_reg_N(TCGv reg, TCGv src)
253
{
254
    tcg_gen_extu_i32_tl(reg, src);
255
    tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
256
    tcg_gen_andi_tl(reg, reg, 0x1);
257
}
258

    
259
static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
260
{
261
    tcg_gen_extu_i32_tl(reg, src);
262
    tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
263
    tcg_gen_andi_tl(reg, reg, 0x1);
264
}
265

    
266
static inline void gen_mov_reg_V(TCGv reg, TCGv src)
267
{
268
    tcg_gen_extu_i32_tl(reg, src);
269
    tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
270
    tcg_gen_andi_tl(reg, reg, 0x1);
271
}
272

    
273
static inline void gen_mov_reg_C(TCGv reg, TCGv src)
274
{
275
    tcg_gen_extu_i32_tl(reg, src);
276
    tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
277
    tcg_gen_andi_tl(reg, reg, 0x1);
278
}
279

    
280
static inline void gen_cc_clear_icc(void)
281
{
282
    tcg_gen_movi_i32(cpu_psr, 0);
283
}
284

    
285
#ifdef TARGET_SPARC64
286
static inline void gen_cc_clear_xcc(void)
287
{
288
    tcg_gen_movi_i32(cpu_xcc, 0);
289
}
290
#endif
291

    
292
/* old op:
293
    if (!T0)
294
        env->psr |= PSR_ZERO;
295
    if ((int32_t) T0 < 0)
296
        env->psr |= PSR_NEG;
297
*/
298
static inline void gen_cc_NZ_icc(TCGv dst)
299
{
300
    TCGv r_temp;
301
    int l1, l2;
302

    
303
    l1 = gen_new_label();
304
    l2 = gen_new_label();
305
    r_temp = tcg_temp_new(TCG_TYPE_TL);
306
    tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
307
    tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
308
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
309
    gen_set_label(l1);
310
    tcg_gen_ext_i32_tl(r_temp, dst);
311
    tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
312
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
313
    gen_set_label(l2);
314
    tcg_temp_free(r_temp);
315
}
316

    
317
#ifdef TARGET_SPARC64
318
static inline void gen_cc_NZ_xcc(TCGv dst)
319
{
320
    int l1, l2;
321

    
322
    l1 = gen_new_label();
323
    l2 = gen_new_label();
324
    tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
325
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
326
    gen_set_label(l1);
327
    tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
328
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
329
    gen_set_label(l2);
330
}
331
#endif
332

    
333
/* old op:
334
    if (T0 < src1)
335
        env->psr |= PSR_CARRY;
336
*/
337
static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
338
{
339
    TCGv r_temp;
340
    int l1;
341

    
342
    l1 = gen_new_label();
343
    r_temp = tcg_temp_new(TCG_TYPE_TL);
344
    tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
345
    tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
346
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
347
    gen_set_label(l1);
348
    tcg_temp_free(r_temp);
349
}
350

    
351
#ifdef TARGET_SPARC64
352
static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
353
{
354
    int l1;
355

    
356
    l1 = gen_new_label();
357
    tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
358
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
359
    gen_set_label(l1);
360
}
361
#endif
362

    
363
/* old op:
364
    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
365
        env->psr |= PSR_OVF;
366
*/
367
static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
368
{
369
    TCGv r_temp;
370

    
371
    r_temp = tcg_temp_new(TCG_TYPE_TL);
372
    tcg_gen_xor_tl(r_temp, src1, src2);
373
    tcg_gen_xori_tl(r_temp, r_temp, -1);
374
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
375
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
376
    tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
377
    tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
378
    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
379
    tcg_temp_free(r_temp);
380
    tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
381
}
382

    
383
#ifdef TARGET_SPARC64
384
static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
385
{
386
    TCGv r_temp;
387

    
388
    r_temp = tcg_temp_new(TCG_TYPE_TL);
389
    tcg_gen_xor_tl(r_temp, src1, src2);
390
    tcg_gen_xori_tl(r_temp, r_temp, -1);
391
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
392
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
393
    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
394
    tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
395
    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
396
    tcg_temp_free(r_temp);
397
    tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
398
}
399
#endif
400

    
401
static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
402
{
403
    TCGv r_temp, r_const;
404
    int l1;
405

    
406
    l1 = gen_new_label();
407

    
408
    r_temp = tcg_temp_new(TCG_TYPE_TL);
409
    tcg_gen_xor_tl(r_temp, src1, src2);
410
    tcg_gen_xori_tl(r_temp, r_temp, -1);
411
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
412
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
413
    tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
414
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
415
    r_const = tcg_const_i32(TT_TOVF);
416
    tcg_gen_helper_0_1(raise_exception, r_const);
417
    tcg_temp_free(r_const);
418
    gen_set_label(l1);
419
    tcg_temp_free(r_temp);
420
}
421

    
422
static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
423
{
424
    int l1;
425

    
426
    l1 = gen_new_label();
427
    tcg_gen_or_tl(cpu_tmp0, src1, src2);
428
    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
429
    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
430
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
431
    gen_set_label(l1);
432
}
433

    
434
static inline void gen_tag_tv(TCGv src1, TCGv src2)
435
{
436
    int l1;
437
    TCGv r_const;
438

    
439
    l1 = gen_new_label();
440
    tcg_gen_or_tl(cpu_tmp0, src1, src2);
441
    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
442
    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
443
    r_const = tcg_const_i32(TT_TOVF);
444
    tcg_gen_helper_0_1(raise_exception, r_const);
445
    tcg_temp_free(r_const);
446
    gen_set_label(l1);
447
}
448

    
449
static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
450
{
451
    tcg_gen_mov_tl(cpu_cc_src, src1);
452
    tcg_gen_mov_tl(cpu_cc_src2, src2);
453
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
454
    gen_cc_clear_icc();
455
    gen_cc_NZ_icc(cpu_cc_dst);
456
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
457
    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
458
#ifdef TARGET_SPARC64
459
    gen_cc_clear_xcc();
460
    gen_cc_NZ_xcc(cpu_cc_dst);
461
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
462
    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
463
#endif
464
    tcg_gen_mov_tl(dst, cpu_cc_dst);
465
}
466

    
467
static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
468
{
469
    tcg_gen_mov_tl(cpu_cc_src, src1);
470
    tcg_gen_mov_tl(cpu_cc_src2, src2);
471
    gen_mov_reg_C(cpu_tmp0, cpu_psr);
472
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
473
    gen_cc_clear_icc();
474
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
475
#ifdef TARGET_SPARC64
476
    gen_cc_clear_xcc();
477
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
478
#endif
479
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
480
    gen_cc_NZ_icc(cpu_cc_dst);
481
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
482
    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
483
#ifdef TARGET_SPARC64
484
    gen_cc_NZ_xcc(cpu_cc_dst);
485
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
486
    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
487
#endif
488
    tcg_gen_mov_tl(dst, cpu_cc_dst);
489
}
490

    
491
static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
492
{
493
    tcg_gen_mov_tl(cpu_cc_src, src1);
494
    tcg_gen_mov_tl(cpu_cc_src2, src2);
495
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
496
    gen_cc_clear_icc();
497
    gen_cc_NZ_icc(cpu_cc_dst);
498
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
499
    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
500
    gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
501
#ifdef TARGET_SPARC64
502
    gen_cc_clear_xcc();
503
    gen_cc_NZ_xcc(cpu_cc_dst);
504
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
505
    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
506
#endif
507
    tcg_gen_mov_tl(dst, cpu_cc_dst);
508
}
509

    
510
static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
511
{
512
    tcg_gen_mov_tl(cpu_cc_src, src1);
513
    tcg_gen_mov_tl(cpu_cc_src2, src2);
514
    gen_tag_tv(cpu_cc_src, cpu_cc_src2);
515
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
516
    gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
517
    gen_cc_clear_icc();
518
    gen_cc_NZ_icc(cpu_cc_dst);
519
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
520
#ifdef TARGET_SPARC64
521
    gen_cc_clear_xcc();
522
    gen_cc_NZ_xcc(cpu_cc_dst);
523
    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
524
    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
525
#endif
526
    tcg_gen_mov_tl(dst, cpu_cc_dst);
527
}
528

    
529
/* old op:
530
    if (src1 < T1)
531
        env->psr |= PSR_CARRY;
532
*/
533
static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
534
{
535
    TCGv r_temp1, r_temp2;
536
    int l1;
537

    
538
    l1 = gen_new_label();
539
    r_temp1 = tcg_temp_new(TCG_TYPE_TL);
540
    r_temp2 = tcg_temp_new(TCG_TYPE_TL);
541
    tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
542
    tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
543
    tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
544
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
545
    gen_set_label(l1);
546
    tcg_temp_free(r_temp1);
547
    tcg_temp_free(r_temp2);
548
}
549

    
550
#ifdef TARGET_SPARC64
551
static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
552
{
553
    int l1;
554

    
555
    l1 = gen_new_label();
556
    tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
557
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
558
    gen_set_label(l1);
559
}
560
#endif
561

    
562
/* old op:
563
    if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
564
        env->psr |= PSR_OVF;
565
*/
566
static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
567
{
568
    TCGv r_temp;
569

    
570
    r_temp = tcg_temp_new(TCG_TYPE_TL);
571
    tcg_gen_xor_tl(r_temp, src1, src2);
572
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
573
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
574
    tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
575
    tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
576
    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
577
    tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
578
    tcg_temp_free(r_temp);
579
}
580

    
581
#ifdef TARGET_SPARC64
582
static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
583
{
584
    TCGv r_temp;
585

    
586
    r_temp = tcg_temp_new(TCG_TYPE_TL);
587
    tcg_gen_xor_tl(r_temp, src1, src2);
588
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
589
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
590
    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
591
    tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
592
    tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
593
    tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
594
    tcg_temp_free(r_temp);
595
}
596
#endif
597

    
598
static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
599
{
600
    TCGv r_temp, r_const;
601
    int l1;
602

    
603
    l1 = gen_new_label();
604

    
605
    r_temp = tcg_temp_new(TCG_TYPE_TL);
606
    tcg_gen_xor_tl(r_temp, src1, src2);
607
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
608
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
609
    tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
610
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
611
    r_const = tcg_const_i32(TT_TOVF);
612
    tcg_gen_helper_0_1(raise_exception, r_const);
613
    tcg_temp_free(r_const);
614
    gen_set_label(l1);
615
    tcg_temp_free(r_temp);
616
}
617

    
618
static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
619
{
620
    tcg_gen_mov_tl(cpu_cc_src, src1);
621
    tcg_gen_mov_tl(cpu_cc_src2, src2);
622
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
623
    gen_cc_clear_icc();
624
    gen_cc_NZ_icc(cpu_cc_dst);
625
    gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
626
    gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
627
#ifdef TARGET_SPARC64
628
    gen_cc_clear_xcc();
629
    gen_cc_NZ_xcc(cpu_cc_dst);
630
    gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
631
    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
632
#endif
633
    tcg_gen_mov_tl(dst, cpu_cc_dst);
634
}
635

    
636
static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
637
{
638
    tcg_gen_mov_tl(cpu_cc_src, src1);
639
    tcg_gen_mov_tl(cpu_cc_src2, src2);
640
    gen_mov_reg_C(cpu_tmp0, cpu_psr);
641
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
642
    gen_cc_clear_icc();
643
    gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
644
#ifdef TARGET_SPARC64
645
    gen_cc_clear_xcc();
646
    gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
647
#endif
648
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
649
    gen_cc_NZ_icc(cpu_cc_dst);
650
    gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
651
    gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
652
#ifdef TARGET_SPARC64
653
    gen_cc_NZ_xcc(cpu_cc_dst);
654
    gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
655
    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
656
#endif
657
    tcg_gen_mov_tl(dst, cpu_cc_dst);
658
}
659

    
660
static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
661
{
662
    tcg_gen_mov_tl(cpu_cc_src, src1);
663
    tcg_gen_mov_tl(cpu_cc_src2, src2);
664
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
665
    gen_cc_clear_icc();
666
    gen_cc_NZ_icc(cpu_cc_dst);
667
    gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
668
    gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
669
    gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
670
#ifdef TARGET_SPARC64
671
    gen_cc_clear_xcc();
672
    gen_cc_NZ_xcc(cpu_cc_dst);
673
    gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
674
    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
675
#endif
676
    tcg_gen_mov_tl(dst, cpu_cc_dst);
677
}
678

    
679
static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
680
{
681
    tcg_gen_mov_tl(cpu_cc_src, src1);
682
    tcg_gen_mov_tl(cpu_cc_src2, src2);
683
    gen_tag_tv(cpu_cc_src, cpu_cc_src2);
684
    tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
685
    gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
686
    gen_cc_clear_icc();
687
    gen_cc_NZ_icc(cpu_cc_dst);
688
    gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
689
#ifdef TARGET_SPARC64
690
    gen_cc_clear_xcc();
691
    gen_cc_NZ_xcc(cpu_cc_dst);
692
    gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
693
    gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
694
#endif
695
    tcg_gen_mov_tl(dst, cpu_cc_dst);
696
}
697

    
698
static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
699
{
700
    TCGv r_temp, r_temp2;
701
    int l1;
702

    
703
    l1 = gen_new_label();
704
    r_temp = tcg_temp_new(TCG_TYPE_TL);
705
    r_temp2 = tcg_temp_new(TCG_TYPE_I32);
706

    
707
    /* old op:
708
    if (!(env->y & 1))
709
        T1 = 0;
710
    */
711
    tcg_gen_mov_tl(cpu_cc_src, src1);
712
    tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
713
    tcg_gen_trunc_tl_i32(r_temp2, r_temp);
714
    tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
715
    tcg_gen_mov_tl(cpu_cc_src2, src2);
716
    tcg_gen_brcondi_i32(TCG_COND_NE, r_temp2, 0, l1);
717
    tcg_gen_movi_tl(cpu_cc_src2, 0);
718
    gen_set_label(l1);
719

    
720
    // b2 = T0 & 1;
721
    // env->y = (b2 << 31) | (env->y >> 1);
722
    tcg_gen_trunc_tl_i32(r_temp2, cpu_cc_src);
723
    tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
724
    tcg_gen_shli_i32(r_temp2, r_temp2, 31);
725
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
726
    tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
727
    tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
728
    tcg_temp_free(r_temp2);
729
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
730

    
731
    // b1 = N ^ V;
732
    gen_mov_reg_N(cpu_tmp0, cpu_psr);
733
    gen_mov_reg_V(r_temp, cpu_psr);
734
    tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
735
    tcg_temp_free(r_temp);
736

    
737
    // T0 = (b1 << 31) | (T0 >> 1);
738
    // src1 = T0;
739
    tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
740
    tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
741
    tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
742

    
743
    /* do addition and update flags */
744
    tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
745

    
746
    gen_cc_clear_icc();
747
    gen_cc_NZ_icc(cpu_cc_dst);
748
    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
749
    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
750
    tcg_gen_mov_tl(dst, cpu_cc_dst);
751
}
752

    
753
static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
754
{
755
    TCGv r_temp, r_temp2;
756

    
757
    r_temp = tcg_temp_new(TCG_TYPE_I64);
758
    r_temp2 = tcg_temp_new(TCG_TYPE_I64);
759

    
760
    tcg_gen_extu_tl_i64(r_temp, src2);
761
    tcg_gen_extu_tl_i64(r_temp2, src1);
762
    tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
763

    
764
    tcg_gen_shri_i64(r_temp, r_temp2, 32);
765
    tcg_gen_trunc_i64_i32(r_temp, r_temp);
766
    tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
767
    tcg_temp_free(r_temp);
768
#ifdef TARGET_SPARC64
769
    tcg_gen_mov_i64(dst, r_temp2);
770
#else
771
    tcg_gen_trunc_i64_tl(dst, r_temp2);
772
#endif
773
    tcg_temp_free(r_temp2);
774
}
775

    
776
static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
777
{
778
    TCGv r_temp, r_temp2;
779

    
780
    r_temp = tcg_temp_new(TCG_TYPE_I64);
781
    r_temp2 = tcg_temp_new(TCG_TYPE_I64);
782

    
783
    tcg_gen_ext_tl_i64(r_temp, src2);
784
    tcg_gen_ext_tl_i64(r_temp2, src1);
785
    tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
786

    
787
    tcg_gen_shri_i64(r_temp, r_temp2, 32);
788
    tcg_gen_trunc_i64_i32(r_temp, r_temp);
789
    tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
790
    tcg_temp_free(r_temp);
791
#ifdef TARGET_SPARC64
792
    tcg_gen_mov_i64(dst, r_temp2);
793
#else
794
    tcg_gen_trunc_i64_tl(dst, r_temp2);
795
#endif
796
    tcg_temp_free(r_temp2);
797
}
798

    
799
#ifdef TARGET_SPARC64
800
static inline void gen_trap_ifdivzero_tl(TCGv divisor)
801
{
802
    TCGv r_const;
803
    int l1;
804

    
805
    l1 = gen_new_label();
806
    tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
807
    r_const = tcg_const_i32(TT_DIV_ZERO);
808
    tcg_gen_helper_0_1(raise_exception, r_const);
809
    tcg_temp_free(r_const);
810
    gen_set_label(l1);
811
}
812

    
813
static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
814
{
815
    int l1, l2;
816

    
817
    l1 = gen_new_label();
818
    l2 = gen_new_label();
819
    tcg_gen_mov_tl(cpu_cc_src, src1);
820
    tcg_gen_mov_tl(cpu_cc_src2, src2);
821
    gen_trap_ifdivzero_tl(cpu_cc_src2);
822
    tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1);
823
    tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
824
    tcg_gen_movi_i64(dst, INT64_MIN);
825
    tcg_gen_br(l2);
826
    gen_set_label(l1);
827
    tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
828
    gen_set_label(l2);
829
}
830
#endif
831

    
832
static inline void gen_op_div_cc(TCGv dst)
833
{
834
    int l1;
835

    
836
    tcg_gen_mov_tl(cpu_cc_dst, dst);
837
    gen_cc_clear_icc();
838
    gen_cc_NZ_icc(cpu_cc_dst);
839
    l1 = gen_new_label();
840
    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1);
841
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
842
    gen_set_label(l1);
843
}
844

    
845
static inline void gen_op_logic_cc(TCGv dst)
846
{
847
    tcg_gen_mov_tl(cpu_cc_dst, dst);
848

    
849
    gen_cc_clear_icc();
850
    gen_cc_NZ_icc(cpu_cc_dst);
851
#ifdef TARGET_SPARC64
852
    gen_cc_clear_xcc();
853
    gen_cc_NZ_xcc(cpu_cc_dst);
854
#endif
855
}
856

    
857
// 1
858
static inline void gen_op_eval_ba(TCGv dst)
859
{
860
    tcg_gen_movi_tl(dst, 1);
861
}
862

    
863
// Z
864
static inline void gen_op_eval_be(TCGv dst, TCGv src)
865
{
866
    gen_mov_reg_Z(dst, src);
867
}
868

    
869
// Z | (N ^ V)
870
static inline void gen_op_eval_ble(TCGv dst, TCGv src)
871
{
872
    gen_mov_reg_N(cpu_tmp0, src);
873
    gen_mov_reg_V(dst, src);
874
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
875
    gen_mov_reg_Z(cpu_tmp0, src);
876
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
877
}
878

    
879
// N ^ V
880
static inline void gen_op_eval_bl(TCGv dst, TCGv src)
881
{
882
    gen_mov_reg_V(cpu_tmp0, src);
883
    gen_mov_reg_N(dst, src);
884
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
885
}
886

    
887
// C | Z
888
static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
889
{
890
    gen_mov_reg_Z(cpu_tmp0, src);
891
    gen_mov_reg_C(dst, src);
892
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
893
}
894

    
895
// C
896
static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
897
{
898
    gen_mov_reg_C(dst, src);
899
}
900

    
901
// V
902
static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
903
{
904
    gen_mov_reg_V(dst, src);
905
}
906

    
907
// 0
908
static inline void gen_op_eval_bn(TCGv dst)
909
{
910
    tcg_gen_movi_tl(dst, 0);
911
}
912

    
913
// N
914
static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
915
{
916
    gen_mov_reg_N(dst, src);
917
}
918

    
919
// !Z
920
static inline void gen_op_eval_bne(TCGv dst, TCGv src)
921
{
922
    gen_mov_reg_Z(dst, src);
923
    tcg_gen_xori_tl(dst, dst, 0x1);
924
}
925

    
926
// !(Z | (N ^ V))
927
static inline void gen_op_eval_bg(TCGv dst, TCGv src)
928
{
929
    gen_mov_reg_N(cpu_tmp0, src);
930
    gen_mov_reg_V(dst, src);
931
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
932
    gen_mov_reg_Z(cpu_tmp0, src);
933
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
934
    tcg_gen_xori_tl(dst, dst, 0x1);
935
}
936

    
937
// !(N ^ V)
938
static inline void gen_op_eval_bge(TCGv dst, TCGv src)
939
{
940
    gen_mov_reg_V(cpu_tmp0, src);
941
    gen_mov_reg_N(dst, src);
942
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
943
    tcg_gen_xori_tl(dst, dst, 0x1);
944
}
945

    
946
// !(C | Z)
947
static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
948
{
949
    gen_mov_reg_Z(cpu_tmp0, src);
950
    gen_mov_reg_C(dst, src);
951
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
952
    tcg_gen_xori_tl(dst, dst, 0x1);
953
}
954

    
955
// !C
956
static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
957
{
958
    gen_mov_reg_C(dst, src);
959
    tcg_gen_xori_tl(dst, dst, 0x1);
960
}
961

    
962
// !N
963
static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
964
{
965
    gen_mov_reg_N(dst, src);
966
    tcg_gen_xori_tl(dst, dst, 0x1);
967
}
968

    
969
// !V
970
static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
971
{
972
    gen_mov_reg_V(dst, src);
973
    tcg_gen_xori_tl(dst, dst, 0x1);
974
}
975

    
976
/*
977
  FPSR bit field FCC1 | FCC0:
978
   0 =
979
   1 <
980
   2 >
981
   3 unordered
982
*/
983
static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
984
                                    unsigned int fcc_offset)
985
{
986
    tcg_gen_extu_i32_tl(reg, src);
987
    tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset);
988
    tcg_gen_andi_tl(reg, reg, 0x1);
989
}
990

    
991
static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
992
                                    unsigned int fcc_offset)
993
{
994
    tcg_gen_extu_i32_tl(reg, src);
995
    tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset);
996
    tcg_gen_andi_tl(reg, reg, 0x1);
997
}
998

    
999
// !0: FCC0 | FCC1
1000
static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
1001
                                    unsigned int fcc_offset)
1002
{
1003
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1004
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1005
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
1006
}
1007

    
1008
// 1 or 2: FCC0 ^ FCC1
1009
static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
1010
                                    unsigned int fcc_offset)
1011
{
1012
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1013
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1014
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1015
}
1016

    
1017
// 1 or 3: FCC0
1018
static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1019
                                    unsigned int fcc_offset)
1020
{
1021
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1022
}
1023

    
1024
// 1: FCC0 & !FCC1
1025
static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1026
                                    unsigned int fcc_offset)
1027
{
1028
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1029
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1030
    tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1031
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1032
}
1033

    
1034
// 2 or 3: FCC1
1035
static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1036
                                    unsigned int fcc_offset)
1037
{
1038
    gen_mov_reg_FCC1(dst, src, fcc_offset);
1039
}
1040

    
1041
// 2: !FCC0 & FCC1
1042
static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1043
                                    unsigned int fcc_offset)
1044
{
1045
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1046
    tcg_gen_xori_tl(dst, dst, 0x1);
1047
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1048
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1049
}
1050

    
1051
// 3: FCC0 & FCC1
1052
static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1053
                                    unsigned int fcc_offset)
1054
{
1055
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1056
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1057
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1058
}
1059

    
1060
// 0: !(FCC0 | FCC1)
1061
static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1062
                                    unsigned int fcc_offset)
1063
{
1064
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1065
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1066
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
1067
    tcg_gen_xori_tl(dst, dst, 0x1);
1068
}
1069

    
1070
// 0 or 3: !(FCC0 ^ FCC1)
1071
static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1072
                                    unsigned int fcc_offset)
1073
{
1074
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1075
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1076
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1077
    tcg_gen_xori_tl(dst, dst, 0x1);
1078
}
1079

    
1080
// 0 or 2: !FCC0
1081
static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1082
                                    unsigned int fcc_offset)
1083
{
1084
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1085
    tcg_gen_xori_tl(dst, dst, 0x1);
1086
}
1087

    
1088
// !1: !(FCC0 & !FCC1)
1089
static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1090
                                    unsigned int fcc_offset)
1091
{
1092
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1093
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1094
    tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1095
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1096
    tcg_gen_xori_tl(dst, dst, 0x1);
1097
}
1098

    
1099
// 0 or 1: !FCC1
1100
static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1101
                                    unsigned int fcc_offset)
1102
{
1103
    gen_mov_reg_FCC1(dst, src, fcc_offset);
1104
    tcg_gen_xori_tl(dst, dst, 0x1);
1105
}
1106

    
1107
// !2: !(!FCC0 & FCC1)
1108
static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1109
                                    unsigned int fcc_offset)
1110
{
1111
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1112
    tcg_gen_xori_tl(dst, dst, 0x1);
1113
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1114
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1115
    tcg_gen_xori_tl(dst, dst, 0x1);
1116
}
1117

    
1118
// !3: !(FCC0 & FCC1)
1119
static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1120
                                    unsigned int fcc_offset)
1121
{
1122
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1123
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1124
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1125
    tcg_gen_xori_tl(dst, dst, 0x1);
1126
}
1127

    
1128
static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1129
                               target_ulong pc2, TCGv r_cond)
1130
{
1131
    int l1;
1132

    
1133
    l1 = gen_new_label();
1134

    
1135
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1136

    
1137
    gen_goto_tb(dc, 0, pc1, pc1 + 4);
1138

    
1139
    gen_set_label(l1);
1140
    gen_goto_tb(dc, 1, pc2, pc2 + 4);
1141
}
1142

    
1143
static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1144
                                target_ulong pc2, TCGv r_cond)
1145
{
1146
    int l1;
1147

    
1148
    l1 = gen_new_label();
1149

    
1150
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1151

    
1152
    gen_goto_tb(dc, 0, pc2, pc1);
1153

    
1154
    gen_set_label(l1);
1155
    gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1156
}
1157

    
1158
static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1159
                                      TCGv r_cond)
1160
{
1161
    int l1, l2;
1162

    
1163
    l1 = gen_new_label();
1164
    l2 = gen_new_label();
1165

    
1166
    tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1167

    
1168
    tcg_gen_movi_tl(cpu_npc, npc1);
1169
    tcg_gen_br(l2);
1170

    
1171
    gen_set_label(l1);
1172
    tcg_gen_movi_tl(cpu_npc, npc2);
1173
    gen_set_label(l2);
1174
}
1175

    
1176
/* call this function before using the condition register as it may
1177
   have been set for a jump */
1178
static inline void flush_cond(DisasContext *dc, TCGv cond)
1179
{
1180
    if (dc->npc == JUMP_PC) {
1181
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1182
        dc->npc = DYNAMIC_PC;
1183
    }
1184
}
1185

    
1186
static inline void save_npc(DisasContext *dc, TCGv cond)
1187
{
1188
    if (dc->npc == JUMP_PC) {
1189
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1190
        dc->npc = DYNAMIC_PC;
1191
    } else if (dc->npc != DYNAMIC_PC) {
1192
        tcg_gen_movi_tl(cpu_npc, dc->npc);
1193
    }
1194
}
1195

    
1196
static inline void save_state(DisasContext *dc, TCGv cond)
1197
{
1198
    tcg_gen_movi_tl(cpu_pc, dc->pc);
1199
    save_npc(dc, cond);
1200
}
1201

    
1202
static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1203
{
1204
    if (dc->npc == JUMP_PC) {
1205
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1206
        tcg_gen_mov_tl(cpu_pc, cpu_npc);
1207
        dc->pc = DYNAMIC_PC;
1208
    } else if (dc->npc == DYNAMIC_PC) {
1209
        tcg_gen_mov_tl(cpu_pc, cpu_npc);
1210
        dc->pc = DYNAMIC_PC;
1211
    } else {
1212
        dc->pc = dc->npc;
1213
    }
1214
}
1215

    
1216
static inline void gen_op_next_insn(void)
1217
{
1218
    tcg_gen_mov_tl(cpu_pc, cpu_npc);
1219
    tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1220
}
1221

    
1222
static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1223
{
1224
    TCGv r_src;
1225

    
1226
#ifdef TARGET_SPARC64
1227
    if (cc)
1228
        r_src = cpu_xcc;
1229
    else
1230
        r_src = cpu_psr;
1231
#else
1232
    r_src = cpu_psr;
1233
#endif
1234
    switch (cond) {
1235
    case 0x0:
1236
        gen_op_eval_bn(r_dst);
1237
        break;
1238
    case 0x1:
1239
        gen_op_eval_be(r_dst, r_src);
1240
        break;
1241
    case 0x2:
1242
        gen_op_eval_ble(r_dst, r_src);
1243
        break;
1244
    case 0x3:
1245
        gen_op_eval_bl(r_dst, r_src);
1246
        break;
1247
    case 0x4:
1248
        gen_op_eval_bleu(r_dst, r_src);
1249
        break;
1250
    case 0x5:
1251
        gen_op_eval_bcs(r_dst, r_src);
1252
        break;
1253
    case 0x6:
1254
        gen_op_eval_bneg(r_dst, r_src);
1255
        break;
1256
    case 0x7:
1257
        gen_op_eval_bvs(r_dst, r_src);
1258
        break;
1259
    case 0x8:
1260
        gen_op_eval_ba(r_dst);
1261
        break;
1262
    case 0x9:
1263
        gen_op_eval_bne(r_dst, r_src);
1264
        break;
1265
    case 0xa:
1266
        gen_op_eval_bg(r_dst, r_src);
1267
        break;
1268
    case 0xb:
1269
        gen_op_eval_bge(r_dst, r_src);
1270
        break;
1271
    case 0xc:
1272
        gen_op_eval_bgu(r_dst, r_src);
1273
        break;
1274
    case 0xd:
1275
        gen_op_eval_bcc(r_dst, r_src);
1276
        break;
1277
    case 0xe:
1278
        gen_op_eval_bpos(r_dst, r_src);
1279
        break;
1280
    case 0xf:
1281
        gen_op_eval_bvc(r_dst, r_src);
1282
        break;
1283
    }
1284
}
1285

    
1286
static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1287
{
1288
    unsigned int offset;
1289

    
1290
    switch (cc) {
1291
    default:
1292
    case 0x0:
1293
        offset = 0;
1294
        break;
1295
    case 0x1:
1296
        offset = 32 - 10;
1297
        break;
1298
    case 0x2:
1299
        offset = 34 - 10;
1300
        break;
1301
    case 0x3:
1302
        offset = 36 - 10;
1303
        break;
1304
    }
1305

    
1306
    switch (cond) {
1307
    case 0x0:
1308
        gen_op_eval_bn(r_dst);
1309
        break;
1310
    case 0x1:
1311
        gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1312
        break;
1313
    case 0x2:
1314
        gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1315
        break;
1316
    case 0x3:
1317
        gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1318
        break;
1319
    case 0x4:
1320
        gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1321
        break;
1322
    case 0x5:
1323
        gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1324
        break;
1325
    case 0x6:
1326
        gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1327
        break;
1328
    case 0x7:
1329
        gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1330
        break;
1331
    case 0x8:
1332
        gen_op_eval_ba(r_dst);
1333
        break;
1334
    case 0x9:
1335
        gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1336
        break;
1337
    case 0xa:
1338
        gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1339
        break;
1340
    case 0xb:
1341
        gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1342
        break;
1343
    case 0xc:
1344
        gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1345
        break;
1346
    case 0xd:
1347
        gen_op_eval_fble(r_dst, cpu_fsr, offset);
1348
        break;
1349
    case 0xe:
1350
        gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1351
        break;
1352
    case 0xf:
1353
        gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1354
        break;
1355
    }
1356
}
1357

    
1358
#ifdef TARGET_SPARC64
1359
// Inverted logic
1360
static const int gen_tcg_cond_reg[8] = {
1361
    -1,
1362
    TCG_COND_NE,
1363
    TCG_COND_GT,
1364
    TCG_COND_GE,
1365
    -1,
1366
    TCG_COND_EQ,
1367
    TCG_COND_LE,
1368
    TCG_COND_LT,
1369
};
1370

    
1371
static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1372
{
1373
    int l1;
1374

    
1375
    l1 = gen_new_label();
1376
    tcg_gen_movi_tl(r_dst, 0);
1377
    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
1378
    tcg_gen_movi_tl(r_dst, 1);
1379
    gen_set_label(l1);
1380
}
1381
#endif
1382

    
1383
/* XXX: potentially incorrect if dynamic npc */
1384
static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1385
                      TCGv r_cond)
1386
{
1387
    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1388
    target_ulong target = dc->pc + offset;
1389

    
1390
    if (cond == 0x0) {
1391
        /* unconditional not taken */
1392
        if (a) {
1393
            dc->pc = dc->npc + 4;
1394
            dc->npc = dc->pc + 4;
1395
        } else {
1396
            dc->pc = dc->npc;
1397
            dc->npc = dc->pc + 4;
1398
        }
1399
    } else if (cond == 0x8) {
1400
        /* unconditional taken */
1401
        if (a) {
1402
            dc->pc = target;
1403
            dc->npc = dc->pc + 4;
1404
        } else {
1405
            dc->pc = dc->npc;
1406
            dc->npc = target;
1407
        }
1408
    } else {
1409
        flush_cond(dc, r_cond);
1410
        gen_cond(r_cond, cc, cond);
1411
        if (a) {
1412
            gen_branch_a(dc, target, dc->npc, r_cond);
1413
            dc->is_br = 1;
1414
        } else {
1415
            dc->pc = dc->npc;
1416
            dc->jump_pc[0] = target;
1417
            dc->jump_pc[1] = dc->npc + 4;
1418
            dc->npc = JUMP_PC;
1419
        }
1420
    }
1421
}
1422

    
1423
/* XXX: potentially incorrect if dynamic npc */
1424
static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1425
                      TCGv r_cond)
1426
{
1427
    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1428
    target_ulong target = dc->pc + offset;
1429

    
1430
    if (cond == 0x0) {
1431
        /* unconditional not taken */
1432
        if (a) {
1433
            dc->pc = dc->npc + 4;
1434
            dc->npc = dc->pc + 4;
1435
        } else {
1436
            dc->pc = dc->npc;
1437
            dc->npc = dc->pc + 4;
1438
        }
1439
    } else if (cond == 0x8) {
1440
        /* unconditional taken */
1441
        if (a) {
1442
            dc->pc = target;
1443
            dc->npc = dc->pc + 4;
1444
        } else {
1445
            dc->pc = dc->npc;
1446
            dc->npc = target;
1447
        }
1448
    } else {
1449
        flush_cond(dc, r_cond);
1450
        gen_fcond(r_cond, cc, cond);
1451
        if (a) {
1452
            gen_branch_a(dc, target, dc->npc, r_cond);
1453
            dc->is_br = 1;
1454
        } else {
1455
            dc->pc = dc->npc;
1456
            dc->jump_pc[0] = target;
1457
            dc->jump_pc[1] = dc->npc + 4;
1458
            dc->npc = JUMP_PC;
1459
        }
1460
    }
1461
}
1462

    
1463
#ifdef TARGET_SPARC64
1464
/* XXX: potentially incorrect if dynamic npc */
1465
static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1466
                          TCGv r_cond, TCGv r_reg)
1467
{
1468
    unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1469
    target_ulong target = dc->pc + offset;
1470

    
1471
    flush_cond(dc, r_cond);
1472
    gen_cond_reg(r_cond, cond, r_reg);
1473
    if (a) {
1474
        gen_branch_a(dc, target, dc->npc, r_cond);
1475
        dc->is_br = 1;
1476
    } else {
1477
        dc->pc = dc->npc;
1478
        dc->jump_pc[0] = target;
1479
        dc->jump_pc[1] = dc->npc + 4;
1480
        dc->npc = JUMP_PC;
1481
    }
1482
}
1483

    
1484
static GenOpFunc * const gen_fcmps[4] = {
1485
    helper_fcmps,
1486
    helper_fcmps_fcc1,
1487
    helper_fcmps_fcc2,
1488
    helper_fcmps_fcc3,
1489
};
1490

    
1491
static GenOpFunc * const gen_fcmpd[4] = {
1492
    helper_fcmpd,
1493
    helper_fcmpd_fcc1,
1494
    helper_fcmpd_fcc2,
1495
    helper_fcmpd_fcc3,
1496
};
1497

    
1498
static GenOpFunc * const gen_fcmpq[4] = {
1499
    helper_fcmpq,
1500
    helper_fcmpq_fcc1,
1501
    helper_fcmpq_fcc2,
1502
    helper_fcmpq_fcc3,
1503
};
1504

    
1505
static GenOpFunc * const gen_fcmpes[4] = {
1506
    helper_fcmpes,
1507
    helper_fcmpes_fcc1,
1508
    helper_fcmpes_fcc2,
1509
    helper_fcmpes_fcc3,
1510
};
1511

    
1512
static GenOpFunc * const gen_fcmped[4] = {
1513
    helper_fcmped,
1514
    helper_fcmped_fcc1,
1515
    helper_fcmped_fcc2,
1516
    helper_fcmped_fcc3,
1517
};
1518

    
1519
static GenOpFunc * const gen_fcmpeq[4] = {
1520
    helper_fcmpeq,
1521
    helper_fcmpeq_fcc1,
1522
    helper_fcmpeq_fcc2,
1523
    helper_fcmpeq_fcc3,
1524
};
1525

    
1526
static inline void gen_op_fcmps(int fccno)
1527
{
1528
    tcg_gen_helper_0_0(gen_fcmps[fccno]);
1529
}
1530

    
1531
static inline void gen_op_fcmpd(int fccno)
1532
{
1533
    tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1534
}
1535

    
1536
static inline void gen_op_fcmpq(int fccno)
1537
{
1538
    tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1539
}
1540

    
1541
static inline void gen_op_fcmpes(int fccno)
1542
{
1543
    tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1544
}
1545

    
1546
static inline void gen_op_fcmped(int fccno)
1547
{
1548
    tcg_gen_helper_0_0(gen_fcmped[fccno]);
1549
}
1550

    
1551
static inline void gen_op_fcmpeq(int fccno)
1552
{
1553
    tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1554
}
1555

    
1556
#else
1557

    
1558
static inline void gen_op_fcmps(int fccno)
1559
{
1560
    tcg_gen_helper_0_0(helper_fcmps);
1561
}
1562

    
1563
static inline void gen_op_fcmpd(int fccno)
1564
{
1565
    tcg_gen_helper_0_0(helper_fcmpd);
1566
}
1567

    
1568
static inline void gen_op_fcmpq(int fccno)
1569
{
1570
    tcg_gen_helper_0_0(helper_fcmpq);
1571
}
1572

    
1573
static inline void gen_op_fcmpes(int fccno)
1574
{
1575
    tcg_gen_helper_0_0(helper_fcmpes);
1576
}
1577

    
1578
static inline void gen_op_fcmped(int fccno)
1579
{
1580
    tcg_gen_helper_0_0(helper_fcmped);
1581
}
1582

    
1583
static inline void gen_op_fcmpeq(int fccno)
1584
{
1585
    tcg_gen_helper_0_0(helper_fcmpeq);
1586
}
1587
#endif
1588

    
1589
static inline void gen_op_fpexception_im(int fsr_flags)
1590
{
1591
    TCGv r_const;
1592

    
1593
    tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1594
    tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1595
    r_const = tcg_const_i32(TT_FP_EXCP);
1596
    tcg_gen_helper_0_1(raise_exception, r_const);
1597
    tcg_temp_free(r_const);
1598
}
1599

    
1600
static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1601
{
1602
#if !defined(CONFIG_USER_ONLY)
1603
    if (!dc->fpu_enabled) {
1604
        TCGv r_const;
1605

    
1606
        save_state(dc, r_cond);
1607
        r_const = tcg_const_i32(TT_NFPU_INSN);
1608
        tcg_gen_helper_0_1(raise_exception, r_const);
1609
        tcg_temp_free(r_const);
1610
        dc->is_br = 1;
1611
        return 1;
1612
    }
1613
#endif
1614
    return 0;
1615
}
1616

    
1617
static inline void gen_op_clear_ieee_excp_and_FTT(void)
1618
{
1619
    tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
1620
}
1621

    
1622
static inline void gen_clear_float_exceptions(void)
1623
{
1624
    tcg_gen_helper_0_0(helper_clear_float_exceptions);
1625
}
1626

    
1627
/* asi moves */
1628
#ifdef TARGET_SPARC64
1629
static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1630
{
1631
    int asi, offset;
1632
    TCGv r_asi;
1633

    
1634
    if (IS_IMM) {
1635
        r_asi = tcg_temp_new(TCG_TYPE_I32);
1636
        offset = GET_FIELD(insn, 25, 31);
1637
        tcg_gen_addi_tl(r_addr, r_addr, offset);
1638
        tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1639
    } else {
1640
        asi = GET_FIELD(insn, 19, 26);
1641
        r_asi = tcg_const_i32(asi);
1642
    }
1643
    return r_asi;
1644
}
1645

    
1646
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1647
                              int sign)
1648
{
1649
    TCGv r_asi, r_size, r_sign;
1650

    
1651
    r_asi = gen_get_asi(insn, addr);
1652
    r_size = tcg_const_i32(size);
1653
    r_sign = tcg_const_i32(sign);
1654
    tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign);
1655
    tcg_temp_free(r_sign);
1656
    tcg_temp_free(r_size);
1657
    tcg_temp_free(r_asi);
1658
}
1659

    
1660
static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1661
{
1662
    TCGv r_asi, r_size;
1663

    
1664
    r_asi = gen_get_asi(insn, addr);
1665
    r_size = tcg_const_i32(size);
1666
    tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size);
1667
    tcg_temp_free(r_size);
1668
    tcg_temp_free(r_asi);
1669
}
1670

    
1671
static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1672
{
1673
    TCGv r_asi, r_size, r_rd;
1674

    
1675
    r_asi = gen_get_asi(insn, addr);
1676
    r_size = tcg_const_i32(size);
1677
    r_rd = tcg_const_i32(rd);
1678
    tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd);
1679
    tcg_temp_free(r_rd);
1680
    tcg_temp_free(r_size);
1681
    tcg_temp_free(r_asi);
1682
}
1683

    
1684
static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1685
{
1686
    TCGv r_asi, r_size, r_rd;
1687

    
1688
    r_asi = gen_get_asi(insn, addr);
1689
    r_size = tcg_const_i32(size);
1690
    r_rd = tcg_const_i32(rd);
1691
    tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd);
1692
    tcg_temp_free(r_rd);
1693
    tcg_temp_free(r_size);
1694
    tcg_temp_free(r_asi);
1695
}
1696

    
1697
static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1698
{
1699
    TCGv r_asi, r_size, r_sign;
1700

    
1701
    r_asi = gen_get_asi(insn, addr);
1702
    r_size = tcg_const_i32(4);
1703
    r_sign = tcg_const_i32(0);
1704
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1705
    tcg_temp_free(r_sign);
1706
    tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1707
    tcg_temp_free(r_size);
1708
    tcg_temp_free(r_asi);
1709
    tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1710
}
1711

    
1712
static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1713
{
1714
    TCGv r_asi, r_size, r_sign;
1715

    
1716
    r_asi = gen_get_asi(insn, addr);
1717
    r_size = tcg_const_i32(8);
1718
    r_sign = tcg_const_i32(0);
1719
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1720
    tcg_temp_free(r_sign);
1721
    tcg_temp_free(r_size);
1722
    tcg_temp_free(r_asi);
1723
    tcg_gen_andi_i64(lo, cpu_tmp64, 0xffffffffULL);
1724
    tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1725
    tcg_gen_andi_i64(hi, cpu_tmp64, 0xffffffffULL);
1726
}
1727

    
1728
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1729
{
1730
    TCGv r_temp, r_asi, r_size;
1731

    
1732
    r_temp = tcg_temp_new(TCG_TYPE_TL);
1733
    gen_movl_reg_TN(rd + 1, r_temp);
1734
    tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1735
                       r_temp);
1736
    tcg_temp_free(r_temp);
1737
    r_asi = gen_get_asi(insn, addr);
1738
    r_size = tcg_const_i32(8);
1739
    tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1740
    tcg_temp_free(r_size);
1741
    tcg_temp_free(r_asi);
1742
}
1743

    
1744
static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1745
                               int rd)
1746
{
1747
    TCGv r_val1, r_asi;
1748

    
1749
    r_val1 = tcg_temp_new(TCG_TYPE_TL);
1750
    gen_movl_reg_TN(rd, r_val1);
1751
    r_asi = gen_get_asi(insn, addr);
1752
    tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1753
    tcg_temp_free(r_asi);
1754
    tcg_temp_free(r_val1);
1755
}
1756

    
1757
static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1758
                                int rd)
1759
{
1760
    TCGv r_asi;
1761

    
1762
    gen_movl_reg_TN(rd, cpu_tmp64);
1763
    r_asi = gen_get_asi(insn, addr);
1764
    tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1765
    tcg_temp_free(r_asi);
1766
}
1767

    
1768
#elif !defined(CONFIG_USER_ONLY)
1769

    
1770
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1771
                              int sign)
1772
{
1773
    TCGv r_asi, r_size, r_sign;
1774

    
1775
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1776
    r_size = tcg_const_i32(size);
1777
    r_sign = tcg_const_i32(sign);
1778
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1779
    tcg_temp_free(r_sign);
1780
    tcg_temp_free(r_size);
1781
    tcg_temp_free(r_asi);
1782
    tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1783
}
1784

    
1785
static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1786
{
1787
    TCGv r_asi, r_size;
1788

    
1789
    tcg_gen_extu_tl_i64(cpu_tmp64, src);
1790
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1791
    r_size = tcg_const_i32(size);
1792
    tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1793
    tcg_temp_free(r_size);
1794
    tcg_temp_free(r_asi);
1795
}
1796

    
1797
static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1798
{
1799
    TCGv r_asi, r_size, r_sign;
1800

    
1801
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1802
    r_size = tcg_const_i32(4);
1803
    r_sign = tcg_const_i32(0);
1804
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1805
    tcg_temp_free(r_sign);
1806
    tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size);
1807
    tcg_temp_free(r_size);
1808
    tcg_temp_free(r_asi);
1809
    tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1810
}
1811

    
1812
static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1813
{
1814
    TCGv r_asi, r_size, r_sign;
1815

    
1816
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1817
    r_size = tcg_const_i32(8);
1818
    r_sign = tcg_const_i32(0);
1819
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign);
1820
    tcg_temp_free(r_sign);
1821
    tcg_temp_free(r_size);
1822
    tcg_temp_free(r_asi);
1823
    tcg_gen_trunc_i64_tl(lo, cpu_tmp64);
1824
    tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1825
    tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1826
}
1827

    
1828
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1829
{
1830
    TCGv r_temp, r_asi, r_size;
1831

    
1832
    r_temp = tcg_temp_new(TCG_TYPE_TL);
1833
    gen_movl_reg_TN(rd + 1, r_temp);
1834
    tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1835
    tcg_temp_free(r_temp);
1836
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1837
    r_size = tcg_const_i32(8);
1838
    tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size);
1839
    tcg_temp_free(r_size);
1840
    tcg_temp_free(r_asi);
1841
}
1842
#endif
1843

    
1844
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1845
static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1846
{
1847
    TCGv r_val, r_asi, r_size;
1848

    
1849
    gen_ld_asi(dst, addr, insn, 1, 0);
1850

    
1851
    r_val = tcg_const_i64(0xffULL);
1852
    r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1853
    r_size = tcg_const_i32(1);
1854
    tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size);
1855
    tcg_temp_free(r_size);
1856
    tcg_temp_free(r_asi);
1857
    tcg_temp_free(r_val);
1858
}
1859
#endif
1860

    
1861
static inline TCGv get_src1(unsigned int insn, TCGv def)
1862
{
1863
    TCGv r_rs1 = def;
1864
    unsigned int rs1;
1865

    
1866
    rs1 = GET_FIELD(insn, 13, 17);
1867
    if (rs1 == 0)
1868
        r_rs1 = tcg_const_tl(0); // XXX how to free?
1869
    else if (rs1 < 8)
1870
        r_rs1 = cpu_gregs[rs1];
1871
    else
1872
        tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1873
    return r_rs1;
1874
}
1875

    
1876
static inline TCGv get_src2(unsigned int insn, TCGv def)
1877
{
1878
    TCGv r_rs2 = def;
1879
    unsigned int rs2;
1880

    
1881
    if (IS_IMM) { /* immediate */
1882
        rs2 = GET_FIELDs(insn, 19, 31);
1883
        r_rs2 = tcg_const_tl((int)rs2); // XXX how to free?
1884
    } else { /* register */
1885
        rs2 = GET_FIELD(insn, 27, 31);
1886
        if (rs2 == 0)
1887
            r_rs2 = tcg_const_tl(0); // XXX how to free?
1888
        else if (rs2 < 8)
1889
            r_rs2 = cpu_gregs[rs2];
1890
        else
1891
            tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1892
    }
1893
    return r_rs2;
1894
}
1895

    
1896
#define CHECK_IU_FEATURE(dc, FEATURE)                      \
1897
    if (!((dc)->features & CPU_FEATURE_ ## FEATURE))       \
1898
        goto illegal_insn;
1899
#define CHECK_FPU_FEATURE(dc, FEATURE)                     \
1900
    if (!((dc)->features & CPU_FEATURE_ ## FEATURE))       \
1901
        goto nfpu_insn;
1902

    
1903
/* before an instruction, dc->pc must be static */
1904
static void disas_sparc_insn(DisasContext * dc)
1905
{
1906
    unsigned int insn, opc, rs1, rs2, rd;
1907

    
1908
    if (unlikely(loglevel & CPU_LOG_TB_OP))
1909
        tcg_gen_debug_insn_start(dc->pc);
1910
    insn = ldl_code(dc->pc);
1911
    opc = GET_FIELD(insn, 0, 1);
1912

    
1913
    rd = GET_FIELD(insn, 2, 6);
1914

    
1915
    cpu_src1 = tcg_temp_new(TCG_TYPE_TL); // const
1916
    cpu_src2 = tcg_temp_new(TCG_TYPE_TL); // const
1917

    
1918
    switch (opc) {
1919
    case 0:                     /* branches/sethi */
1920
        {
1921
            unsigned int xop = GET_FIELD(insn, 7, 9);
1922
            int32_t target;
1923
            switch (xop) {
1924
#ifdef TARGET_SPARC64
1925
            case 0x1:           /* V9 BPcc */
1926
                {
1927
                    int cc;
1928

    
1929
                    target = GET_FIELD_SP(insn, 0, 18);
1930
                    target = sign_extend(target, 18);
1931
                    target <<= 2;
1932
                    cc = GET_FIELD_SP(insn, 20, 21);
1933
                    if (cc == 0)
1934
                        do_branch(dc, target, insn, 0, cpu_cond);
1935
                    else if (cc == 2)
1936
                        do_branch(dc, target, insn, 1, cpu_cond);
1937
                    else
1938
                        goto illegal_insn;
1939
                    goto jmp_insn;
1940
                }
1941
            case 0x3:           /* V9 BPr */
1942
                {
1943
                    target = GET_FIELD_SP(insn, 0, 13) |
1944
                        (GET_FIELD_SP(insn, 20, 21) << 14);
1945
                    target = sign_extend(target, 16);
1946
                    target <<= 2;
1947
                    cpu_src1 = get_src1(insn, cpu_src1);
1948
                    do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1949
                    goto jmp_insn;
1950
                }
1951
            case 0x5:           /* V9 FBPcc */
1952
                {
1953
                    int cc = GET_FIELD_SP(insn, 20, 21);
1954
                    if (gen_trap_ifnofpu(dc, cpu_cond))
1955
                        goto jmp_insn;
1956
                    target = GET_FIELD_SP(insn, 0, 18);
1957
                    target = sign_extend(target, 19);
1958
                    target <<= 2;
1959
                    do_fbranch(dc, target, insn, cc, cpu_cond);
1960
                    goto jmp_insn;
1961
                }
1962
#else
1963
            case 0x7:           /* CBN+x */
1964
                {
1965
                    goto ncp_insn;
1966
                }
1967
#endif
1968
            case 0x2:           /* BN+x */
1969
                {
1970
                    target = GET_FIELD(insn, 10, 31);
1971
                    target = sign_extend(target, 22);
1972
                    target <<= 2;
1973
                    do_branch(dc, target, insn, 0, cpu_cond);
1974
                    goto jmp_insn;
1975
                }
1976
            case 0x6:           /* FBN+x */
1977
                {
1978
                    if (gen_trap_ifnofpu(dc, cpu_cond))
1979
                        goto jmp_insn;
1980
                    target = GET_FIELD(insn, 10, 31);
1981
                    target = sign_extend(target, 22);
1982
                    target <<= 2;
1983
                    do_fbranch(dc, target, insn, 0, cpu_cond);
1984
                    goto jmp_insn;
1985
                }
1986
            case 0x4:           /* SETHI */
1987
                if (rd) { // nop
1988
                    uint32_t value = GET_FIELD(insn, 10, 31);
1989
                    TCGv r_const;
1990

    
1991
                    r_const = tcg_const_tl(value << 10);
1992
                    gen_movl_TN_reg(rd, r_const);
1993
                    tcg_temp_free(r_const);
1994
                }
1995
                break;
1996
            case 0x0:           /* UNIMPL */
1997
            default:
1998
                goto illegal_insn;
1999
            }
2000
            break;
2001
        }
2002
        break;
2003
    case 1:
2004
        /*CALL*/ {
2005
            target_long target = GET_FIELDs(insn, 2, 31) << 2;
2006
            TCGv r_const;
2007

    
2008
            r_const = tcg_const_tl(dc->pc);
2009
            gen_movl_TN_reg(15, r_const);
2010
            tcg_temp_free(r_const);
2011
            target += dc->pc;
2012
            gen_mov_pc_npc(dc, cpu_cond);
2013
            dc->npc = target;
2014
        }
2015
        goto jmp_insn;
2016
    case 2:                     /* FPU & Logical Operations */
2017
        {
2018
            unsigned int xop = GET_FIELD(insn, 7, 12);
2019
            if (xop == 0x3a) {  /* generate trap */
2020
                int cond;
2021

    
2022
                cpu_src1 = get_src1(insn, cpu_src1);
2023
                if (IS_IMM) {
2024
                    rs2 = GET_FIELD(insn, 25, 31);
2025
                    tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
2026
                } else {
2027
                    rs2 = GET_FIELD(insn, 27, 31);
2028
                    if (rs2 != 0) {
2029
                        gen_movl_reg_TN(rs2, cpu_src2);
2030
                        tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2031
                    } else
2032
                        tcg_gen_mov_tl(cpu_dst, cpu_src1);
2033
                }
2034
                cond = GET_FIELD(insn, 3, 6);
2035
                if (cond == 0x8) {
2036
                    save_state(dc, cpu_cond);
2037
                    tcg_gen_helper_0_1(helper_trap, cpu_dst);
2038
                } else if (cond != 0) {
2039
                    TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
2040
#ifdef TARGET_SPARC64
2041
                    /* V9 icc/xcc */
2042
                    int cc = GET_FIELD_SP(insn, 11, 12);
2043

    
2044
                    save_state(dc, cpu_cond);
2045
                    if (cc == 0)
2046
                        gen_cond(r_cond, 0, cond);
2047
                    else if (cc == 2)
2048
                        gen_cond(r_cond, 1, cond);
2049
                    else
2050
                        goto illegal_insn;
2051
#else
2052
                    save_state(dc, cpu_cond);
2053
                    gen_cond(r_cond, 0, cond);
2054
#endif
2055
                    tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
2056
                    tcg_temp_free(r_cond);
2057
                }
2058
                gen_op_next_insn();
2059
                tcg_gen_exit_tb(0);
2060
                dc->is_br = 1;
2061
                goto jmp_insn;
2062
            } else if (xop == 0x28) {
2063
                rs1 = GET_FIELD(insn, 13, 17);
2064
                switch(rs1) {
2065
                case 0: /* rdy */
2066
#ifndef TARGET_SPARC64
2067
                case 0x01 ... 0x0e: /* undefined in the SPARCv8
2068
                                       manual, rdy on the microSPARC
2069
                                       II */
2070
                case 0x0f:          /* stbar in the SPARCv8 manual,
2071
                                       rdy on the microSPARC II */
2072
                case 0x10 ... 0x1f: /* implementation-dependent in the
2073
                                       SPARCv8 manual, rdy on the
2074
                                       microSPARC II */
2075
#endif
2076
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2077
                                  offsetof(CPUSPARCState, y));
2078
                    gen_movl_TN_reg(rd, cpu_tmp0);
2079
                    break;
2080
#ifdef TARGET_SPARC64
2081
                case 0x2: /* V9 rdccr */
2082
                    tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2083
                    gen_movl_TN_reg(rd, cpu_dst);
2084
                    break;
2085
                case 0x3: /* V9 rdasi */
2086
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2087
                                   offsetof(CPUSPARCState, asi));
2088
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2089
                    gen_movl_TN_reg(rd, cpu_dst);
2090
                    break;
2091
                case 0x4: /* V9 rdtick */
2092
                    {
2093
                        TCGv r_tickptr;
2094

    
2095
                        r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2096
                        tcg_gen_ld_ptr(r_tickptr, cpu_env,
2097
                                       offsetof(CPUState, tick));
2098
                        tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2099
                                           r_tickptr);
2100
                        tcg_temp_free(r_tickptr);
2101
                        gen_movl_TN_reg(rd, cpu_dst);
2102
                    }
2103
                    break;
2104
                case 0x5: /* V9 rdpc */
2105
                    {
2106
                        TCGv r_const;
2107

    
2108
                        r_const = tcg_const_tl(dc->pc);
2109
                        gen_movl_TN_reg(rd, r_const);
2110
                        tcg_temp_free(r_const);
2111
                    }
2112
                    break;
2113
                case 0x6: /* V9 rdfprs */
2114
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2115
                                   offsetof(CPUSPARCState, fprs));
2116
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2117
                    gen_movl_TN_reg(rd, cpu_dst);
2118
                    break;
2119
                case 0xf: /* V9 membar */
2120
                    break; /* no effect */
2121
                case 0x13: /* Graphics Status */
2122
                    if (gen_trap_ifnofpu(dc, cpu_cond))
2123
                        goto jmp_insn;
2124
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2125
                                  offsetof(CPUSPARCState, gsr));
2126
                    gen_movl_TN_reg(rd, cpu_tmp0);
2127
                    break;
2128
                case 0x17: /* Tick compare */
2129
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2130
                                  offsetof(CPUSPARCState, tick_cmpr));
2131
                    gen_movl_TN_reg(rd, cpu_tmp0);
2132
                    break;
2133
                case 0x18: /* System tick */
2134
                    {
2135
                        TCGv r_tickptr;
2136

    
2137
                        r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2138
                        tcg_gen_ld_ptr(r_tickptr, cpu_env,
2139
                                       offsetof(CPUState, stick));
2140
                        tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2141
                                           r_tickptr);
2142
                        tcg_temp_free(r_tickptr);
2143
                        gen_movl_TN_reg(rd, cpu_dst);
2144
                    }
2145
                    break;
2146
                case 0x19: /* System tick compare */
2147
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2148
                                  offsetof(CPUSPARCState, stick_cmpr));
2149
                    gen_movl_TN_reg(rd, cpu_tmp0);
2150
                    break;
2151
                case 0x10: /* Performance Control */
2152
                case 0x11: /* Performance Instrumentation Counter */
2153
                case 0x12: /* Dispatch Control */
2154
                case 0x14: /* Softint set, WO */
2155
                case 0x15: /* Softint clear, WO */
2156
                case 0x16: /* Softint write */
2157
#endif
2158
                default:
2159
                    goto illegal_insn;
2160
                }
2161
#if !defined(CONFIG_USER_ONLY)
2162
            } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2163
#ifndef TARGET_SPARC64
2164
                if (!supervisor(dc))
2165
                    goto priv_insn;
2166
                tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
2167
#else
2168
                if (!hypervisor(dc))
2169
                    goto priv_insn;
2170
                rs1 = GET_FIELD(insn, 13, 17);
2171
                switch (rs1) {
2172
                case 0: // hpstate
2173
                    // gen_op_rdhpstate();
2174
                    break;
2175
                case 1: // htstate
2176
                    // gen_op_rdhtstate();
2177
                    break;
2178
                case 3: // hintp
2179
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2180
                                   offsetof(CPUSPARCState, hintp));
2181
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2182
                    break;
2183
                case 5: // htba
2184
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2185
                                   offsetof(CPUSPARCState, htba));
2186
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2187
                    break;
2188
                case 6: // hver
2189
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2190
                                   offsetof(CPUSPARCState, hver));
2191
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2192
                    break;
2193
                case 31: // hstick_cmpr
2194
                    tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2195
                    tcg_gen_st_i32(cpu_tmp32, cpu_env,
2196
                                   offsetof(CPUSPARCState, hstick_cmpr));
2197
                    break;
2198
                default:
2199
                    goto illegal_insn;
2200
                }
2201
#endif
2202
                gen_movl_TN_reg(rd, cpu_dst);
2203
                break;
2204
            } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2205
                if (!supervisor(dc))
2206
                    goto priv_insn;
2207
#ifdef TARGET_SPARC64
2208
                rs1 = GET_FIELD(insn, 13, 17);
2209
                switch (rs1) {
2210
                case 0: // tpc
2211
                    {
2212
                        TCGv r_tsptr;
2213

    
2214
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2215
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2216
                                       offsetof(CPUState, tsptr));
2217
                        tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2218
                                      offsetof(trap_state, tpc));
2219
                        tcg_temp_free(r_tsptr);
2220
                    }
2221
                    break;
2222
                case 1: // tnpc
2223
                    {
2224
                        TCGv r_tsptr;
2225

    
2226
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2227
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2228
                                       offsetof(CPUState, tsptr));
2229
                        tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2230
                                      offsetof(trap_state, tnpc));
2231
                        tcg_temp_free(r_tsptr);
2232
                    }
2233
                    break;
2234
                case 2: // tstate
2235
                    {
2236
                        TCGv r_tsptr;
2237

    
2238
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2239
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2240
                                       offsetof(CPUState, tsptr));
2241
                        tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2242
                                      offsetof(trap_state, tstate));
2243
                        tcg_temp_free(r_tsptr);
2244
                    }
2245
                    break;
2246
                case 3: // tt
2247
                    {
2248
                        TCGv r_tsptr;
2249

    
2250
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2251
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2252
                                       offsetof(CPUState, tsptr));
2253
                        tcg_gen_ld_i32(cpu_tmp0, r_tsptr,
2254
                                       offsetof(trap_state, tt));
2255
                        tcg_temp_free(r_tsptr);
2256
                    }
2257
                    break;
2258
                case 4: // tick
2259
                    {
2260
                        TCGv r_tickptr;
2261

    
2262
                        r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2263
                        tcg_gen_ld_ptr(r_tickptr, cpu_env,
2264
                                       offsetof(CPUState, tick));
2265
                        tcg_gen_helper_1_1(helper_tick_get_count, cpu_tmp0,
2266
                                           r_tickptr);
2267
                        gen_movl_TN_reg(rd, cpu_tmp0);
2268
                        tcg_temp_free(r_tickptr);
2269
                    }
2270
                    break;
2271
                case 5: // tba
2272
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2273
                                  offsetof(CPUSPARCState, tbr));
2274
                    break;
2275
                case 6: // pstate
2276
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2277
                                   offsetof(CPUSPARCState, pstate));
2278
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2279
                    break;
2280
                case 7: // tl
2281
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2282
                                   offsetof(CPUSPARCState, tl));
2283
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2284
                    break;
2285
                case 8: // pil
2286
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2287
                                   offsetof(CPUSPARCState, psrpil));
2288
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2289
                    break;
2290
                case 9: // cwp
2291
                    tcg_gen_helper_1_0(helper_rdcwp, cpu_tmp0);
2292
                    break;
2293
                case 10: // cansave
2294
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2295
                                   offsetof(CPUSPARCState, cansave));
2296
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2297
                    break;
2298
                case 11: // canrestore
2299
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2300
                                   offsetof(CPUSPARCState, canrestore));
2301
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2302
                    break;
2303
                case 12: // cleanwin
2304
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2305
                                   offsetof(CPUSPARCState, cleanwin));
2306
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2307
                    break;
2308
                case 13: // otherwin
2309
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2310
                                   offsetof(CPUSPARCState, otherwin));
2311
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2312
                    break;
2313
                case 14: // wstate
2314
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2315
                                   offsetof(CPUSPARCState, wstate));
2316
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2317
                    break;
2318
                case 16: // UA2005 gl
2319
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2320
                                   offsetof(CPUSPARCState, gl));
2321
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2322
                    break;
2323
                case 26: // UA2005 strand status
2324
                    if (!hypervisor(dc))
2325
                        goto priv_insn;
2326
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2327
                                   offsetof(CPUSPARCState, ssr));
2328
                    tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2329
                    break;
2330
                case 31: // ver
2331
                    tcg_gen_ld_tl(cpu_tmp0, cpu_env,
2332
                                  offsetof(CPUSPARCState, version));
2333
                    break;
2334
                case 15: // fq
2335
                default:
2336
                    goto illegal_insn;
2337
                }
2338
#else
2339
                tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2340
                               offsetof(CPUSPARCState, wim));
2341
                tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2342
#endif
2343
                gen_movl_TN_reg(rd, cpu_tmp0);
2344
                break;
2345
            } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2346
#ifdef TARGET_SPARC64
2347
                tcg_gen_helper_0_0(helper_flushw);
2348
#else
2349
                if (!supervisor(dc))
2350
                    goto priv_insn;
2351
                tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, tbr));
2352
                gen_movl_TN_reg(rd, cpu_tmp0);
2353
#endif
2354
                break;
2355
#endif
2356
            } else if (xop == 0x34) {   /* FPU Operations */
2357
                if (gen_trap_ifnofpu(dc, cpu_cond))
2358
                    goto jmp_insn;
2359
                gen_op_clear_ieee_excp_and_FTT();
2360
                rs1 = GET_FIELD(insn, 13, 17);
2361
                rs2 = GET_FIELD(insn, 27, 31);
2362
                xop = GET_FIELD(insn, 18, 26);
2363
                switch (xop) {
2364
                    case 0x1: /* fmovs */
2365
                        gen_op_load_fpr_FT0(rs2);
2366
                        gen_op_store_FT0_fpr(rd);
2367
                        break;
2368
                    case 0x5: /* fnegs */
2369
                        gen_op_load_fpr_FT1(rs2);
2370
                        tcg_gen_helper_0_0(helper_fnegs);
2371
                        gen_op_store_FT0_fpr(rd);
2372
                        break;
2373
                    case 0x9: /* fabss */
2374
                        gen_op_load_fpr_FT1(rs2);
2375
                        tcg_gen_helper_0_0(helper_fabss);
2376
                        gen_op_store_FT0_fpr(rd);
2377
                        break;
2378
                    case 0x29: /* fsqrts */
2379
                        CHECK_FPU_FEATURE(dc, FSQRT);
2380
                        gen_op_load_fpr_FT1(rs2);
2381
                        gen_clear_float_exceptions();
2382
                        tcg_gen_helper_0_0(helper_fsqrts);
2383
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2384
                        gen_op_store_FT0_fpr(rd);
2385
                        break;
2386
                    case 0x2a: /* fsqrtd */
2387
                        CHECK_FPU_FEATURE(dc, FSQRT);
2388
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2389
                        gen_clear_float_exceptions();
2390
                        tcg_gen_helper_0_0(helper_fsqrtd);
2391
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2392
                        gen_op_store_DT0_fpr(DFPREG(rd));
2393
                        break;
2394
                    case 0x2b: /* fsqrtq */
2395
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2396
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2397
                        gen_clear_float_exceptions();
2398
                        tcg_gen_helper_0_0(helper_fsqrtq);
2399
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2400
                        gen_op_store_QT0_fpr(QFPREG(rd));
2401
                        break;
2402
                    case 0x41:
2403
                        gen_op_load_fpr_FT0(rs1);
2404
                        gen_op_load_fpr_FT1(rs2);
2405
                        gen_clear_float_exceptions();
2406
                        tcg_gen_helper_0_0(helper_fadds);
2407
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2408
                        gen_op_store_FT0_fpr(rd);
2409
                        break;
2410
                    case 0x42:
2411
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2412
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2413
                        gen_clear_float_exceptions();
2414
                        tcg_gen_helper_0_0(helper_faddd);
2415
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2416
                        gen_op_store_DT0_fpr(DFPREG(rd));
2417
                        break;
2418
                    case 0x43: /* faddq */
2419
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2420
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2421
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2422
                        gen_clear_float_exceptions();
2423
                        tcg_gen_helper_0_0(helper_faddq);
2424
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2425
                        gen_op_store_QT0_fpr(QFPREG(rd));
2426
                        break;
2427
                    case 0x45:
2428
                        gen_op_load_fpr_FT0(rs1);
2429
                        gen_op_load_fpr_FT1(rs2);
2430
                        gen_clear_float_exceptions();
2431
                        tcg_gen_helper_0_0(helper_fsubs);
2432
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2433
                        gen_op_store_FT0_fpr(rd);
2434
                        break;
2435
                    case 0x46:
2436
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2437
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2438
                        gen_clear_float_exceptions();
2439
                        tcg_gen_helper_0_0(helper_fsubd);
2440
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2441
                        gen_op_store_DT0_fpr(DFPREG(rd));
2442
                        break;
2443
                    case 0x47: /* fsubq */
2444
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2445
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2446
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2447
                        gen_clear_float_exceptions();
2448
                        tcg_gen_helper_0_0(helper_fsubq);
2449
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2450
                        gen_op_store_QT0_fpr(QFPREG(rd));
2451
                        break;
2452
                    case 0x49: /* fmuls */
2453
                        CHECK_FPU_FEATURE(dc, FMUL);
2454
                        gen_op_load_fpr_FT0(rs1);
2455
                        gen_op_load_fpr_FT1(rs2);
2456
                        gen_clear_float_exceptions();
2457
                        tcg_gen_helper_0_0(helper_fmuls);
2458
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2459
                        gen_op_store_FT0_fpr(rd);
2460
                        break;
2461
                    case 0x4a: /* fmuld */
2462
                        CHECK_FPU_FEATURE(dc, FMUL);
2463
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2464
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2465
                        gen_clear_float_exceptions();
2466
                        tcg_gen_helper_0_0(helper_fmuld);
2467
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2468
                        gen_op_store_DT0_fpr(DFPREG(rd));
2469
                        break;
2470
                    case 0x4b: /* fmulq */
2471
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2472
                        CHECK_FPU_FEATURE(dc, FMUL);
2473
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2474
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2475
                        gen_clear_float_exceptions();
2476
                        tcg_gen_helper_0_0(helper_fmulq);
2477
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2478
                        gen_op_store_QT0_fpr(QFPREG(rd));
2479
                        break;
2480
                    case 0x4d:
2481
                        gen_op_load_fpr_FT0(rs1);
2482
                        gen_op_load_fpr_FT1(rs2);
2483
                        gen_clear_float_exceptions();
2484
                        tcg_gen_helper_0_0(helper_fdivs);
2485
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2486
                        gen_op_store_FT0_fpr(rd);
2487
                        break;
2488
                    case 0x4e:
2489
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2490
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2491
                        gen_clear_float_exceptions();
2492
                        tcg_gen_helper_0_0(helper_fdivd);
2493
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2494
                        gen_op_store_DT0_fpr(DFPREG(rd));
2495
                        break;
2496
                    case 0x4f: /* fdivq */
2497
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2498
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2499
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2500
                        gen_clear_float_exceptions();
2501
                        tcg_gen_helper_0_0(helper_fdivq);
2502
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2503
                        gen_op_store_QT0_fpr(QFPREG(rd));
2504
                        break;
2505
                    case 0x69:
2506
                        CHECK_FPU_FEATURE(dc, FSMULD);
2507
                        gen_op_load_fpr_FT0(rs1);
2508
                        gen_op_load_fpr_FT1(rs2);
2509
                        gen_clear_float_exceptions();
2510
                        tcg_gen_helper_0_0(helper_fsmuld);
2511
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2512
                        gen_op_store_DT0_fpr(DFPREG(rd));
2513
                        break;
2514
                    case 0x6e: /* fdmulq */
2515
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2516
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2517
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2518
                        gen_clear_float_exceptions();
2519
                        tcg_gen_helper_0_0(helper_fdmulq);
2520
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2521
                        gen_op_store_QT0_fpr(QFPREG(rd));
2522
                        break;
2523
                    case 0xc4:
2524
                        gen_op_load_fpr_FT1(rs2);
2525
                        gen_clear_float_exceptions();
2526
                        tcg_gen_helper_0_0(helper_fitos);
2527
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2528
                        gen_op_store_FT0_fpr(rd);
2529
                        break;
2530
                    case 0xc6:
2531
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2532
                        gen_clear_float_exceptions();
2533
                        tcg_gen_helper_0_0(helper_fdtos);
2534
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2535
                        gen_op_store_FT0_fpr(rd);
2536
                        break;
2537
                    case 0xc7: /* fqtos */
2538
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2539
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2540
                        gen_clear_float_exceptions();
2541
                        tcg_gen_helper_0_0(helper_fqtos);
2542
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2543
                        gen_op_store_FT0_fpr(rd);
2544
                        break;
2545
                    case 0xc8:
2546
                        gen_op_load_fpr_FT1(rs2);
2547
                        tcg_gen_helper_0_0(helper_fitod);
2548
                        gen_op_store_DT0_fpr(DFPREG(rd));
2549
                        break;
2550
                    case 0xc9:
2551
                        gen_op_load_fpr_FT1(rs2);
2552
                        tcg_gen_helper_0_0(helper_fstod);
2553
                        gen_op_store_DT0_fpr(DFPREG(rd));
2554
                        break;
2555
                    case 0xcb: /* fqtod */
2556
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2557
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2558
                        gen_clear_float_exceptions();
2559
                        tcg_gen_helper_0_0(helper_fqtod);
2560
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2561
                        gen_op_store_DT0_fpr(DFPREG(rd));
2562
                        break;
2563
                    case 0xcc: /* fitoq */
2564
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2565
                        gen_op_load_fpr_FT1(rs2);
2566
                        tcg_gen_helper_0_0(helper_fitoq);
2567
                        gen_op_store_QT0_fpr(QFPREG(rd));
2568
                        break;
2569
                    case 0xcd: /* fstoq */
2570
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2571
                        gen_op_load_fpr_FT1(rs2);
2572
                        tcg_gen_helper_0_0(helper_fstoq);
2573
                        gen_op_store_QT0_fpr(QFPREG(rd));
2574
                        break;
2575
                    case 0xce: /* fdtoq */
2576
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2577
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2578
                        tcg_gen_helper_0_0(helper_fdtoq);
2579
                        gen_op_store_QT0_fpr(QFPREG(rd));
2580
                        break;
2581
                    case 0xd1:
2582
                        gen_op_load_fpr_FT1(rs2);
2583
                        gen_clear_float_exceptions();
2584
                        tcg_gen_helper_0_0(helper_fstoi);
2585
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2586
                        gen_op_store_FT0_fpr(rd);
2587
                        break;
2588
                    case 0xd2:
2589
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2590
                        gen_clear_float_exceptions();
2591
                        tcg_gen_helper_0_0(helper_fdtoi);
2592
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2593
                        gen_op_store_FT0_fpr(rd);
2594
                        break;
2595
                    case 0xd3: /* fqtoi */
2596
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2597
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2598
                        gen_clear_float_exceptions();
2599
                        tcg_gen_helper_0_0(helper_fqtoi);
2600
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2601
                        gen_op_store_FT0_fpr(rd);
2602
                        break;
2603
#ifdef TARGET_SPARC64
2604
                    case 0x2: /* V9 fmovd */
2605
                        gen_op_load_fpr_DT0(DFPREG(rs2));
2606
                        gen_op_store_DT0_fpr(DFPREG(rd));
2607
                        break;
2608
                    case 0x3: /* V9 fmovq */
2609
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2610
                        gen_op_load_fpr_QT0(QFPREG(rs2));
2611
                        gen_op_store_QT0_fpr(QFPREG(rd));
2612
                        break;
2613
                    case 0x6: /* V9 fnegd */
2614
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2615
                        tcg_gen_helper_0_0(helper_fnegd);
2616
                        gen_op_store_DT0_fpr(DFPREG(rd));
2617
                        break;
2618
                    case 0x7: /* V9 fnegq */
2619
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2620
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2621
                        tcg_gen_helper_0_0(helper_fnegq);
2622
                        gen_op_store_QT0_fpr(QFPREG(rd));
2623
                        break;
2624
                    case 0xa: /* V9 fabsd */
2625
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2626
                        tcg_gen_helper_0_0(helper_fabsd);
2627
                        gen_op_store_DT0_fpr(DFPREG(rd));
2628
                        break;
2629
                    case 0xb: /* V9 fabsq */
2630
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2631
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2632
                        tcg_gen_helper_0_0(helper_fabsq);
2633
                        gen_op_store_QT0_fpr(QFPREG(rd));
2634
                        break;
2635
                    case 0x81: /* V9 fstox */
2636
                        gen_op_load_fpr_FT1(rs2);
2637
                        gen_clear_float_exceptions();
2638
                        tcg_gen_helper_0_0(helper_fstox);
2639
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2640
                        gen_op_store_DT0_fpr(DFPREG(rd));
2641
                        break;
2642
                    case 0x82: /* V9 fdtox */
2643
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2644
                        gen_clear_float_exceptions();
2645
                        tcg_gen_helper_0_0(helper_fdtox);
2646
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2647
                        gen_op_store_DT0_fpr(DFPREG(rd));
2648
                        break;
2649
                    case 0x83: /* V9 fqtox */
2650
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2651
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2652
                        gen_clear_float_exceptions();
2653
                        tcg_gen_helper_0_0(helper_fqtox);
2654
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2655
                        gen_op_store_DT0_fpr(DFPREG(rd));
2656
                        break;
2657
                    case 0x84: /* V9 fxtos */
2658
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2659
                        gen_clear_float_exceptions();
2660
                        tcg_gen_helper_0_0(helper_fxtos);
2661
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2662
                        gen_op_store_FT0_fpr(rd);
2663
                        break;
2664
                    case 0x88: /* V9 fxtod */
2665
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2666
                        gen_clear_float_exceptions();
2667
                        tcg_gen_helper_0_0(helper_fxtod);
2668
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2669
                        gen_op_store_DT0_fpr(DFPREG(rd));
2670
                        break;
2671
                    case 0x8c: /* V9 fxtoq */
2672
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2673
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2674
                        gen_clear_float_exceptions();
2675
                        tcg_gen_helper_0_0(helper_fxtoq);
2676
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2677
                        gen_op_store_QT0_fpr(QFPREG(rd));
2678
                        break;
2679
#endif
2680
                    default:
2681
                        goto illegal_insn;
2682
                }
2683
            } else if (xop == 0x35) {   /* FPU Operations */
2684
#ifdef TARGET_SPARC64
2685
                int cond;
2686
#endif
2687
                if (gen_trap_ifnofpu(dc, cpu_cond))
2688
                    goto jmp_insn;
2689
                gen_op_clear_ieee_excp_and_FTT();
2690
                rs1 = GET_FIELD(insn, 13, 17);
2691
                rs2 = GET_FIELD(insn, 27, 31);
2692
                xop = GET_FIELD(insn, 18, 26);
2693
#ifdef TARGET_SPARC64
2694
                if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2695
                    int l1;
2696

    
2697
                    l1 = gen_new_label();
2698
                    cond = GET_FIELD_SP(insn, 14, 17);
2699
                    cpu_src1 = get_src1(insn, cpu_src1);
2700
                    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2701
                                       0, l1);
2702
                    gen_op_load_fpr_FT0(rs2);
2703
                    gen_op_store_FT0_fpr(rd);
2704
                    gen_set_label(l1);
2705
                    break;
2706
                } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2707
                    int l1;
2708

    
2709
                    l1 = gen_new_label();
2710
                    cond = GET_FIELD_SP(insn, 14, 17);
2711
                    cpu_src1 = get_src1(insn, cpu_src1);
2712
                    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2713
                                       0, l1);
2714
                    gen_op_load_fpr_DT0(DFPREG(rs2));
2715
                    gen_op_store_DT0_fpr(DFPREG(rd));
2716
                    gen_set_label(l1);
2717
                    break;
2718
                } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2719
                    int l1;
2720

    
2721
                    CHECK_FPU_FEATURE(dc, FLOAT128);
2722
                    l1 = gen_new_label();
2723
                    cond = GET_FIELD_SP(insn, 14, 17);
2724
                    cpu_src1 = get_src1(insn, cpu_src1);
2725
                    tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2726
                                       0, l1);
2727
                    gen_op_load_fpr_QT0(QFPREG(rs2));
2728
                    gen_op_store_QT0_fpr(QFPREG(rd));
2729
                    gen_set_label(l1);
2730
                    break;
2731
                }
2732
#endif
2733
                switch (xop) {
2734
#ifdef TARGET_SPARC64
2735
#define FMOVCC(size_FDQ, fcc)                                           \
2736
                    {                                                   \
2737
                        TCGv r_cond;                                    \
2738
                        int l1;                                         \
2739
                                                                        \
2740
                        l1 = gen_new_label();                           \
2741
                        r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2742
                        cond = GET_FIELD_SP(insn, 14, 17);              \
2743
                        gen_fcond(r_cond, fcc, cond);                   \
2744
                        tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2745
                                           0, l1);                      \
2746
                        glue(glue(gen_op_load_fpr_, size_FDQ), T0)      \
2747
                            (glue(size_FDQ, FPREG(rs2)));               \
2748
                        glue(glue(gen_op_store_, size_FDQ), T0_fpr)     \
2749
                            (glue(size_FDQ, FPREG(rd)));                \
2750
                        gen_set_label(l1);                              \
2751
                        tcg_temp_free(r_cond);                          \
2752
                    }
2753
                    case 0x001: /* V9 fmovscc %fcc0 */
2754
                        FMOVCC(F, 0);
2755
                        break;
2756
                    case 0x002: /* V9 fmovdcc %fcc0 */
2757
                        FMOVCC(D, 0);
2758
                        break;
2759
                    case 0x003: /* V9 fmovqcc %fcc0 */
2760
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2761
                        FMOVCC(Q, 0);
2762
                        break;
2763
                    case 0x041: /* V9 fmovscc %fcc1 */
2764
                        FMOVCC(F, 1);
2765
                        break;
2766
                    case 0x042: /* V9 fmovdcc %fcc1 */
2767
                        FMOVCC(D, 1);
2768
                        break;
2769
                    case 0x043: /* V9 fmovqcc %fcc1 */
2770
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2771
                        FMOVCC(Q, 1);
2772
                        break;
2773
                    case 0x081: /* V9 fmovscc %fcc2 */
2774
                        FMOVCC(F, 2);
2775
                        break;
2776
                    case 0x082: /* V9 fmovdcc %fcc2 */
2777
                        FMOVCC(D, 2);
2778
                        break;
2779
                    case 0x083: /* V9 fmovqcc %fcc2 */
2780
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2781
                        FMOVCC(Q, 2);
2782
                        break;
2783
                    case 0x0c1: /* V9 fmovscc %fcc3 */
2784
                        FMOVCC(F, 3);
2785
                        break;
2786
                    case 0x0c2: /* V9 fmovdcc %fcc3 */
2787
                        FMOVCC(D, 3);
2788
                        break;
2789
                    case 0x0c3: /* V9 fmovqcc %fcc3 */
2790
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2791
                        FMOVCC(Q, 3);
2792
                        break;
2793
#undef FMOVCC
2794
#define FMOVCC(size_FDQ, icc)                                           \
2795
                    {                                                   \
2796
                        TCGv r_cond;                                    \
2797
                        int l1;                                         \
2798
                                                                        \
2799
                        l1 = gen_new_label();                           \
2800
                        r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2801
                        cond = GET_FIELD_SP(insn, 14, 17);              \
2802
                        gen_cond(r_cond, icc, cond);                    \
2803
                        tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond,         \
2804
                                           0, l1);                      \
2805
                        glue(glue(gen_op_load_fpr_, size_FDQ), T0)      \
2806
                            (glue(size_FDQ, FPREG(rs2)));               \
2807
                        glue(glue(gen_op_store_, size_FDQ), T0_fpr)     \
2808
                            (glue(size_FDQ, FPREG(rd)));                \
2809
                        gen_set_label(l1);                              \
2810
                        tcg_temp_free(r_cond);                          \
2811
                    }
2812

    
2813
                    case 0x101: /* V9 fmovscc %icc */
2814
                        FMOVCC(F, 0);
2815
                        break;
2816
                    case 0x102: /* V9 fmovdcc %icc */
2817
                        FMOVCC(D, 0);
2818
                    case 0x103: /* V9 fmovqcc %icc */
2819
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2820
                        FMOVCC(Q, 0);
2821
                        break;
2822
                    case 0x181: /* V9 fmovscc %xcc */
2823
                        FMOVCC(F, 1);
2824
                        break;
2825
                    case 0x182: /* V9 fmovdcc %xcc */
2826
                        FMOVCC(D, 1);
2827
                        break;
2828
                    case 0x183: /* V9 fmovqcc %xcc */
2829
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2830
                        FMOVCC(Q, 1);
2831
                        break;
2832
#undef FMOVCC
2833
#endif
2834
                    case 0x51: /* fcmps, V9 %fcc */
2835
                        gen_op_load_fpr_FT0(rs1);
2836
                        gen_op_load_fpr_FT1(rs2);
2837
                        gen_op_fcmps(rd & 3);
2838
                        break;
2839
                    case 0x52: /* fcmpd, V9 %fcc */
2840
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2841
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2842
                        gen_op_fcmpd(rd & 3);
2843
                        break;
2844
                    case 0x53: /* fcmpq, V9 %fcc */
2845
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2846
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2847
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2848
                        gen_op_fcmpq(rd & 3);
2849
                        break;
2850
                    case 0x55: /* fcmpes, V9 %fcc */
2851
                        gen_op_load_fpr_FT0(rs1);
2852
                        gen_op_load_fpr_FT1(rs2);
2853
                        gen_op_fcmpes(rd & 3);
2854
                        break;
2855
                    case 0x56: /* fcmped, V9 %fcc */
2856
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2857
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2858
                        gen_op_fcmped(rd & 3);
2859
                        break;
2860
                    case 0x57: /* fcmpeq, V9 %fcc */
2861
                        CHECK_FPU_FEATURE(dc, FLOAT128);
2862
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2863
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2864
                        gen_op_fcmpeq(rd & 3);
2865
                        break;
2866
                    default:
2867
                        goto illegal_insn;
2868
                }
2869
            } else if (xop == 0x2) {
2870
                // clr/mov shortcut
2871

    
2872
                rs1 = GET_FIELD(insn, 13, 17);
2873
                if (rs1 == 0) {
2874
                    // or %g0, x, y -> mov T0, x; mov y, T0
2875
                    if (IS_IMM) {       /* immediate */
2876
                        TCGv r_const;
2877

    
2878
                        rs2 = GET_FIELDs(insn, 19, 31);
2879
                        r_const = tcg_const_tl((int)rs2);
2880
                        gen_movl_TN_reg(rd, r_const);
2881
                        tcg_temp_free(r_const);
2882
                    } else {            /* register */
2883
                        rs2 = GET_FIELD(insn, 27, 31);
2884
                        gen_movl_reg_TN(rs2, cpu_dst);
2885
                        gen_movl_TN_reg(rd, cpu_dst);
2886
                    }
2887
                } else {
2888
                    cpu_src1 = get_src1(insn, cpu_src1);
2889
                    if (IS_IMM) {       /* immediate */
2890
                        rs2 = GET_FIELDs(insn, 19, 31);
2891
                        tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
2892
                        gen_movl_TN_reg(rd, cpu_dst);
2893
                    } else {            /* register */
2894
                        // or x, %g0, y -> mov T1, x; mov y, T1
2895
                        rs2 = GET_FIELD(insn, 27, 31);
2896
                        if (rs2 != 0) {
2897
                            gen_movl_reg_TN(rs2, cpu_src2);
2898
                            tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2899
                            gen_movl_TN_reg(rd, cpu_dst);
2900
                        } else
2901
                            gen_movl_TN_reg(rd, cpu_src1);
2902
                    }
2903
                }
2904
#ifdef TARGET_SPARC64
2905
            } else if (xop == 0x25) { /* sll, V9 sllx */
2906
                cpu_src1 = get_src1(insn, cpu_src1);
2907
                if (IS_IMM) {   /* immediate */
2908
                    rs2 = GET_FIELDs(insn, 20, 31);
2909
                    if (insn & (1 << 12)) {
2910
                        tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2911
                    } else {
2912
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2913
                        tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2914
                    }
2915
                } else {                /* register */
2916
                    rs2 = GET_FIELD(insn, 27, 31);
2917
                    gen_movl_reg_TN(rs2, cpu_src2);
2918
                    if (insn & (1 << 12)) {
2919
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2920
                        tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2921
                    } else {
2922
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2923
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2924
                        tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0);
2925
                    }
2926
                }
2927
                gen_movl_TN_reg(rd, cpu_dst);
2928
            } else if (xop == 0x26) { /* srl, V9 srlx */
2929
                cpu_src1 = get_src1(insn, cpu_src1);
2930
                if (IS_IMM) {   /* immediate */
2931
                    rs2 = GET_FIELDs(insn, 20, 31);
2932
                    if (insn & (1 << 12)) {
2933
                        tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2934
                    } else {
2935
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2936
                        tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2937
                    }
2938
                } else {                /* register */
2939
                    rs2 = GET_FIELD(insn, 27, 31);
2940
                    gen_movl_reg_TN(rs2, cpu_src2);
2941
                    if (insn & (1 << 12)) {
2942
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2943
                        tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
2944
                    } else {
2945
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2946
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2947
                        tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
2948
                    }
2949
                }
2950
                gen_movl_TN_reg(rd, cpu_dst);
2951
            } else if (xop == 0x27) { /* sra, V9 srax */
2952
                cpu_src1 = get_src1(insn, cpu_src1);
2953
                if (IS_IMM) {   /* immediate */
2954
                    rs2 = GET_FIELDs(insn, 20, 31);
2955
                    if (insn & (1 << 12)) {
2956
                        tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2957
                    } else {
2958
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2959
                        tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2960
                        tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2961
                    }
2962
                } else {                /* register */
2963
                    rs2 = GET_FIELD(insn, 27, 31);
2964
                    gen_movl_reg_TN(rs2, cpu_src2);
2965
                    if (insn & (1 << 12)) {
2966
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2967
                        tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
2968
                    } else {
2969
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2970
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2971
                        tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
2972
                    }
2973
                }
2974
                gen_movl_TN_reg(rd, cpu_dst);
2975
#endif
2976
            } else if (xop < 0x36) {
2977
                cpu_src1 = get_src1(insn, cpu_src1);
2978
                cpu_src2 = get_src2(insn, cpu_src2);
2979
                if (xop < 0x20) {
2980
                    switch (xop & ~0x10) {
2981
                    case 0x0:
2982
                        if (xop & 0x10)
2983
                            gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
2984
                        else
2985
                            tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2986
                        break;
2987
                    case 0x1:
2988
                        tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
2989
                        if (xop & 0x10)
2990
                            gen_op_logic_cc(cpu_dst);
2991
                        break;
2992
                    case 0x2:
2993
                        tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2994
                        if (xop & 0x10)
2995
                            gen_op_logic_cc(cpu_dst);
2996
                        break;
2997
                    case 0x3:
2998
                        tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
2999
                        if (xop & 0x10)
3000
                            gen_op_logic_cc(cpu_dst);
3001
                        break;
3002
                    case 0x4:
3003
                        if (xop & 0x10)
3004
                            gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3005
                        else
3006
                            tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
3007
                        break;
3008
                    case 0x5:
3009
                        tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3010
                        tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
3011
                        if (xop & 0x10)
3012
                            gen_op_logic_cc(cpu_dst);
3013
                        break;
3014
                    case 0x6:
3015
                        tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3016
                        tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
3017
                        if (xop & 0x10)
3018
                            gen_op_logic_cc(cpu_dst);
3019
                        break;
3020
                    case 0x7:
3021
                        tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3022
                        tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
3023
                        if (xop & 0x10)
3024
                            gen_op_logic_cc(cpu_dst);
3025
                        break;
3026
                    case 0x8:
3027
                        if (xop & 0x10)
3028
                            gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
3029
                        else {
3030
                            gen_mov_reg_C(cpu_tmp0, cpu_psr);
3031
                            tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3032
                            tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
3033
                        }
3034
                        break;
3035
#ifdef TARGET_SPARC64
3036
                    case 0x9: /* V9 mulx */
3037
                        tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
3038
                        break;
3039
#endif
3040
                    case 0xa:
3041
                        CHECK_IU_FEATURE(dc, MUL);
3042
                        gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3043
                        if (xop & 0x10)
3044
                            gen_op_logic_cc(cpu_dst);
3045
                        break;
3046
                    case 0xb:
3047
                        CHECK_IU_FEATURE(dc, MUL);
3048
                        gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3049
                        if (xop & 0x10)
3050
                            gen_op_logic_cc(cpu_dst);
3051
                        break;
3052
                    case 0xc:
3053
                        if (xop & 0x10)
3054
                            gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3055
                        else {
3056
                            gen_mov_reg_C(cpu_tmp0, cpu_psr);
3057
                            tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3058
                            tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
3059
                        }
3060
                        break;
3061
#ifdef TARGET_SPARC64
3062
                    case 0xd: /* V9 udivx */
3063
                        tcg_gen_mov_tl(cpu_cc_src, cpu_src1);
3064
                        tcg_gen_mov_tl(cpu_cc_src2, cpu_src2);
3065
                        gen_trap_ifdivzero_tl(cpu_cc_src2);
3066
                        tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2);
3067
                        break;
3068
#endif
3069
                    case 0xe:
3070
                        CHECK_IU_FEATURE(dc, DIV);
3071
                        tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1,
3072
                                           cpu_src2);
3073
                        if (xop & 0x10)
3074
                            gen_op_div_cc(cpu_dst);
3075
                        break;
3076
                    case 0xf:
3077
                        CHECK_IU_FEATURE(dc, DIV);
3078
                        tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1,
3079
                                           cpu_src2);
3080
                        if (xop & 0x10)
3081
                            gen_op_div_cc(cpu_dst);
3082
                        break;
3083
                    default:
3084
                        goto illegal_insn;
3085
                    }
3086
                    gen_movl_TN_reg(rd, cpu_dst);
3087
                } else {
3088
                    switch (xop) {
3089
                    case 0x20: /* taddcc */
3090
                        gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3091
                        gen_movl_TN_reg(rd, cpu_dst);
3092
                        break;
3093
                    case 0x21: /* tsubcc */
3094
                        gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3095
                        gen_movl_TN_reg(rd, cpu_dst);
3096
                        break;
3097
                    case 0x22: /* taddcctv */
3098
                        save_state(dc, cpu_cond);
3099
                        gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3100
                        gen_movl_TN_reg(rd, cpu_dst);
3101
                        break;
3102
                    case 0x23: /* tsubcctv */
3103
                        save_state(dc, cpu_cond);
3104
                        gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3105
                        gen_movl_TN_reg(rd, cpu_dst);
3106
                        break;
3107
                    case 0x24: /* mulscc */
3108
                        gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3109
                        gen_movl_TN_reg(rd, cpu_dst);
3110
                        break;
3111
#ifndef TARGET_SPARC64
3112
                    case 0x25:  /* sll */
3113
                        if (IS_IMM) { /* immediate */
3114
                            rs2 = GET_FIELDs(insn, 20, 31);
3115
                            tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3116
                        } else { /* register */
3117
                            tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3118
                            tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3119
                        }
3120
                        gen_movl_TN_reg(rd, cpu_dst);
3121
                        break;
3122
                    case 0x26:  /* srl */
3123
                        if (IS_IMM) { /* immediate */
3124
                            rs2 = GET_FIELDs(insn, 20, 31);
3125
                            tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3126
                        } else { /* register */
3127
                            tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3128
                            tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3129
                        }
3130
                        gen_movl_TN_reg(rd, cpu_dst);
3131
                        break;
3132
                    case 0x27:  /* sra */
3133
                        if (IS_IMM) { /* immediate */
3134
                            rs2 = GET_FIELDs(insn, 20, 31);
3135
                            tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3136
                        } else { /* register */
3137
                            tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3138
                            tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3139
                        }
3140
                        gen_movl_TN_reg(rd, cpu_dst);
3141
                        break;
3142
#endif
3143
                    case 0x30:
3144
                        {
3145
                            switch(rd) {
3146
                            case 0: /* wry */
3147
                                tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3148
                                tcg_gen_st_tl(cpu_tmp0, cpu_env,
3149
                                              offsetof(CPUSPARCState, y));
3150
                                break;
3151
#ifndef TARGET_SPARC64
3152
                            case 0x01 ... 0x0f: /* undefined in the
3153
                                                   SPARCv8 manual, nop
3154
                                                   on the microSPARC
3155
                                                   II */
3156
                            case 0x10 ... 0x1f: /* implementation-dependent
3157
                                                   in the SPARCv8
3158
                                                   manual, nop on the
3159
                                                   microSPARC II */
3160
                                break;
3161
#else
3162
                            case 0x2: /* V9 wrccr */
3163
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3164
                                tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
3165
                                break;
3166
                            case 0x3: /* V9 wrasi */
3167
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3168
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3169
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3170
                                               offsetof(CPUSPARCState, asi));
3171
                                break;
3172
                            case 0x6: /* V9 wrfprs */
3173
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3174
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3175
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3176
                                               offsetof(CPUSPARCState, fprs));
3177
                                save_state(dc, cpu_cond);
3178
                                gen_op_next_insn();
3179
                                tcg_gen_exit_tb(0);
3180
                                dc->is_br = 1;
3181
                                break;
3182
                            case 0xf: /* V9 sir, nop if user */
3183
#if !defined(CONFIG_USER_ONLY)
3184
                                if (supervisor(dc))
3185
                                    ; // XXX
3186
#endif
3187
                                break;
3188
                            case 0x13: /* Graphics Status */
3189
                                if (gen_trap_ifnofpu(dc, cpu_cond))
3190
                                    goto jmp_insn;
3191
                                tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3192
                                tcg_gen_st_tl(cpu_tmp0, cpu_env,
3193
                                              offsetof(CPUSPARCState, gsr));
3194
                                break;
3195
                            case 0x17: /* Tick compare */
3196
#if !defined(CONFIG_USER_ONLY)
3197
                                if (!supervisor(dc))
3198
                                    goto illegal_insn;
3199
#endif
3200
                                {
3201
                                    TCGv r_tickptr;
3202

    
3203
                                    tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3204
                                                   cpu_src2);
3205
                                    tcg_gen_st_tl(cpu_tmp0, cpu_env,
3206
                                                  offsetof(CPUSPARCState,
3207
                                                           tick_cmpr));
3208
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3209
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3210
                                                   offsetof(CPUState, tick));
3211
                                    tcg_gen_helper_0_2(helper_tick_set_limit,
3212
                                                       r_tickptr, cpu_tmp0);
3213
                                    tcg_temp_free(r_tickptr);
3214
                                }
3215
                                break;
3216
                            case 0x18: /* System tick */
3217
#if !defined(CONFIG_USER_ONLY)
3218
                                if (!supervisor(dc))
3219
                                    goto illegal_insn;
3220
#endif
3221
                                {
3222
                                    TCGv r_tickptr;
3223

    
3224
                                    tcg_gen_xor_tl(cpu_dst, cpu_src1,
3225
                                                   cpu_src2);
3226
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3227
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3228
                                                   offsetof(CPUState, stick));
3229
                                    tcg_gen_helper_0_2(helper_tick_set_count,
3230
                                                       r_tickptr, cpu_dst);
3231
                                    tcg_temp_free(r_tickptr);
3232
                                }
3233
                                break;
3234
                            case 0x19: /* System tick compare */
3235
#if !defined(CONFIG_USER_ONLY)
3236
                                if (!supervisor(dc))
3237
                                    goto illegal_insn;
3238
#endif
3239
                                {
3240
                                    TCGv r_tickptr;
3241

    
3242
                                    tcg_gen_xor_tl(cpu_tmp0, cpu_src1,
3243
                                                   cpu_src2);
3244
                                    tcg_gen_st_tl(cpu_tmp0, cpu_env,
3245
                                                  offsetof(CPUSPARCState,
3246
                                                           stick_cmpr));
3247
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3248
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3249
                                                   offsetof(CPUState, stick));
3250
                                    tcg_gen_helper_0_2(helper_tick_set_limit,
3251
                                                       r_tickptr, cpu_tmp0);
3252
                                    tcg_temp_free(r_tickptr);
3253
                                }
3254
                                break;
3255

    
3256
                            case 0x10: /* Performance Control */
3257
                            case 0x11: /* Performance Instrumentation
3258
                                          Counter */
3259
                            case 0x12: /* Dispatch Control */
3260
                            case 0x14: /* Softint set */
3261
                            case 0x15: /* Softint clear */
3262
                            case 0x16: /* Softint write */
3263
#endif
3264
                            default:
3265
                                goto illegal_insn;
3266
                            }
3267
                        }
3268
                        break;
3269
#if !defined(CONFIG_USER_ONLY)
3270
                    case 0x31: /* wrpsr, V9 saved, restored */
3271
                        {
3272
                            if (!supervisor(dc))
3273
                                goto priv_insn;
3274
#ifdef TARGET_SPARC64
3275
                            switch (rd) {
3276
                            case 0:
3277
                                tcg_gen_helper_0_0(helper_saved);
3278
                                break;
3279
                            case 1:
3280
                                tcg_gen_helper_0_0(helper_restored);
3281
                                break;
3282
                            case 2: /* UA2005 allclean */
3283
                            case 3: /* UA2005 otherw */
3284
                            case 4: /* UA2005 normalw */
3285
                            case 5: /* UA2005 invalw */
3286
                                // XXX
3287
                            default:
3288
                                goto illegal_insn;
3289
                            }
3290
#else
3291
                            tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3292
                            tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3293
                            save_state(dc, cpu_cond);
3294
                            gen_op_next_insn();
3295
                            tcg_gen_exit_tb(0);
3296
                            dc->is_br = 1;
3297
#endif
3298
                        }
3299
                        break;
3300
                    case 0x32: /* wrwim, V9 wrpr */
3301
                        {
3302
                            if (!supervisor(dc))
3303
                                goto priv_insn;
3304
                            tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3305
#ifdef TARGET_SPARC64
3306
                            switch (rd) {
3307
                            case 0: // tpc
3308
                                {
3309
                                    TCGv r_tsptr;
3310

    
3311
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3312
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3313
                                                   offsetof(CPUState, tsptr));
3314
                                    tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3315
                                                  offsetof(trap_state, tpc));
3316
                                    tcg_temp_free(r_tsptr);
3317
                                }
3318
                                break;
3319
                            case 1: // tnpc
3320
                                {
3321
                                    TCGv r_tsptr;
3322

    
3323
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3324
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3325
                                                   offsetof(CPUState, tsptr));
3326
                                    tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3327
                                                  offsetof(trap_state, tnpc));
3328
                                    tcg_temp_free(r_tsptr);
3329
                                }
3330
                                break;
3331
                            case 2: // tstate
3332
                                {
3333
                                    TCGv r_tsptr;
3334

    
3335
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3336
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3337
                                                   offsetof(CPUState, tsptr));
3338
                                    tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3339
                                                  offsetof(trap_state,
3340
                                                           tstate));
3341
                                    tcg_temp_free(r_tsptr);
3342
                                }
3343
                                break;
3344
                            case 3: // tt
3345
                                {
3346
                                    TCGv r_tsptr;
3347

    
3348
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3349
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3350
                                                   offsetof(CPUState, tsptr));
3351
                                    tcg_gen_st_i32(cpu_tmp0, r_tsptr,
3352
                                                   offsetof(trap_state, tt));
3353
                                    tcg_temp_free(r_tsptr);
3354
                                }
3355
                                break;
3356
                            case 4: // tick
3357
                                {
3358
                                    TCGv r_tickptr;
3359

    
3360
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3361
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3362
                                                   offsetof(CPUState, tick));
3363
                                    tcg_gen_helper_0_2(helper_tick_set_count,
3364
                                                       r_tickptr, cpu_tmp0);
3365
                                    tcg_temp_free(r_tickptr);
3366
                                }
3367
                                break;
3368
                            case 5: // tba
3369
                                tcg_gen_st_tl(cpu_tmp0, cpu_env,
3370
                                              offsetof(CPUSPARCState, tbr));
3371
                                break;
3372
                            case 6: // pstate
3373
                                save_state(dc, cpu_cond);
3374
                                tcg_gen_helper_0_1(helper_wrpstate, cpu_tmp0);
3375
                                gen_op_next_insn();
3376
                                tcg_gen_exit_tb(0);
3377
                                dc->is_br = 1;
3378
                                break;
3379
                            case 7: // tl
3380
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3381
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3382
                                               offsetof(CPUSPARCState, tl));
3383
                                break;
3384
                            case 8: // pil
3385
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3386
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3387
                                               offsetof(CPUSPARCState,
3388
                                                        psrpil));
3389
                                break;
3390
                            case 9: // cwp
3391
                                tcg_gen_helper_0_1(helper_wrcwp, cpu_tmp0);
3392
                                break;
3393
                            case 10: // cansave
3394
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3395
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3396
                                               offsetof(CPUSPARCState,
3397
                                                        cansave));
3398
                                break;
3399
                            case 11: // canrestore
3400
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3401
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3402
                                               offsetof(CPUSPARCState,
3403
                                                        canrestore));
3404
                                break;
3405
                            case 12: // cleanwin
3406
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3407
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3408
                                               offsetof(CPUSPARCState,
3409
                                                        cleanwin));
3410
                                break;
3411
                            case 13: // otherwin
3412
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3413
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3414
                                               offsetof(CPUSPARCState,
3415
                                                        otherwin));
3416
                                break;
3417
                            case 14: // wstate
3418
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3419
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3420
                                               offsetof(CPUSPARCState,
3421
                                                        wstate));
3422
                                break;
3423
                            case 16: // UA2005 gl
3424
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3425
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3426
                                               offsetof(CPUSPARCState, gl));
3427
                                break;
3428
                            case 26: // UA2005 strand status
3429
                                if (!hypervisor(dc))
3430
                                    goto priv_insn;
3431
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3432
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3433
                                               offsetof(CPUSPARCState, ssr));
3434
                                break;
3435
                            default:
3436
                                goto illegal_insn;
3437
                            }
3438
#else
3439
                            tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3440
                            tcg_gen_st_i32(cpu_tmp32, cpu_env,
3441
                                           offsetof(CPUSPARCState, wim));
3442
#endif
3443
                        }
3444
                        break;
3445
                    case 0x33: /* wrtbr, UA2005 wrhpr */
3446
                        {
3447
#ifndef TARGET_SPARC64
3448
                            if (!supervisor(dc))
3449
                                goto priv_insn;
3450
                            tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3451
                            tcg_gen_st_tl(cpu_tmp0, cpu_env,
3452
                                          offsetof(CPUSPARCState, tbr));
3453
#else
3454
                            if (!hypervisor(dc))
3455
                                goto priv_insn;
3456
                            tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3457
                            switch (rd) {
3458
                            case 0: // hpstate
3459
                                // XXX gen_op_wrhpstate();
3460
                                save_state(dc, cpu_cond);
3461
                                gen_op_next_insn();
3462
                                tcg_gen_exit_tb(0);
3463
                                dc->is_br = 1;
3464
                                break;
3465
                            case 1: // htstate
3466
                                // XXX gen_op_wrhtstate();
3467
                                break;
3468
                            case 3: // hintp
3469
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3470
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3471
                                               offsetof(CPUSPARCState, hintp));
3472
                                break;
3473
                            case 5: // htba
3474
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3475
                                tcg_gen_st_i32(cpu_tmp32, cpu_env,
3476
                                               offsetof(CPUSPARCState, htba));
3477
                                break;
3478
                            case 31: // hstick_cmpr
3479
                                {
3480
                                    TCGv r_tickptr;
3481

    
3482
                                    tcg_gen_st_tl(cpu_tmp0, cpu_env,
3483
                                                  offsetof(CPUSPARCState,
3484
                                                           hstick_cmpr));
3485
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3486
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3487
                                                   offsetof(CPUState, hstick));
3488
                                    tcg_gen_helper_0_2(helper_tick_set_limit,
3489
                                                       r_tickptr, cpu_tmp0);
3490
                                    tcg_temp_free(r_tickptr);
3491
                                }
3492
                                break;
3493
                            case 6: // hver readonly
3494
                            default:
3495
                                goto illegal_insn;
3496
                            }
3497
#endif
3498
                        }
3499
                        break;
3500
#endif
3501
#ifdef TARGET_SPARC64
3502
                    case 0x2c: /* V9 movcc */
3503
                        {
3504
                            int cc = GET_FIELD_SP(insn, 11, 12);
3505
                            int cond = GET_FIELD_SP(insn, 14, 17);
3506
                            TCGv r_cond;
3507
                            int l1;
3508

    
3509
                            r_cond = tcg_temp_new(TCG_TYPE_TL);
3510
                            if (insn & (1 << 18)) {
3511
                                if (cc == 0)
3512
                                    gen_cond(r_cond, 0, cond);
3513
                                else if (cc == 2)
3514
                                    gen_cond(r_cond, 1, cond);
3515
                                else
3516
                                    goto illegal_insn;
3517
                            } else {
3518
                                gen_fcond(r_cond, cc, cond);
3519
                            }
3520

    
3521
                            l1 = gen_new_label();
3522

    
3523
                            tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
3524
                            if (IS_IMM) {       /* immediate */
3525
                                TCGv r_const;
3526

    
3527
                                rs2 = GET_FIELD_SPs(insn, 0, 10);
3528
                                r_const = tcg_const_tl((int)rs2);
3529
                                gen_movl_TN_reg(rd, r_const);
3530
                                tcg_temp_free(r_const);
3531
                            } else {
3532
                                rs2 = GET_FIELD_SP(insn, 0, 4);
3533
                                gen_movl_reg_TN(rs2, cpu_tmp0);
3534
                                gen_movl_TN_reg(rd, cpu_tmp0);
3535
                            }
3536
                            gen_set_label(l1);
3537
                            tcg_temp_free(r_cond);
3538
                            break;
3539
                        }
3540
                    case 0x2d: /* V9 sdivx */
3541
                        gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3542
                        gen_movl_TN_reg(rd, cpu_dst);
3543
                        break;
3544
                    case 0x2e: /* V9 popc */
3545
                        {
3546
                            cpu_src2 = get_src2(insn, cpu_src2);
3547
                            tcg_gen_helper_1_1(helper_popc, cpu_dst,
3548
                                               cpu_src2);
3549
                            gen_movl_TN_reg(rd, cpu_dst);
3550
                        }
3551
                    case 0x2f: /* V9 movr */
3552
                        {
3553
                            int cond = GET_FIELD_SP(insn, 10, 12);
3554
                            int l1;
3555

    
3556
                            cpu_src1 = get_src1(insn, cpu_src1);
3557

    
3558
                            l1 = gen_new_label();
3559

    
3560
                            tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
3561
                                              cpu_src1, 0, l1);
3562
                            if (IS_IMM) {       /* immediate */
3563
                                TCGv r_const;
3564

    
3565
                                rs2 = GET_FIELD_SPs(insn, 0, 9);
3566
                                r_const = tcg_const_tl((int)rs2);
3567
                                gen_movl_TN_reg(rd, r_const);
3568
                                tcg_temp_free(r_const);
3569
                            } else {
3570
                                rs2 = GET_FIELD_SP(insn, 0, 4);
3571
                                gen_movl_reg_TN(rs2, cpu_tmp0);
3572
                                gen_movl_TN_reg(rd, cpu_tmp0);
3573
                            }
3574
                            gen_set_label(l1);
3575
                            break;
3576
                        }
3577
#endif
3578
                    default:
3579
                        goto illegal_insn;
3580
                    }
3581
                }
3582
            } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3583
#ifdef TARGET_SPARC64
3584
                int opf = GET_FIELD_SP(insn, 5, 13);
3585
                rs1 = GET_FIELD(insn, 13, 17);
3586
                rs2 = GET_FIELD(insn, 27, 31);
3587
                if (gen_trap_ifnofpu(dc, cpu_cond))
3588
                    goto jmp_insn;
3589

    
3590
                switch (opf) {
3591
                case 0x000: /* VIS I edge8cc */
3592
                case 0x001: /* VIS II edge8n */
3593
                case 0x002: /* VIS I edge8lcc */
3594
                case 0x003: /* VIS II edge8ln */
3595
                case 0x004: /* VIS I edge16cc */
3596
                case 0x005: /* VIS II edge16n */
3597
                case 0x006: /* VIS I edge16lcc */
3598
                case 0x007: /* VIS II edge16ln */
3599
                case 0x008: /* VIS I edge32cc */
3600
                case 0x009: /* VIS II edge32n */
3601
                case 0x00a: /* VIS I edge32lcc */
3602
                case 0x00b: /* VIS II edge32ln */
3603
                    // XXX
3604
                    goto illegal_insn;
3605
                case 0x010: /* VIS I array8 */
3606
                    CHECK_FPU_FEATURE(dc, VIS1);
3607
                    cpu_src1 = get_src1(insn, cpu_src1);
3608
                    gen_movl_reg_TN(rs2, cpu_src2);
3609
                    tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3610
                                       cpu_src2);
3611
                    gen_movl_TN_reg(rd, cpu_dst);
3612
                    break;
3613
                case 0x012: /* VIS I array16 */
3614
                    CHECK_FPU_FEATURE(dc, VIS1);
3615
                    cpu_src1 = get_src1(insn, cpu_src1);
3616
                    gen_movl_reg_TN(rs2, cpu_src2);
3617
                    tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3618
                                       cpu_src2);
3619
                    tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3620
                    gen_movl_TN_reg(rd, cpu_dst);
3621
                    break;
3622
                case 0x014: /* VIS I array32 */
3623
                    CHECK_FPU_FEATURE(dc, VIS1);
3624
                    cpu_src1 = get_src1(insn, cpu_src1);
3625
                    gen_movl_reg_TN(rs2, cpu_src2);
3626
                    tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3627
                                       cpu_src2);
3628
                    tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3629
                    gen_movl_TN_reg(rd, cpu_dst);
3630
                    break;
3631
                case 0x018: /* VIS I alignaddr */
3632
                    CHECK_FPU_FEATURE(dc, VIS1);
3633
                    cpu_src1 = get_src1(insn, cpu_src1);
3634
                    gen_movl_reg_TN(rs2, cpu_src2);
3635
                    tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3636
                                       cpu_src2);
3637
                    gen_movl_TN_reg(rd, cpu_dst);
3638
                    break;
3639
                case 0x019: /* VIS II bmask */
3640
                case 0x01a: /* VIS I alignaddrl */
3641
                    // XXX
3642
                    goto illegal_insn;
3643
                case 0x020: /* VIS I fcmple16 */
3644
                    CHECK_FPU_FEATURE(dc, VIS1);
3645
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3646
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3647
                    tcg_gen_helper_0_0(helper_fcmple16);
3648
                    gen_op_store_DT0_fpr(DFPREG(rd));
3649
                    break;
3650
                case 0x022: /* VIS I fcmpne16 */
3651
                    CHECK_FPU_FEATURE(dc, VIS1);
3652
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3653
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3654
                    tcg_gen_helper_0_0(helper_fcmpne16);
3655
                    gen_op_store_DT0_fpr(DFPREG(rd));
3656
                    break;
3657
                case 0x024: /* VIS I fcmple32 */
3658
                    CHECK_FPU_FEATURE(dc, VIS1);
3659
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3660
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3661
                    tcg_gen_helper_0_0(helper_fcmple32);
3662
                    gen_op_store_DT0_fpr(DFPREG(rd));
3663
                    break;
3664
                case 0x026: /* VIS I fcmpne32 */
3665
                    CHECK_FPU_FEATURE(dc, VIS1);
3666
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3667
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3668
                    tcg_gen_helper_0_0(helper_fcmpne32);
3669
                    gen_op_store_DT0_fpr(DFPREG(rd));
3670
                    break;
3671
                case 0x028: /* VIS I fcmpgt16 */
3672
                    CHECK_FPU_FEATURE(dc, VIS1);
3673
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3674
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3675
                    tcg_gen_helper_0_0(helper_fcmpgt16);
3676
                    gen_op_store_DT0_fpr(DFPREG(rd));
3677
                    break;
3678
                case 0x02a: /* VIS I fcmpeq16 */
3679
                    CHECK_FPU_FEATURE(dc, VIS1);
3680
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3681
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3682
                    tcg_gen_helper_0_0(helper_fcmpeq16);
3683
                    gen_op_store_DT0_fpr(DFPREG(rd));
3684
                    break;
3685
                case 0x02c: /* VIS I fcmpgt32 */
3686
                    CHECK_FPU_FEATURE(dc, VIS1);
3687
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3688
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3689
                    tcg_gen_helper_0_0(helper_fcmpgt32);
3690
                    gen_op_store_DT0_fpr(DFPREG(rd));
3691
                    break;
3692
                case 0x02e: /* VIS I fcmpeq32 */
3693
                    CHECK_FPU_FEATURE(dc, VIS1);
3694
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3695
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3696
                    tcg_gen_helper_0_0(helper_fcmpeq32);
3697
                    gen_op_store_DT0_fpr(DFPREG(rd));
3698
                    break;
3699
                case 0x031: /* VIS I fmul8x16 */
3700
                    CHECK_FPU_FEATURE(dc, VIS1);
3701
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3702
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3703
                    tcg_gen_helper_0_0(helper_fmul8x16);
3704
                    gen_op_store_DT0_fpr(DFPREG(rd));
3705
                    break;
3706
                case 0x033: /* VIS I fmul8x16au */
3707
                    CHECK_FPU_FEATURE(dc, VIS1);
3708
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3709
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3710
                    tcg_gen_helper_0_0(helper_fmul8x16au);
3711
                    gen_op_store_DT0_fpr(DFPREG(rd));
3712
                    break;
3713
                case 0x035: /* VIS I fmul8x16al */
3714
                    CHECK_FPU_FEATURE(dc, VIS1);
3715
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3716
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3717
                    tcg_gen_helper_0_0(helper_fmul8x16al);
3718
                    gen_op_store_DT0_fpr(DFPREG(rd));
3719
                    break;
3720
                case 0x036: /* VIS I fmul8sux16 */
3721
                    CHECK_FPU_FEATURE(dc, VIS1);
3722
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3723
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3724
                    tcg_gen_helper_0_0(helper_fmul8sux16);
3725
                    gen_op_store_DT0_fpr(DFPREG(rd));
3726
                    break;
3727
                case 0x037: /* VIS I fmul8ulx16 */
3728
                    CHECK_FPU_FEATURE(dc, VIS1);
3729
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3730
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3731
                    tcg_gen_helper_0_0(helper_fmul8ulx16);
3732
                    gen_op_store_DT0_fpr(DFPREG(rd));
3733
                    break;
3734
                case 0x038: /* VIS I fmuld8sux16 */
3735
                    CHECK_FPU_FEATURE(dc, VIS1);
3736
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3737
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3738
                    tcg_gen_helper_0_0(helper_fmuld8sux16);
3739
                    gen_op_store_DT0_fpr(DFPREG(rd));
3740
                    break;
3741
                case 0x039: /* VIS I fmuld8ulx16 */
3742
                    CHECK_FPU_FEATURE(dc, VIS1);
3743
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3744
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3745
                    tcg_gen_helper_0_0(helper_fmuld8ulx16);
3746
                    gen_op_store_DT0_fpr(DFPREG(rd));
3747
                    break;
3748
                case 0x03a: /* VIS I fpack32 */
3749
                case 0x03b: /* VIS I fpack16 */
3750
                case 0x03d: /* VIS I fpackfix */
3751
                case 0x03e: /* VIS I pdist */
3752
                    // XXX
3753
                    goto illegal_insn;
3754
                case 0x048: /* VIS I faligndata */
3755
                    CHECK_FPU_FEATURE(dc, VIS1);
3756
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3757
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3758
                    tcg_gen_helper_0_0(helper_faligndata);
3759
                    gen_op_store_DT0_fpr(DFPREG(rd));
3760
                    break;
3761
                case 0x04b: /* VIS I fpmerge */
3762
                    CHECK_FPU_FEATURE(dc, VIS1);
3763
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3764
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3765
                    tcg_gen_helper_0_0(helper_fpmerge);
3766
                    gen_op_store_DT0_fpr(DFPREG(rd));
3767
                    break;
3768
                case 0x04c: /* VIS II bshuffle */
3769
                    // XXX
3770
                    goto illegal_insn;
3771
                case 0x04d: /* VIS I fexpand */
3772
                    CHECK_FPU_FEATURE(dc, VIS1);
3773
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3774
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3775
                    tcg_gen_helper_0_0(helper_fexpand);
3776
                    gen_op_store_DT0_fpr(DFPREG(rd));
3777
                    break;
3778
                case 0x050: /* VIS I fpadd16 */
3779
                    CHECK_FPU_FEATURE(dc, VIS1);
3780
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3781
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3782
                    tcg_gen_helper_0_0(helper_fpadd16);
3783
                    gen_op_store_DT0_fpr(DFPREG(rd));
3784
                    break;
3785
                case 0x051: /* VIS I fpadd16s */
3786
                    CHECK_FPU_FEATURE(dc, VIS1);
3787
                    gen_op_load_fpr_FT0(rs1);
3788
                    gen_op_load_fpr_FT1(rs2);
3789
                    tcg_gen_helper_0_0(helper_fpadd16s);
3790
                    gen_op_store_FT0_fpr(rd);
3791
                    break;
3792
                case 0x052: /* VIS I fpadd32 */
3793
                    CHECK_FPU_FEATURE(dc, VIS1);
3794
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3795
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3796
                    tcg_gen_helper_0_0(helper_fpadd32);
3797
                    gen_op_store_DT0_fpr(DFPREG(rd));
3798
                    break;
3799
                case 0x053: /* VIS I fpadd32s */
3800
                    CHECK_FPU_FEATURE(dc, VIS1);
3801
                    gen_op_load_fpr_FT0(rs1);
3802
                    gen_op_load_fpr_FT1(rs2);
3803
                    tcg_gen_helper_0_0(helper_fpadd32s);
3804
                    gen_op_store_FT0_fpr(rd);
3805
                    break;
3806
                case 0x054: /* VIS I fpsub16 */
3807
                    CHECK_FPU_FEATURE(dc, VIS1);
3808
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3809
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3810
                    tcg_gen_helper_0_0(helper_fpsub16);
3811
                    gen_op_store_DT0_fpr(DFPREG(rd));
3812
                    break;
3813
                case 0x055: /* VIS I fpsub16s */
3814
                    CHECK_FPU_FEATURE(dc, VIS1);
3815
                    gen_op_load_fpr_FT0(rs1);
3816
                    gen_op_load_fpr_FT1(rs2);
3817
                    tcg_gen_helper_0_0(helper_fpsub16s);
3818
                    gen_op_store_FT0_fpr(rd);
3819
                    break;
3820
                case 0x056: /* VIS I fpsub32 */
3821
                    CHECK_FPU_FEATURE(dc, VIS1);
3822
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3823
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3824
                    tcg_gen_helper_0_0(helper_fpadd32);
3825
                    gen_op_store_DT0_fpr(DFPREG(rd));
3826
                    break;
3827
                case 0x057: /* VIS I fpsub32s */
3828
                    CHECK_FPU_FEATURE(dc, VIS1);
3829
                    gen_op_load_fpr_FT0(rs1);
3830
                    gen_op_load_fpr_FT1(rs2);
3831
                    tcg_gen_helper_0_0(helper_fpsub32s);
3832
                    gen_op_store_FT0_fpr(rd);
3833
                    break;
3834
                case 0x060: /* VIS I fzero */
3835
                    CHECK_FPU_FEATURE(dc, VIS1);
3836
                    tcg_gen_helper_0_0(helper_movl_DT0_0);
3837
                    gen_op_store_DT0_fpr(DFPREG(rd));
3838
                    break;
3839
                case 0x061: /* VIS I fzeros */
3840
                    CHECK_FPU_FEATURE(dc, VIS1);
3841
                    tcg_gen_helper_0_0(helper_movl_FT0_0);
3842
                    gen_op_store_FT0_fpr(rd);
3843
                    break;
3844
                case 0x062: /* VIS I fnor */
3845
                    CHECK_FPU_FEATURE(dc, VIS1);
3846
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3847
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3848
                    tcg_gen_helper_0_0(helper_fnor);
3849
                    gen_op_store_DT0_fpr(DFPREG(rd));
3850
                    break;
3851
                case 0x063: /* VIS I fnors */
3852
                    CHECK_FPU_FEATURE(dc, VIS1);
3853
                    gen_op_load_fpr_FT0(rs1);
3854
                    gen_op_load_fpr_FT1(rs2);
3855
                    tcg_gen_helper_0_0(helper_fnors);
3856
                    gen_op_store_FT0_fpr(rd);
3857
                    break;
3858
                case 0x064: /* VIS I fandnot2 */
3859
                    CHECK_FPU_FEATURE(dc, VIS1);
3860
                    gen_op_load_fpr_DT1(DFPREG(rs1));
3861
                    gen_op_load_fpr_DT0(DFPREG(rs2));
3862
                    tcg_gen_helper_0_0(helper_fandnot);
3863
                    gen_op_store_DT0_fpr(DFPREG(rd));
3864
                    break;
3865
                case 0x065: /* VIS I fandnot2s */
3866
                    CHECK_FPU_FEATURE(dc, VIS1);
3867
                    gen_op_load_fpr_FT1(rs1);
3868
                    gen_op_load_fpr_FT0(rs2);
3869
                    tcg_gen_helper_0_0(helper_fandnots);
3870
                    gen_op_store_FT0_fpr(rd);
3871
                    break;
3872
                case 0x066: /* VIS I fnot2 */
3873
                    CHECK_FPU_FEATURE(dc, VIS1);
3874
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3875
                    tcg_gen_helper_0_0(helper_fnot);
3876
                    gen_op_store_DT0_fpr(DFPREG(rd));
3877
                    break;
3878
                case 0x067: /* VIS I fnot2s */
3879
                    CHECK_FPU_FEATURE(dc, VIS1);
3880
                    gen_op_load_fpr_FT1(rs2);
3881
                    tcg_gen_helper_0_0(helper_fnot);
3882
                    gen_op_store_FT0_fpr(rd);
3883
                    break;
3884
                case 0x068: /* VIS I fandnot1 */
3885
                    CHECK_FPU_FEATURE(dc, VIS1);
3886
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3887
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3888
                    tcg_gen_helper_0_0(helper_fandnot);
3889
                    gen_op_store_DT0_fpr(DFPREG(rd));
3890
                    break;
3891
                case 0x069: /* VIS I fandnot1s */
3892
                    CHECK_FPU_FEATURE(dc, VIS1);
3893
                    gen_op_load_fpr_FT0(rs1);
3894
                    gen_op_load_fpr_FT1(rs2);
3895
                    tcg_gen_helper_0_0(helper_fandnots);
3896
                    gen_op_store_FT0_fpr(rd);
3897
                    break;
3898
                case 0x06a: /* VIS I fnot1 */
3899
                    CHECK_FPU_FEATURE(dc, VIS1);
3900
                    gen_op_load_fpr_DT1(DFPREG(rs1));
3901
                    tcg_gen_helper_0_0(helper_fnot);
3902
                    gen_op_store_DT0_fpr(DFPREG(rd));
3903
                    break;
3904
                case 0x06b: /* VIS I fnot1s */
3905
                    CHECK_FPU_FEATURE(dc, VIS1);
3906
                    gen_op_load_fpr_FT1(rs1);
3907
                    tcg_gen_helper_0_0(helper_fnot);
3908
                    gen_op_store_FT0_fpr(rd);
3909
                    break;
3910
                case 0x06c: /* VIS I fxor */
3911
                    CHECK_FPU_FEATURE(dc, VIS1);
3912
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3913
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3914
                    tcg_gen_helper_0_0(helper_fxor);
3915
                    gen_op_store_DT0_fpr(DFPREG(rd));
3916
                    break;
3917
                case 0x06d: /* VIS I fxors */
3918
                    CHECK_FPU_FEATURE(dc, VIS1);
3919
                    gen_op_load_fpr_FT0(rs1);
3920
                    gen_op_load_fpr_FT1(rs2);
3921
                    tcg_gen_helper_0_0(helper_fxors);
3922
                    gen_op_store_FT0_fpr(rd);
3923
                    break;
3924
                case 0x06e: /* VIS I fnand */
3925
                    CHECK_FPU_FEATURE(dc, VIS1);
3926
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3927
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3928
                    tcg_gen_helper_0_0(helper_fnand);
3929
                    gen_op_store_DT0_fpr(DFPREG(rd));
3930
                    break;
3931
                case 0x06f: /* VIS I fnands */
3932
                    CHECK_FPU_FEATURE(dc, VIS1);
3933
                    gen_op_load_fpr_FT0(rs1);
3934
                    gen_op_load_fpr_FT1(rs2);
3935
                    tcg_gen_helper_0_0(helper_fnands);
3936
                    gen_op_store_FT0_fpr(rd);
3937
                    break;
3938
                case 0x070: /* VIS I fand */
3939
                    CHECK_FPU_FEATURE(dc, VIS1);
3940
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3941
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3942
                    tcg_gen_helper_0_0(helper_fand);
3943
                    gen_op_store_DT0_fpr(DFPREG(rd));
3944
                    break;
3945
                case 0x071: /* VIS I fands */
3946
                    CHECK_FPU_FEATURE(dc, VIS1);
3947
                    gen_op_load_fpr_FT0(rs1);
3948
                    gen_op_load_fpr_FT1(rs2);
3949
                    tcg_gen_helper_0_0(helper_fands);
3950
                    gen_op_store_FT0_fpr(rd);
3951
                    break;
3952
                case 0x072: /* VIS I fxnor */
3953
                    CHECK_FPU_FEATURE(dc, VIS1);
3954
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3955
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3956
                    tcg_gen_helper_0_0(helper_fxnor);
3957
                    gen_op_store_DT0_fpr(DFPREG(rd));
3958
                    break;
3959
                case 0x073: /* VIS I fxnors */
3960
                    CHECK_FPU_FEATURE(dc, VIS1);
3961
                    gen_op_load_fpr_FT0(rs1);
3962
                    gen_op_load_fpr_FT1(rs2);
3963
                    tcg_gen_helper_0_0(helper_fxnors);
3964
                    gen_op_store_FT0_fpr(rd);
3965
                    break;
3966
                case 0x074: /* VIS I fsrc1 */
3967
                    CHECK_FPU_FEATURE(dc, VIS1);
3968
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3969
                    gen_op_store_DT0_fpr(DFPREG(rd));
3970
                    break;
3971
                case 0x075: /* VIS I fsrc1s */
3972
                    CHECK_FPU_FEATURE(dc, VIS1);
3973
                    gen_op_load_fpr_FT0(rs1);
3974
                    gen_op_store_FT0_fpr(rd);
3975
                    break;
3976
                case 0x076: /* VIS I fornot2 */
3977
                    CHECK_FPU_FEATURE(dc, VIS1);
3978
                    gen_op_load_fpr_DT1(DFPREG(rs1));
3979
                    gen_op_load_fpr_DT0(DFPREG(rs2));
3980
                    tcg_gen_helper_0_0(helper_fornot);
3981
                    gen_op_store_DT0_fpr(DFPREG(rd));
3982
                    break;
3983
                case 0x077: /* VIS I fornot2s */
3984
                    CHECK_FPU_FEATURE(dc, VIS1);
3985
                    gen_op_load_fpr_FT1(rs1);
3986
                    gen_op_load_fpr_FT0(rs2);
3987
                    tcg_gen_helper_0_0(helper_fornots);
3988
                    gen_op_store_FT0_fpr(rd);
3989
                    break;
3990
                case 0x078: /* VIS I fsrc2 */
3991
                    CHECK_FPU_FEATURE(dc, VIS1);
3992
                    gen_op_load_fpr_DT0(DFPREG(rs2));
3993
                    gen_op_store_DT0_fpr(DFPREG(rd));
3994
                    break;
3995
                case 0x079: /* VIS I fsrc2s */
3996
                    CHECK_FPU_FEATURE(dc, VIS1);
3997
                    gen_op_load_fpr_FT0(rs2);
3998
                    gen_op_store_FT0_fpr(rd);
3999
                    break;
4000
                case 0x07a: /* VIS I fornot1 */
4001
                    CHECK_FPU_FEATURE(dc, VIS1);
4002
                    gen_op_load_fpr_DT0(DFPREG(rs1));
4003
                    gen_op_load_fpr_DT1(DFPREG(rs2));
4004
                    tcg_gen_helper_0_0(helper_fornot);
4005
                    gen_op_store_DT0_fpr(DFPREG(rd));
4006
                    break;
4007
                case 0x07b: /* VIS I fornot1s */
4008
                    CHECK_FPU_FEATURE(dc, VIS1);
4009
                    gen_op_load_fpr_FT0(rs1);
4010
                    gen_op_load_fpr_FT1(rs2);
4011
                    tcg_gen_helper_0_0(helper_fornots);
4012
                    gen_op_store_FT0_fpr(rd);
4013
                    break;
4014
                case 0x07c: /* VIS I for */
4015
                    CHECK_FPU_FEATURE(dc, VIS1);
4016
                    gen_op_load_fpr_DT0(DFPREG(rs1));
4017
                    gen_op_load_fpr_DT1(DFPREG(rs2));
4018
                    tcg_gen_helper_0_0(helper_for);
4019
                    gen_op_store_DT0_fpr(DFPREG(rd));
4020
                    break;
4021
                case 0x07d: /* VIS I fors */
4022
                    CHECK_FPU_FEATURE(dc, VIS1);
4023
                    gen_op_load_fpr_FT0(rs1);
4024
                    gen_op_load_fpr_FT1(rs2);
4025
                    tcg_gen_helper_0_0(helper_fors);
4026
                    gen_op_store_FT0_fpr(rd);
4027
                    break;
4028
                case 0x07e: /* VIS I fone */
4029
                    CHECK_FPU_FEATURE(dc, VIS1);
4030
                    tcg_gen_helper_0_0(helper_movl_DT0_1);
4031
                    gen_op_store_DT0_fpr(DFPREG(rd));
4032
                    break;
4033
                case 0x07f: /* VIS I fones */
4034
                    CHECK_FPU_FEATURE(dc, VIS1);
4035
                    tcg_gen_helper_0_0(helper_movl_FT0_1);
4036
                    gen_op_store_FT0_fpr(rd);
4037
                    break;
4038
                case 0x080: /* VIS I shutdown */
4039
                case 0x081: /* VIS II siam */
4040
                    // XXX
4041
                    goto illegal_insn;
4042
                default:
4043
                    goto illegal_insn;
4044
                }
4045
#else
4046
                goto ncp_insn;
4047
#endif
4048
            } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
4049
#ifdef TARGET_SPARC64
4050
                goto illegal_insn;
4051
#else
4052
                goto ncp_insn;
4053
#endif
4054
#ifdef TARGET_SPARC64
4055
            } else if (xop == 0x39) { /* V9 return */
4056
                TCGv r_const;
4057

    
4058
                save_state(dc, cpu_cond);
4059
                cpu_src1 = get_src1(insn, cpu_src1);
4060
                if (IS_IMM) {   /* immediate */
4061
                    rs2 = GET_FIELDs(insn, 19, 31);
4062
                    tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4063
                } else {                /* register */
4064
                    rs2 = GET_FIELD(insn, 27, 31);
4065
                    if (rs2) {
4066
                        gen_movl_reg_TN(rs2, cpu_src2);
4067
                        tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4068
                    } else
4069
                        tcg_gen_mov_tl(cpu_dst, cpu_src1);
4070
                }
4071
                tcg_gen_helper_0_0(helper_restore);
4072
                gen_mov_pc_npc(dc, cpu_cond);
4073
                r_const = tcg_const_i32(3);
4074
                tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const);
4075
                tcg_temp_free(r_const);
4076
                tcg_gen_mov_tl(cpu_npc, cpu_dst);
4077
                dc->npc = DYNAMIC_PC;
4078
                goto jmp_insn;
4079
#endif
4080
            } else {
4081
                cpu_src1 = get_src1(insn, cpu_src1);
4082
                if (IS_IMM) {   /* immediate */
4083
                    rs2 = GET_FIELDs(insn, 19, 31);
4084
                    tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
4085
                } else {                /* register */
4086
                    rs2 = GET_FIELD(insn, 27, 31);
4087
                    if (rs2) {
4088
                        gen_movl_reg_TN(rs2, cpu_src2);
4089
                        tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4090
                    } else
4091
                        tcg_gen_mov_tl(cpu_dst, cpu_src1);
4092
                }
4093
                switch (xop) {
4094
                case 0x38:      /* jmpl */
4095
                    {
4096
                        TCGv r_const;
4097

    
4098
                        r_const = tcg_const_tl(dc->pc);
4099
                        gen_movl_TN_reg(rd, r_const);
4100
                        tcg_temp_free(r_const);
4101
                        gen_mov_pc_npc(dc, cpu_cond);
4102
                        r_const = tcg_const_i32(3);
4103
                        tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4104
                                           r_const);
4105
                        tcg_temp_free(r_const);
4106
                        tcg_gen_mov_tl(cpu_npc, cpu_dst);
4107
                        dc->npc = DYNAMIC_PC;
4108
                    }
4109
                    goto jmp_insn;
4110
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4111
                case 0x39:      /* rett, V9 return */
4112
                    {
4113
                        TCGv r_const;
4114

    
4115
                        if (!supervisor(dc))
4116
                            goto priv_insn;
4117
                        gen_mov_pc_npc(dc, cpu_cond);
4118
                        r_const = tcg_const_i32(3);
4119
                        tcg_gen_helper_0_2(helper_check_align, cpu_dst,
4120
                                           r_const);
4121
                        tcg_temp_free(r_const);
4122
                        tcg_gen_mov_tl(cpu_npc, cpu_dst);
4123
                        dc->npc = DYNAMIC_PC;
4124
                        tcg_gen_helper_0_0(helper_rett);
4125
                    }
4126
                    goto jmp_insn;
4127
#endif
4128
                case 0x3b: /* flush */
4129
                    if (!((dc)->features & CPU_FEATURE_FLUSH))
4130
                        goto unimp_flush;
4131
                    tcg_gen_helper_0_1(helper_flush, cpu_dst);
4132
                    break;
4133
                case 0x3c:      /* save */
4134
                    save_state(dc, cpu_cond);
4135
                    tcg_gen_helper_0_0(helper_save);
4136
                    gen_movl_TN_reg(rd, cpu_dst);
4137
                    break;
4138
                case 0x3d:      /* restore */
4139
                    save_state(dc, cpu_cond);
4140
                    tcg_gen_helper_0_0(helper_restore);
4141
                    gen_movl_TN_reg(rd, cpu_dst);
4142
                    break;
4143
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4144
                case 0x3e:      /* V9 done/retry */
4145
                    {
4146
                        switch (rd) {
4147
                        case 0:
4148
                            if (!supervisor(dc))
4149
                                goto priv_insn;
4150
                            dc->npc = DYNAMIC_PC;
4151
                            dc->pc = DYNAMIC_PC;
4152
                            tcg_gen_helper_0_0(helper_done);
4153
                            goto jmp_insn;
4154
                        case 1:
4155
                            if (!supervisor(dc))
4156
                                goto priv_insn;
4157
                            dc->npc = DYNAMIC_PC;
4158
                            dc->pc = DYNAMIC_PC;
4159
                            tcg_gen_helper_0_0(helper_retry);
4160
                            goto jmp_insn;
4161
                        default:
4162
                            goto illegal_insn;
4163
                        }
4164
                    }
4165
                    break;
4166
#endif
4167
                default:
4168
                    goto illegal_insn;
4169
                }
4170
            }
4171
            break;
4172
        }
4173
        break;
4174
    case 3:                     /* load/store instructions */
4175
        {
4176
            unsigned int xop = GET_FIELD(insn, 7, 12);
4177

    
4178
            cpu_src1 = get_src1(insn, cpu_src1);
4179
            if (xop == 0x3c || xop == 0x3e)
4180
            {
4181
                rs2 = GET_FIELD(insn, 27, 31);
4182
                gen_movl_reg_TN(rs2, cpu_src2);
4183
            }
4184
            else if (IS_IMM) {       /* immediate */
4185
                rs2 = GET_FIELDs(insn, 19, 31);
4186
                tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
4187
            } else {            /* register */
4188
                rs2 = GET_FIELD(insn, 27, 31);
4189
                if (rs2 != 0) {
4190
                    gen_movl_reg_TN(rs2, cpu_src2);
4191
                    tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4192
                } else
4193
                    tcg_gen_mov_tl(cpu_addr, cpu_src1);
4194
            }
4195
            if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4196
                (xop > 0x17 && xop <= 0x1d ) ||
4197
                (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4198
                switch (xop) {
4199
                case 0x0:       /* load unsigned word */
4200
                    ABI32_MASK(cpu_addr);
4201
                    tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4202
                    break;
4203
                case 0x1:       /* load unsigned byte */
4204
                    ABI32_MASK(cpu_addr);
4205
                    tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4206
                    break;
4207
                case 0x2:       /* load unsigned halfword */
4208
                    ABI32_MASK(cpu_addr);
4209
                    tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4210
                    break;
4211
                case 0x3:       /* load double word */
4212
                    if (rd & 1)
4213
                        goto illegal_insn;
4214
                    else {
4215
                        TCGv r_const;
4216

    
4217
                        save_state(dc, cpu_cond);
4218
                        r_const = tcg_const_i32(7);
4219
                        tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4220
                                           r_const); // XXX remove
4221
                        tcg_temp_free(r_const);
4222
                        ABI32_MASK(cpu_addr);
4223
                        tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4224
                        tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4225
                        tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4226
                        gen_movl_TN_reg(rd + 1, cpu_tmp0);
4227
                        tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4228
                        tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4229
                        tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4230
                    }
4231
                    break;
4232
                case 0x9:       /* load signed byte */
4233
                    ABI32_MASK(cpu_addr);
4234
                    tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4235
                    break;
4236
                case 0xa:       /* load signed halfword */
4237
                    ABI32_MASK(cpu_addr);
4238
                    tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4239
                    break;
4240
                case 0xd:       /* ldstub -- XXX: should be atomically */
4241
                    {
4242
                        TCGv r_const;
4243

    
4244
                        ABI32_MASK(cpu_addr);
4245
                        tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4246
                        r_const = tcg_const_tl(0xff);
4247
                        tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4248
                        tcg_temp_free(r_const);
4249
                    }
4250
                    break;
4251
                case 0x0f:      /* swap register with memory. Also
4252
                                   atomically */
4253
                    CHECK_IU_FEATURE(dc, SWAP);
4254
                    gen_movl_reg_TN(rd, cpu_val);
4255
                    ABI32_MASK(cpu_addr);
4256
                    tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4257
                    tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4258
                    tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
4259
                    break;
4260
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4261
                case 0x10:      /* load word alternate */
4262
#ifndef TARGET_SPARC64
4263
                    if (IS_IMM)
4264
                        goto illegal_insn;
4265
                    if (!supervisor(dc))
4266
                        goto priv_insn;
4267
#endif
4268
                    save_state(dc, cpu_cond);
4269
                    gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4270
                    break;
4271
                case 0x11:      /* load unsigned byte alternate */
4272
#ifndef TARGET_SPARC64
4273
                    if (IS_IMM)
4274
                        goto illegal_insn;
4275
                    if (!supervisor(dc))
4276
                        goto priv_insn;
4277
#endif
4278
                    save_state(dc, cpu_cond);
4279
                    gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4280
                    break;
4281
                case 0x12:      /* load unsigned halfword alternate */
4282
#ifndef TARGET_SPARC64
4283
                    if (IS_IMM)
4284
                        goto illegal_insn;
4285
                    if (!supervisor(dc))
4286
                        goto priv_insn;
4287
#endif
4288
                    save_state(dc, cpu_cond);
4289
                    gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4290
                    break;
4291
                case 0x13:      /* load double word alternate */
4292
#ifndef TARGET_SPARC64
4293
                    if (IS_IMM)
4294
                        goto illegal_insn;
4295
                    if (!supervisor(dc))
4296
                        goto priv_insn;
4297
#endif
4298
                    if (rd & 1)
4299
                        goto illegal_insn;
4300
                    save_state(dc, cpu_cond);
4301
                    gen_ldda_asi(cpu_tmp0, cpu_val, cpu_addr, insn);
4302
                    gen_movl_TN_reg(rd + 1, cpu_tmp0);
4303
                    break;
4304
                case 0x19:      /* load signed byte alternate */
4305
#ifndef TARGET_SPARC64
4306
                    if (IS_IMM)
4307
                        goto illegal_insn;
4308
                    if (!supervisor(dc))
4309
                        goto priv_insn;
4310
#endif
4311
                    save_state(dc, cpu_cond);
4312
                    gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4313
                    break;
4314
                case 0x1a:      /* load signed halfword alternate */
4315
#ifndef TARGET_SPARC64
4316
                    if (IS_IMM)
4317
                        goto illegal_insn;
4318
                    if (!supervisor(dc))
4319
                        goto priv_insn;
4320
#endif
4321
                    save_state(dc, cpu_cond);
4322
                    gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4323
                    break;
4324
                case 0x1d:      /* ldstuba -- XXX: should be atomically */
4325
#ifndef TARGET_SPARC64
4326
                    if (IS_IMM)
4327
                        goto illegal_insn;
4328
                    if (!supervisor(dc))
4329
                        goto priv_insn;
4330
#endif
4331
                    save_state(dc, cpu_cond);
4332
                    gen_ldstub_asi(cpu_val, cpu_addr, insn);
4333
                    break;
4334
                case 0x1f:      /* swap reg with alt. memory. Also
4335
                                   atomically */
4336
                    CHECK_IU_FEATURE(dc, SWAP);
4337
#ifndef TARGET_SPARC64
4338
                    if (IS_IMM)
4339
                        goto illegal_insn;
4340
                    if (!supervisor(dc))
4341
                        goto priv_insn;
4342
#endif
4343
                    save_state(dc, cpu_cond);
4344
                    gen_movl_reg_TN(rd, cpu_val);
4345
                    gen_swap_asi(cpu_val, cpu_addr, insn);
4346
                    break;
4347

    
4348
#ifndef TARGET_SPARC64
4349
                case 0x30: /* ldc */
4350
                case 0x31: /* ldcsr */
4351
                case 0x33: /* lddc */
4352
                    goto ncp_insn;
4353
#endif
4354
#endif
4355
#ifdef TARGET_SPARC64
4356
                case 0x08: /* V9 ldsw */
4357
                    ABI32_MASK(cpu_addr);
4358
                    tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4359
                    break;
4360
                case 0x0b: /* V9 ldx */
4361
                    ABI32_MASK(cpu_addr);
4362
                    tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4363
                    break;
4364
                case 0x18: /* V9 ldswa */
4365
                    save_state(dc, cpu_cond);
4366
                    gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4367
                    break;
4368
                case 0x1b: /* V9 ldxa */
4369
                    save_state(dc, cpu_cond);
4370
                    gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4371
                    break;
4372
                case 0x2d: /* V9 prefetch, no effect */
4373
                    goto skip_move;
4374
                case 0x30: /* V9 ldfa */
4375
                    save_state(dc, cpu_cond);
4376
                    gen_ldf_asi(cpu_addr, insn, 4, rd);
4377
                    goto skip_move;
4378
                case 0x33: /* V9 lddfa */
4379
                    save_state(dc, cpu_cond);
4380
                    gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4381
                    goto skip_move;
4382
                case 0x3d: /* V9 prefetcha, no effect */
4383
                    goto skip_move;
4384
                case 0x32: /* V9 ldqfa */
4385
                    CHECK_FPU_FEATURE(dc, FLOAT128);
4386
                    save_state(dc, cpu_cond);
4387
                    gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4388
                    goto skip_move;
4389
#endif
4390
                default:
4391
                    goto illegal_insn;
4392
                }
4393
                gen_movl_TN_reg(rd, cpu_val);
4394
#ifdef TARGET_SPARC64
4395
            skip_move: ;
4396
#endif
4397
            } else if (xop >= 0x20 && xop < 0x24) {
4398
                if (gen_trap_ifnofpu(dc, cpu_cond))
4399
                    goto jmp_insn;
4400
                save_state(dc, cpu_cond);
4401
                switch (xop) {
4402
                case 0x20:      /* load fpreg */
4403
                    ABI32_MASK(cpu_addr);
4404
                    tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4405
                    tcg_gen_st_i32(cpu_tmp32, cpu_env,
4406
                                   offsetof(CPUState, fpr[rd]));
4407
                    break;
4408
                case 0x21:      /* load fsr */
4409
                    ABI32_MASK(cpu_addr);
4410
                    tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4411
                    tcg_gen_st_i32(cpu_tmp32, cpu_env,
4412
                                   offsetof(CPUState, ft0));
4413
                    tcg_gen_helper_0_0(helper_ldfsr);
4414
                    break;
4415
                case 0x22:      /* load quad fpreg */
4416
                    {
4417
                        TCGv r_const;
4418

    
4419
                        CHECK_FPU_FEATURE(dc, FLOAT128);
4420
                        r_const = tcg_const_i32(dc->mem_idx);
4421
                        tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const);
4422
                        tcg_temp_free(r_const);
4423
                        gen_op_store_QT0_fpr(QFPREG(rd));
4424
                    }
4425
                    break;
4426
                case 0x23:      /* load double fpreg */
4427
                    {
4428
                        TCGv r_const;
4429

    
4430
                        r_const = tcg_const_i32(dc->mem_idx);
4431
                        tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const);
4432
                        tcg_temp_free(r_const);
4433
                        gen_op_store_DT0_fpr(DFPREG(rd));
4434
                    }
4435
                    break;
4436
                default:
4437
                    goto illegal_insn;
4438
                }
4439
            } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4440
                       xop == 0xe || xop == 0x1e) {
4441
                gen_movl_reg_TN(rd, cpu_val);
4442
                switch (xop) {
4443
                case 0x4: /* store word */
4444
                    ABI32_MASK(cpu_addr);
4445
                    tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4446
                    break;
4447
                case 0x5: /* store byte */
4448
                    ABI32_MASK(cpu_addr);
4449
                    tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4450
                    break;
4451
                case 0x6: /* store halfword */
4452
                    ABI32_MASK(cpu_addr);
4453
                    tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4454
                    break;
4455
                case 0x7: /* store double word */
4456
                    if (rd & 1)
4457
                        goto illegal_insn;
4458
                    else {
4459
                        TCGv r_low, r_const;
4460

    
4461
                        save_state(dc, cpu_cond);
4462
                        ABI32_MASK(cpu_addr);
4463
                        r_const = tcg_const_i32(7);
4464
                        tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4465
                                           r_const); // XXX remove
4466
                        tcg_temp_free(r_const);
4467
                        r_low = tcg_temp_new(TCG_TYPE_TL);
4468
                        gen_movl_reg_TN(rd + 1, r_low);
4469
                        tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
4470
                                           r_low);
4471
                        tcg_temp_free(r_low);
4472
                        tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4473
                    }
4474
                    break;
4475
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4476
                case 0x14: /* store word alternate */
4477
#ifndef TARGET_SPARC64
4478
                    if (IS_IMM)
4479
                        goto illegal_insn;
4480
                    if (!supervisor(dc))
4481
                        goto priv_insn;
4482
#endif
4483
                    save_state(dc, cpu_cond);
4484
                    gen_st_asi(cpu_val, cpu_addr, insn, 4);
4485
                    break;
4486
                case 0x15: /* store byte alternate */
4487
#ifndef TARGET_SPARC64
4488
                    if (IS_IMM)
4489
                        goto illegal_insn;
4490
                    if (!supervisor(dc))
4491
                        goto priv_insn;
4492
#endif
4493
                    save_state(dc, cpu_cond);
4494
                    gen_st_asi(cpu_val, cpu_addr, insn, 1);
4495
                    break;
4496
                case 0x16: /* store halfword alternate */
4497
#ifndef TARGET_SPARC64
4498
                    if (IS_IMM)
4499
                        goto illegal_insn;
4500
                    if (!supervisor(dc))
4501
                        goto priv_insn;
4502
#endif
4503
                    save_state(dc, cpu_cond);
4504
                    gen_st_asi(cpu_val, cpu_addr, insn, 2);
4505
                    break;
4506
                case 0x17: /* store double word alternate */
4507
#ifndef TARGET_SPARC64
4508
                    if (IS_IMM)
4509
                        goto illegal_insn;
4510
                    if (!supervisor(dc))
4511
                        goto priv_insn;
4512
#endif
4513
                    if (rd & 1)
4514
                        goto illegal_insn;
4515
                    else {
4516
                        save_state(dc, cpu_cond);
4517
                        gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4518
                    }
4519
                    break;
4520
#endif
4521
#ifdef TARGET_SPARC64
4522
                case 0x0e: /* V9 stx */
4523
                    ABI32_MASK(cpu_addr);
4524
                    tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4525
                    break;
4526
                case 0x1e: /* V9 stxa */
4527
                    save_state(dc, cpu_cond);
4528
                    gen_st_asi(cpu_val, cpu_addr, insn, 8);
4529
                    break;
4530
#endif
4531
                default:
4532
                    goto illegal_insn;
4533
                }
4534
            } else if (xop > 0x23 && xop < 0x28) {
4535
                if (gen_trap_ifnofpu(dc, cpu_cond))
4536
                    goto jmp_insn;
4537
                save_state(dc, cpu_cond);
4538
                switch (xop) {
4539
                case 0x24: /* store fpreg */
4540
                    ABI32_MASK(cpu_addr);
4541
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4542
                                   offsetof(CPUState, fpr[rd]));
4543
                    tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4544
                    break;
4545
                case 0x25: /* stfsr, V9 stxfsr */
4546
                    ABI32_MASK(cpu_addr);
4547
                    tcg_gen_helper_0_0(helper_stfsr);
4548
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4549
                                   offsetof(CPUState, ft0));
4550
                    tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4551
                    break;
4552
                case 0x26:
4553
#ifdef TARGET_SPARC64
4554
                    /* V9 stqf, store quad fpreg */
4555
                    {
4556
                        TCGv r_const;
4557

    
4558
                        CHECK_FPU_FEATURE(dc, FLOAT128);
4559
                        gen_op_load_fpr_QT0(QFPREG(rd));
4560
                        r_const = tcg_const_i32(dc->mem_idx);
4561
                        tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const);
4562
                        tcg_temp_free(r_const);
4563
                    }
4564
                    break;
4565
#else /* !TARGET_SPARC64 */
4566
                    /* stdfq, store floating point queue */
4567
#if defined(CONFIG_USER_ONLY)
4568
                    goto illegal_insn;
4569
#else
4570
                    if (!supervisor(dc))
4571
                        goto priv_insn;
4572
                    if (gen_trap_ifnofpu(dc, cpu_cond))
4573
                        goto jmp_insn;
4574
                    goto nfq_insn;
4575
#endif
4576
#endif
4577
                case 0x27: /* store double fpreg */
4578
                    {
4579
                        TCGv r_const;
4580

    
4581
                        gen_op_load_fpr_DT0(DFPREG(rd));
4582
                        r_const = tcg_const_i32(dc->mem_idx);
4583
                        tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const);
4584
                        tcg_temp_free(r_const);
4585
                    }
4586
                    break;
4587
                default:
4588
                    goto illegal_insn;
4589
                }
4590
            } else if (xop > 0x33 && xop < 0x3f) {
4591
                save_state(dc, cpu_cond);
4592
                switch (xop) {
4593
#ifdef TARGET_SPARC64
4594
                case 0x34: /* V9 stfa */
4595
                    gen_op_load_fpr_FT0(rd);
4596
                    gen_stf_asi(cpu_addr, insn, 4, rd);
4597
                    break;
4598
                case 0x36: /* V9 stqfa */
4599
                    {
4600
                        TCGv r_const;
4601

    
4602
                        CHECK_FPU_FEATURE(dc, FLOAT128);
4603
                        r_const = tcg_const_i32(7);
4604
                        tcg_gen_helper_0_2(helper_check_align, cpu_addr,
4605
                                           r_const);
4606
                        tcg_temp_free(r_const);
4607
                        gen_op_load_fpr_QT0(QFPREG(rd));
4608
                        gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4609
                    }
4610
                    break;
4611
                case 0x37: /* V9 stdfa */
4612
                    gen_op_load_fpr_DT0(DFPREG(rd));
4613
                    gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4614
                    break;
4615
                case 0x3c: /* V9 casa */
4616
                    gen_cas_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4617
                    gen_movl_TN_reg(rd, cpu_val);
4618
                    break;
4619
                case 0x3e: /* V9 casxa */
4620
                    gen_casx_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4621
                    gen_movl_TN_reg(rd, cpu_val);
4622
                    break;
4623
#else
4624
                case 0x34: /* stc */
4625
                case 0x35: /* stcsr */
4626
                case 0x36: /* stdcq */
4627
                case 0x37: /* stdc */
4628
                    goto ncp_insn;
4629
#endif
4630
                default:
4631
                    goto illegal_insn;
4632
                }
4633
            }
4634
            else
4635
                goto illegal_insn;
4636
        }
4637
        break;
4638
    }
4639
    /* default case for non jump instructions */
4640
    if (dc->npc == DYNAMIC_PC) {
4641
        dc->pc = DYNAMIC_PC;
4642
        gen_op_next_insn();
4643
    } else if (dc->npc == JUMP_PC) {
4644
        /* we can do a static jump */
4645
        gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4646
        dc->is_br = 1;
4647
    } else {
4648
        dc->pc = dc->npc;
4649
        dc->npc = dc->npc + 4;
4650
    }
4651
 jmp_insn:
4652
    return;
4653
 illegal_insn:
4654
    {
4655
        TCGv r_const;
4656

    
4657
        save_state(dc, cpu_cond);
4658
        r_const = tcg_const_i32(TT_ILL_INSN);
4659
        tcg_gen_helper_0_1(raise_exception, r_const);
4660
        tcg_temp_free(r_const);
4661
        dc->is_br = 1;
4662
    }
4663
    return;
4664
 unimp_flush:
4665
    {
4666
        TCGv r_const;
4667

    
4668
        save_state(dc, cpu_cond);
4669
        r_const = tcg_const_i32(TT_UNIMP_FLUSH);
4670
        tcg_gen_helper_0_1(raise_exception, r_const);
4671
        tcg_temp_free(r_const);
4672
        dc->is_br = 1;
4673
    }
4674
    return;
4675
#if !defined(CONFIG_USER_ONLY)
4676
 priv_insn:
4677
    {
4678
        TCGv r_const;
4679

    
4680
        save_state(dc, cpu_cond);
4681
        r_const = tcg_const_i32(TT_PRIV_INSN);
4682
        tcg_gen_helper_0_1(raise_exception, r_const);
4683
        tcg_temp_free(r_const);
4684
        dc->is_br = 1;
4685
    }
4686
    return;
4687
#endif
4688
 nfpu_insn:
4689
    save_state(dc, cpu_cond);
4690
    gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4691
    dc->is_br = 1;
4692
    return;
4693
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
4694
 nfq_insn:
4695
    save_state(dc, cpu_cond);
4696
    gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4697
    dc->is_br = 1;
4698
    return;
4699
#endif
4700
#ifndef TARGET_SPARC64
4701
 ncp_insn:
4702
    {
4703
        TCGv r_const;
4704

    
4705
        save_state(dc, cpu_cond);
4706
        r_const = tcg_const_i32(TT_NCP_INSN);
4707
        tcg_gen_helper_0_1(raise_exception, r_const);
4708
        tcg_temp_free(r_const);
4709
        dc->is_br = 1;
4710
    }
4711
    return;
4712
#endif
4713
}
4714

    
4715
static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4716
                                                 int spc, CPUSPARCState *env)
4717
{
4718
    target_ulong pc_start, last_pc;
4719
    uint16_t *gen_opc_end;
4720
    DisasContext dc1, *dc = &dc1;
4721
    int j, lj = -1;
4722

    
4723
    memset(dc, 0, sizeof(DisasContext));
4724
    dc->tb = tb;
4725
    pc_start = tb->pc;
4726
    dc->pc = pc_start;
4727
    last_pc = dc->pc;
4728
    dc->npc = (target_ulong) tb->cs_base;
4729
    dc->mem_idx = cpu_mmu_index(env);
4730
    dc->features = env->features;
4731
    if ((dc->features & CPU_FEATURE_FLOAT)) {
4732
        dc->fpu_enabled = cpu_fpu_enabled(env);
4733
#if defined(CONFIG_USER_ONLY)
4734
        dc->features |= CPU_FEATURE_FLOAT128;
4735
#endif
4736
    } else
4737
        dc->fpu_enabled = 0;
4738
    gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4739

    
4740
    cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4741
    cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4742
    cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4743

    
4744
    cpu_dst = tcg_temp_local_new(TCG_TYPE_TL);
4745

    
4746
    // loads and stores
4747
    cpu_val = tcg_temp_local_new(TCG_TYPE_TL);
4748
    cpu_addr = tcg_temp_local_new(TCG_TYPE_TL);
4749

    
4750
    do {
4751
        if (env->nb_breakpoints > 0) {
4752
            for(j = 0; j < env->nb_breakpoints; j++) {
4753
                if (env->breakpoints[j] == dc->pc) {
4754
                    if (dc->pc != pc_start)
4755
                        save_state(dc, cpu_cond);
4756
                    tcg_gen_helper_0_0(helper_debug);
4757
                    tcg_gen_exit_tb(0);
4758
                    dc->is_br = 1;
4759
                    goto exit_gen_loop;
4760
                }
4761
            }
4762
        }
4763
        if (spc) {
4764
            if (loglevel > 0)
4765
                fprintf(logfile, "Search PC...\n");
4766
            j = gen_opc_ptr - gen_opc_buf;
4767
            if (lj < j) {
4768
                lj++;
4769
                while (lj < j)
4770
                    gen_opc_instr_start[lj++] = 0;
4771
                gen_opc_pc[lj] = dc->pc;
4772
                gen_opc_npc[lj] = dc->npc;
4773
                gen_opc_instr_start[lj] = 1;
4774
            }
4775
        }
4776
        last_pc = dc->pc;
4777
        disas_sparc_insn(dc);
4778

    
4779
        if (dc->is_br)
4780
            break;
4781
        /* if the next PC is different, we abort now */
4782
        if (dc->pc != (last_pc + 4))
4783
            break;
4784
        /* if we reach a page boundary, we stop generation so that the
4785
           PC of a TT_TFAULT exception is always in the right page */
4786
        if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4787
            break;
4788
        /* if single step mode, we generate only one instruction and
4789
           generate an exception */
4790
        if (env->singlestep_enabled) {
4791
            tcg_gen_movi_tl(cpu_pc, dc->pc);
4792
            tcg_gen_exit_tb(0);
4793
            break;
4794
        }
4795
    } while ((gen_opc_ptr < gen_opc_end) &&
4796
             (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
4797

    
4798
 exit_gen_loop:
4799
    tcg_temp_free(cpu_addr);
4800
    tcg_temp_free(cpu_val);
4801
    tcg_temp_free(cpu_dst);
4802
    tcg_temp_free(cpu_tmp64);
4803
    tcg_temp_free(cpu_tmp32);
4804
    tcg_temp_free(cpu_tmp0);
4805
    if (!dc->is_br) {
4806
        if (dc->pc != DYNAMIC_PC &&
4807
            (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4808
            /* static PC and NPC: we can use direct chaining */
4809
            gen_goto_tb(dc, 0, dc->pc, dc->npc);
4810
        } else {
4811
            if (dc->pc != DYNAMIC_PC)
4812
                tcg_gen_movi_tl(cpu_pc, dc->pc);
4813
            save_npc(dc, cpu_cond);
4814
            tcg_gen_exit_tb(0);
4815
        }
4816
    }
4817
    *gen_opc_ptr = INDEX_op_end;
4818
    if (spc) {
4819
        j = gen_opc_ptr - gen_opc_buf;
4820
        lj++;
4821
        while (lj <= j)
4822
            gen_opc_instr_start[lj++] = 0;
4823
#if 0
4824
        if (loglevel > 0) {
4825
            page_dump(logfile);
4826
        }
4827
#endif
4828
        gen_opc_jump_pc[0] = dc->jump_pc[0];
4829
        gen_opc_jump_pc[1] = dc->jump_pc[1];
4830
    } else {
4831
        tb->size = last_pc + 4 - pc_start;
4832
    }
4833
#ifdef DEBUG_DISAS
4834
    if (loglevel & CPU_LOG_TB_IN_ASM) {
4835
        fprintf(logfile, "--------------\n");
4836
        fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4837
        target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4838
        fprintf(logfile, "\n");
4839
    }
4840
#endif
4841
    return 0;
4842
}
4843

    
4844
int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4845
{
4846
    return gen_intermediate_code_internal(tb, 0, env);
4847
}
4848

    
4849
int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4850
{
4851
    return gen_intermediate_code_internal(tb, 1, env);
4852
}
4853

    
4854
void gen_intermediate_code_init(CPUSPARCState *env)
4855
{
4856
    unsigned int i;
4857
    static int inited;
4858
    static const char * const gregnames[8] = {
4859
        NULL, // g0 not used
4860
        "g1",
4861
        "g2",
4862
        "g3",
4863
        "g4",
4864
        "g5",
4865
        "g6",
4866
        "g7",
4867
    };
4868

    
4869
    /* init various static tables */
4870
    if (!inited) {
4871
        inited = 1;
4872

    
4873
        cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4874
        cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4875
                                         offsetof(CPUState, regwptr),
4876
                                         "regwptr");
4877
#ifdef TARGET_SPARC64
4878
        cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4879
                                     TCG_AREG0, offsetof(CPUState, xcc),
4880
                                     "xcc");
4881
#endif
4882
        cpu_cond = tcg_global_mem_new(TCG_TYPE_TL,
4883
                                      TCG_AREG0, offsetof(CPUState, cond),
4884
                                      "cond");
4885
        cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4886
                                        TCG_AREG0, offsetof(CPUState, cc_src),
4887
                                        "cc_src");
4888
        cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4889
                                         offsetof(CPUState, cc_src2),
4890
                                         "cc_src2");
4891
        cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4892
                                        TCG_AREG0, offsetof(CPUState, cc_dst),
4893
                                        "cc_dst");
4894
        cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4895
                                     TCG_AREG0, offsetof(CPUState, psr),
4896
                                     "psr");
4897
        cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4898
                                     TCG_AREG0, offsetof(CPUState, fsr),
4899
                                     "fsr");
4900
        cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,