Revision d999f7e0

b/hw/ac97.c
278 278
    if (level) {
279 279
        s->glob_sta |= masks[r - s->bm_regs];
280 280
        dolog ("set irq level=1\n");
281
        qemu_set_irq(s->pci_dev->irq[0], 1);
281
        qemu_set_irq (s->pci_dev->irq[0], 1);
282 282
    }
283 283
    else {
284 284
        s->glob_sta &= ~masks[r - s->bm_regs];
285 285
        dolog ("set irq level=0\n");
286
        qemu_set_irq(s->pci_dev->irq[0], 0);
286
        qemu_set_irq (s->pci_dev->irq[0], 0);
287 287
    }
288 288
}
289 289

  
......
1331 1331
    s = &d->ac97;
1332 1332
    s->pci_dev = &d->dev;
1333 1333
    c = d->dev.config;
1334
    pci_config_set_vendor_id(c, PCI_VENDOR_ID_INTEL); /* ro */
1335
    pci_config_set_device_id(c, PCI_DEVICE_ID_INTEL_82801AA_5); /* ro */
1334
    pci_config_set_vendor_id (c, PCI_VENDOR_ID_INTEL); /* ro */
1335
    pci_config_set_device_id (c, PCI_DEVICE_ID_INTEL_82801AA_5); /* ro */
1336 1336

  
1337 1337
    c[0x04] = 0x00;      /* pcicmd pci command rw, ro */
1338 1338
    c[0x05] = 0x00;
......
1342 1342

  
1343 1343
    c[0x08] = 0x01;      /* rid revision ro */
1344 1344
    c[0x09] = 0x00;      /* pi programming interface ro */
1345
    pci_config_set_class(c, PCI_CLASS_MULTIMEDIA_AUDIO); /* ro */
1345
    pci_config_set_class (c, PCI_CLASS_MULTIMEDIA_AUDIO); /* ro */
1346 1346
    c[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; /* headtyp header type ro */
1347 1347

  
1348 1348
    c[0x10] = 0x01;      /* nabmar native audio mixer base
b/hw/adlib.c
115 115
    }
116 116
}
117 117

  
118
static IO_WRITE_PROTO(adlib_write)
118
static IO_WRITE_PROTO (adlib_write)
119 119
{
120 120
    AdlibState *s = opaque;
121 121
    int a = nport & 3;
......
133 133
#endif
134 134
}
135 135

  
136
static IO_READ_PROTO(adlib_read)
136
static IO_READ_PROTO (adlib_read)
137 137
{
138 138
    AdlibState *s = opaque;
139 139
    uint8_t data;
b/hw/cs4231a.c
216 216
      944,   912,  1008,   976,   816,   784,   880,   848
217 217
};
218 218

  
219
static void cs_reset(void *opaque)
219
static void cs_reset (void *opaque)
220 220
{
221 221
    CSState *s = opaque;
222 222

  
......
597 597
    return dma_pos;
598 598
}
599 599

  
600
static void cs_save(QEMUFile *f, void *opaque)
600
static void cs_save (QEMUFile *f, void *opaque)
601 601
{
602 602
    CSState *s = opaque;
603 603
    unsigned int i;
604 604
    uint32_t val;
605 605

  
606 606
    for (i = 0; i < CS_REGS; i++)
607
        qemu_put_be32s(f, &s->regs[i]);
607
        qemu_put_be32s (f, &s->regs[i]);
608 608

  
609
    qemu_put_buffer(f, s->dregs, CS_DREGS);
610
    val = s->dma_running; qemu_put_be32s(f, &val);
611
    val = s->audio_free;  qemu_put_be32s(f, &val);
612
    val = s->transferred; qemu_put_be32s(f, &val);
613
    val = s->aci_counter; qemu_put_be32s(f, &val);
609
    qemu_put_buffer (f, s->dregs, CS_DREGS);
610
    val = s->dma_running; qemu_put_be32s (f, &val);
611
    val = s->audio_free;  qemu_put_be32s (f, &val);
612
    val = s->transferred; qemu_put_be32s (f, &val);
613
    val = s->aci_counter; qemu_put_be32s (f, &val);
614 614
}
615 615

  
616
static int cs_load(QEMUFile *f, void *opaque, int version_id)
616
static int cs_load (QEMUFile *f, void *opaque, int version_id)
617 617
{
618 618
    CSState *s = opaque;
619 619
    unsigned int i;
......
623 623
        return -EINVAL;
624 624

  
625 625
    for (i = 0; i < CS_REGS; i++)
626
        qemu_get_be32s(f, &s->regs[i]);
626
        qemu_get_be32s (f, &s->regs[i]);
627 627

  
628
    qemu_get_buffer(f, s->dregs, CS_DREGS);
628
    qemu_get_buffer (f, s->dregs, CS_DREGS);
629 629

  
630
    qemu_get_be32s(f, &dma_running);
631
    qemu_get_be32s(f, &val); s->audio_free  = val;
632
    qemu_get_be32s(f, &val); s->transferred = val;
633
    qemu_get_be32s(f, &val); s->aci_counter = val;
630
    qemu_get_be32s (f, &dma_running);
631
    qemu_get_be32s (f, &val); s->audio_free  = val;
632
    qemu_get_be32s (f, &val); s->transferred = val;
633
    qemu_get_be32s (f, &val); s->aci_counter = val;
634 634
    if (dma_running && (s->dregs[Interface_Configuration] & PEN))
635 635
        cs_reset_voices (s, s->dregs[FS_And_Playback_Data_Format]);
636 636
    return 0;
b/hw/es1370.c
327 327
    else {
328 328
        s->status = new_status & ~STAT_INTR;
329 329
    }
330
    qemu_set_irq(s->pci_dev->irq[0], !!level);
330
    qemu_set_irq (s->pci_dev->irq[0], !!level);
331 331
}
332 332

  
333 333
static void es1370_reset (ES1370State *s)
......
353 353
            s->dac_voice[i] = NULL;
354 354
        }
355 355
    }
356
    qemu_irq_lower(s->pci_dev->irq[0]);
356
    qemu_irq_lower (s->pci_dev->irq[0]);
357 357
}
358 358

  
359 359
static void es1370_maybe_lower_irq (ES1370State *s, uint32_t sctl)
......
1026 1026
    }
1027 1027

  
1028 1028
    c = d->dev.config;
1029
    pci_config_set_vendor_id(c, PCI_VENDOR_ID_ENSONIQ);
1030
    pci_config_set_device_id(c, PCI_DEVICE_ID_ENSONIQ_ES1370);
1029
    pci_config_set_vendor_id (c, PCI_VENDOR_ID_ENSONIQ);
1030
    pci_config_set_device_id (c, PCI_DEVICE_ID_ENSONIQ_ES1370);
1031 1031
    c[0x07] = 2 << 1;
1032
    pci_config_set_class(c, PCI_CLASS_MULTIMEDIA_AUDIO);
1032
    pci_config_set_class (c, PCI_CLASS_MULTIMEDIA_AUDIO);
1033 1033

  
1034 1034
#if 1
1035 1035
    c[0x2c] = 0x42;
b/hw/sb16.c
1066 1066
    }
1067 1067
}
1068 1068

  
1069
static IO_WRITE_PROTO(mixer_write_indexb)
1069
static IO_WRITE_PROTO (mixer_write_indexb)
1070 1070
{
1071 1071
    SB16State *s = opaque;
1072 1072
    (void) nport;
1073 1073
    s->mixer_nreg = val;
1074 1074
}
1075 1075

  
1076
static IO_WRITE_PROTO(mixer_write_datab)
1076
static IO_WRITE_PROTO (mixer_write_datab)
1077 1077
{
1078 1078
    SB16State *s = opaque;
1079 1079

  
......
1129 1129
    s->mixer_regs[s->mixer_nreg] = val;
1130 1130
}
1131 1131

  
1132
static IO_WRITE_PROTO(mixer_write_indexw)
1132
static IO_WRITE_PROTO (mixer_write_indexw)
1133 1133
{
1134 1134
    mixer_write_indexb (opaque, nport, val & 0xff);
1135 1135
    mixer_write_datab (opaque, nport, (val >> 8) & 0xff);
1136 1136
}
1137 1137

  
1138
static IO_READ_PROTO(mixer_read)
1138
static IO_READ_PROTO (mixer_read)
1139 1139
{
1140 1140
    SB16State *s = opaque;
1141 1141

  

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