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/*
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* ARM micro operations
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2005-2007 CodeSourcery, LLC
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h" |
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void OPPROTO op_addl_T0_T1_cc(void) |
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{
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unsigned int src1; |
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src1 = T0; |
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T0 += T1; |
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env->NZF = T0; |
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env->CF = T0 < src1; |
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env->VF = (src1 ^ T1 ^ -1) & (src1 ^ T0);
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} |
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void OPPROTO op_adcl_T0_T1_cc(void) |
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{
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unsigned int src1; |
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src1 = T0; |
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if (!env->CF) {
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T0 += T1; |
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env->CF = T0 < src1; |
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} else {
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T0 += T1 + 1;
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env->CF = T0 <= src1; |
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} |
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env->VF = (src1 ^ T1 ^ -1) & (src1 ^ T0);
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env->NZF = T0; |
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FORCE_RET(); |
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} |
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|
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#define OPSUB(sub, sbc, res, T0, T1) \
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\ |
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void OPPROTO op_ ## sub ## l_T0_T1_cc(void) \ |
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{ \
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unsigned int src1; \ |
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src1 = T0; \ |
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T0 -= T1; \ |
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env->NZF = T0; \ |
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env->CF = src1 >= T1; \ |
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env->VF = (src1 ^ T1) & (src1 ^ T0); \ |
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res = T0; \ |
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} \ |
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\ |
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void OPPROTO op_ ## sbc ## l_T0_T1_cc(void) \ |
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{ \
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unsigned int src1; \ |
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src1 = T0; \ |
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if (!env->CF) { \
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T0 = T0 - T1 - 1; \
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env->CF = src1 > T1; \ |
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} else { \
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T0 = T0 - T1; \ |
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env->CF = src1 >= T1; \ |
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} \ |
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env->VF = (src1 ^ T1) & (src1 ^ T0); \ |
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env->NZF = T0; \ |
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res = T0; \ |
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FORCE_RET(); \ |
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} |
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|
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OPSUB(sub, sbc, T0, T0, T1) |
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|
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OPSUB(rsb, rsc, T0, T1, T0) |
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void OPPROTO op_addq_T0_T1(void) |
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{
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uint64_t res; |
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res = ((uint64_t)T1 << 32) | T0;
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res += ((uint64_t)(env->regs[PARAM2]) << 32) | (env->regs[PARAM1]);
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T1 = res >> 32;
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T0 = res; |
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} |
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|
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void OPPROTO op_addq_lo_T0_T1(void) |
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{
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uint64_t res; |
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res = ((uint64_t)T1 << 32) | T0;
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res += (uint64_t)(env->regs[PARAM1]); |
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T1 = res >> 32;
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T0 = res; |
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} |
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|
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/* Dual 16-bit accumulate. */
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void OPPROTO op_addq_T0_T1_dual(void) |
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{
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uint64_t res; |
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res = ((uint64_t)(env->regs[PARAM2]) << 32) | (env->regs[PARAM1]);
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res += (int32_t)T0; |
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res += (int32_t)T1; |
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env->regs[PARAM1] = (uint32_t)res; |
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env->regs[PARAM2] = res >> 32;
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} |
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/* Dual 16-bit subtract accumulate. */
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void OPPROTO op_subq_T0_T1_dual(void) |
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{
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uint64_t res; |
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res = ((uint64_t)(env->regs[PARAM2]) << 32) | (env->regs[PARAM1]);
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res += (int32_t)T0; |
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res -= (int32_t)T1; |
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env->regs[PARAM1] = (uint32_t)res; |
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env->regs[PARAM2] = res >> 32;
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} |
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void OPPROTO op_logicq_cc(void) |
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{
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env->NZF = (T1 & 0x80000000) | ((T0 | T1) != 0); |
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} |
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/* memory access */
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#define MEMSUFFIX _raw
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#include "op_mem.h" |
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#if !defined(CONFIG_USER_ONLY)
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#define MEMSUFFIX _user
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#include "op_mem.h" |
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#define MEMSUFFIX _kernel
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#include "op_mem.h" |
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#endif
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void OPPROTO op_clrex(void) |
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{
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cpu_lock(); |
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helper_clrex(env); |
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cpu_unlock(); |
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} |
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|
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/* T1 based, use T0 as shift count */
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void OPPROTO op_shll_T1_T0(void) |
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{
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int shift;
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shift = T0 & 0xff;
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if (shift >= 32) |
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T1 = 0;
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else
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T1 = T1 << shift; |
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FORCE_RET(); |
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} |
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void OPPROTO op_shrl_T1_T0(void) |
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{
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int shift;
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shift = T0 & 0xff;
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if (shift >= 32) |
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T1 = 0;
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else
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T1 = (uint32_t)T1 >> shift; |
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FORCE_RET(); |
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} |
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void OPPROTO op_sarl_T1_T0(void) |
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{
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int shift;
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shift = T0 & 0xff;
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if (shift >= 32) |
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shift = 31;
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T1 = (int32_t)T1 >> shift; |
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} |
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void OPPROTO op_rorl_T1_T0(void) |
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{
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int shift;
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shift = T0 & 0x1f;
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if (shift) {
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T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
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} |
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FORCE_RET(); |
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} |
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/* T1 based, use T0 as shift count and compute CF */
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void OPPROTO op_shll_T1_T0_cc(void) |
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{
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int shift;
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shift = T0 & 0xff;
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if (shift >= 32) { |
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if (shift == 32) |
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env->CF = T1 & 1;
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else
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env->CF = 0;
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T1 = 0;
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} else if (shift != 0) { |
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env->CF = (T1 >> (32 - shift)) & 1; |
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T1 = T1 << shift; |
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} |
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FORCE_RET(); |
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} |
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void OPPROTO op_shrl_T1_T0_cc(void) |
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{
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int shift;
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shift = T0 & 0xff;
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if (shift >= 32) { |
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if (shift == 32) |
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env->CF = (T1 >> 31) & 1; |
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else
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env->CF = 0;
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T1 = 0;
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} else if (shift != 0) { |
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env->CF = (T1 >> (shift - 1)) & 1; |
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T1 = (uint32_t)T1 >> shift; |
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} |
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FORCE_RET(); |
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} |
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void OPPROTO op_sarl_T1_T0_cc(void) |
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{
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int shift;
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shift = T0 & 0xff;
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if (shift >= 32) { |
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env->CF = (T1 >> 31) & 1; |
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T1 = (int32_t)T1 >> 31;
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} else if (shift != 0) { |
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env->CF = (T1 >> (shift - 1)) & 1; |
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T1 = (int32_t)T1 >> shift; |
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} |
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FORCE_RET(); |
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} |
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void OPPROTO op_rorl_T1_T0_cc(void) |
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{
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int shift1, shift;
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shift1 = T0 & 0xff;
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shift = shift1 & 0x1f;
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if (shift == 0) { |
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if (shift1 != 0) |
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env->CF = (T1 >> 31) & 1; |
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} else {
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env->CF = (T1 >> (shift - 1)) & 1; |
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T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
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} |
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FORCE_RET(); |
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} |
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/* VFP support. We follow the convention used for VFP instrunctions:
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Single precition routines have a "s" suffix, double precision a
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"d" suffix. */
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#define VFP_OP(name, p) void OPPROTO op_vfp_##name##p(void) |
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#define VFP_BINOP(name) \
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VFP_OP(name, s) \ |
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{ \
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FT0s = float32_ ## name (FT0s, FT1s, &env->vfp.fp_status); \ |
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} \ |
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VFP_OP(name, d) \ |
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{ \
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FT0d = float64_ ## name (FT0d, FT1d, &env->vfp.fp_status); \ |
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} |
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VFP_BINOP(add) |
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VFP_BINOP(sub) |
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VFP_BINOP(mul) |
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VFP_BINOP(div) |
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#undef VFP_BINOP
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#define VFP_HELPER(name) \
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VFP_OP(name, s) \ |
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{ \
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do_vfp_##name##s(); \ |
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} \ |
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VFP_OP(name, d) \ |
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{ \
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do_vfp_##name##d(); \ |
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} |
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VFP_HELPER(abs) |
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VFP_HELPER(sqrt) |
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VFP_HELPER(cmp) |
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VFP_HELPER(cmpe) |
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#undef VFP_HELPER
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/* XXX: Will this do the right thing for NANs. Should invert the signbit
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without looking at the rest of the value. */
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VFP_OP(neg, s) |
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{
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FT0s = float32_chs(FT0s); |
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} |
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VFP_OP(neg, d) |
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{
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FT0d = float64_chs(FT0d); |
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} |
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VFP_OP(F1_ld0, s) |
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{
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union {
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uint32_t i; |
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float32 s; |
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} v; |
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v.i = 0;
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FT1s = v.s; |
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} |
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VFP_OP(F1_ld0, d) |
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{
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union {
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uint64_t i; |
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float64 d; |
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} v; |
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v.i = 0;
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FT1d = v.d; |
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} |
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/* Helper routines to perform bitwise copies between float and int. */
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static inline float32 vfp_itos(uint32_t i) |
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{
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union {
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uint32_t i; |
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float32 s; |
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} v; |
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v.i = i; |
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return v.s;
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} |
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static inline uint32_t vfp_stoi(float32 s) |
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{
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union {
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uint32_t i; |
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float32 s; |
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} v; |
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v.s = s; |
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return v.i;
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} |
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|
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static inline float64 vfp_itod(uint64_t i) |
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{
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union {
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uint64_t i; |
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float64 d; |
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} v; |
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|
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v.i = i; |
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return v.d;
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} |
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|
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static inline uint64_t vfp_dtoi(float64 d) |
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{
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union {
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uint64_t i; |
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float64 d; |
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} v; |
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v.d = d; |
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return v.i;
|
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} |
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|
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/* Integer to float conversion. */
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VFP_OP(uito, s) |
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{
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FT0s = uint32_to_float32(vfp_stoi(FT0s), &env->vfp.fp_status); |
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} |
| 373 |
|
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VFP_OP(uito, d) |
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{
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FT0d = uint32_to_float64(vfp_stoi(FT0s), &env->vfp.fp_status); |
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} |
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VFP_OP(sito, s) |
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{
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FT0s = int32_to_float32(vfp_stoi(FT0s), &env->vfp.fp_status); |
| 382 |
} |
| 383 |
|
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VFP_OP(sito, d) |
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{
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FT0d = int32_to_float64(vfp_stoi(FT0s), &env->vfp.fp_status); |
| 387 |
} |
| 388 |
|
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/* Float to integer conversion. */
|
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VFP_OP(toui, s) |
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{
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FT0s = vfp_itos(float32_to_uint32(FT0s, &env->vfp.fp_status)); |
| 393 |
} |
| 394 |
|
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VFP_OP(toui, d) |
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{
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FT0s = vfp_itos(float64_to_uint32(FT0d, &env->vfp.fp_status)); |
| 398 |
} |
| 399 |
|
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VFP_OP(tosi, s) |
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{
|
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FT0s = vfp_itos(float32_to_int32(FT0s, &env->vfp.fp_status)); |
| 403 |
} |
| 404 |
|
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VFP_OP(tosi, d) |
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{
|
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FT0s = vfp_itos(float64_to_int32(FT0d, &env->vfp.fp_status)); |
| 408 |
} |
| 409 |
|
| 410 |
/* TODO: Set rounding mode properly. */
|
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VFP_OP(touiz, s) |
| 412 |
{
|
| 413 |
FT0s = vfp_itos(float32_to_uint32_round_to_zero(FT0s, &env->vfp.fp_status)); |
| 414 |
} |
| 415 |
|
| 416 |
VFP_OP(touiz, d) |
| 417 |
{
|
| 418 |
FT0s = vfp_itos(float64_to_uint32_round_to_zero(FT0d, &env->vfp.fp_status)); |
| 419 |
} |
| 420 |
|
| 421 |
VFP_OP(tosiz, s) |
| 422 |
{
|
| 423 |
FT0s = vfp_itos(float32_to_int32_round_to_zero(FT0s, &env->vfp.fp_status)); |
| 424 |
} |
| 425 |
|
| 426 |
VFP_OP(tosiz, d) |
| 427 |
{
|
| 428 |
FT0s = vfp_itos(float64_to_int32_round_to_zero(FT0d, &env->vfp.fp_status)); |
| 429 |
} |
| 430 |
|
| 431 |
/* floating point conversion */
|
| 432 |
VFP_OP(fcvtd, s) |
| 433 |
{
|
| 434 |
FT0d = float32_to_float64(FT0s, &env->vfp.fp_status); |
| 435 |
} |
| 436 |
|
| 437 |
VFP_OP(fcvts, d) |
| 438 |
{
|
| 439 |
FT0s = float64_to_float32(FT0d, &env->vfp.fp_status); |
| 440 |
} |
| 441 |
|
| 442 |
/* VFP3 fixed point conversion. */
|
| 443 |
#define VFP_CONV_FIX(name, p, ftype, itype, sign) \
|
| 444 |
VFP_OP(name##to, p) \ |
| 445 |
{ \
|
| 446 |
ftype tmp; \ |
| 447 |
tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(FT0##p), \ |
| 448 |
&env->vfp.fp_status); \ |
| 449 |
FT0##p = ftype##_scalbn(tmp, PARAM1, &env->vfp.fp_status); \ |
| 450 |
} \ |
| 451 |
VFP_OP(to##name, p) \ |
| 452 |
{ \
|
| 453 |
ftype tmp; \ |
| 454 |
tmp = ftype##_scalbn(FT0##p, PARAM1, &env->vfp.fp_status); \ |
| 455 |
FT0##p = vfp_ito##p((itype)ftype##_to_##sign##int32_round_to_zero(tmp, \ |
| 456 |
&env->vfp.fp_status)); \ |
| 457 |
} |
| 458 |
|
| 459 |
VFP_CONV_FIX(sh, d, float64, int16, ) |
| 460 |
VFP_CONV_FIX(sl, d, float64, int32, ) |
| 461 |
VFP_CONV_FIX(uh, d, float64, uint16, u) |
| 462 |
VFP_CONV_FIX(ul, d, float64, uint32, u) |
| 463 |
VFP_CONV_FIX(sh, s, float32, int16, ) |
| 464 |
VFP_CONV_FIX(sl, s, float32, int32, ) |
| 465 |
VFP_CONV_FIX(uh, s, float32, uint16, u) |
| 466 |
VFP_CONV_FIX(ul, s, float32, uint32, u) |
| 467 |
|
| 468 |
/* Get and Put values from registers. */
|
| 469 |
VFP_OP(getreg_F0, d) |
| 470 |
{
|
| 471 |
FT0d = *(float64 *)((char *) env + PARAM1);
|
| 472 |
} |
| 473 |
|
| 474 |
VFP_OP(getreg_F0, s) |
| 475 |
{
|
| 476 |
FT0s = *(float32 *)((char *) env + PARAM1);
|
| 477 |
} |
| 478 |
|
| 479 |
VFP_OP(getreg_F1, d) |
| 480 |
{
|
| 481 |
FT1d = *(float64 *)((char *) env + PARAM1);
|
| 482 |
} |
| 483 |
|
| 484 |
VFP_OP(getreg_F1, s) |
| 485 |
{
|
| 486 |
FT1s = *(float32 *)((char *) env + PARAM1);
|
| 487 |
} |
| 488 |
|
| 489 |
VFP_OP(setreg_F0, d) |
| 490 |
{
|
| 491 |
*(float64 *)((char *) env + PARAM1) = FT0d;
|
| 492 |
} |
| 493 |
|
| 494 |
VFP_OP(setreg_F0, s) |
| 495 |
{
|
| 496 |
*(float32 *)((char *) env + PARAM1) = FT0s;
|
| 497 |
} |
| 498 |
|
| 499 |
void OPPROTO op_vfp_movl_T0_fpscr(void) |
| 500 |
{
|
| 501 |
do_vfp_get_fpscr (); |
| 502 |
} |
| 503 |
|
| 504 |
void OPPROTO op_vfp_movl_T0_fpscr_flags(void) |
| 505 |
{
|
| 506 |
T0 = env->vfp.xregs[ARM_VFP_FPSCR] & (0xf << 28); |
| 507 |
} |
| 508 |
|
| 509 |
void OPPROTO op_vfp_movl_fpscr_T0(void) |
| 510 |
{
|
| 511 |
do_vfp_set_fpscr(); |
| 512 |
} |
| 513 |
|
| 514 |
void OPPROTO op_vfp_movl_T0_xreg(void) |
| 515 |
{
|
| 516 |
T0 = env->vfp.xregs[PARAM1]; |
| 517 |
} |
| 518 |
|
| 519 |
void OPPROTO op_vfp_movl_xreg_T0(void) |
| 520 |
{
|
| 521 |
env->vfp.xregs[PARAM1] = T0; |
| 522 |
} |
| 523 |
|
| 524 |
/* Move between FT0s to T0 */
|
| 525 |
void OPPROTO op_vfp_mrs(void) |
| 526 |
{
|
| 527 |
T0 = vfp_stoi(FT0s); |
| 528 |
} |
| 529 |
|
| 530 |
void OPPROTO op_vfp_msr(void) |
| 531 |
{
|
| 532 |
FT0s = vfp_itos(T0); |
| 533 |
} |
| 534 |
|
| 535 |
/* Move between FT0d and {T0,T1} */
|
| 536 |
void OPPROTO op_vfp_mrrd(void) |
| 537 |
{
|
| 538 |
CPU_DoubleU u; |
| 539 |
|
| 540 |
u.d = FT0d; |
| 541 |
T0 = u.l.lower; |
| 542 |
T1 = u.l.upper; |
| 543 |
} |
| 544 |
|
| 545 |
void OPPROTO op_vfp_mdrr(void) |
| 546 |
{
|
| 547 |
CPU_DoubleU u; |
| 548 |
|
| 549 |
u.l.lower = T0; |
| 550 |
u.l.upper = T1; |
| 551 |
FT0d = u.d; |
| 552 |
} |
| 553 |
|
| 554 |
/* Load immediate. PARAM1 is the 32 most significant bits of the value. */
|
| 555 |
void OPPROTO op_vfp_fconstd(void) |
| 556 |
{
|
| 557 |
CPU_DoubleU u; |
| 558 |
u.l.upper = PARAM1; |
| 559 |
u.l.lower = 0;
|
| 560 |
FT0d = u.d; |
| 561 |
} |
| 562 |
|
| 563 |
void OPPROTO op_vfp_fconsts(void) |
| 564 |
{
|
| 565 |
FT0s = vfp_itos(PARAM1); |
| 566 |
} |
| 567 |
|
| 568 |
void OPPROTO op_movl_cp_T0(void) |
| 569 |
{
|
| 570 |
helper_set_cp(env, PARAM1, T0); |
| 571 |
FORCE_RET(); |
| 572 |
} |
| 573 |
|
| 574 |
void OPPROTO op_movl_T0_cp(void) |
| 575 |
{
|
| 576 |
T0 = helper_get_cp(env, PARAM1); |
| 577 |
FORCE_RET(); |
| 578 |
} |
| 579 |
|
| 580 |
void OPPROTO op_movl_cp15_T0(void) |
| 581 |
{
|
| 582 |
helper_set_cp15(env, PARAM1, T0); |
| 583 |
FORCE_RET(); |
| 584 |
} |
| 585 |
|
| 586 |
void OPPROTO op_movl_T0_cp15(void) |
| 587 |
{
|
| 588 |
T0 = helper_get_cp15(env, PARAM1); |
| 589 |
FORCE_RET(); |
| 590 |
} |
| 591 |
|
| 592 |
/* Access to user mode registers from privileged modes. */
|
| 593 |
void OPPROTO op_movl_T0_user(void) |
| 594 |
{
|
| 595 |
int regno = PARAM1;
|
| 596 |
if (regno == 13) { |
| 597 |
T0 = env->banked_r13[0];
|
| 598 |
} else if (regno == 14) { |
| 599 |
T0 = env->banked_r14[0];
|
| 600 |
} else if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { |
| 601 |
T0 = env->usr_regs[regno - 8];
|
| 602 |
} else {
|
| 603 |
T0 = env->regs[regno]; |
| 604 |
} |
| 605 |
FORCE_RET(); |
| 606 |
} |
| 607 |
|
| 608 |
|
| 609 |
void OPPROTO op_movl_user_T0(void) |
| 610 |
{
|
| 611 |
int regno = PARAM1;
|
| 612 |
if (regno == 13) { |
| 613 |
env->banked_r13[0] = T0;
|
| 614 |
} else if (regno == 14) { |
| 615 |
env->banked_r14[0] = T0;
|
| 616 |
} else if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) { |
| 617 |
env->usr_regs[regno - 8] = T0;
|
| 618 |
} else {
|
| 619 |
env->regs[regno] = T0; |
| 620 |
} |
| 621 |
FORCE_RET(); |
| 622 |
} |
| 623 |
|
| 624 |
void OPPROTO op_movl_T1_r13_banked(void) |
| 625 |
{
|
| 626 |
T1 = helper_get_r13_banked(env, PARAM1); |
| 627 |
} |
| 628 |
|
| 629 |
void OPPROTO op_movl_r13_T1_banked(void) |
| 630 |
{
|
| 631 |
helper_set_r13_banked(env, PARAM1, T1); |
| 632 |
} |
| 633 |
|
| 634 |
void OPPROTO op_v7m_mrs_T0(void) |
| 635 |
{
|
| 636 |
T0 = helper_v7m_mrs(env, PARAM1); |
| 637 |
} |
| 638 |
|
| 639 |
void OPPROTO op_v7m_msr_T0(void) |
| 640 |
{
|
| 641 |
helper_v7m_msr(env, PARAM1, T0); |
| 642 |
} |
| 643 |
|
| 644 |
void OPPROTO op_movl_T0_sp(void) |
| 645 |
{
|
| 646 |
if (PARAM1 == env->v7m.current_sp)
|
| 647 |
T0 = env->regs[13];
|
| 648 |
else
|
| 649 |
T0 = env->v7m.other_sp; |
| 650 |
FORCE_RET(); |
| 651 |
} |
| 652 |
|
| 653 |
#include "op_neon.h" |
| 654 |
|
| 655 |
/* iwMMXt support */
|
| 656 |
#include "op_iwmmxt.c" |