Revision d9bce9d9 target-ppc/helper.c
| b/target-ppc/helper.c | ||
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| 37 | 37 |
/*****************************************************************************/ |
| 38 | 38 |
/* PowerPC MMU emulation */ |
| 39 | 39 |
|
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#if defined(CONFIG_USER_ONLY)
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#if defined(CONFIG_USER_ONLY) |
|
| 41 | 41 |
int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw, |
| 42 | 42 |
int is_user, int is_softmmu) |
| 43 | 43 |
{
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int exception, error_code; |
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if (rw == 2) {
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exception = EXCP_ISI; |
| 48 | 48 |
error_code = 0; |
| ... | ... | |
| 277 | 277 |
ppc_tlb_t *tlb; |
| 278 | 278 |
int nr, best, way; |
| 279 | 279 |
int ret; |
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best = -1; |
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ret = -1; /* No TLB found */ |
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for (way = 0; way < env->nb_ways; way++) {
|
| ... | ... | |
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if (loglevel > 0) {
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fprintf(logfile, "%s\n", __func__); |
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} |
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#endif
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#endif |
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if ((access_type == ACCESS_CODE && msr_ir == 0) || |
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(access_type != ACCESS_CODE && msr_dr == 0)) {
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/* No address translation */ |
| ... | ... | |
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__func__, eaddr, ctx->raddr); |
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} |
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#endif |
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return ret; |
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} |
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|
| ... | ... | |
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int exception = 0, error_code = 0; |
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int access_type; |
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int ret = 0; |
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if (rw == 2) {
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/* code access */ |
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rw = 0; |
| ... | ... | |
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|
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/*****************************************************************************/ |
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/* Special registers manipulation */ |
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#if defined(TARGET_PPC64) |
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target_ulong ppc_load_asr (CPUPPCState *env) |
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{
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return env->asr; |
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} |
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void ppc_store_asr (CPUPPCState *env, target_ulong value) |
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{
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if (env->asr != value) {
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env->asr = value; |
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tlb_flush(env, 1); |
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} |
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} |
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#endif |
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target_ulong do_load_sdr1 (CPUPPCState *env) |
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{
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return env->sdr1; |
| ... | ... | |
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xer_ov = (value >> XER_OV) & 0x01; |
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xer_ca = (value >> XER_CA) & 0x01; |
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xer_cmp = (value >> XER_CMP) & 0xFF; |
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xer_bc = (value >> XER_BC) & 0x3F;
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xer_bc = (value >> XER_BC) & 0x7F;
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} |
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|
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/* Swap temporary saved registers with GPRs */ |
| ... | ... | |
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{
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return |
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#if defined (TARGET_PPC64) |
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(msr_sf << MSR_SF) | |
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(msr_isf << MSR_ISF) | |
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(msr_hv << MSR_HV) | |
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((target_ulong)msr_sf << MSR_SF) |
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((target_ulong)msr_isf << MSR_ISF) |
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((target_ulong)msr_hv << MSR_HV) |
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#endif |
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(msr_ucle << MSR_UCLE) | |
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(msr_vr << MSR_VR) | /* VR / SPE */ |
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(msr_ap << MSR_AP) | |
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(msr_sa << MSR_SA) | |
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(msr_key << MSR_KEY) | |
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(msr_pow << MSR_POW) | /* POW / WE */ |
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(msr_tlb << MSR_TLB) | /* TLB / TGPE / CE */ |
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(msr_ile << MSR_ILE) | |
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(msr_ee << MSR_EE) | |
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(msr_pr << MSR_PR) | |
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(msr_fp << MSR_FP) | |
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(msr_me << MSR_ME) | |
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(msr_fe0 << MSR_FE0) | |
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(msr_se << MSR_SE) | /* SE / DWE / UBLE */ |
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(msr_be << MSR_BE) | /* BE / DE */ |
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(msr_fe1 << MSR_FE1) | |
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(msr_al << MSR_AL) | |
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(msr_ip << MSR_IP) | |
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(msr_ir << MSR_IR) | /* IR / IS */ |
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(msr_dr << MSR_DR) | /* DR / DS */ |
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(msr_pe << MSR_PE) | /* PE / EP */ |
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(msr_px << MSR_PX) | /* PX / PMM */ |
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(msr_ri << MSR_RI) | |
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(msr_le << MSR_LE); |
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((target_ulong)msr_ucle << MSR_UCLE) |
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((target_ulong)msr_vr << MSR_VR) | /* VR / SPE */
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((target_ulong)msr_ap << MSR_AP) |
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((target_ulong)msr_sa << MSR_SA) |
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((target_ulong)msr_key << MSR_KEY) |
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((target_ulong)msr_pow << MSR_POW) | /* POW / WE */
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((target_ulong)msr_tlb << MSR_TLB) | /* TLB / TGPE / CE */
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((target_ulong)msr_ile << MSR_ILE) |
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((target_ulong)msr_ee << MSR_EE) |
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((target_ulong)msr_pr << MSR_PR) |
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((target_ulong)msr_fp << MSR_FP) |
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((target_ulong)msr_me << MSR_ME) |
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((target_ulong)msr_fe0 << MSR_FE0) |
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((target_ulong)msr_se << MSR_SE) | /* SE / DWE / UBLE */
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((target_ulong)msr_be << MSR_BE) | /* BE / DE */
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((target_ulong)msr_fe1 << MSR_FE1) |
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((target_ulong)msr_al << MSR_AL) |
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((target_ulong)msr_ip << MSR_IP) |
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((target_ulong)msr_ir << MSR_IR) | /* IR / IS */
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((target_ulong)msr_dr << MSR_DR) | /* DR / DS */
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((target_ulong)msr_pe << MSR_PE) | /* PE / EP */
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((target_ulong)msr_px << MSR_PX) | /* PX / PMM */
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((target_ulong)msr_ri << MSR_RI) |
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((target_ulong)msr_le << MSR_LE);
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} |
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void do_store_msr (CPUPPCState *env, target_ulong value) |
| ... | ... | |
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|
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enter_pm = 0; |
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switch (PPC_EXCP(env)) {
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case PPC_FLAGS_EXCP_603: |
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/* Don't handle SLEEP mode: we should disable all clocks... |
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* No dynamic power-management. |
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*/ |
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if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0) |
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enter_pm = 1; |
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break; |
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case PPC_FLAGS_EXCP_604: |
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if (msr_pow == 1) |
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enter_pm = 1; |
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break; |
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case PPC_FLAGS_EXCP_7x0: |
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if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0) |
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enter_pm = 1; |
| ... | ... | |
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} |
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} |
| 1173 | 1199 |
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#if defined(TARGET_PPC64) |
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void ppc_store_msr_32 (CPUPPCState *env, target_ulong value) |
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{
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do_store_msr(env, (uint32_t)value); |
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} |
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#endif |
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void do_compute_hflags (CPUPPCState *env) |
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{
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/* Compute current hflags */ |
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env->hflags = (msr_pr << MSR_PR) | (msr_le << MSR_LE) | |
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(msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_fe1 << MSR_FE1) | |
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(msr_vr << MSR_VR) | (msr_ap << MSR_AP) | (msr_sa << MSR_SA) |
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(msr_vr << MSR_VR) | (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | |
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(msr_se << MSR_SE) | (msr_be << MSR_BE); |
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#if defined (TARGET_PPC64) |
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env->hflags |= (msr_sf << MSR_SF) | (msr_hv << MSR_HV);
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env->hflags |= (msr_sf << (MSR_SF - 32)) | (msr_hv << (MSR_HV - 32));
|
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#endif |
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} |
| 1185 | 1218 |
|
| ... | ... | |
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#else /* defined (CONFIG_USER_ONLY) */ |
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static void dump_syscall(CPUState *env) |
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{
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fprintf(logfile, "syscall r0=0x%08x r3=0x%08x r4=0x%08x "
|
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"r5=0x%08x r6=0x%08x nip=0x%08x\n",
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fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX
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" r5=0x" REGX " r6=0x" REGX " nip=0x" REGX "\n",
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env->gpr[0], env->gpr[3], env->gpr[4], |
| 1199 | 1232 |
env->gpr[5], env->gpr[6], env->nip); |
| 1200 | 1233 |
} |
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