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/*
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 *  PowerPC emulation cpu definitions for qemu.
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 * 
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 *  Copyright (c) 2003-2007 Jocelyn Mayer
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#if !defined (__CPU_PPC_H__)
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#define __CPU_PPC_H__
22

    
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#include "config.h"
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#include <stdint.h>
25

    
26
#if defined (TARGET_PPC64)
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typedef uint64_t ppc_gpr_t;
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#define TARGET_LONG_BITS 64
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#define REGX "%016" PRIx64
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#elif defined(TARGET_E500)
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/* GPR are 64 bits: used by vector extension */
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typedef uint64_t ppc_gpr_t;
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#define TARGET_LONG_BITS 32
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#define REGX "%08" PRIx32
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#else
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typedef uint32_t ppc_gpr_t;
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#define TARGET_LONG_BITS 32
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#define REGX "%08" PRIx32
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#endif
40

    
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#include "cpu-defs.h"
42

    
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#include <setjmp.h>
44

    
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#include "softfloat.h"
46

    
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#define TARGET_HAS_ICE 1
48

    
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#if defined (TARGET_PPC64)
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#define ELF_MACHINE     EM_PPC64
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#else
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#define ELF_MACHINE     EM_PPC
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#endif
54

    
55
/* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
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 *                              have different cache line sizes
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 */
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#define ICACHE_LINE_SIZE 32
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#define DCACHE_LINE_SIZE 32
60

    
61
/* XXX: put this in a common place */
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#define likely(x)   __builtin_expect(!!(x), 1)
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#define unlikely(x) __builtin_expect(!!(x), 0)
64

    
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/*****************************************************************************/
66
/* PVR definitions for most known PowerPC */
67
enum {
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    /* PowerPC 401 cores */
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    CPU_PPC_401A1     = 0x00210000,
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    CPU_PPC_401B2     = 0x00220000,
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    CPU_PPC_401C2     = 0x00230000,
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    CPU_PPC_401D2     = 0x00240000,
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    CPU_PPC_401E2     = 0x00250000,
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    CPU_PPC_401F2     = 0x00260000,
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    CPU_PPC_401G2     = 0x00270000,
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#define CPU_PPC_401 CPU_PPC_401G2
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    CPU_PPC_IOP480    = 0x40100000, /* 401B2 ? */
78
    CPU_PPC_COBRA     = 0x10100000, /* IBM Processor for Network Resources */
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    /* PowerPC 403 cores */
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    CPU_PPC_403GA     = 0x00200011,
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    CPU_PPC_403GB     = 0x00200100,
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    CPU_PPC_403GC     = 0x00200200,
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    CPU_PPC_403GCX    = 0x00201400,
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#define CPU_PPC_403 CPU_PPC_403GCX
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    /* PowerPC 405 cores */
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    CPU_PPC_405CR     = 0x40110145,
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#define CPU_PPC_405GP CPU_PPC_405CR
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    CPU_PPC_405EP     = 0x51210950,
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    CPU_PPC_405GPR    = 0x50910951,
90
    CPU_PPC_405D2     = 0x20010000,
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    CPU_PPC_405D4     = 0x41810000,
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#define CPU_PPC_405 CPU_PPC_405D4
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    CPU_PPC_NPE405H   = 0x414100C0,
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    CPU_PPC_NPE405H2  = 0x41410140,
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    CPU_PPC_NPE405L   = 0x416100C0,
96
    /* XXX: missing 405LP, LC77700 */
97
    /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
98
#if 0
99
    CPU_PPC_STB01000  = xxx,
100
#endif
101
#if 0
102
    CPU_PPC_STB01010  = xxx,
103
#endif
104
#if 0
105
    CPU_PPC_STB0210   = xxx,
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#endif
107
    CPU_PPC_STB03     = 0x40310000,
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#if 0
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    CPU_PPC_STB043    = xxx,
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#endif
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#if 0
112
    CPU_PPC_STB045    = xxx,
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#endif
114
    CPU_PPC_STB25     = 0x51510950,
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#if 0
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    CPU_PPC_STB130    = xxx,
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#endif
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    /* Xilinx cores */
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    CPU_PPC_X2VP4     = 0x20010820,
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#define CPU_PPC_X2VP7 CPU_PPC_X2VP4
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    CPU_PPC_X2VP20    = 0x20010860,
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#define CPU_PPC_X2VP50 CPU_PPC_X2VP20
123
    /* PowerPC 440 cores */
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    CPU_PPC_440EP     = 0x422218D3,
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#define CPU_PPC_440GR CPU_PPC_440EP
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    CPU_PPC_440GP     = 0x40120481,
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    CPU_PPC_440GX     = 0x51B21850,
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    CPU_PPC_440GXc    = 0x51B21892,
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    CPU_PPC_440GXf    = 0x51B21894,
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    CPU_PPC_440SP     = 0x53221850,
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    CPU_PPC_440SP2    = 0x53221891,
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    CPU_PPC_440SPE    = 0x53421890,
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    /* XXX: missing 440GRX */
134
    /* PowerPC 460 cores - TODO */
135
    /* PowerPC MPC 5xx cores */
136
    CPU_PPC_5xx       = 0x00020020,
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    /* PowerPC MPC 8xx cores (aka PowerQUICC) */
138
    CPU_PPC_8xx       = 0x00500000,
139
    /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
140
    CPU_PPC_82xx_HIP3 = 0x00810101,
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    CPU_PPC_82xx_HIP4 = 0x80811014,
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    CPU_PPC_827x      = 0x80822013,
143
    /* eCores */
144
    CPU_PPC_e200      = 0x81120000,
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    CPU_PPC_e500v110  = 0x80200010,
146
    CPU_PPC_e500v120  = 0x80200020,
147
    CPU_PPC_e500v210  = 0x80210010,
148
    CPU_PPC_e500v220  = 0x80210020,
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#define CPU_PPC_e500 CPU_PPC_e500v220
150
    CPU_PPC_e600      = 0x80040010,
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    /* PowerPC 6xx cores */
152
    CPU_PPC_601       = 0x00010001,
153
    CPU_PPC_602       = 0x00050100,
154
    CPU_PPC_603       = 0x00030100,
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    CPU_PPC_603E      = 0x00060101,
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    CPU_PPC_603P      = 0x00070000,
157
    CPU_PPC_603E7v    = 0x00070100,
158
    CPU_PPC_603E7v2   = 0x00070201,
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    CPU_PPC_603E7     = 0x00070200,
160
    CPU_PPC_603R      = 0x00071201,
161
    CPU_PPC_G2        = 0x00810011,
162
    CPU_PPC_G2H4      = 0x80811010,
163
    CPU_PPC_G2gp      = 0x80821010,
164
    CPU_PPC_G2ls      = 0x90810010,
165
    CPU_PPC_G2LE      = 0x80820010,
166
    CPU_PPC_G2LEgp    = 0x80822010,
167
    CPU_PPC_G2LEls    = 0xA0822010,
168
    CPU_PPC_604       = 0x00040000,
169
    CPU_PPC_604E      = 0x00090100, /* Also 2110 & 2120 */
170
    CPU_PPC_604R      = 0x000a0101,
171
    /* PowerPC 74x/75x cores (aka G3) */
172
    CPU_PPC_74x       = 0x00080000,
173
    CPU_PPC_740E      = 0x00080100,
174
    CPU_PPC_750E      = 0x00080200,
175
    CPU_PPC_755_10    = 0x00083100,
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    CPU_PPC_755_11    = 0x00083101,
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    CPU_PPC_755_20    = 0x00083200,
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    CPU_PPC_755D      = 0x00083202,
179
    CPU_PPC_755E      = 0x00083203,
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#define CPU_PPC_755 CPU_PPC_755E
181
    CPU_PPC_74xP      = 0x10080000,
182
    CPU_PPC_750CXE21  = 0x00082201,
183
    CPU_PPC_750CXE22  = 0x00082212,
184
    CPU_PPC_750CXE23  = 0x00082203,
185
    CPU_PPC_750CXE24  = 0x00082214,
186
    CPU_PPC_750CXE24b = 0x00083214,
187
    CPU_PPC_750CXE31  = 0x00083211,
188
    CPU_PPC_750CXE31b = 0x00083311,
189
#define CPU_PPC_750CXE CPU_PPC_750CXE31b
190
    CPU_PPC_750CXR    = 0x00083410,
191
    CPU_PPC_750FX10   = 0x70000100,
192
    CPU_PPC_750FX20   = 0x70000200,
193
    CPU_PPC_750FX21   = 0x70000201,
194
    CPU_PPC_750FX22   = 0x70000202,
195
    CPU_PPC_750FX23   = 0x70000203,
196
#define CPU_PPC_750FX CPU_PPC_750FX23
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    CPU_PPC_750FL     = 0x700A0203,
198
    CPU_PPC_750GX10   = 0x70020100,
199
    CPU_PPC_750GX11   = 0x70020101,
200
    CPU_PPC_750GX12   = 0x70020102,
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#define CPU_PPC_750GX CPU_PPC_750GX12
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    CPU_PPC_750GL     = 0x70020102,
203
    CPU_PPC_750L30    = 0x00088300,
204
    CPU_PPC_750L32    = 0x00088302,
205
    CPU_PPC_750CL     = 0x00087200,
206
    /* PowerPC 74xx cores (aka G4) */
207
    CPU_PPC_7400      = 0x000C0100,
208
    CPU_PPC_7410C     = 0x800C1102,
209
    CPU_PPC_7410D     = 0x800C1103,
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    CPU_PPC_7410E     = 0x800C1104,
211
    CPU_PPC_7441      = 0x80000210,
212
    CPU_PPC_7445      = 0x80010100,
213
    CPU_PPC_7447      = 0x80020100,
214
    CPU_PPC_7447A     = 0x80030101,
215
    CPU_PPC_7448      = 0x80040100,
216
    CPU_PPC_7450      = 0x80000200,
217
    CPU_PPC_7450b     = 0x80000201,
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    CPU_PPC_7451      = 0x80000203,
219
    CPU_PPC_7451G     = 0x80000210,
220
    CPU_PPC_7455      = 0x80010201,
221
    CPU_PPC_7455F     = 0x80010303,
222
    CPU_PPC_7455G     = 0x80010304,
223
    CPU_PPC_7457      = 0x80020101,
224
    CPU_PPC_7457C     = 0x80020102,
225
    CPU_PPC_7457A     = 0x80030000,
226
    /* 64 bits PowerPC */
227
    CPU_PPC_620       = 0x00140000,
228
    CPU_PPC_630       = 0x00400000,
229
    CPU_PPC_631       = 0x00410000,
230
    CPU_PPC_POWER4    = 0x00350000,
231
    CPU_PPC_POWER4P   = 0x00380000,
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    CPU_PPC_POWER5    = 0x003A0000,
233
    CPU_PPC_POWER5P   = 0x003B0000,
234
    CPU_PPC_970       = 0x00390000,
235
    CPU_PPC_970FX10   = 0x00391100,
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    CPU_PPC_970FX20   = 0x003C0200,
237
    CPU_PPC_970FX21   = 0x003C0201,
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    CPU_PPC_970FX30   = 0x003C0300,
239
    CPU_PPC_970FX31   = 0x003C0301,
240
#define CPU_PPC_970FX CPU_PPC_970FX31
241
    CPU_PPC_970MP10   = 0x00440100,
242
    CPU_PPC_970MP11   = 0x00440101,
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#define CPU_PPC_970MP CPU_PPC_970MP11
244
    CPU_PPC_CELL10    = 0x00700100,
245
    CPU_PPC_CELL20    = 0x00700400,
246
    CPU_PPC_CELL30    = 0x00700500,
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    CPU_PPC_CELL31    = 0x00700501,
248
#define CPU_PPC_CELL32 CPU_PPC_CELL31
249
#define CPU_PPC_CELL CPU_PPC_CELL32
250
    CPU_PPC_RS64      = 0x00330000,
251
    CPU_PPC_RS64II    = 0x00340000,
252
    CPU_PPC_RS64III   = 0x00360000,
253
    CPU_PPC_RS64IV    = 0x00370000,
254
    /* Original POWER */
255
    /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
256
     * POWER2 (RIOS2) & RSC2 (P2SC) here
257
     */
258
#if 0
259
    CPU_POWER         = xxx,
260
#endif
261
#if 0
262
    CPU_POWER2        = xxx,
263
#endif
264
};
265

    
266
/* System version register (used on MPC 8xxx) */
267
enum {
268
    PPC_SVR_8540      = 0x80300000,
269
    PPC_SVR_8541E     = 0x807A0010,
270
    PPC_SVR_8543v10   = 0x80320010,
271
    PPC_SVR_8543v11   = 0x80320011,
272
    PPC_SVR_8543v20   = 0x80320020,
273
    PPC_SVR_8543Ev10  = 0x803A0010,
274
    PPC_SVR_8543Ev11  = 0x803A0011,
275
    PPC_SVR_8543Ev20  = 0x803A0020,
276
    PPC_SVR_8545      = 0x80310220,
277
    PPC_SVR_8545E     = 0x80390220,
278
    PPC_SVR_8547E     = 0x80390120,
279
    PPC_SCR_8548v10   = 0x80310010,
280
    PPC_SCR_8548v11   = 0x80310011,
281
    PPC_SCR_8548v20   = 0x80310020,
282
    PPC_SVR_8548Ev10  = 0x80390010,
283
    PPC_SVR_8548Ev11  = 0x80390011,
284
    PPC_SVR_8548Ev20  = 0x80390020,
285
    PPC_SVR_8555E     = 0x80790010,
286
    PPC_SVR_8560v10   = 0x80700010,
287
    PPC_SVR_8560v20   = 0x80700020,
288
};
289

    
290
/*****************************************************************************/
291
/* Instruction types */
292
enum {
293
    PPC_NONE        = 0x00000000,
294
    /* integer operations instructions             */
295
    /* flow control instructions                   */
296
    /* virtual memory instructions                 */
297
    /* ld/st with reservation instructions         */
298
    /* cache control instructions                  */
299
    /* spr/msr access instructions                 */
300
    PPC_INSNS_BASE  = 0x00000001,
301
#define PPC_INTEGER PPC_INSNS_BASE
302
#define PPC_FLOW    PPC_INSNS_BASE
303
#define PPC_MEM     PPC_INSNS_BASE
304
#define PPC_RES     PPC_INSNS_BASE
305
#define PPC_CACHE   PPC_INSNS_BASE
306
#define PPC_MISC    PPC_INSNS_BASE
307
    /* floating point operations instructions      */
308
    PPC_FLOAT       = 0x00000002,
309
    /* more floating point operations instructions */
310
    PPC_FLOAT_EXT   = 0x00000004,
311
    /* external control instructions               */
312
    PPC_EXTERN      = 0x00000008,
313
    /* segment register access instructions        */
314
    PPC_SEGMENT     = 0x00000010,
315
    /* Optional cache control instructions         */
316
    PPC_CACHE_OPT   = 0x00000020,
317
    /* Optional floating point op instructions     */
318
    PPC_FLOAT_OPT   = 0x00000040,
319
    /* Optional memory control instructions        */
320
    PPC_MEM_TLBIA   = 0x00000080,
321
    PPC_MEM_TLBIE   = 0x00000100,
322
    PPC_MEM_TLBSYNC = 0x00000200,
323
    /* eieio & sync                                */
324
    PPC_MEM_SYNC    = 0x00000400,
325
    /* PowerPC 6xx TLB management instructions     */
326
    PPC_6xx_TLB     = 0x00000800,
327
    /* Altivec support                             */
328
    PPC_ALTIVEC     = 0x00001000,
329
    /* Time base support                           */
330
    PPC_TB          = 0x00002000,
331
    /* Embedded PowerPC dedicated instructions     */
332
    PPC_EMB_COMMON  = 0x00004000,
333
    /* PowerPC 40x exception model                 */
334
    PPC_40x_EXCP    = 0x00008000,
335
    /* PowerPC 40x specific instructions           */
336
    PPC_40x_SPEC    = 0x00010000,
337
    /* PowerPC 405 Mac instructions                */
338
    PPC_405_MAC     = 0x00020000,
339
    /* PowerPC 440 specific instructions           */
340
    PPC_440_SPEC    = 0x00040000,
341
    /* Specific extensions */
342
    /* Power-to-PowerPC bridge (601)               */
343
    PPC_POWER_BR    = 0x00080000,
344
    /* PowerPC 602 specific */
345
    PPC_602_SPEC    = 0x00100000,
346
    /* Deprecated instructions                     */
347
    /* Original POWER instruction set              */
348
    PPC_POWER       = 0x00200000,
349
    /* POWER2 instruction set extension            */
350
    PPC_POWER2      = 0x00400000,
351
    /* Power RTC support */
352
    PPC_POWER_RTC   = 0x00800000,
353
    /* 64 bits PowerPC instructions                */
354
    /* 64 bits PowerPC instruction set             */
355
    PPC_64B         = 0x01000000,
356
    /* 64 bits hypervisor extensions               */
357
    PPC_64H         = 0x02000000,
358
    /* 64 bits PowerPC "bridge" features           */
359
    PPC_64_BRIDGE   = 0x04000000,
360
    /* BookE (embedded) PowerPC specification      */
361
    PPC_BOOKE       = 0x08000000,
362
    /* eieio */
363
    PPC_MEM_EIEIO   = 0x10000000,
364
    /* e500 vector instructions */
365
    PPC_E500_VECTOR = 0x20000000,
366
    /* PowerPC 4xx dedicated instructions     */
367
    PPC_4xx_COMMON  = 0x40000000,
368
    /* PowerPC 2.03 specification extensions */
369
    PPC_203         = 0x80000000,
370
};
371

    
372
/* CPU run-time flags (MMU and exception model) */
373
enum {
374
    /* MMU model */
375
    PPC_FLAGS_MMU_MASK     = 0x0000000F,
376
    /* Standard 32 bits PowerPC MMU */
377
    PPC_FLAGS_MMU_32B      = 0x00000000,
378
    /* Standard 64 bits PowerPC MMU */
379
    PPC_FLAGS_MMU_64B      = 0x00000001,
380
    /* PowerPC 601 MMU */
381
    PPC_FLAGS_MMU_601      = 0x00000002,
382
    /* PowerPC 6xx MMU with software TLB */
383
    PPC_FLAGS_MMU_SOFT_6xx = 0x00000003,
384
    /* PowerPC 4xx MMU with software TLB */
385
    PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,
386
    /* PowerPC 403 MMU */
387
    PPC_FLAGS_MMU_403      = 0x00000005,
388
    /* Freescale e500 MMU model */
389
    PPC_FLAGS_MMU_e500     = 0x00000006,
390
    /* BookE MMU model */
391
    PPC_FLAGS_MMU_BOOKE    = 0x00000007,
392
    /* Exception model */
393
    PPC_FLAGS_EXCP_MASK    = 0x000000F0,
394
    /* Standard PowerPC exception model */
395
    PPC_FLAGS_EXCP_STD     = 0x00000000,
396
    /* PowerPC 40x exception model */
397
    PPC_FLAGS_EXCP_40x     = 0x00000010,
398
    /* PowerPC 601 exception model */
399
    PPC_FLAGS_EXCP_601     = 0x00000020,
400
    /* PowerPC 602 exception model */
401
    PPC_FLAGS_EXCP_602     = 0x00000030,
402
    /* PowerPC 603 exception model */
403
    PPC_FLAGS_EXCP_603     = 0x00000040,
404
    /* PowerPC 604 exception model */
405
    PPC_FLAGS_EXCP_604     = 0x00000050,
406
    /* PowerPC 7x0 exception model */
407
    PPC_FLAGS_EXCP_7x0     = 0x00000060,
408
    /* PowerPC 7x5 exception model */
409
    PPC_FLAGS_EXCP_7x5     = 0x00000070,
410
    /* PowerPC 74xx exception model */
411
    PPC_FLAGS_EXCP_74xx    = 0x00000080,
412
    /* PowerPC 970 exception model */
413
    PPC_FLAGS_EXCP_970     = 0x00000090,
414
    /* BookE exception model */
415
    PPC_FLAGS_EXCP_BOOKE   = 0x000000A0,
416
};
417

    
418
#define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK)
419
#define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK)
420

    
421
/*****************************************************************************/
422
/* Supported instruction set definitions */
423
/* This generates an empty opcode table... */
424
#define PPC_INSNS_TODO (PPC_NONE)
425
#define PPC_FLAGS_TODO (0x00000000)
426

    
427
/* PowerPC 40x instruction set */
428
#define PPC_INSNS_EMB (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_EMB_COMMON)
429
/* PowerPC 401 */
430
#define PPC_INSNS_401 (PPC_INSNS_TODO)
431
#define PPC_FLAGS_401 (PPC_FLAGS_TODO)
432
/* PowerPC 403 */
433
#define PPC_INSNS_403 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO |         \
434
                       PPC_MEM_TLBIA | PPC_4xx_COMMON | PPC_40x_EXCP |        \
435
                       PPC_40x_SPEC)
436
#define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x)
437
/* PowerPC 405 */
438
#define PPC_INSNS_405 (PPC_INSNS_EMB | PPC_MEM_SYNC | PPC_MEM_EIEIO |         \
439
                       PPC_CACHE_OPT | PPC_MEM_TLBIA | PPC_TB |               \
440
                       PPC_4xx_COMMON | PPC_40x_SPEC |  PPC_40x_EXCP |        \
441
                       PPC_405_MAC)
442
#define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
443
/* PowerPC 440 */
444
#define PPC_INSNS_440 (PPC_INSNS_EMB | PPC_CACHE_OPT | PPC_BOOKE |            \
445
                       PPC_4xx_COMMON | PPC_405_MAC | PPC_440_SPEC)
446
#define PPC_FLAGS_440 (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE)
447
/* Generic BookE PowerPC */
448
#define PPC_INSNS_BOOKE (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO |          \
449
                         PPC_FLOAT | PPC_FLOAT_OPT | PPC_CACHE_OPT)
450
#define PPC_FLAGS_BOOKE (PPC_FLAGS_MMU_BOOKE | PPC_FLAGS_EXCP_BOOKE)
451
/* e500 core */
452
#define PPC_INSNS_E500 (PPC_INSNS_EMB | PPC_BOOKE | PPC_MEM_EIEIO |           \
453
                        PPC_CACHE_OPT | PPC_E500_VECTOR)
454
#define PPC_FLAGS_E500 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
455
/* Non-embedded PowerPC */
456
#define PPC_INSNS_COMMON  (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC |        \
457
                            PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
458
/* PowerPC 601 */
459
#define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)
460
#define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601)
461
/* PowerPC 602 */
462
#define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB |       \
463
                       PPC_MEM_TLBSYNC | PPC_TB | PPC_602_SPEC)
464
#define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602)
465
/* PowerPC 603 */
466
#define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB |       \
467
                       PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
468
#define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
469
/* PowerPC G2 */
470
#define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB |        \
471
                      PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB)
472
#define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
473
/* PowerPC 604 */
474
#define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN |        \
475
                       PPC_MEM_TLBSYNC | PPC_TB)
476
#define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604)
477
/* PowerPC 740/750 (aka G3) */
478
#define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN |        \
479
                       PPC_MEM_TLBSYNC | PPC_TB)
480
#define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0)
481
/* PowerPC 745/755 */
482
#define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN |        \
483
                       PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB)
484
#define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5)
485
/* PowerPC 74xx (aka G4) */
486
#define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC |      \
487
                        PPC_MEM_TLBSYNC | PPC_TB)
488
#define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx)
489

    
490
/* Default PowerPC will be 604/970 */
491
#define PPC_INSNS_PPC32 PPC_INSNS_604
492
#define PPC_FLAGS_PPC32 PPC_FLAGS_604
493
#if 0
494
#define PPC_INSNS_PPC64 PPC_INSNS_970
495
#define PPC_FLAGS_PPC64 PPC_FLAGS_970
496
#endif
497
#define PPC_INSNS_DEFAULT PPC_INSNS_604
498
#define PPC_FLAGS_DEFAULT PPC_FLAGS_604
499
typedef struct ppc_def_t ppc_def_t;
500

    
501
/*****************************************************************************/
502
/* Types used to describe some PowerPC registers */
503
typedef struct CPUPPCState CPUPPCState;
504
typedef struct opc_handler_t opc_handler_t;
505
typedef struct ppc_tb_t ppc_tb_t;
506
typedef struct ppc_spr_t ppc_spr_t;
507
typedef struct ppc_dcr_t ppc_dcr_t;
508
typedef struct ppc_avr_t ppc_avr_t;
509
typedef struct ppc_tlb_t ppc_tlb_t;
510

    
511
/* SPR access micro-ops generations callbacks */
512
struct ppc_spr_t {
513
    void (*uea_read)(void *opaque, int spr_num);
514
    void (*uea_write)(void *opaque, int spr_num);
515
#if !defined(CONFIG_USER_ONLY)
516
    void (*oea_read)(void *opaque, int spr_num);
517
    void (*oea_write)(void *opaque, int spr_num);
518
#endif
519
    const unsigned char *name;
520
};
521

    
522
/* Altivec registers (128 bits) */
523
struct ppc_avr_t {
524
    uint32_t u[4];
525
};
526

    
527
/* Software TLB cache */
528
struct ppc_tlb_t {
529
    target_ulong pte0;
530
    target_ulong pte1;
531
    target_ulong EPN;
532
    target_ulong PID;
533
    int size;
534
};
535

    
536
/*****************************************************************************/
537
/* Machine state register bits definition                                    */
538
#define MSR_SF   63 /* Sixty-four-bit mode                            hflags */
539
#define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */
540
#define MSR_HV   60 /* hypervisor state                               hflags */
541
#define MSR_UCLE 26 /* User-mode cache lock enable on e500                   */
542
#define MSR_VR   25 /* altivec available                              hflags */
543
#define MSR_SPE  25 /* SPE enable on e500                             hflags */
544
#define MSR_AP   23 /* Access privilege state on 602                  hflags */
545
#define MSR_SA   22 /* Supervisor access mode on 602                  hflags */
546
#define MSR_KEY  19 /* key bit on 603e                                       */
547
#define MSR_POW  18 /* Power management                                      */
548
#define MSR_WE   18 /* Wait state enable on embedded PowerPC                 */
549
#define MSR_TGPR 17 /* TGPR usage on 602/603                                 */
550
#define MSR_TLB  17 /* TLB update on ?                                       */
551
#define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC         */
552
#define MSR_ILE  16 /* Interrupt little-endian mode                          */
553
#define MSR_EE   15 /* External interrupt enable                             */
554
#define MSR_PR   14 /* Problem state                                  hflags */
555
#define MSR_FP   13 /* Floating point available                       hflags */
556
#define MSR_ME   12 /* Machine check interrupt enable                        */
557
#define MSR_FE0  11 /* Floating point exception mode 0                hflags */
558
#define MSR_SE   10 /* Single-step trace enable                       hflags */
559
#define MSR_DWE  10 /* Debug wait enable on 405                              */
560
#define MSR_UBLE 10 /* User BTB lock enable on e500                          */
561
#define MSR_BE   9  /* Branch trace enable                            hflags */
562
#define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC           */
563
#define MSR_FE1  8  /* Floating point exception mode 1                hflags */
564
#define MSR_AL   7  /* AL bit on POWER                                       */
565
#define MSR_IP   6  /* Interrupt prefix                                      */
566
#define MSR_IR   5  /* Instruction relocate                                  */
567
#define MSR_IS   5  /* Instruction address space on embedded PowerPC         */
568
#define MSR_DR   4  /* Data relocate                                         */
569
#define MSR_DS   4  /* Data address space on embedded PowerPC                */
570
#define MSR_PE   3  /* Protection enable on 403                              */
571
#define MSR_EP   3  /* Exception prefix on 601                               */
572
#define MSR_PX   2  /* Protection exclusive on 403                           */
573
#define MSR_PMM  2  /* Performance monitor mark on POWER                     */
574
#define MSR_RI   1  /* Recoverable interrupt                                 */
575
#define MSR_LE   0  /* Little-endian mode                             hflags */
576
#define msr_sf   env->msr[MSR_SF]
577
#define msr_isf  env->msr[MSR_ISF]
578
#define msr_hv   env->msr[MSR_HV]
579
#define msr_ucle env->msr[MSR_UCLE]
580
#define msr_vr   env->msr[MSR_VR]
581
#define msr_spe  env->msr[MSR_SPE]
582
#define msr_ap   env->msr[MSR_AP]
583
#define msr_sa   env->msr[MSR_SA]
584
#define msr_key  env->msr[MSR_KEY]
585
#define msr_pow  env->msr[MSR_POW]
586
#define msr_we   env->msr[MSR_WE]
587
#define msr_tgpr env->msr[MSR_TGPR]
588
#define msr_tlb  env->msr[MSR_TLB]
589
#define msr_ce   env->msr[MSR_CE]
590
#define msr_ile  env->msr[MSR_ILE]
591
#define msr_ee   env->msr[MSR_EE]
592
#define msr_pr   env->msr[MSR_PR]
593
#define msr_fp   env->msr[MSR_FP]
594
#define msr_me   env->msr[MSR_ME]
595
#define msr_fe0  env->msr[MSR_FE0]
596
#define msr_se   env->msr[MSR_SE]
597
#define msr_dwe  env->msr[MSR_DWE]
598
#define msr_uble env->msr[MSR_UBLE]
599
#define msr_be   env->msr[MSR_BE]
600
#define msr_de   env->msr[MSR_DE]
601
#define msr_fe1  env->msr[MSR_FE1]
602
#define msr_al   env->msr[MSR_AL]
603
#define msr_ip   env->msr[MSR_IP]
604
#define msr_ir   env->msr[MSR_IR]
605
#define msr_is   env->msr[MSR_IS]
606
#define msr_dr   env->msr[MSR_DR]
607
#define msr_ds   env->msr[MSR_DS]
608
#define msr_pe   env->msr[MSR_PE]
609
#define msr_ep   env->msr[MSR_EP]
610
#define msr_px   env->msr[MSR_PX]
611
#define msr_pmm  env->msr[MSR_PMM]
612
#define msr_ri   env->msr[MSR_RI]
613
#define msr_le   env->msr[MSR_LE]
614

    
615
/*****************************************************************************/
616
/* The whole PowerPC CPU context */
617
struct CPUPPCState {
618
    /* First are the most commonly used resources
619
     * during translated code execution
620
     */
621
#if TARGET_LONG_BITS > HOST_LONG_BITS
622
    /* temporary fixed-point registers
623
     * used to emulate 64 bits target on 32 bits hosts
624
     */
625
    target_ulong t0, t1, t2;
626
#endif
627
    ppc_avr_t t0_avr, t1_avr, t2_avr;
628

    
629
    /* general purpose registers */
630
    ppc_gpr_t gpr[32];
631
    /* LR */
632
    target_ulong lr;
633
    /* CTR */
634
    target_ulong ctr;
635
    /* condition register */
636
    uint8_t crf[8];
637
    /* XER */
638
    /* XXX: We use only 5 fields, but we want to keep the structure aligned */
639
    uint8_t xer[8];
640
    /* Reservation address */
641
    target_ulong reserve;
642

    
643
    /* Those ones are used in supervisor mode only */
644
    /* machine state register */
645
    uint8_t msr[64];
646
    /* temporary general purpose registers */
647
    ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */
648

    
649
    /* Floating point execution context */
650
    /* temporary float registers */
651
    float64 ft0;
652
    float64 ft1;
653
    float64 ft2;
654
    float_status fp_status;
655
    /* floating point registers */
656
    float64 fpr[32];
657
    /* floating point status and control register */
658
    uint8_t fpscr[8];
659

    
660
    CPU_COMMON
661

    
662
    int halted; /* TRUE if the CPU is in suspend state */
663

    
664
    int access_type; /* when a memory exception occurs, the access
665
                        type is stored here */
666

    
667
    /* MMU context */
668
    /* Address space register */
669
    target_ulong asr;
670
    /* segment registers */
671
    target_ulong sdr1;
672
    target_ulong sr[16];
673
    /* BATs */
674
    int nb_BATs;
675
    target_ulong DBAT[2][8];
676
    target_ulong IBAT[2][8];
677

    
678
    /* Other registers */
679
    /* Special purpose registers */
680
    target_ulong spr[1024];
681
    /* Altivec registers */
682
    ppc_avr_t avr[32];
683
    uint32_t vscr;
684
    /* SPE registers */
685
    ppc_gpr_t spe_acc;
686
    uint32_t spe_fscr;
687

    
688
    /* Internal devices resources */
689
    /* Time base and decrementer */
690
    ppc_tb_t *tb_env;
691
    /* Device control registers */
692
    int (*dcr_read)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong *val);
693
    int (*dcr_write)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong val);
694
    ppc_dcr_t *dcr_env;
695

    
696
    /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
697
    int nb_tlb;      /* Total number of TLB                                  */
698
    int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
699
    int nb_ways;     /* Number of ways in the TLB set                        */
700
    int last_way;    /* Last used way used to allocate TLB in a LRU way      */
701
    int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */
702
    ppc_tlb_t *tlb;  /* TLB is optional. Allocate them only if needed        */
703
    /* Callbacks for specific checks on some implementations */
704
    int (*tlb_check_more)(CPUPPCState *env, struct ppc_tlb_t *tlb, int *prot,
705
                          target_ulong vaddr, int rw, int acc_type,
706
                          int is_user);
707
    /* 403 dedicated access protection registers */
708
    target_ulong pb[4];
709

    
710
    /* Those resources are used during exception processing */
711
    /* CPU model definition */
712
    uint64_t msr_mask;
713
    uint32_t flags;
714

    
715
    int exception_index;
716
    int error_code;
717
    int interrupt_request;
718

    
719
    /* Those resources are used only during code translation */
720
    /* Next instruction pointer */
721
    target_ulong nip;
722
    /* SPR translation callbacks */
723
    ppc_spr_t spr_cb[1024];
724
    /* opcode handlers */
725
    opc_handler_t *opcodes[0x40];
726

    
727
    /* Those resources are used only in Qemu core */
728
    jmp_buf jmp_env;
729
    int user_mode_only; /* user mode only simulation */
730
    uint32_t hflags;
731

    
732
    /* Power management */
733
    int power_mode;
734

    
735
    /* temporary hack to handle OSI calls (only used if non NULL) */
736
    int (*osi_call)(struct CPUPPCState *env);
737
};
738

    
739
/* Context used internally during MMU translations */
740
typedef struct mmu_ctx_t mmu_ctx_t;
741
struct mmu_ctx_t {
742
    target_phys_addr_t raddr;      /* Real address              */
743
    int prot;                      /* Protection bits           */
744
    target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */
745
    target_ulong ptem;             /* Virtual segment ID | API  */
746
    int key;                       /* Access key                */
747
};
748

    
749
/*****************************************************************************/
750
CPUPPCState *cpu_ppc_init(void);
751
int cpu_ppc_exec(CPUPPCState *s);
752
void cpu_ppc_close(CPUPPCState *s);
753
/* you can call this signal handler from your SIGBUS and SIGSEGV
754
   signal handlers to inform the virtual CPU of exceptions. non zero
755
   is returned if the signal was handled by the virtual CPU.  */
756
int cpu_ppc_signal_handler(int host_signum, void *pinfo, 
757
                           void *puc);
758

    
759
void do_interrupt (CPUPPCState *env);
760
void cpu_loop_exit(void);
761

    
762
void dump_stack (CPUPPCState *env);
763

    
764
#if !defined(CONFIG_USER_ONLY)
765
target_ulong do_load_ibatu (CPUPPCState *env, int nr);
766
target_ulong do_load_ibatl (CPUPPCState *env, int nr);
767
void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value);
768
void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value);
769
target_ulong do_load_dbatu (CPUPPCState *env, int nr);
770
target_ulong do_load_dbatl (CPUPPCState *env, int nr);
771
void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value);
772
void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value);
773
target_ulong do_load_sdr1 (CPUPPCState *env);
774
void do_store_sdr1 (CPUPPCState *env, target_ulong value);
775
#if defined(TARGET_PPC64)
776
target_ulong ppc_load_asr (CPUPPCState *env);
777
void ppc_store_asr (CPUPPCState *env, target_ulong value);
778
#endif
779
target_ulong do_load_sr (CPUPPCState *env, int srnum);
780
void do_store_sr (CPUPPCState *env, int srnum, target_ulong value);
781
#endif
782
uint32_t ppc_load_xer (CPUPPCState *env);
783
void ppc_store_xer (CPUPPCState *env, uint32_t value);
784
target_ulong do_load_msr (CPUPPCState *env);
785
void do_store_msr (CPUPPCState *env, target_ulong value);
786
void ppc_store_msr32 (CPUPPCState *env, uint32_t value);
787

    
788
void do_compute_hflags (CPUPPCState *env);
789

    
790
int ppc_find_by_name (const unsigned char *name, ppc_def_t **def);
791
int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
792
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
793
int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
794

    
795
/* Time-base and decrementer management */
796
#ifndef NO_CPU_IO_DEFS
797
uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
798
uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
799
void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
800
void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
801
uint32_t cpu_ppc_load_decr (CPUPPCState *env);
802
void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
803
uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
804
uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
805
#if !defined(CONFIG_USER_ONLY)
806
void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
807
void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
808
target_ulong load_40x_pit (CPUPPCState *env);
809
void store_40x_pit (CPUPPCState *env, target_ulong val);
810
void store_booke_tcr (CPUPPCState *env, target_ulong val);
811
void store_booke_tsr (CPUPPCState *env, target_ulong val);
812
#endif
813
#endif
814

    
815
#define TARGET_PAGE_BITS 12
816
#include "cpu-all.h"
817

    
818
/*****************************************************************************/
819
/* Registers definitions */
820
#define ugpr(n) (env->gpr[n])
821

    
822
#define XER_SO 31
823
#define XER_OV 30
824
#define XER_CA 29
825
#define XER_CMP 8
826
#define XER_BC 0
827
#define xer_so  env->xer[4]
828
#define xer_ov  env->xer[6]
829
#define xer_ca  env->xer[2]
830
#define xer_cmp env->xer[1]
831
#define xer_bc env->xer[0]
832

    
833
/* SPR definitions */
834
#define SPR_MQ           (0x000)
835
#define SPR_XER          (0x001)
836
#define SPR_601_VRTCU    (0x004)
837
#define SPR_601_VRTCL    (0x005)
838
#define SPR_601_UDECR    (0x006)
839
#define SPR_LR           (0x008)
840
#define SPR_CTR          (0x009)
841
#define SPR_DSISR        (0x012)
842
#define SPR_DAR          (0x013)
843
#define SPR_601_RTCU     (0x014)
844
#define SPR_601_RTCL     (0x015)
845
#define SPR_DECR         (0x016)
846
#define SPR_SDR1         (0x019)
847
#define SPR_SRR0         (0x01A)
848
#define SPR_SRR1         (0x01B)
849
#define SPR_BOOKE_PID    (0x030)
850
#define SPR_BOOKE_DECAR  (0x036)
851
#define SPR_CSRR0        (0x03A)
852
#define SPR_CSRR1        (0x03B)
853
#define SPR_BOOKE_DEAR   (0x03D)
854
#define SPR_BOOKE_ESR    (0x03E)
855
#define SPR_BOOKE_EVPR   (0x03F)
856
#define SPR_8xx_EIE      (0x050)
857
#define SPR_8xx_EID      (0x051)
858
#define SPR_8xx_NRE      (0x052)
859
#define SPR_58x_CMPA     (0x090)
860
#define SPR_58x_CMPB     (0x091)
861
#define SPR_58x_CMPC     (0x092)
862
#define SPR_58x_CMPD     (0x093)
863
#define SPR_58x_ICR      (0x094)
864
#define SPR_58x_DER      (0x094)
865
#define SPR_58x_COUNTA   (0x096)
866
#define SPR_58x_COUNTB   (0x097)
867
#define SPR_58x_CMPE     (0x098)
868
#define SPR_58x_CMPF     (0x099)
869
#define SPR_58x_CMPG     (0x09A)
870
#define SPR_58x_CMPH     (0x09B)
871
#define SPR_58x_LCTRL1   (0x09C)
872
#define SPR_58x_LCTRL2   (0x09D)
873
#define SPR_58x_ICTRL    (0x09E)
874
#define SPR_58x_BAR      (0x09F)
875
#define SPR_VRSAVE       (0x100)
876
#define SPR_USPRG0       (0x100)
877
#define SPR_USPRG4       (0x104)
878
#define SPR_USPRG5       (0x105)
879
#define SPR_USPRG6       (0x106)
880
#define SPR_USPRG7       (0x107)
881
#define SPR_VTBL         (0x10C)
882
#define SPR_VTBU         (0x10D)
883
#define SPR_SPRG0        (0x110)
884
#define SPR_SPRG1        (0x111)
885
#define SPR_SPRG2        (0x112)
886
#define SPR_SPRG3        (0x113)
887
#define SPR_SPRG4        (0x114)
888
#define SPR_SCOMC        (0x114)
889
#define SPR_SPRG5        (0x115)
890
#define SPR_SCOMD        (0x115)
891
#define SPR_SPRG6        (0x116)
892
#define SPR_SPRG7        (0x117)
893
#define SPR_ASR          (0x118)
894
#define SPR_EAR          (0x11A)
895
#define SPR_TBL          (0x11C)
896
#define SPR_TBU          (0x11D)
897
#define SPR_SVR          (0x11E)
898
#define SPR_BOOKE_PIR    (0x11E)
899
#define SPR_PVR          (0x11F)
900
#define SPR_HSPRG0       (0x130)
901
#define SPR_BOOKE_DBSR   (0x130)
902
#define SPR_HSPRG1       (0x131)
903
#define SPR_BOOKE_DBCR0  (0x134)
904
#define SPR_IBCR         (0x135)
905
#define SPR_BOOKE_DBCR1  (0x135)
906
#define SPR_DBCR         (0x136)
907
#define SPR_HDEC         (0x136)
908
#define SPR_BOOKE_DBCR2  (0x136)
909
#define SPR_HIOR         (0x137)
910
#define SPR_MBAR         (0x137)
911
#define SPR_RMOR         (0x138)
912
#define SPR_BOOKE_IAC1   (0x138)
913
#define SPR_HRMOR        (0x139)
914
#define SPR_BOOKE_IAC2   (0x139)
915
#define SPR_HSSR0        (0x13A)
916
#define SPR_BOOKE_IAC3   (0x13A)
917
#define SPR_HSSR1        (0x13B)
918
#define SPR_BOOKE_IAC4   (0x13B)
919
#define SPR_LPCR         (0x13C)
920
#define SPR_BOOKE_DAC1   (0x13C)
921
#define SPR_LPIDR        (0x13D)
922
#define SPR_DABR2        (0x13D)
923
#define SPR_BOOKE_DAC2   (0x13D)
924
#define SPR_BOOKE_DVC1   (0x13E)
925
#define SPR_BOOKE_DVC2   (0x13F)
926
#define SPR_BOOKE_TSR    (0x150)
927
#define SPR_BOOKE_TCR    (0x154)
928
#define SPR_BOOKE_IVOR0  (0x190)
929
#define SPR_BOOKE_IVOR1  (0x191)
930
#define SPR_BOOKE_IVOR2  (0x192)
931
#define SPR_BOOKE_IVOR3  (0x193)
932
#define SPR_BOOKE_IVOR4  (0x194)
933
#define SPR_BOOKE_IVOR5  (0x195)
934
#define SPR_BOOKE_IVOR6  (0x196)
935
#define SPR_BOOKE_IVOR7  (0x197)
936
#define SPR_BOOKE_IVOR8  (0x198)
937
#define SPR_BOOKE_IVOR9  (0x199)
938
#define SPR_BOOKE_IVOR10 (0x19A)
939
#define SPR_BOOKE_IVOR11 (0x19B)
940
#define SPR_BOOKE_IVOR12 (0x19C)
941
#define SPR_BOOKE_IVOR13 (0x19D)
942
#define SPR_BOOKE_IVOR14 (0x19E)
943
#define SPR_BOOKE_IVOR15 (0x19F)
944
#define SPR_E500_SPEFSCR (0x200)
945
#define SPR_E500_BBEAR   (0x201)
946
#define SPR_E500_BBTAR   (0x202)
947
#define SPR_BOOKE_ATBL   (0x20E)
948
#define SPR_BOOKE_ATBU   (0x20F)
949
#define SPR_IBAT0U       (0x210)
950
#define SPR_E500_IVOR32  (0x210)
951
#define SPR_IBAT0L       (0x211)
952
#define SPR_E500_IVOR33  (0x211)
953
#define SPR_IBAT1U       (0x212)
954
#define SPR_E500_IVOR34  (0x212)
955
#define SPR_IBAT1L       (0x213)
956
#define SPR_E500_IVOR35  (0x213)
957
#define SPR_IBAT2U       (0x214)
958
#define SPR_IBAT2L       (0x215)
959
#define SPR_E500_L1CFG0  (0x215)
960
#define SPR_IBAT3U       (0x216)
961
#define SPR_E500_L1CFG1  (0x216)
962
#define SPR_IBAT3L       (0x217)
963
#define SPR_DBAT0U       (0x218)
964
#define SPR_DBAT0L       (0x219)
965
#define SPR_DBAT1U       (0x21A)
966
#define SPR_DBAT1L       (0x21B)
967
#define SPR_DBAT2U       (0x21C)
968
#define SPR_DBAT2L       (0x21D)
969
#define SPR_DBAT3U       (0x21E)
970
#define SPR_DBAT3L       (0x21F)
971
#define SPR_IBAT4U       (0x230)
972
#define SPR_IBAT4L       (0x231)
973
#define SPR_IBAT5U       (0x232)
974
#define SPR_IBAT5L       (0x233)
975
#define SPR_IBAT6U       (0x234)
976
#define SPR_IBAT6L       (0x235)
977
#define SPR_IBAT7U       (0x236)
978
#define SPR_IBAT7L       (0x237)
979
#define SPR_DBAT4U       (0x238)
980
#define SPR_DBAT4L       (0x239)
981
#define SPR_DBAT5U       (0x23A)
982
#define SPR_E500_MCSRR0  (0x23A)
983
#define SPR_DBAT5L       (0x23B)
984
#define SPR_E500_MCSRR1  (0x23B)
985
#define SPR_DBAT6U       (0x23C)
986
#define SPR_E500_MCSR    (0x23C)
987
#define SPR_DBAT6L       (0x23D)
988
#define SPR_E500_MCAR    (0x23D)
989
#define SPR_DBAT7U       (0x23E)
990
#define SPR_DBAT7L       (0x23F)
991
#define SPR_E500_MAS0    (0x270)
992
#define SPR_E500_MAS1    (0x271)
993
#define SPR_E500_MAS2    (0x272)
994
#define SPR_E500_MAS3    (0x273)
995
#define SPR_E500_MAS4    (0x274)
996
#define SPR_E500_MAS6    (0x276)
997
#define SPR_E500_PID1    (0x279)
998
#define SPR_E500_PID2    (0x27A)
999
#define SPR_E500_TLB0CFG (0x2B0)
1000
#define SPR_E500_TLB1CFG (0x2B1)
1001
#define SPR_440_INV0     (0x370)
1002
#define SPR_440_INV1     (0x371)
1003
#define SPR_440_INV2     (0x372)
1004
#define SPR_440_INV3     (0x373)
1005
#define SPR_440_IVT0     (0x374)
1006
#define SPR_440_IVT1     (0x375)
1007
#define SPR_440_IVT2     (0x376)
1008
#define SPR_440_IVT3     (0x377)
1009
#define SPR_440_DNV0     (0x390)
1010
#define SPR_440_DNV1     (0x391)
1011
#define SPR_440_DNV2     (0x392)
1012
#define SPR_440_DNV3     (0x393)
1013
#define SPR_440_DVT0     (0x394)
1014
#define SPR_440_DVT1     (0x395)
1015
#define SPR_440_DVT2     (0x396)
1016
#define SPR_440_DVT3     (0x397)
1017
#define SPR_440_DVLIM    (0x398)
1018
#define SPR_440_IVLIM    (0x399)
1019
#define SPR_440_RSTCFG   (0x39B)
1020
#define SPR_440_DCBTRL   (0x39C)
1021
#define SPR_440_DCBTRH   (0x39D)
1022
#define SPR_440_ICBTRL   (0x39E)
1023
#define SPR_440_ICBTRH   (0x39F)
1024
#define SPR_UMMCR0       (0x3A8)
1025
#define SPR_UPMC1        (0x3A9)
1026
#define SPR_UPMC2        (0x3AA)
1027
#define SPR_USIA         (0x3AB)
1028
#define SPR_UMMCR1       (0x3AC)
1029
#define SPR_UPMC3        (0x3AD)
1030
#define SPR_UPMC4        (0x3AE)
1031
#define SPR_USDA         (0x3AF)
1032
#define SPR_40x_ZPR      (0x3B0)
1033
#define SPR_E500_MAS7    (0x3B0)
1034
#define SPR_40x_PID      (0x3B1)
1035
#define SPR_440_MMUCR    (0x3B2)
1036
#define SPR_4xx_CCR0     (0x3B3)
1037
#define SPR_405_IAC3     (0x3B4)
1038
#define SPR_405_IAC4     (0x3B5)
1039
#define SPR_405_DVC1     (0x3B6)
1040
#define SPR_405_DVC2     (0x3B7)
1041
#define SPR_MMCR0        (0x3B8)
1042
#define SPR_PMC1         (0x3B9)
1043
#define SPR_40x_SGR      (0x3B9)
1044
#define SPR_PMC2         (0x3BA)
1045
#define SPR_40x_DCWR     (0x3BA)
1046
#define SPR_SIA          (0x3BB)
1047
#define SPR_405_SLER     (0x3BB)
1048
#define SPR_MMCR1        (0x3BC)
1049
#define SPR_405_SU0R     (0x3BC)
1050
#define SPR_PMC3         (0x3BD)
1051
#define SPR_405_DBCR1    (0x3BD)
1052
#define SPR_PMC4         (0x3BE)
1053
#define SPR_SDA          (0x3BF)
1054
#define SPR_403_VTBL     (0x3CC)
1055
#define SPR_403_VTBU     (0x3CD)
1056
#define SPR_DMISS        (0x3D0)
1057
#define SPR_DCMP         (0x3D1)
1058
#define SPR_HASH1        (0x3D2)
1059
#define SPR_HASH2        (0x3D3)
1060
#define SPR_4xx_ICDBDR   (0x3D3)
1061
#define SPR_IMISS        (0x3D4)
1062
#define SPR_40x_ESR      (0x3D4)
1063
#define SPR_ICMP         (0x3D5)
1064
#define SPR_40x_DEAR     (0x3D5)
1065
#define SPR_RPA          (0x3D6)
1066
#define SPR_40x_EVPR     (0x3D6)
1067
#define SPR_403_CDBCR    (0x3D7)
1068
#define SPR_TCR          (0x3D8)
1069
#define SPR_40x_TSR      (0x3D8)
1070
#define SPR_IBR          (0x3DA)
1071
#define SPR_40x_TCR      (0x3DA)
1072
#define SPR_ESASR        (0x3DB)
1073
#define SPR_40x_PIT      (0x3DB)
1074
#define SPR_403_TBL      (0x3DC)
1075
#define SPR_403_TBU      (0x3DD)
1076
#define SPR_SEBR         (0x3DE)
1077
#define SPR_40x_SRR2     (0x3DE)
1078
#define SPR_SER          (0x3DF)
1079
#define SPR_40x_SRR3     (0x3DF)
1080
#define SPR_HID0         (0x3F0)
1081
#define SPR_40x_DBSR     (0x3F0)
1082
#define SPR_HID1         (0x3F1)
1083
#define SPR_IABR         (0x3F2)
1084
#define SPR_40x_DBCR0    (0x3F2)
1085
#define SPR_601_HID2     (0x3F2)
1086
#define SPR_E500_L1CSR0  (0x3F2)
1087
#define SPR_HID2         (0x3F3)
1088
#define SPR_E500_L1CSR1  (0x3F3)
1089
#define SPR_440_DBDR     (0x3F3)
1090
#define SPR_40x_IAC1     (0x3F4)
1091
#define SPR_E500_MMUCSR0 (0x3F4)
1092
#define SPR_DABR         (0x3F5)
1093
#define DABR_MASK (~(target_ulong)0x7)
1094
#define SPR_E500_BUCSR   (0x3F5)
1095
#define SPR_40x_IAC2     (0x3F5)
1096
#define SPR_601_HID5     (0x3F5)
1097
#define SPR_40x_DAC1     (0x3F6)
1098
#define SPR_40x_DAC2     (0x3F7)
1099
#define SPR_E500_MMUCFG  (0x3F7)
1100
#define SPR_L2PM         (0x3F8)
1101
#define SPR_750_HID2     (0x3F8)
1102
#define SPR_L2CR         (0x3F9)
1103
#define SPR_IABR2        (0x3FA)
1104
#define SPR_40x_DCCR     (0x3FA)
1105
#define SPR_ICTC         (0x3FB)
1106
#define SPR_40x_ICCR     (0x3FB)
1107
#define SPR_THRM1        (0x3FC)
1108
#define SPR_403_PBL1     (0x3FC)
1109
#define SPR_SP           (0x3FD)
1110
#define SPR_THRM2        (0x3FD)
1111
#define SPR_403_PBU1     (0x3FD)
1112
#define SPR_LT           (0x3FE)
1113
#define SPR_THRM3        (0x3FE)
1114
#define SPR_FPECR        (0x3FE)
1115
#define SPR_403_PBL2     (0x3FE)
1116
#define SPR_PIR          (0x3FF)
1117
#define SPR_403_PBU2     (0x3FF)
1118
#define SPR_601_HID15    (0x3FF)
1119
#define SPR_E500_SVR     (0x3FF)
1120

    
1121
/*****************************************************************************/
1122
/* Memory access type :
1123
 * may be needed for precise access rights control and precise exceptions.
1124
 */
1125
enum {
1126
    /* 1 bit to define user level / supervisor access */
1127
    ACCESS_USER  = 0x00,
1128
    ACCESS_SUPER = 0x01,
1129
    /* Type of instruction that generated the access */
1130
    ACCESS_CODE  = 0x10, /* Code fetch access                */
1131
    ACCESS_INT   = 0x20, /* Integer load/store access        */
1132
    ACCESS_FLOAT = 0x30, /* floating point load/store access */
1133
    ACCESS_RES   = 0x40, /* load/store with reservation      */
1134
    ACCESS_EXT   = 0x50, /* external access                  */
1135
    ACCESS_CACHE = 0x60, /* Cache manipulation               */
1136
};
1137

    
1138
/*****************************************************************************/
1139
/* Exceptions */
1140
#define EXCP_NONE          -1
1141
/* PowerPC hardware exceptions : exception vectors defined in PowerPC book 3 */
1142
#define EXCP_RESET         0x0100 /* System reset                            */
1143
#define EXCP_MACHINE_CHECK 0x0200 /* Machine check exception                 */
1144
#define EXCP_DSI           0x0300 /* Data storage exception                  */
1145
#define EXCP_DSEG          0x0380 /* Data segment exception                  */
1146
#define EXCP_ISI           0x0400 /* Instruction storage exception           */
1147
#define EXCP_ISEG          0x0480 /* Instruction segment exception           */
1148
#define EXCP_EXTERNAL      0x0500 /* External interruption                   */
1149
#define EXCP_ALIGN         0x0600 /* Alignment exception                     */
1150
#define EXCP_PROGRAM       0x0700 /* Program exception                       */
1151
#define EXCP_NO_FP         0x0800 /* Floating point unavailable exception    */
1152
#define EXCP_DECR          0x0900 /* Decrementer exception                   */
1153
#define EXCP_HDECR         0x0980 /* Hypervisor decrementer exception        */
1154
#define EXCP_SYSCALL       0x0C00 /* System call                             */
1155
#define EXCP_TRACE         0x0D00 /* Trace exception                         */
1156
#define EXCP_PERF          0x0F00 /* Performance monitor exception           */
1157
/* Exceptions defined in PowerPC 32 bits programming environment manual      */
1158
#define EXCP_FP_ASSIST     0x0E00 /* Floating-point assist                   */
1159
/* Implementation specific exceptions                                        */
1160
/* 40x exceptions                                                            */
1161
#define EXCP_40x_PIT       0x1000 /* Programmable interval timer interrupt   */
1162
#define EXCP_40x_FIT       0x1010 /* Fixed interval timer interrupt          */
1163
#define EXCP_40x_WATCHDOG  0x1020 /* Watchdog timer exception                */
1164
#define EXCP_40x_DTLBMISS  0x1100 /* Data TLB miss exception                 */
1165
#define EXCP_40x_ITLBMISS  0x1200 /* Instruction TLB miss exception          */
1166
#define EXCP_40x_DEBUG     0x2000 /* Debug exception                         */
1167
/* 405 specific exceptions                                                   */
1168
#define EXCP_405_APU       0x0F20 /* APU unavailable exception               */
1169
/* TLB assist exceptions (602/603)                                           */
1170
#define EXCP_I_TLBMISS     0x1000 /* Instruction TLB miss                    */
1171
#define EXCP_DL_TLBMISS    0x1100 /* Data load TLB miss                      */
1172
#define EXCP_DS_TLBMISS    0x1200 /* Data store TLB miss                     */
1173
/* Breakpoint exceptions (602/603/604/620/740/745/750/755...)                */
1174
#define EXCP_IABR          0x1300 /* Instruction address breakpoint          */
1175
#define EXCP_SMI           0x1400 /* System management interrupt             */
1176
/* Altivec related exceptions                                                */
1177
#define EXCP_VPU           0x0F20 /* VPU unavailable exception               */
1178
/* 601 specific exceptions                                                   */
1179
#define EXCP_601_IO        0x0600 /* IO error exception                      */
1180
#define EXCP_601_RUNM      0x2000 /* Run mode exception                      */
1181
/* 602 specific exceptions                                                   */
1182
#define EXCP_602_WATCHDOG  0x1500 /* Watchdog exception                      */
1183
#define EXCP_602_EMUL      0x1600 /* Emulation trap exception                */
1184
/* G2 specific exceptions                                                    */
1185
#define EXCP_G2_CRIT       0x0A00 /* Critical interrupt                      */
1186
/* MPC740/745/750 & IBM 750 specific exceptions                              */
1187
#define EXCP_THRM          0x1700 /* Thermal management interrupt            */
1188
/* 74xx specific exceptions                                                  */
1189
#define EXCP_74xx_VPUA     0x1600 /* VPU assist exception                    */
1190
/* 970FX specific exceptions                                                 */
1191
#define EXCP_970_SOFTP     0x1500 /* Soft patch exception                    */
1192
#define EXCP_970_MAINT     0x1600 /* Maintenance exception                   */
1193
#define EXCP_970_THRM      0x1800 /* Thermal exception                       */
1194
#define EXCP_970_VPUA      0x1700 /* VPU assist exception                    */
1195
/* End of exception vectors area                                             */
1196
#define EXCP_PPC_MAX       0x4000
1197
/* Qemu exceptions: special cases we want to stop translation                */
1198
#define EXCP_MTMSR         0x11000 /* mtmsr instruction:                     */
1199
                                   /* may change privilege level             */
1200
#define EXCP_BRANCH        0x11001 /* branch instruction                     */
1201
#define EXCP_SYSCALL_USER  0x12000 /* System call in user mode only          */
1202
#define EXCP_INTERRUPT_CRITICAL 0x13000 /* critical IRQ                      */
1203

    
1204
/* Error codes */
1205
enum {
1206
    /* Exception subtypes for EXCP_ALIGN                            */
1207
    EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception           */
1208
    EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store */
1209
    EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access    */
1210
    EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary */
1211
    EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary  */
1212
    EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access           */
1213
    /* Exception subtypes for EXCP_PROGRAM                          */
1214
    /* FP exceptions */
1215
    EXCP_FP            = 0x10,
1216
    EXCP_FP_OX         = 0x01,  /* FP overflow                      */
1217
    EXCP_FP_UX         = 0x02,  /* FP underflow                     */
1218
    EXCP_FP_ZX         = 0x03,  /* FP divide by zero                */
1219
    EXCP_FP_XX         = 0x04,  /* FP inexact                       */
1220
    EXCP_FP_VXNAN      = 0x05,  /* FP invalid SNaN op               */
1221
    EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite substraction */
1222
    EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide       */
1223
    EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide           */
1224
    EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero       */
1225
    EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare               */
1226
    EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation             */
1227
    EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root           */
1228
    EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion    */
1229
    /* Invalid instruction */
1230
    EXCP_INVAL         = 0x20,
1231
    EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction              */
1232
    EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction         */
1233
    EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access               */
1234
    EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr */
1235
    /* Privileged instruction */
1236
    EXCP_PRIV          = 0x30,
1237
    EXCP_PRIV_OPC      = 0x01,
1238
    EXCP_PRIV_REG      = 0x02,
1239
    /* Trap */
1240
    EXCP_TRAP          = 0x40,
1241
};
1242

    
1243
/*****************************************************************************/
1244

    
1245
#endif /* !defined (__CPU_PPC_H__) */