| 67 |
67 |
}
|
| 68 |
68 |
#endif
|
| 69 |
69 |
|
| 70 |
|
target_ulong helper_clo (target_ulong t0)
|
|
70 |
target_ulong helper_clo (target_ulong arg1)
|
| 71 |
71 |
{
|
| 72 |
|
return clo32(t0);
|
|
72 |
return clo32(arg1);
|
| 73 |
73 |
}
|
| 74 |
74 |
|
| 75 |
|
target_ulong helper_clz (target_ulong t0)
|
|
75 |
target_ulong helper_clz (target_ulong arg1)
|
| 76 |
76 |
{
|
| 77 |
|
return clz32(t0);
|
|
77 |
return clz32(arg1);
|
| 78 |
78 |
}
|
| 79 |
79 |
|
| 80 |
80 |
#if defined(TARGET_MIPS64)
|
| 81 |
|
target_ulong helper_dclo (target_ulong t0)
|
|
81 |
target_ulong helper_dclo (target_ulong arg1)
|
| 82 |
82 |
{
|
| 83 |
|
return clo64(t0);
|
|
83 |
return clo64(arg1);
|
| 84 |
84 |
}
|
| 85 |
85 |
|
| 86 |
|
target_ulong helper_dclz (target_ulong t0)
|
|
86 |
target_ulong helper_dclz (target_ulong arg1)
|
| 87 |
87 |
{
|
| 88 |
|
return clz64(t0);
|
|
88 |
return clz64(arg1);
|
| 89 |
89 |
}
|
| 90 |
90 |
#endif /* TARGET_MIPS64 */
|
| 91 |
91 |
|
| ... | ... | |
| 101 |
101 |
env->active_tc.HI[0] = (int32_t)(HILO >> 32);
|
| 102 |
102 |
}
|
| 103 |
103 |
|
| 104 |
|
static inline void set_HIT0_LO (target_ulong t0, uint64_t HILO)
|
|
104 |
static inline void set_HIT0_LO (target_ulong arg1, uint64_t HILO)
|
| 105 |
105 |
{
|
| 106 |
106 |
env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
|
| 107 |
|
t0 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
|
|
107 |
arg1 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
|
| 108 |
108 |
}
|
| 109 |
109 |
|
| 110 |
|
static inline void set_HI_LOT0 (target_ulong t0, uint64_t HILO)
|
|
110 |
static inline void set_HI_LOT0 (target_ulong arg1, uint64_t HILO)
|
| 111 |
111 |
{
|
| 112 |
|
t0 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
|
|
112 |
arg1 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
|
| 113 |
113 |
env->active_tc.HI[0] = (int32_t)(HILO >> 32);
|
| 114 |
114 |
}
|
| 115 |
115 |
|
| 116 |
116 |
/* Multiplication variants of the vr54xx. */
|
| 117 |
|
target_ulong helper_muls (target_ulong t0, target_ulong t1)
|
|
117 |
target_ulong helper_muls (target_ulong arg1, target_ulong arg2)
|
| 118 |
118 |
{
|
| 119 |
|
set_HI_LOT0(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
|
|
119 |
set_HI_LOT0(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
|
| 120 |
120 |
|
| 121 |
|
return t0;
|
|
121 |
return arg1;
|
| 122 |
122 |
}
|
| 123 |
123 |
|
| 124 |
|
target_ulong helper_mulsu (target_ulong t0, target_ulong t1)
|
|
124 |
target_ulong helper_mulsu (target_ulong arg1, target_ulong arg2)
|
| 125 |
125 |
{
|
| 126 |
|
set_HI_LOT0(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
|
|
126 |
set_HI_LOT0(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
|
| 127 |
127 |
|
| 128 |
|
return t0;
|
|
128 |
return arg1;
|
| 129 |
129 |
}
|
| 130 |
130 |
|
| 131 |
|
target_ulong helper_macc (target_ulong t0, target_ulong t1)
|
|
131 |
target_ulong helper_macc (target_ulong arg1, target_ulong arg2)
|
| 132 |
132 |
{
|
| 133 |
|
set_HI_LOT0(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
|
|
133 |
set_HI_LOT0(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
|
| 134 |
134 |
|
| 135 |
|
return t0;
|
|
135 |
return arg1;
|
| 136 |
136 |
}
|
| 137 |
137 |
|
| 138 |
|
target_ulong helper_macchi (target_ulong t0, target_ulong t1)
|
|
138 |
target_ulong helper_macchi (target_ulong arg1, target_ulong arg2)
|
| 139 |
139 |
{
|
| 140 |
|
set_HIT0_LO(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
|
|
140 |
set_HIT0_LO(arg1, ((int64_t)get_HILO()) + ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
|
| 141 |
141 |
|
| 142 |
|
return t0;
|
|
142 |
return arg1;
|
| 143 |
143 |
}
|
| 144 |
144 |
|
| 145 |
|
target_ulong helper_maccu (target_ulong t0, target_ulong t1)
|
|
145 |
target_ulong helper_maccu (target_ulong arg1, target_ulong arg2)
|
| 146 |
146 |
{
|
| 147 |
|
set_HI_LOT0(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
|
|
147 |
set_HI_LOT0(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
|
| 148 |
148 |
|
| 149 |
|
return t0;
|
|
149 |
return arg1;
|
| 150 |
150 |
}
|
| 151 |
151 |
|
| 152 |
|
target_ulong helper_macchiu (target_ulong t0, target_ulong t1)
|
|
152 |
target_ulong helper_macchiu (target_ulong arg1, target_ulong arg2)
|
| 153 |
153 |
{
|
| 154 |
|
set_HIT0_LO(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
|
|
154 |
set_HIT0_LO(arg1, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
|
| 155 |
155 |
|
| 156 |
|
return t0;
|
|
156 |
return arg1;
|
| 157 |
157 |
}
|
| 158 |
158 |
|
| 159 |
|
target_ulong helper_msac (target_ulong t0, target_ulong t1)
|
|
159 |
target_ulong helper_msac (target_ulong arg1, target_ulong arg2)
|
| 160 |
160 |
{
|
| 161 |
|
set_HI_LOT0(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
|
|
161 |
set_HI_LOT0(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
|
| 162 |
162 |
|
| 163 |
|
return t0;
|
|
163 |
return arg1;
|
| 164 |
164 |
}
|
| 165 |
165 |
|
| 166 |
|
target_ulong helper_msachi (target_ulong t0, target_ulong t1)
|
|
166 |
target_ulong helper_msachi (target_ulong arg1, target_ulong arg2)
|
| 167 |
167 |
{
|
| 168 |
|
set_HIT0_LO(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
|
|
168 |
set_HIT0_LO(arg1, ((int64_t)get_HILO()) - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
|
| 169 |
169 |
|
| 170 |
|
return t0;
|
|
170 |
return arg1;
|
| 171 |
171 |
}
|
| 172 |
172 |
|
| 173 |
|
target_ulong helper_msacu (target_ulong t0, target_ulong t1)
|
|
173 |
target_ulong helper_msacu (target_ulong arg1, target_ulong arg2)
|
| 174 |
174 |
{
|
| 175 |
|
set_HI_LOT0(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
|
|
175 |
set_HI_LOT0(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
|
| 176 |
176 |
|
| 177 |
|
return t0;
|
|
177 |
return arg1;
|
| 178 |
178 |
}
|
| 179 |
179 |
|
| 180 |
|
target_ulong helper_msachiu (target_ulong t0, target_ulong t1)
|
|
180 |
target_ulong helper_msachiu (target_ulong arg1, target_ulong arg2)
|
| 181 |
181 |
{
|
| 182 |
|
set_HIT0_LO(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
|
|
182 |
set_HIT0_LO(arg1, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
|
| 183 |
183 |
|
| 184 |
|
return t0;
|
|
184 |
return arg1;
|
| 185 |
185 |
}
|
| 186 |
186 |
|
| 187 |
|
target_ulong helper_mulhi (target_ulong t0, target_ulong t1)
|
|
187 |
target_ulong helper_mulhi (target_ulong arg1, target_ulong arg2)
|
| 188 |
188 |
{
|
| 189 |
|
set_HIT0_LO(t0, (int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
|
|
189 |
set_HIT0_LO(arg1, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
|
| 190 |
190 |
|
| 191 |
|
return t0;
|
|
191 |
return arg1;
|
| 192 |
192 |
}
|
| 193 |
193 |
|
| 194 |
|
target_ulong helper_mulhiu (target_ulong t0, target_ulong t1)
|
|
194 |
target_ulong helper_mulhiu (target_ulong arg1, target_ulong arg2)
|
| 195 |
195 |
{
|
| 196 |
|
set_HIT0_LO(t0, (uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
|
|
196 |
set_HIT0_LO(arg1, (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
|
| 197 |
197 |
|
| 198 |
|
return t0;
|
|
198 |
return arg1;
|
| 199 |
199 |
}
|
| 200 |
200 |
|
| 201 |
|
target_ulong helper_mulshi (target_ulong t0, target_ulong t1)
|
|
201 |
target_ulong helper_mulshi (target_ulong arg1, target_ulong arg2)
|
| 202 |
202 |
{
|
| 203 |
|
set_HIT0_LO(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
|
|
203 |
set_HIT0_LO(arg1, 0 - ((int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2));
|
| 204 |
204 |
|
| 205 |
|
return t0;
|
|
205 |
return arg1;
|
| 206 |
206 |
}
|
| 207 |
207 |
|
| 208 |
|
target_ulong helper_mulshiu (target_ulong t0, target_ulong t1)
|
|
208 |
target_ulong helper_mulshiu (target_ulong arg1, target_ulong arg2)
|
| 209 |
209 |
{
|
| 210 |
|
set_HIT0_LO(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
|
|
210 |
set_HIT0_LO(arg1, 0 - ((uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2));
|
| 211 |
211 |
|
| 212 |
|
return t0;
|
|
212 |
return arg1;
|
| 213 |
213 |
}
|
| 214 |
214 |
|
| 215 |
215 |
#ifdef TARGET_MIPS64
|
| 216 |
|
void helper_dmult (target_ulong t0, target_ulong t1)
|
|
216 |
void helper_dmult (target_ulong arg1, target_ulong arg2)
|
| 217 |
217 |
{
|
| 218 |
|
muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1);
|
|
218 |
muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
|
| 219 |
219 |
}
|
| 220 |
220 |
|
| 221 |
|
void helper_dmultu (target_ulong t0, target_ulong t1)
|
|
221 |
void helper_dmultu (target_ulong arg1, target_ulong arg2)
|
| 222 |
222 |
{
|
| 223 |
|
mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1);
|
|
223 |
mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
|
| 224 |
224 |
}
|
| 225 |
225 |
#endif
|
| 226 |
226 |
|
| ... | ... | |
| 232 |
232 |
#define GET_OFFSET(addr, offset) (addr - (offset))
|
| 233 |
233 |
#endif
|
| 234 |
234 |
|
| 235 |
|
target_ulong helper_lwl(target_ulong t0, target_ulong t1, int mem_idx)
|
|
235 |
target_ulong helper_lwl(target_ulong arg1, target_ulong arg2, int mem_idx)
|
| 236 |
236 |
{
|
| 237 |
237 |
target_ulong tmp;
|
| 238 |
238 |
|
| ... | ... | |
| 249 |
249 |
case 2: ldfun = ldub_user; break;
|
| 250 |
250 |
}
|
| 251 |
251 |
#endif
|
| 252 |
|
tmp = ldfun(t0);
|
| 253 |
|
t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
|
|
252 |
tmp = ldfun(arg2);
|
|
253 |
arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
|
| 254 |
254 |
|
| 255 |
|
if (GET_LMASK(t0) <= 2) {
|
| 256 |
|
tmp = ldfun(GET_OFFSET(t0, 1));
|
| 257 |
|
t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
|
|
255 |
if (GET_LMASK(arg2) <= 2) {
|
|
256 |
tmp = ldfun(GET_OFFSET(arg2, 1));
|
|
257 |
arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
|
| 258 |
258 |
}
|
| 259 |
259 |
|
| 260 |
|
if (GET_LMASK(t0) <= 1) {
|
| 261 |
|
tmp = ldfun(GET_OFFSET(t0, 2));
|
| 262 |
|
t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
|
|
260 |
if (GET_LMASK(arg2) <= 1) {
|
|
261 |
tmp = ldfun(GET_OFFSET(arg2, 2));
|
|
262 |
arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
|
| 263 |
263 |
}
|
| 264 |
264 |
|
| 265 |
|
if (GET_LMASK(t0) == 0) {
|
| 266 |
|
tmp = ldfun(GET_OFFSET(t0, 3));
|
| 267 |
|
t1 = (t1 & 0xFFFFFF00) | tmp;
|
|
265 |
if (GET_LMASK(arg2) == 0) {
|
|
266 |
tmp = ldfun(GET_OFFSET(arg2, 3));
|
|
267 |
arg1 = (arg1 & 0xFFFFFF00) | tmp;
|
| 268 |
268 |
}
|
| 269 |
|
return (int32_t)t1;
|
|
269 |
return (int32_t)arg1;
|
| 270 |
270 |
}
|
| 271 |
271 |
|
| 272 |
|
target_ulong helper_lwr(target_ulong t0, target_ulong t1, int mem_idx)
|
|
272 |
target_ulong helper_lwr(target_ulong arg1, target_ulong arg2, int mem_idx)
|
| 273 |
273 |
{
|
| 274 |
274 |
target_ulong tmp;
|
| 275 |
275 |
|
| ... | ... | |
| 286 |
286 |
case 2: ldfun = ldub_user; break;
|
| 287 |
287 |
}
|
| 288 |
288 |
#endif
|
| 289 |
|
tmp = ldfun(t0);
|
| 290 |
|
t1 = (t1 & 0xFFFFFF00) | tmp;
|
|
289 |
tmp = ldfun(arg2);
|
|
290 |
arg1 = (arg1 & 0xFFFFFF00) | tmp;
|
| 291 |
291 |
|
| 292 |
|
if (GET_LMASK(t0) >= 1) {
|
| 293 |
|
tmp = ldfun(GET_OFFSET(t0, -1));
|
| 294 |
|
t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
|
|
292 |
if (GET_LMASK(arg2) >= 1) {
|
|
293 |
tmp = ldfun(GET_OFFSET(arg2, -1));
|
|
294 |
arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8);
|
| 295 |
295 |
}
|
| 296 |
296 |
|
| 297 |
|
if (GET_LMASK(t0) >= 2) {
|
| 298 |
|
tmp = ldfun(GET_OFFSET(t0, -2));
|
| 299 |
|
t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
|
|
297 |
if (GET_LMASK(arg2) >= 2) {
|
|
298 |
tmp = ldfun(GET_OFFSET(arg2, -2));
|
|
299 |
arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16);
|
| 300 |
300 |
}
|
| 301 |
301 |
|
| 302 |
|
if (GET_LMASK(t0) == 3) {
|
| 303 |
|
tmp = ldfun(GET_OFFSET(t0, -3));
|
| 304 |
|
t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
|
|
302 |
if (GET_LMASK(arg2) == 3) {
|
|
303 |
tmp = ldfun(GET_OFFSET(arg2, -3));
|
|
304 |
arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24);
|
| 305 |
305 |
}
|
| 306 |
|
return (int32_t)t1;
|
|
306 |
return (int32_t)arg1;
|
| 307 |
307 |
}
|
| 308 |
308 |
|
| 309 |
|
void helper_swl(target_ulong t0, target_ulong t1, int mem_idx)
|
|
309 |
void helper_swl(target_ulong arg1, target_ulong arg2, int mem_idx)
|
| 310 |
310 |
{
|
| 311 |
311 |
#ifdef CONFIG_USER_ONLY
|
| 312 |
312 |
#define stfun stb_raw
|
| ... | ... | |
| 321 |
321 |
case 2: stfun = stb_user; break;
|
| 322 |
322 |
}
|
| 323 |
323 |
#endif
|
| 324 |
|
stfun(t0, (uint8_t)(t1 >> 24));
|
|
324 |
stfun(arg2, (uint8_t)(arg1 >> 24));
|
| 325 |
325 |
|
| 326 |
|
if (GET_LMASK(t0) <= 2)
|
| 327 |
|
stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 16));
|
|
326 |
if (GET_LMASK(arg2) <= 2)
|
|
327 |
stfun(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16));
|
| 328 |
328 |
|
| 329 |
|
if (GET_LMASK(t0) <= 1)
|
| 330 |
|
stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 8));
|
|
329 |
if (GET_LMASK(arg2) <= 1)
|
|
330 |
stfun(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8));
|
| 331 |
331 |
|
| 332 |
|
if (GET_LMASK(t0) == 0)
|
| 333 |
|
stfun(GET_OFFSET(t0, 3), (uint8_t)t1);
|
|
332 |
if (GET_LMASK(arg2) == 0)
|
|
333 |
stfun(GET_OFFSET(arg2, 3), (uint8_t)arg1);
|
| 334 |
334 |
}
|
| 335 |
335 |
|
| 336 |
|
void helper_swr(target_ulong t0, target_ulong t1, int mem_idx)
|
|
336 |
void helper_swr(target_ulong arg1, target_ulong arg2, int mem_idx)
|
| 337 |
337 |
{
|
| 338 |
338 |
#ifdef CONFIG_USER_ONLY
|
| 339 |
339 |
#define stfun stb_raw
|
| ... | ... | |
| 348 |
348 |
case 2: stfun = stb_user; break;
|
| 349 |
349 |
}
|
| 350 |
350 |
#endif
|
| 351 |
|
stfun(t0, (uint8_t)t1);
|
|
351 |
stfun(arg2, (uint8_t)arg1);
|
| 352 |
352 |
|
| 353 |
|
if (GET_LMASK(t0) >= 1)
|
| 354 |
|
stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
|
|
353 |
if (GET_LMASK(arg2) >= 1)
|
|
354 |
stfun(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8));
|
| 355 |
355 |
|
| 356 |
|
if (GET_LMASK(t0) >= 2)
|
| 357 |
|
stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
|
|
356 |
if (GET_LMASK(arg2) >= 2)
|
|
357 |
stfun(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16));
|
| 358 |
358 |
|
| 359 |
|
if (GET_LMASK(t0) == 3)
|
| 360 |
|
stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
|
|
359 |
if (GET_LMASK(arg2) == 3)
|
|
360 |
stfun(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24));
|
| 361 |
361 |
}
|
| 362 |
362 |
|
| 363 |
363 |
#if defined(TARGET_MIPS64)
|
| ... | ... | |
| 370 |
370 |
#define GET_LMASK64(v) (((v) & 7) ^ 7)
|
| 371 |
371 |
#endif
|
| 372 |
372 |
|
| 373 |
|
target_ulong helper_ldl(target_ulong t0, target_ulong t1, int mem_idx)
|
|
373 |
target_ulong helper_ldl(target_ulong arg1, target_ulong arg2, int mem_idx)
|
| 374 |
374 |
{
|
| 375 |
375 |
uint64_t tmp;
|
| 376 |
376 |
|
| ... | ... | |
| 387 |
387 |
case 2: ldfun = ldub_user; break;
|
| 388 |
388 |
}
|
| 389 |
389 |
#endif
|
| 390 |
|
tmp = ldfun(t0);
|
| 391 |
|
t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
|
|
390 |
tmp = ldfun(arg2);
|
|
391 |
arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
|
| 392 |
392 |
|
| 393 |
|
if (GET_LMASK64(t0) <= 6) {
|
| 394 |
|
tmp = ldfun(GET_OFFSET(t0, 1));
|
| 395 |
|
t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
|
|
393 |
if (GET_LMASK64(arg2) <= 6) {
|
|
394 |
tmp = ldfun(GET_OFFSET(arg2, 1));
|
|
395 |
arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
|
| 396 |
396 |
}
|
| 397 |
397 |
|
| 398 |
|
if (GET_LMASK64(t0) <= 5) {
|
| 399 |
|
tmp = ldfun(GET_OFFSET(t0, 2));
|
| 400 |
|
t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
|
|
398 |
if (GET_LMASK64(arg2) <= 5) {
|
|
399 |
tmp = ldfun(GET_OFFSET(arg2, 2));
|
|
400 |
arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
|
| 401 |
401 |
}
|
| 402 |
402 |
|
| 403 |
|
if (GET_LMASK64(t0) <= 4) {
|
| 404 |
|
tmp = ldfun(GET_OFFSET(t0, 3));
|
| 405 |
|
t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
|
|
403 |
if (GET_LMASK64(arg2) <= 4) {
|
|
404 |
tmp = ldfun(GET_OFFSET(arg2, 3));
|
|
405 |
arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
|
| 406 |
406 |
}
|
| 407 |
407 |
|
| 408 |
|
if (GET_LMASK64(t0) <= 3) {
|
| 409 |
|
tmp = ldfun(GET_OFFSET(t0, 4));
|
| 410 |
|
t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
|
|
408 |
if (GET_LMASK64(arg2) <= 3) {
|
|
409 |
tmp = ldfun(GET_OFFSET(arg2, 4));
|
|
410 |
arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
|
| 411 |
411 |
}
|
| 412 |
412 |
|
| 413 |
|
if (GET_LMASK64(t0) <= 2) {
|
| 414 |
|
tmp = ldfun(GET_OFFSET(t0, 5));
|
| 415 |
|
t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
|
|
413 |
if (GET_LMASK64(arg2) <= 2) {
|
|
414 |
tmp = ldfun(GET_OFFSET(arg2, 5));
|
|
415 |
arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
|
| 416 |
416 |
}
|
| 417 |
417 |
|
| 418 |
|
if (GET_LMASK64(t0) <= 1) {
|
| 419 |
|
tmp = ldfun(GET_OFFSET(t0, 6));
|
| 420 |
|
t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
|
|
418 |
if (GET_LMASK64(arg2) <= 1) {
|
|
419 |
tmp = ldfun(GET_OFFSET(arg2, 6));
|
|
420 |
arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
|
| 421 |
421 |
}
|
| 422 |
422 |
|
| 423 |
|
if (GET_LMASK64(t0) == 0) {
|
| 424 |
|
tmp = ldfun(GET_OFFSET(t0, 7));
|
| 425 |
|
t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
|
|
423 |
if (GET_LMASK64(arg2) == 0) {
|
|
424 |
tmp = ldfun(GET_OFFSET(arg2, 7));
|
|
425 |
arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
|
| 426 |
426 |
}
|
| 427 |
427 |
|
| 428 |
|
return t1;
|
|
428 |
return arg1;
|
| 429 |
429 |
}
|
| 430 |
430 |
|
| 431 |
|
target_ulong helper_ldr(target_ulong t0, target_ulong t1, int mem_idx)
|
|
431 |
target_ulong helper_ldr(target_ulong arg1, target_ulong arg2, int mem_idx)
|
| 432 |
432 |
{
|
| 433 |
433 |
uint64_t tmp;
|
| 434 |
434 |
|
| ... | ... | |
| 445 |
445 |
case 2: ldfun = ldub_user; break;
|
| 446 |
446 |
}
|
| 447 |
447 |
#endif
|
| 448 |
|
tmp = ldfun(t0);
|
| 449 |
|
t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
|
|
448 |
tmp = ldfun(arg2);
|
|
449 |
arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
|
| 450 |
450 |
|
| 451 |
|
if (GET_LMASK64(t0) >= 1) {
|
| 452 |
|
tmp = ldfun(GET_OFFSET(t0, -1));
|
| 453 |
|
t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
|
|
451 |
if (GET_LMASK64(arg2) >= 1) {
|
|
452 |
tmp = ldfun(GET_OFFSET(arg2, -1));
|
|
453 |
arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
|
| 454 |
454 |
}
|
| 455 |
455 |
|
| 456 |
|
if (GET_LMASK64(t0) >= 2) {
|
| 457 |
|
tmp = ldfun(GET_OFFSET(t0, -2));
|
| 458 |
|
t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
|
|
456 |
if (GET_LMASK64(arg2) >= 2) {
|
|
457 |
tmp = ldfun(GET_OFFSET(arg2, -2));
|
|
458 |
arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
|
| 459 |
459 |
}
|
| 460 |
460 |
|
| 461 |
|
if (GET_LMASK64(t0) >= 3) {
|
| 462 |
|
tmp = ldfun(GET_OFFSET(t0, -3));
|
| 463 |
|
t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
|
|
461 |
if (GET_LMASK64(arg2) >= 3) {
|
|
462 |
tmp = ldfun(GET_OFFSET(arg2, -3));
|
|
463 |
arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
|
| 464 |
464 |
}
|
| 465 |
465 |
|
| 466 |
|
if (GET_LMASK64(t0) >= 4) {
|
| 467 |
|
tmp = ldfun(GET_OFFSET(t0, -4));
|
| 468 |
|
t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
|
|
466 |
if (GET_LMASK64(arg2) >= 4) {
|
|
467 |
tmp = ldfun(GET_OFFSET(arg2, -4));
|
|
468 |
arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
|
| 469 |
469 |
}
|
| 470 |
470 |
|
| 471 |
|
if (GET_LMASK64(t0) >= 5) {
|
| 472 |
|
tmp = ldfun(GET_OFFSET(t0, -5));
|
| 473 |
|
t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
|
|
471 |
if (GET_LMASK64(arg2) >= 5) {
|
|
472 |
tmp = ldfun(GET_OFFSET(arg2, -5));
|
|
473 |
arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
|
| 474 |
474 |
}
|
| 475 |
475 |
|
| 476 |
|
if (GET_LMASK64(t0) >= 6) {
|
| 477 |
|
tmp = ldfun(GET_OFFSET(t0, -6));
|
| 478 |
|
t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
|
|
476 |
if (GET_LMASK64(arg2) >= 6) {
|
|
477 |
tmp = ldfun(GET_OFFSET(arg2, -6));
|
|
478 |
arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
|
| 479 |
479 |
}
|
| 480 |
480 |
|
| 481 |
|
if (GET_LMASK64(t0) == 7) {
|
| 482 |
|
tmp = ldfun(GET_OFFSET(t0, -7));
|
| 483 |
|
t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
|
|
481 |
if (GET_LMASK64(arg2) == 7) {
|
|
482 |
tmp = ldfun(GET_OFFSET(arg2, -7));
|
|
483 |
arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
|
| 484 |
484 |
}
|
| 485 |
485 |
|
| 486 |
|
return t1;
|
|
486 |
return arg1;
|
| 487 |
487 |
}
|
| 488 |
488 |
|
| 489 |
|
void helper_sdl(target_ulong t0, target_ulong t1, int mem_idx)
|
|
489 |
void helper_sdl(target_ulong arg1, target_ulong arg2, int mem_idx)
|
| 490 |
490 |
{
|
| 491 |
491 |
#ifdef CONFIG_USER_ONLY
|
| 492 |
492 |
#define stfun stb_raw
|
| ... | ... | |
| 501 |
501 |
case 2: stfun = stb_user; break;
|
| 502 |
502 |
}
|
| 503 |
503 |
#endif
|
| 504 |
|
stfun(t0, (uint8_t)(t1 >> 56));
|
|
504 |
stfun(arg2, (uint8_t)(arg1 >> 56));
|
| 505 |
505 |
|
| 506 |
|
if (GET_LMASK64(t0) <= 6)
|
| 507 |
|
stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 48));
|
|
506 |
if (GET_LMASK64(arg2) <= 6)
|
|
507 |
stfun(GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48));
|
| 508 |
508 |
|
| 509 |
|
if (GET_LMASK64(t0) <= 5)
|
| 510 |
|
stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 40));
|
|
509 |
if (GET_LMASK64(arg2) <= 5)
|
|
510 |
stfun(GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40));
|
| 511 |
511 |
|
| 512 |
|
if (GET_LMASK64(t0) <= 4)
|
| 513 |
|
stfun(GET_OFFSET(t0, 3), (uint8_t)(t1 >> 32));
|
|
512 |
if (GET_LMASK64(arg2) <= 4)
|
|
513 |
stfun(GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32));
|
| 514 |
514 |
|
| 515 |
|
if (GET_LMASK64(t0) <= 3)
|
| 516 |
|
stfun(GET_OFFSET(t0, 4), (uint8_t)(t1 >> 24));
|
|
515 |
if (GET_LMASK64(arg2) <= 3)
|
|
516 |
stfun(GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24));
|
| 517 |
517 |
|
| 518 |
|
if (GET_LMASK64(t0) <= 2)
|
| 519 |
|
stfun(GET_OFFSET(t0, 5), (uint8_t)(t1 >> 16));
|
|
518 |
if (GET_LMASK64(arg2) <= 2)
|
|
519 |
stfun(GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16));
|
| 520 |
520 |
|
| 521 |
|
if (GET_LMASK64(t0) <= 1)
|
| 522 |
|
stfun(GET_OFFSET(t0, 6), (uint8_t)(t1 >> 8));
|
|
521 |
if (GET_LMASK64(arg2) <= 1)
|
|
522 |
stfun(GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8));
|
| 523 |
523 |
|
| 524 |
|
if (GET_LMASK64(t0) <= 0)
|
| 525 |
|
stfun(GET_OFFSET(t0, 7), (uint8_t)t1);
|
|
524 |
if (GET_LMASK64(arg2) <= 0)
|
|
525 |
stfun(GET_OFFSET(arg2, 7), (uint8_t)arg1);
|
| 526 |
526 |
}
|
| 527 |
527 |
|
| 528 |
|
void helper_sdr(target_ulong t0, target_ulong t1, int mem_idx)
|
|
528 |
void helper_sdr(target_ulong arg1, target_ulong arg2, int mem_idx)
|
| 529 |
529 |
{
|
| 530 |
530 |
#ifdef CONFIG_USER_ONLY
|
| 531 |
531 |
#define stfun stb_raw
|
| ... | ... | |
| 540 |
540 |
case 2: stfun = stb_user; break;
|
| 541 |
541 |
}
|
| 542 |
542 |
#endif
|
| 543 |
|
stfun(t0, (uint8_t)t1);
|
|
543 |
stfun(arg2, (uint8_t)arg1);
|
| 544 |
544 |
|
| 545 |
|
if (GET_LMASK64(t0) >= 1)
|
| 546 |
|
stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
|
|
545 |
if (GET_LMASK64(arg2) >= 1)
|
|
546 |
stfun(GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8));
|
| 547 |
547 |
|
| 548 |
|
if (GET_LMASK64(t0) >= 2)
|
| 549 |
|
stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
|
|
548 |
if (GET_LMASK64(arg2) >= 2)
|
|
549 |
stfun(GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16));
|
| 550 |
550 |
|
| 551 |
|
if (GET_LMASK64(t0) >= 3)
|
| 552 |
|
stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
|
|
551 |
if (GET_LMASK64(arg2) >= 3)
|
|
552 |
stfun(GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24));
|
| 553 |
553 |
|
| 554 |
|
if (GET_LMASK64(t0) >= 4)
|
| 555 |
|
stfun(GET_OFFSET(t0, -4), (uint8_t)(t1 >> 32));
|
|
554 |
if (GET_LMASK64(arg2) >= 4)
|
|
555 |
stfun(GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32));
|
| 556 |
556 |
|
| 557 |
|
if (GET_LMASK64(t0) >= 5)
|
| 558 |
|
stfun(GET_OFFSET(t0, -5), (uint8_t)(t1 >> 40));
|
|
557 |
if (GET_LMASK64(arg2) >= 5)
|
|
558 |
stfun(GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40));
|
| 559 |
559 |
|
| 560 |
|
if (GET_LMASK64(t0) >= 6)
|
| 561 |
|
stfun(GET_OFFSET(t0, -6), (uint8_t)(t1 >> 48));
|
|
560 |
if (GET_LMASK64(arg2) >= 6)
|
|
561 |
stfun(GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48));
|
| 562 |
562 |
|
| 563 |
|
if (GET_LMASK64(t0) == 7)
|
| 564 |
|
stfun(GET_OFFSET(t0, -7), (uint8_t)(t1 >> 56));
|
|
563 |
if (GET_LMASK64(arg2) == 7)
|
|
564 |
stfun(GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56));
|
| 565 |
565 |
}
|
| 566 |
566 |
#endif /* TARGET_MIPS64 */
|
| 567 |
567 |
|
| ... | ... | |
| 805 |
805 |
}
|
| 806 |
806 |
#endif /* TARGET_MIPS64 */
|
| 807 |
807 |
|
| 808 |
|
void helper_mtc0_index (target_ulong t0)
|
|
808 |
void helper_mtc0_index (target_ulong arg1)
|
| 809 |
809 |
{
|
| 810 |
810 |
int num = 1;
|
| 811 |
811 |
unsigned int tmp = env->tlb->nb_tlb;
|
| ... | ... | |
| 814 |
814 |
tmp >>= 1;
|
| 815 |
815 |
num <<= 1;
|
| 816 |
816 |
} while (tmp);
|
| 817 |
|
env->CP0_Index = (env->CP0_Index & 0x80000000) | (t0 & (num - 1));
|
|
817 |
env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
|
| 818 |
818 |
}
|
| 819 |
819 |
|
| 820 |
|
void helper_mtc0_mvpcontrol (target_ulong t0)
|
|
820 |
void helper_mtc0_mvpcontrol (target_ulong arg1)
|
| 821 |
821 |
{
|
| 822 |
822 |
uint32_t mask = 0;
|
| 823 |
823 |
uint32_t newval;
|
| ... | ... | |
| 827 |
827 |
(1 << CP0MVPCo_EVP);
|
| 828 |
828 |
if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
|
| 829 |
829 |
mask |= (1 << CP0MVPCo_STLB);
|
| 830 |
|
newval = (env->mvp->CP0_MVPControl & ~mask) | (t0 & mask);
|
|
830 |
newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
|
| 831 |
831 |
|
| 832 |
832 |
// TODO: Enable/disable shared TLB, enable/disable VPEs.
|
| 833 |
833 |
|
| 834 |
834 |
env->mvp->CP0_MVPControl = newval;
|
| 835 |
835 |
}
|
| 836 |
836 |
|
| 837 |
|
void helper_mtc0_vpecontrol (target_ulong t0)
|
|
837 |
void helper_mtc0_vpecontrol (target_ulong arg1)
|
| 838 |
838 |
{
|
| 839 |
839 |
uint32_t mask;
|
| 840 |
840 |
uint32_t newval;
|
| 841 |
841 |
|
| 842 |
842 |
mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
|
| 843 |
843 |
(1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
|
| 844 |
|
newval = (env->CP0_VPEControl & ~mask) | (t0 & mask);
|
|
844 |
newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
|
| 845 |
845 |
|
| 846 |
846 |
/* Yield scheduler intercept not implemented. */
|
| 847 |
847 |
/* Gating storage scheduler intercept not implemented. */
|
| ... | ... | |
| 851 |
851 |
env->CP0_VPEControl = newval;
|
| 852 |
852 |
}
|
| 853 |
853 |
|
| 854 |
|
void helper_mtc0_vpeconf0 (target_ulong t0)
|
|
854 |
void helper_mtc0_vpeconf0 (target_ulong arg1)
|
| 855 |
855 |
{
|
| 856 |
856 |
uint32_t mask = 0;
|
| 857 |
857 |
uint32_t newval;
|
| ... | ... | |
| 861 |
861 |
mask |= (0xff << CP0VPEC0_XTC);
|
| 862 |
862 |
mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
|
| 863 |
863 |
}
|
| 864 |
|
newval = (env->CP0_VPEConf0 & ~mask) | (t0 & mask);
|
|
864 |
newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
|
| 865 |
865 |
|
| 866 |
866 |
// TODO: TC exclusive handling due to ERL/EXL.
|
| 867 |
867 |
|
| 868 |
868 |
env->CP0_VPEConf0 = newval;
|
| 869 |
869 |
}
|
| 870 |
870 |
|
| 871 |
|
void helper_mtc0_vpeconf1 (target_ulong t0)
|
|
871 |
void helper_mtc0_vpeconf1 (target_ulong arg1)
|
| 872 |
872 |
{
|
| 873 |
873 |
uint32_t mask = 0;
|
| 874 |
874 |
uint32_t newval;
|
| ... | ... | |
| 876 |
876 |
if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
|
| 877 |
877 |
mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
|
| 878 |
878 |
(0xff << CP0VPEC1_NCP1);
|
| 879 |
|
newval = (env->CP0_VPEConf1 & ~mask) | (t0 & mask);
|
|
879 |
newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
|
| 880 |
880 |
|
| 881 |
881 |
/* UDI not implemented. */
|
| 882 |
882 |
/* CP2 not implemented. */
|
| ... | ... | |
| 886 |
886 |
env->CP0_VPEConf1 = newval;
|
| 887 |
887 |
}
|
| 888 |
888 |
|
| 889 |
|
void helper_mtc0_yqmask (target_ulong t0)
|
|
889 |
void helper_mtc0_yqmask (target_ulong arg1)
|
| 890 |
890 |
{
|
| 891 |
891 |
/* Yield qualifier inputs not implemented. */
|
| 892 |
892 |
env->CP0_YQMask = 0x00000000;
|
| 893 |
893 |
}
|
| 894 |
894 |
|
| 895 |
|
void helper_mtc0_vpeopt (target_ulong t0)
|
|
895 |
void helper_mtc0_vpeopt (target_ulong arg1)
|
| 896 |
896 |
{
|
| 897 |
|
env->CP0_VPEOpt = t0 & 0x0000ffff;
|
|
897 |
env->CP0_VPEOpt = arg1 & 0x0000ffff;
|
| 898 |
898 |
}
|
| 899 |
899 |
|
| 900 |
|
void helper_mtc0_entrylo0 (target_ulong t0)
|
|
900 |
void helper_mtc0_entrylo0 (target_ulong arg1)
|
| 901 |
901 |
{
|
| 902 |
902 |
/* Large physaddr (PABITS) not implemented */
|
| 903 |
903 |
/* 1k pages not implemented */
|
| 904 |
|
env->CP0_EntryLo0 = t0 & 0x3FFFFFFF;
|
|
904 |
env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
|
| 905 |
905 |
}
|
| 906 |
906 |
|
| 907 |
|
void helper_mtc0_tcstatus (target_ulong t0)
|
|
907 |
void helper_mtc0_tcstatus (target_ulong arg1)
|
| 908 |
908 |
{
|
| 909 |
909 |
uint32_t mask = env->CP0_TCStatus_rw_bitmask;
|
| 910 |
910 |
uint32_t newval;
|
| 911 |
911 |
|
| 912 |
|
newval = (env->active_tc.CP0_TCStatus & ~mask) | (t0 & mask);
|
|
912 |
newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
|
| 913 |
913 |
|
| 914 |
914 |
// TODO: Sync with CP0_Status.
|
| 915 |
915 |
|
| 916 |
916 |
env->active_tc.CP0_TCStatus = newval;
|
| 917 |
917 |
}
|
| 918 |
918 |
|
| 919 |
|
void helper_mttc0_tcstatus (target_ulong t0)
|
|
919 |
void helper_mttc0_tcstatus (target_ulong arg1)
|
| 920 |
920 |
{
|
| 921 |
921 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
| 922 |
922 |
|
| 923 |
923 |
// TODO: Sync with CP0_Status.
|
| 924 |
924 |
|
| 925 |
925 |
if (other_tc == env->current_tc)
|
| 926 |
|
env->active_tc.CP0_TCStatus = t0;
|
|
926 |
env->active_tc.CP0_TCStatus = arg1;
|
| 927 |
927 |
else
|
| 928 |
|
env->tcs[other_tc].CP0_TCStatus = t0;
|
|
928 |
env->tcs[other_tc].CP0_TCStatus = arg1;
|
| 929 |
929 |
}
|
| 930 |
930 |
|
| 931 |
|
void helper_mtc0_tcbind (target_ulong t0)
|
|
931 |
void helper_mtc0_tcbind (target_ulong arg1)
|
| 932 |
932 |
{
|
| 933 |
933 |
uint32_t mask = (1 << CP0TCBd_TBE);
|
| 934 |
934 |
uint32_t newval;
|
| 935 |
935 |
|
| 936 |
936 |
if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
|
| 937 |
937 |
mask |= (1 << CP0TCBd_CurVPE);
|
| 938 |
|
newval = (env->active_tc.CP0_TCBind & ~mask) | (t0 & mask);
|
|
938 |
newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
|
| 939 |
939 |
env->active_tc.CP0_TCBind = newval;
|
| 940 |
940 |
}
|
| 941 |
941 |
|
| 942 |
|
void helper_mttc0_tcbind (target_ulong t0)
|
|
942 |
void helper_mttc0_tcbind (target_ulong arg1)
|
| 943 |
943 |
{
|
| 944 |
944 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
| 945 |
945 |
uint32_t mask = (1 << CP0TCBd_TBE);
|
| ... | ... | |
| 948 |
948 |
if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
|
| 949 |
949 |
mask |= (1 << CP0TCBd_CurVPE);
|
| 950 |
950 |
if (other_tc == env->current_tc) {
|
| 951 |
|
newval = (env->active_tc.CP0_TCBind & ~mask) | (t0 & mask);
|
|
951 |
newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
|
| 952 |
952 |
env->active_tc.CP0_TCBind = newval;
|
| 953 |
953 |
} else {
|
| 954 |
|
newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (t0 & mask);
|
|
954 |
newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
|
| 955 |
955 |
env->tcs[other_tc].CP0_TCBind = newval;
|
| 956 |
956 |
}
|
| 957 |
957 |
}
|
| 958 |
958 |
|
| 959 |
|
void helper_mtc0_tcrestart (target_ulong t0)
|
|
959 |
void helper_mtc0_tcrestart (target_ulong arg1)
|
| 960 |
960 |
{
|
| 961 |
|
env->active_tc.PC = t0;
|
|
961 |
env->active_tc.PC = arg1;
|
| 962 |
962 |
env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
|
| 963 |
963 |
env->CP0_LLAddr = 0ULL;
|
| 964 |
964 |
/* MIPS16 not implemented. */
|
| 965 |
965 |
}
|
| 966 |
966 |
|
| 967 |
|
void helper_mttc0_tcrestart (target_ulong t0)
|
|
967 |
void helper_mttc0_tcrestart (target_ulong arg1)
|
| 968 |
968 |
{
|
| 969 |
969 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
| 970 |
970 |
|
| 971 |
971 |
if (other_tc == env->current_tc) {
|
| 972 |
|
env->active_tc.PC = t0;
|
|
972 |
env->active_tc.PC = arg1;
|
| 973 |
973 |
env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
|
| 974 |
974 |
env->CP0_LLAddr = 0ULL;
|
| 975 |
975 |
/* MIPS16 not implemented. */
|
| 976 |
976 |
} else {
|
| 977 |
|
env->tcs[other_tc].PC = t0;
|
|
977 |
env->tcs[other_tc].PC = arg1;
|
| 978 |
978 |
env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
|
| 979 |
979 |
env->CP0_LLAddr = 0ULL;
|
| 980 |
980 |
/* MIPS16 not implemented. */
|
| 981 |
981 |
}
|
| 982 |
982 |
}
|
| 983 |
983 |
|
| 984 |
|
void helper_mtc0_tchalt (target_ulong t0)
|
|
984 |
void helper_mtc0_tchalt (target_ulong arg1)
|
| 985 |
985 |
{
|
| 986 |
|
env->active_tc.CP0_TCHalt = t0 & 0x1;
|
|
986 |
env->active_tc.CP0_TCHalt = arg1 & 0x1;
|
| 987 |
987 |
|
| 988 |
988 |
// TODO: Halt TC / Restart (if allocated+active) TC.
|
| 989 |
989 |
}
|
| 990 |
990 |
|
| 991 |
|
void helper_mttc0_tchalt (target_ulong t0)
|
|
991 |
void helper_mttc0_tchalt (target_ulong arg1)
|
| 992 |
992 |
{
|
| 993 |
993 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
| 994 |
994 |
|
| 995 |
995 |
// TODO: Halt TC / Restart (if allocated+active) TC.
|
| 996 |
996 |
|
| 997 |
997 |
if (other_tc == env->current_tc)
|
| 998 |
|
env->active_tc.CP0_TCHalt = t0;
|
|
998 |
env->active_tc.CP0_TCHalt = arg1;
|
| 999 |
999 |
else
|
| 1000 |
|
env->tcs[other_tc].CP0_TCHalt = t0;
|
|
1000 |
env->tcs[other_tc].CP0_TCHalt = arg1;
|
| 1001 |
1001 |
}
|
| 1002 |
1002 |
|
| 1003 |
|
void helper_mtc0_tccontext (target_ulong t0)
|
|
1003 |
void helper_mtc0_tccontext (target_ulong arg1)
|
| 1004 |
1004 |
{
|
| 1005 |
|
env->active_tc.CP0_TCContext = t0;
|
|
1005 |
env->active_tc.CP0_TCContext = arg1;
|
| 1006 |
1006 |
}
|
| 1007 |
1007 |
|
| 1008 |
|
void helper_mttc0_tccontext (target_ulong t0)
|
|
1008 |
void helper_mttc0_tccontext (target_ulong arg1)
|
| 1009 |
1009 |
{
|
| 1010 |
1010 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
| 1011 |
1011 |
|
| 1012 |
1012 |
if (other_tc == env->current_tc)
|
| 1013 |
|
env->active_tc.CP0_TCContext = t0;
|
|
1013 |
env->active_tc.CP0_TCContext = arg1;
|
| 1014 |
1014 |
else
|
| 1015 |
|
env->tcs[other_tc].CP0_TCContext = t0;
|
|
1015 |
env->tcs[other_tc].CP0_TCContext = arg1;
|
| 1016 |
1016 |
}
|
| 1017 |
1017 |
|
| 1018 |
|
void helper_mtc0_tcschedule (target_ulong t0)
|
|
1018 |
void helper_mtc0_tcschedule (target_ulong arg1)
|
| 1019 |
1019 |
{
|
| 1020 |
|
env->active_tc.CP0_TCSchedule = t0;
|
|
1020 |
env->active_tc.CP0_TCSchedule = arg1;
|
| 1021 |
1021 |
}
|
| 1022 |
1022 |
|
| 1023 |
|
void helper_mttc0_tcschedule (target_ulong t0)
|
|
1023 |
void helper_mttc0_tcschedule (target_ulong arg1)
|
| 1024 |
1024 |
{
|
| 1025 |
1025 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
| 1026 |
1026 |
|
| 1027 |
1027 |
if (other_tc == env->current_tc)
|
| 1028 |
|
env->active_tc.CP0_TCSchedule = t0;
|
|
1028 |
env->active_tc.CP0_TCSchedule = arg1;
|
| 1029 |
1029 |
else
|
| 1030 |
|
env->tcs[other_tc].CP0_TCSchedule = t0;
|
|
1030 |
env->tcs[other_tc].CP0_TCSchedule = arg1;
|
| 1031 |
1031 |
}
|
| 1032 |
1032 |
|
| 1033 |
|
void helper_mtc0_tcschefback (target_ulong t0)
|
|
1033 |
void helper_mtc0_tcschefback (target_ulong arg1)
|
| 1034 |
1034 |
{
|
| 1035 |
|
env->active_tc.CP0_TCScheFBack = t0;
|
|
1035 |
env->active_tc.CP0_TCScheFBack = arg1;
|
| 1036 |
1036 |
}
|
| 1037 |
1037 |
|
| 1038 |
|
void helper_mttc0_tcschefback (target_ulong t0)
|
|
1038 |
void helper_mttc0_tcschefback (target_ulong arg1)
|
| 1039 |
1039 |
{
|
| 1040 |
1040 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
| 1041 |
1041 |
|
| 1042 |
1042 |
if (other_tc == env->current_tc)
|
| 1043 |
|
env->active_tc.CP0_TCScheFBack = t0;
|
|
1043 |
env->active_tc.CP0_TCScheFBack = arg1;
|
| 1044 |
1044 |
else
|
| 1045 |
|
env->tcs[other_tc].CP0_TCScheFBack = t0;
|
|
1045 |
env->tcs[other_tc].CP0_TCScheFBack = arg1;
|
| 1046 |
1046 |
}
|
| 1047 |
1047 |
|
| 1048 |
|
void helper_mtc0_entrylo1 (target_ulong t0)
|
|
1048 |
void helper_mtc0_entrylo1 (target_ulong arg1)
|
| 1049 |
1049 |
{
|
| 1050 |
1050 |
/* Large physaddr (PABITS) not implemented */
|
| 1051 |
1051 |
/* 1k pages not implemented */
|
| 1052 |
|
env->CP0_EntryLo1 = t0 & 0x3FFFFFFF;
|
|
1052 |
env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
|
| 1053 |
1053 |
}
|
| 1054 |
1054 |
|
| 1055 |
|
void helper_mtc0_context (target_ulong t0)
|
|
1055 |
void helper_mtc0_context (target_ulong arg1)
|
| 1056 |
1056 |
{
|
| 1057 |
|
env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (t0 & ~0x007FFFFF);
|
|
1057 |
env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
|
| 1058 |
1058 |
}
|
| 1059 |
1059 |
|
| 1060 |
|
void helper_mtc0_pagemask (target_ulong t0)
|
|
1060 |
void helper_mtc0_pagemask (target_ulong arg1)
|
| 1061 |
1061 |
{
|
| 1062 |
1062 |
/* 1k pages not implemented */
|
| 1063 |
|
env->CP0_PageMask = t0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
|
|
1063 |
env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
|
| 1064 |
1064 |
}
|
| 1065 |
1065 |
|
| 1066 |
|
void helper_mtc0_pagegrain (target_ulong t0)
|
|
1066 |
void helper_mtc0_pagegrain (target_ulong arg1)
|
| 1067 |
1067 |
{
|
| 1068 |
1068 |
/* SmartMIPS not implemented */
|
| 1069 |
1069 |
/* Large physaddr (PABITS) not implemented */
|
| ... | ... | |
| 1071 |
1071 |
env->CP0_PageGrain = 0;
|
| 1072 |
1072 |
}
|
| 1073 |
1073 |
|
| 1074 |
|
void helper_mtc0_wired (target_ulong t0)
|
|
1074 |
void helper_mtc0_wired (target_ulong arg1)
|
| 1075 |
1075 |
{
|
| 1076 |
|
env->CP0_Wired = t0 % env->tlb->nb_tlb;
|
|
1076 |
env->CP0_Wired = arg1 % env->tlb->nb_tlb;
|
| 1077 |
1077 |
}
|
| 1078 |
1078 |
|
| 1079 |
|
void helper_mtc0_srsconf0 (target_ulong t0)
|
|
1079 |
void helper_mtc0_srsconf0 (target_ulong arg1)
|
| 1080 |
1080 |
{
|
| 1081 |
|
env->CP0_SRSConf0 |= t0 & env->CP0_SRSConf0_rw_bitmask;
|
|
1081 |
env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
|
| 1082 |
1082 |
}
|
| 1083 |
1083 |
|
| 1084 |
|
void helper_mtc0_srsconf1 (target_ulong t0)
|
|
1084 |
void helper_mtc0_srsconf1 (target_ulong arg1)
|
| 1085 |
1085 |
{
|
| 1086 |
|
env->CP0_SRSConf1 |= t0 & env->CP0_SRSConf1_rw_bitmask;
|
|
1086 |
env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
|
| 1087 |
1087 |
}
|
| 1088 |
1088 |
|
| 1089 |
|
void helper_mtc0_srsconf2 (target_ulong t0)
|
|
1089 |
void helper_mtc0_srsconf2 (target_ulong arg1)
|
| 1090 |
1090 |
{
|
| 1091 |
|
env->CP0_SRSConf2 |= t0 & env->CP0_SRSConf2_rw_bitmask;
|
|
1091 |
env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
|
| 1092 |
1092 |
}
|
| 1093 |
1093 |
|
| 1094 |
|
void helper_mtc0_srsconf3 (target_ulong t0)
|
|
1094 |
void helper_mtc0_srsconf3 (target_ulong arg1)
|
| 1095 |
1095 |
{
|
| 1096 |
|
env->CP0_SRSConf3 |= t0 & env->CP0_SRSConf3_rw_bitmask;
|
|
1096 |
env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
|
| 1097 |
1097 |
}
|
| 1098 |
1098 |
|
| 1099 |
|
void helper_mtc0_srsconf4 (target_ulong t0)
|
|
1099 |
void helper_mtc0_srsconf4 (target_ulong arg1)
|
| 1100 |
1100 |
{
|
| 1101 |
|
env->CP0_SRSConf4 |= t0 & env->CP0_SRSConf4_rw_bitmask;
|
|
1101 |
env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
|
| 1102 |
1102 |
}
|
| 1103 |
1103 |
|
| 1104 |
|
void helper_mtc0_hwrena (target_ulong t0)
|
|
1104 |
void helper_mtc0_hwrena (target_ulong arg1)
|
| 1105 |
1105 |
{
|
| 1106 |
|
env->CP0_HWREna = t0 & 0x0000000F;
|
|
1106 |
env->CP0_HWREna = arg1 & 0x0000000F;
|
| 1107 |
1107 |
}
|
| 1108 |
1108 |
|
| 1109 |
|
void helper_mtc0_count (target_ulong t0)
|
|
1109 |
void helper_mtc0_count (target_ulong arg1)
|
| 1110 |
1110 |
{
|
| 1111 |
|
cpu_mips_store_count(env, t0);
|
|
1111 |
cpu_mips_store_count(env, arg1);
|
| 1112 |
1112 |
}
|
| 1113 |
1113 |
|
| 1114 |
|
void helper_mtc0_entryhi (target_ulong t0)
|
|
1114 |
void helper_mtc0_entryhi (target_ulong arg1)
|
| 1115 |
1115 |
{
|
| 1116 |
1116 |
target_ulong old, val;
|
| 1117 |
1117 |
|
| 1118 |
1118 |
/* 1k pages not implemented */
|
| 1119 |
|
val = t0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
|
|
1119 |
val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
|
| 1120 |
1120 |
#if defined(TARGET_MIPS64)
|
| 1121 |
1121 |
val &= env->SEGMask;
|
| 1122 |
1122 |
#endif
|
| ... | ... | |
| 1131 |
1131 |
cpu_mips_tlb_flush(env, 1);
|
| 1132 |
1132 |
}
|
| 1133 |
1133 |
|
| 1134 |
|
void helper_mttc0_entryhi(target_ulong t0)
|
|
1134 |
void helper_mttc0_entryhi(target_ulong arg1)
|
| 1135 |
1135 |
{
|
| 1136 |
1136 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
| 1137 |
1137 |
int32_t tcstatus;
|
| 1138 |
1138 |
|
| 1139 |
|
env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (t0 & ~0xff);
|
|
1139 |
env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (arg1 & ~0xff);
|
| 1140 |
1140 |
if (other_tc == env->current_tc) {
|
| 1141 |
|
tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (t0 & 0xff);
|
|
1141 |
tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (arg1 & 0xff);
|
| 1142 |
1142 |
env->active_tc.CP0_TCStatus = tcstatus;
|
| 1143 |
1143 |
} else {
|
| 1144 |
|
tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (t0 & 0xff);
|
|
1144 |
tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (arg1 & 0xff);
|
| 1145 |
1145 |
env->tcs[other_tc].CP0_TCStatus = tcstatus;
|
| 1146 |
1146 |
}
|
| 1147 |
1147 |
}
|
| 1148 |
1148 |
|
| 1149 |
|
void helper_mtc0_compare (target_ulong t0)
|
|
1149 |
void helper_mtc0_compare (target_ulong arg1)
|
| 1150 |
1150 |
{
|
| 1151 |
|
cpu_mips_store_compare(env, t0);
|
|
1151 |
cpu_mips_store_compare(env, arg1);
|
| 1152 |
1152 |
}
|
| 1153 |
1153 |
|
| 1154 |
|
void helper_mtc0_status (target_ulong t0)
|
|
1154 |
void helper_mtc0_status (target_ulong arg1)
|
| 1155 |
1155 |
{
|
| 1156 |
1156 |
uint32_t val, old;
|
| 1157 |
1157 |
uint32_t mask = env->CP0_Status_rw_bitmask;
|
| 1158 |
1158 |
|
| 1159 |
|
val = t0 & mask;
|
|
1159 |
val = arg1 & mask;
|
| 1160 |
1160 |
old = env->CP0_Status;
|
| 1161 |
1161 |
env->CP0_Status = (env->CP0_Status & ~mask) | val;
|
| 1162 |
1162 |
compute_hflags(env);
|
| ... | ... | |
| 1175 |
1175 |
cpu_mips_update_irq(env);
|
| 1176 |
1176 |
}
|
| 1177 |
1177 |
|
| 1178 |
|
void helper_mttc0_status(target_ulong t0)
|
|
1178 |
void helper_mttc0_status(target_ulong arg1)
|
| 1179 |
1179 |
{
|
| 1180 |
1180 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
| 1181 |
1181 |
int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus;
|
| 1182 |
1182 |
|
| 1183 |
|
env->CP0_Status = t0 & ~0xf1000018;
|
| 1184 |
|
tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (t0 & (0xf << CP0St_CU0));
|
| 1185 |
|
tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((t0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
|
| 1186 |
|
tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((t0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
|
|
1183 |
env->CP0_Status = arg1 & ~0xf1000018;
|
|
1184 |
tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (arg1 & (0xf << CP0St_CU0));
|
|
1185 |
tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((arg1 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
|
|
1186 |
tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((arg1 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
|
| 1187 |
1187 |
if (other_tc == env->current_tc)
|
| 1188 |
1188 |
env->active_tc.CP0_TCStatus = tcstatus;
|
| 1189 |
1189 |
else
|
| 1190 |
1190 |
env->tcs[other_tc].CP0_TCStatus = tcstatus;
|
| 1191 |
1191 |
}
|
| 1192 |
1192 |
|
| 1193 |
|
void helper_mtc0_intctl (target_ulong t0)
|
|
1193 |
void helper_mtc0_intctl (target_ulong arg1)
|
| 1194 |
1194 |
{
|
| 1195 |
1195 |
/* vectored interrupts not implemented, no performance counters. */
|
| 1196 |
|
env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (t0 & 0x000002e0);
|
|
1196 |
env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (arg1 & 0x000002e0);
|
| 1197 |
1197 |
}
|
| 1198 |
1198 |
|
| 1199 |
|
void helper_mtc0_srsctl (target_ulong t0)
|
|
1199 |
void helper_mtc0_srsctl (target_ulong arg1)
|
| 1200 |
1200 |
{
|
| 1201 |
1201 |
uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
|
| 1202 |
|
env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (t0 & mask);
|
|
1202 |
env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
|
| 1203 |
1203 |
}
|
| 1204 |
1204 |
|
| 1205 |
|
void helper_mtc0_cause (target_ulong t0)
|
|
1205 |
void helper_mtc0_cause (target_ulong arg1)
|
| 1206 |
1206 |
{
|
| 1207 |
1207 |
uint32_t mask = 0x00C00300;
|
| 1208 |
1208 |
uint32_t old = env->CP0_Cause;
|
| ... | ... | |
| 1210 |
1210 |
if (env->insn_flags & ISA_MIPS32R2)
|
| 1211 |
1211 |
mask |= 1 << CP0Ca_DC;
|
| 1212 |
1212 |
|
| 1213 |
|
env->CP0_Cause = (env->CP0_Cause & ~mask) | (t0 & mask);
|
|
1213 |
env->CP0_Cause = (env->CP0_Cause & ~mask) | (arg1 & mask);
|
| 1214 |
1214 |
|
| 1215 |
1215 |
if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
|
| 1216 |
1216 |
if (env->CP0_Cause & (1 << CP0Ca_DC))
|
| ... | ... | |
| 1221 |
1221 |
|
| 1222 |
1222 |
/* Handle the software interrupt as an hardware one, as they
|
| 1223 |
1223 |
are very similar */
|
| 1224 |
|
if (t0 & CP0Ca_IP_mask) {
|
|
1224 |
if (arg1 & CP0Ca_IP_mask) {
|
| 1225 |
1225 |
cpu_mips_update_irq(env);
|
| 1226 |
1226 |
}
|
| 1227 |
1227 |
}
|
| 1228 |
1228 |
|
| 1229 |
|
void helper_mtc0_ebase (target_ulong t0)
|
|
1229 |
void helper_mtc0_ebase (target_ulong arg1)
|
| 1230 |
1230 |
{
|
| 1231 |
1231 |
/* vectored interrupts not implemented */
|
| 1232 |
1232 |
/* Multi-CPU not implemented */
|
| 1233 |
|
env->CP0_EBase = 0x80000000 | (t0 & 0x3FFFF000);
|
|
1233 |
env->CP0_EBase = 0x80000000 | (arg1 & 0x3FFFF000);
|
| 1234 |
1234 |
}
|
| 1235 |
1235 |
|
| 1236 |
|
void helper_mtc0_config0 (target_ulong t0)
|
|
1236 |
void helper_mtc0_config0 (target_ulong arg1)
|
| 1237 |
1237 |
{
|
| 1238 |
|
env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (t0 & 0x00000007);
|
|
1238 |
env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
|
| 1239 |
1239 |
}
|
| 1240 |
1240 |
|
| 1241 |
|
void helper_mtc0_config2 (target_ulong t0)
|
|
1241 |
void helper_mtc0_config2 (target_ulong arg1)
|
| 1242 |
1242 |
{
|
| 1243 |
1243 |
/* tertiary/secondary caches not implemented */
|
| 1244 |
1244 |
env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
|
| 1245 |
1245 |
}
|
| 1246 |
1246 |
|
| 1247 |
|
void helper_mtc0_watchlo (target_ulong t0, uint32_t sel)
|
|
1247 |
void helper_mtc0_watchlo (target_ulong arg1, uint32_t sel)
|
| 1248 |
1248 |
{
|
| 1249 |
1249 |
/* Watch exceptions for instructions, data loads, data stores
|
| 1250 |
1250 |
not implemented. */
|
| 1251 |
|
env->CP0_WatchLo[sel] = (t0 & ~0x7);
|
|
1251 |
env->CP0_WatchLo[sel] = (arg1 & ~0x7);
|
| 1252 |
1252 |
}
|
| 1253 |
1253 |
|
| 1254 |
|
void helper_mtc0_watchhi (target_ulong t0, uint32_t sel)
|
|
1254 |
void helper_mtc0_watchhi (target_ulong arg1, uint32_t sel)
|
| 1255 |
1255 |
{
|
| 1256 |
|
env->CP0_WatchHi[sel] = (t0 & 0x40FF0FF8);
|
| 1257 |
|
env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & t0 & 0x7);
|
|
1256 |
env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
|
|
1257 |
env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
|
| 1258 |
1258 |
}
|
| 1259 |
1259 |
|
| 1260 |
|
void helper_mtc0_xcontext (target_ulong t0)
|
|
1260 |
void helper_mtc0_xcontext (target_ulong arg1)
|
| 1261 |
1261 |
{
|
| 1262 |
1262 |
target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
|
| 1263 |
|
env->CP0_XContext = (env->CP0_XContext & mask) | (t0 & ~mask);
|
|
1263 |
env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
|
| 1264 |
1264 |
}
|
| 1265 |
1265 |
|
| 1266 |
|
void helper_mtc0_framemask (target_ulong t0)
|
|
1266 |
void helper_mtc0_framemask (target_ulong arg1)
|
| 1267 |
1267 |
{
|
| 1268 |
|
env->CP0_Framemask = t0; /* XXX */
|
|
1268 |
env->CP0_Framemask = arg1; /* XXX */
|
| 1269 |
1269 |
}
|
| 1270 |
1270 |
|
| 1271 |
|
void helper_mtc0_debug (target_ulong t0)
|
|
1271 |
void helper_mtc0_debug (target_ulong arg1)
|
| 1272 |
1272 |
{
|
| 1273 |
|
env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (t0 & 0x13300120);
|
| 1274 |
|
if (t0 & (1 << CP0DB_DM))
|
|
1273 |
env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
|
|
1274 |
if (arg1 & (1 << CP0DB_DM))
|
| 1275 |
1275 |
env->hflags |= MIPS_HFLAG_DM;
|
| 1276 |
1276 |
else
|
| 1277 |
1277 |
env->hflags &= ~MIPS_HFLAG_DM;
|
| 1278 |
1278 |
}
|
| 1279 |
1279 |
|
| 1280 |
|
void helper_mttc0_debug(target_ulong t0)
|
|
1280 |
void helper_mttc0_debug(target_ulong arg1)
|
| 1281 |
1281 |
{
|
| 1282 |
1282 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
| 1283 |
|
uint32_t val = t0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
|
|
1283 |
uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
|
| 1284 |
1284 |
|
| 1285 |
1285 |
/* XXX: Might be wrong, check with EJTAG spec. */
|
| 1286 |
1286 |
if (other_tc == env->current_tc)
|
| ... | ... | |
| 1288 |
1288 |
else
|
| 1289 |
1289 |
env->tcs[other_tc].CP0_Debug_tcstatus = val;
|
| 1290 |
1290 |
env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
|
| 1291 |
|
(t0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
|
|
1291 |
(arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
|
| 1292 |
1292 |
}
|
| 1293 |
1293 |
|
| 1294 |
|
void helper_mtc0_performance0 (target_ulong t0)
|
|
1294 |
void helper_mtc0_performance0 (target_ulong arg1)
|
| 1295 |
1295 |
{
|
| 1296 |
|
env->CP0_Performance0 = t0 & 0x000007ff;
|
|
1296 |
env->CP0_Performance0 = arg1 & 0x000007ff;
|
| 1297 |
1297 |
}
|
| 1298 |
1298 |
|
| 1299 |
|
void helper_mtc0_taglo (target_ulong t0)
|
|
1299 |
void helper_mtc0_taglo (target_ulong arg1)
|
| 1300 |
1300 |
{
|
| 1301 |
|
env->CP0_TagLo = t0 & 0xFFFFFCF6;
|
|
1301 |
env->CP0_TagLo = arg1 & 0xFFFFFCF6;
|
| 1302 |
1302 |
}
|
| 1303 |
1303 |
|
| 1304 |
|
void helper_mtc0_datalo (target_ulong t0)
|
|
1304 |
void helper_mtc0_datalo (target_ulong arg1)
|
| 1305 |
1305 |
{
|
| 1306 |
|
env->CP0_DataLo = t0; /* XXX */
|
|
1306 |
env->CP0_DataLo = arg1; /* XXX */
|
| 1307 |
1307 |
}
|
| 1308 |
1308 |
|
| 1309 |
|
void helper_mtc0_taghi (target_ulong t0)
|
|
1309 |
void helper_mtc0_taghi (target_ulong arg1)
|
| 1310 |
1310 |
{
|
| 1311 |
|
env->CP0_TagHi = t0; /* XXX */
|
|
1311 |
env->CP0_TagHi = arg1; /* XXX */
|
| 1312 |
1312 |
}
|
| 1313 |
1313 |
|
| 1314 |
|
void helper_mtc0_datahi (target_ulong t0)
|
|
1314 |
void helper_mtc0_datahi (target_ulong arg1)
|
| 1315 |
1315 |
{
|
| 1316 |
|
env->CP0_DataHi = t0; /* XXX */
|
|
1316 |
env->CP0_DataHi = arg1; /* XXX */
|
| 1317 |
1317 |
}
|
| 1318 |
1318 |
|
| 1319 |
1319 |
/* MIPS MT functions */
|
| ... | ... | |
| 1367 |
1367 |
return env->tcs[other_tc].DSPControl;
|
| 1368 |
1368 |
}
|
| 1369 |
1369 |
|
| 1370 |
|
void helper_mttgpr(target_ulong t0, uint32_t sel)
|
|
1370 |
void helper_mttgpr(target_ulong arg1, uint32_t sel)
|
| 1371 |
1371 |
{
|
| 1372 |
1372 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
| 1373 |
1373 |
|
| 1374 |
1374 |
if (other_tc == env->current_tc)
|
| 1375 |
|
env->active_tc.gpr[sel] = t0;
|
|
1375 |
env->active_tc.gpr[sel] = arg1;
|
| 1376 |
1376 |
else
|
| 1377 |
|
env->tcs[other_tc].gpr[sel] = t0;
|
|
1377 |
env->tcs[other_tc].gpr[sel] = arg1;
|
| 1378 |
1378 |
}
|
| 1379 |
1379 |
|
| 1380 |
|
void helper_mttlo(target_ulong t0, uint32_t sel)
|
|
1380 |
void helper_mttlo(target_ulong arg1, uint32_t sel)
|
| 1381 |
1381 |
{
|
| 1382 |
1382 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
| 1383 |
1383 |
|
| 1384 |
1384 |
if (other_tc == env->current_tc)
|
| 1385 |
|
env->active_tc.LO[sel] = t0;
|
|
1385 |
env->active_tc.LO[sel] = arg1;
|
| 1386 |
1386 |
else
|
| 1387 |
|
env->tcs[other_tc].LO[sel] = t0;
|
|
1387 |
env->tcs[other_tc].LO[sel] = arg1;
|
| 1388 |
1388 |
}
|
| 1389 |
1389 |
|
| 1390 |
|
void helper_mtthi(target_ulong t0, uint32_t sel)
|
|
1390 |
void helper_mtthi(target_ulong arg1, uint32_t sel)
|
| 1391 |
1391 |
{
|
| 1392 |
1392 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
| 1393 |
1393 |
|
| 1394 |
1394 |
if (other_tc == env->current_tc)
|
| 1395 |
|
env->active_tc.HI[sel] = t0;
|
|
1395 |
env->active_tc.HI[sel] = arg1;
|
| 1396 |
1396 |
else
|
| 1397 |
|
env->tcs[other_tc].HI[sel] = t0;
|
|
1397 |
env->tcs[other_tc].HI[sel] = arg1;
|
| 1398 |
1398 |
}
|
| 1399 |
1399 |
|
| 1400 |
|
void helper_mttacx(target_ulong t0, uint32_t sel)
|
|
1400 |
void helper_mttacx(target_ulong arg1, uint32_t sel)
|
| 1401 |
1401 |
{
|
| 1402 |
1402 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
| 1403 |
1403 |
|
| 1404 |
1404 |
if (other_tc == env->current_tc)
|
| 1405 |
|
env->active_tc.ACX[sel] = t0;
|
|
1405 |
env->active_tc.ACX[sel] = arg1;
|
| 1406 |
1406 |
else
|
| 1407 |
|
env->tcs[other_tc].ACX[sel] = t0;
|
|
1407 |
env->tcs[other_tc].ACX[sel] = arg1;
|
| 1408 |
1408 |
}
|
| 1409 |
1409 |
|
| 1410 |
|
void helper_mttdsp(target_ulong t0)
|
|
1410 |
void helper_mttdsp(target_ulong arg1)
|
| 1411 |
1411 |
{
|
| 1412 |
1412 |
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
|
| 1413 |
1413 |
|
| 1414 |
1414 |
if (other_tc == env->current_tc)
|
| 1415 |
|
env->active_tc.DSPControl = t0;
|
|
1415 |
env->active_tc.DSPControl = arg1;
|
| 1416 |
1416 |
else
|
| 1417 |
|
env->tcs[other_tc].DSPControl = t0;
|
|
1417 |
env->tcs[other_tc].DSPControl = arg1;
|
| 1418 |
1418 |
}
|
| 1419 |
1419 |
|
| 1420 |
1420 |
/* MIPS MT functions */
|
| 1421 |
|
target_ulong helper_dmt(target_ulong t0)
|
|
1421 |
target_ulong helper_dmt(target_ulong arg1)
|
| 1422 |
1422 |
{
|
| 1423 |
1423 |
// TODO
|
| 1424 |
|
t0 = 0;
|
| 1425 |
|
// rt = t0
|
|
1424 |
arg1 = 0;
|
|
1425 |
// rt = arg1
|
| 1426 |
1426 |
|
| 1427 |
|
return t0;
|
|
1427 |
return arg1;
|
| 1428 |
1428 |
}
|
| 1429 |
1429 |
|
| 1430 |
|
target_ulong helper_emt(target_ulong t0)
|
|
1430 |
target_ulong helper_emt(target_ulong arg1)
|
| 1431 |
1431 |
{
|
| 1432 |
1432 |
// TODO
|
| 1433 |
|
t0 = 0;
|
| 1434 |
|
// rt = t0
|
|
1433 |
arg1 = 0;
|
|
1434 |
// rt = arg1
|
| 1435 |
1435 |
|
| 1436 |
|
return t0;
|
|
1436 |
return arg1;
|
| 1437 |
1437 |
}
|
| 1438 |
1438 |
|
| 1439 |
|
target_ulong helper_dvpe(target_ulong t0)
|
|
1439 |
target_ulong helper_dvpe(target_ulong arg1)
|
| 1440 |
1440 |
{
|
| 1441 |
1441 |
// TODO
|
| 1442 |
|
t0 = 0;
|
| 1443 |
|
// rt = t0
|
|
1442 |
arg1 = 0;
|
|
1443 |
// rt = arg1
|
| 1444 |
1444 |
|
| 1445 |
|
return t0;
|
|
1445 |
return arg1;
|
| 1446 |
1446 |
}
|
| 1447 |
1447 |
|
| 1448 |
|
target_ulong helper_evpe(target_ulong t0)
|
|
1448 |
target_ulong helper_evpe(target_ulong arg1)
|
| 1449 |
1449 |
{
|
| 1450 |
1450 |
// TODO
|
| 1451 |
|
t0 = 0;
|
| 1452 |
|
// rt = t0
|
|
1451 |
arg1 = 0;
|
|
1452 |
// rt = arg1
|
| 1453 |
1453 |
|
| 1454 |
|
return t0;
|
|
1454 |
return arg1;
|
| 1455 |
1455 |
}
|
| 1456 |
1456 |
#endif /* !CONFIG_USER_ONLY */
|
| 1457 |
1457 |
|
| 1458 |
|
void helper_fork(target_ulong t0, target_ulong t1)
|
|
1458 |
void helper_fork(target_ulong arg1, target_ulong arg2)
|
| 1459 |
1459 |
{
|
| 1460 |
|
// t0 = rt, t1 = rs
|
| 1461 |
|
t0 = 0;
|
|
1460 |
// arg1 = rt, arg2 = rs
|
|
1461 |
arg1 = 0;
|
| 1462 |
1462 |
// TODO: store to TC register
|
| 1463 |
1463 |
}
|
| 1464 |
1464 |
|
| 1465 |
|
target_ulong helper_yield(target_ulong t0)
|
|
1465 |
target_ulong helper_yield(target_ulong arg1)
|
| 1466 |
1466 |
{
|
| 1467 |
|
if (t0 < 0) {
|
|
1467 |
if (arg1 < 0) {
|
| 1468 |
1468 |
/* No scheduling policy implemented. */
|
| 1469 |
|
if (t0 != -2) {
|
|
1469 |
if (arg1 != -2) {
|
| 1470 |
1470 |
if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
|
| 1471 |
1471 |
env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
|
| 1472 |
1472 |
env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
| ... | ... | |
| 1474 |
1474 |
helper_raise_exception(EXCP_THREAD);
|
| 1475 |
1475 |
}
|
| 1476 |
1476 |
}
|
| 1477 |
|
} else if (t0 == 0) {
|
|
1477 |
} else if (arg1 == 0) {
|
| 1478 |
1478 |
if (0 /* TODO: TC underflow */) {
|
| 1479 |
1479 |
env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
| 1480 |
1480 |
helper_raise_exception(EXCP_THREAD);
|
| 1481 |
1481 |
} else {
|
| 1482 |
1482 |
// TODO: Deallocate TC
|
| 1483 |
1483 |
}
|
| 1484 |
|
} else if (t0 > 0) {
|
|
1484 |
} else if (arg1 > 0) {
|
| 1485 |
1485 |
/* Yield qualifier inputs not implemented. */
|
| 1486 |
1486 |
env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
| 1487 |
1487 |
env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
|
| ... | ... | |
| 1884 |
1884 |
|
| 1885 |
1885 |
target_ulong helper_cfc1 (uint32_t reg)
|
| 1886 |
1886 |
{
|
| 1887 |
|
target_ulong t0;
|
|
1887 |
target_ulong arg1;
|
| 1888 |
1888 |
|
| 1889 |
1889 |
switch (reg) {
|
| 1890 |
1890 |
case 0:
|
| 1891 |
|
t0 = (int32_t)env->active_fpu.fcr0;
|
|
1891 |
arg1 = (int32_t)env->active_fpu.fcr0;
|
| 1892 |
1892 |
break;
|
| 1893 |
1893 |
case 25:
|
| 1894 |
|
t0 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
|
|
1894 |
arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
|
| 1895 |
1895 |
break;
|
| 1896 |
1896 |
case 26:
|
| 1897 |
|
t0 = env->active_fpu.fcr31 & 0x0003f07c;
|
|
1897 |
arg1 = env->active_fpu.fcr31 & 0x0003f07c;
|
| 1898 |
1898 |
break;
|
| 1899 |
1899 |
case 28:
|
| 1900 |
|
t0 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
|
|
1900 |
arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
|
| 1901 |
1901 |
break;
|
| 1902 |
1902 |
default:
|
| 1903 |
|
t0 = (int32_t)env->active_fpu.fcr31;
|
|
1903 |
arg1 = (int32_t)env->active_fpu.fcr31;
|
| 1904 |
1904 |
break;
|
| 1905 |
1905 |
}
|
| 1906 |
1906 |
|
| 1907 |
|
return t0;
|
|
1907 |
return arg1;
|
| 1908 |
1908 |
}
|
| 1909 |
1909 |
|
| 1910 |
|
void helper_ctc1 (target_ulong t0, uint32_t reg)
|
|
1910 |
void helper_ctc1 (target_ulong arg1, uint32_t reg)
|
| 1911 |
1911 |
{
|
| 1912 |
1912 |
switch(reg) {
|
| 1913 |
1913 |
case 25:
|
| 1914 |
|
if (t0 & 0xffffff00)
|
|
1914 |
if (arg1 & 0xffffff00)
|
| 1915 |
1915 |
return;
|
| 1916 |
|
env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((t0 & 0xfe) << 24) |
|
| 1917 |
|
((t0 & 0x1) << 23);
|
|
1916 |
env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
|
|
1917 |
((arg1 & 0x1) << 23);
|
| 1918 |
1918 |
break;
|
| 1919 |
1919 |
case 26:
|
| 1920 |
|
if (t0 & 0x007c0000)
|
|
1920 |
if (arg1 & 0x007c0000)
|
| 1921 |
1921 |
return;
|
| 1922 |
|
env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (t0 & 0x0003f07c);
|
|
1922 |
env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
|
| 1923 |
1923 |
break;
|
| 1924 |
1924 |
case 28:
|
| 1925 |
|
if (t0 & 0x007c0000)
|
|
1925 |
if (arg1 & 0x007c0000)
|
| 1926 |
1926 |
return;
|
| 1927 |
|
env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (t0 & 0x00000f83) |
|
| 1928 |
|
((t0 & 0x4) << 22);
|
|
1927 |
env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
|
|
1928 |
((arg1 & 0x4) << 22);
|
| 1929 |
1929 |
break;
|
| 1930 |
1930 |
case 31:
|
| 1931 |
|
if (t0 & 0x007c0000)
|
|
1931 |
if (arg1 & 0x007c0000)
|
| 1932 |
1932 |
return;
|
| 1933 |
|
env->active_fpu.fcr31 = t0;
|
|
1933 |
env->active_fpu.fcr31 = arg1;
|
| 1934 |
1934 |
break;
|
| 1935 |
1935 |
default:
|
| 1936 |
1936 |
return;
|