Revision d9bea114 target-mips/translate.c
| b/target-mips/translate.c | ||
|---|---|---|
| 546 | 546 |
/* Moves to/from shadow registers. */ |
| 547 | 547 |
static inline void gen_load_srsgpr (int from, int to) |
| 548 | 548 |
{
|
| 549 |
TCGv r_tmp1 = tcg_temp_new();
|
|
| 549 |
TCGv t0 = tcg_temp_new();
|
|
| 550 | 550 |
|
| 551 | 551 |
if (from == 0) |
| 552 |
tcg_gen_movi_tl(r_tmp1, 0);
|
|
| 552 |
tcg_gen_movi_tl(t0, 0);
|
|
| 553 | 553 |
else {
|
| 554 |
TCGv_i32 r_tmp2 = tcg_temp_new_i32();
|
|
| 554 |
TCGv_i32 t2 = tcg_temp_new_i32();
|
|
| 555 | 555 |
TCGv_ptr addr = tcg_temp_new_ptr(); |
| 556 | 556 |
|
| 557 |
tcg_gen_ld_i32(r_tmp2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
|
|
| 558 |
tcg_gen_shri_i32(r_tmp2, r_tmp2, CP0SRSCtl_PSS);
|
|
| 559 |
tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xf);
|
|
| 560 |
tcg_gen_muli_i32(r_tmp2, r_tmp2, sizeof(target_ulong) * 32);
|
|
| 561 |
tcg_gen_ext_i32_ptr(addr, r_tmp2);
|
|
| 557 |
tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
|
|
| 558 |
tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
|
|
| 559 |
tcg_gen_andi_i32(t2, t2, 0xf);
|
|
| 560 |
tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
|
|
| 561 |
tcg_gen_ext_i32_ptr(addr, t2);
|
|
| 562 | 562 |
tcg_gen_add_ptr(addr, cpu_env, addr); |
| 563 | 563 |
|
| 564 |
tcg_gen_ld_tl(r_tmp1, addr, sizeof(target_ulong) * from);
|
|
| 564 |
tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from);
|
|
| 565 | 565 |
tcg_temp_free_ptr(addr); |
| 566 |
tcg_temp_free_i32(r_tmp2);
|
|
| 566 |
tcg_temp_free_i32(t2);
|
|
| 567 | 567 |
} |
| 568 |
gen_store_gpr(r_tmp1, to);
|
|
| 569 |
tcg_temp_free(r_tmp1);
|
|
| 568 |
gen_store_gpr(t0, to);
|
|
| 569 |
tcg_temp_free(t0);
|
|
| 570 | 570 |
} |
| 571 | 571 |
|
| 572 | 572 |
static inline void gen_store_srsgpr (int from, int to) |
| 573 | 573 |
{
|
| 574 | 574 |
if (to != 0) {
|
| 575 |
TCGv r_tmp1 = tcg_temp_new();
|
|
| 576 |
TCGv_i32 r_tmp2 = tcg_temp_new_i32();
|
|
| 575 |
TCGv t0 = tcg_temp_new();
|
|
| 576 |
TCGv_i32 t2 = tcg_temp_new_i32();
|
|
| 577 | 577 |
TCGv_ptr addr = tcg_temp_new_ptr(); |
| 578 | 578 |
|
| 579 |
gen_load_gpr(r_tmp1, from);
|
|
| 580 |
tcg_gen_ld_i32(r_tmp2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
|
|
| 581 |
tcg_gen_shri_i32(r_tmp2, r_tmp2, CP0SRSCtl_PSS);
|
|
| 582 |
tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xf);
|
|
| 583 |
tcg_gen_muli_i32(r_tmp2, r_tmp2, sizeof(target_ulong) * 32);
|
|
| 584 |
tcg_gen_ext_i32_ptr(addr, r_tmp2);
|
|
| 579 |
gen_load_gpr(t0, from);
|
|
| 580 |
tcg_gen_ld_i32(t2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
|
|
| 581 |
tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS);
|
|
| 582 |
tcg_gen_andi_i32(t2, t2, 0xf);
|
|
| 583 |
tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32);
|
|
| 584 |
tcg_gen_ext_i32_ptr(addr, t2);
|
|
| 585 | 585 |
tcg_gen_add_ptr(addr, cpu_env, addr); |
| 586 | 586 |
|
| 587 |
tcg_gen_st_tl(r_tmp1, addr, sizeof(target_ulong) * to);
|
|
| 587 |
tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to);
|
|
| 588 | 588 |
tcg_temp_free_ptr(addr); |
| 589 |
tcg_temp_free_i32(r_tmp2);
|
|
| 590 |
tcg_temp_free(r_tmp1);
|
|
| 589 |
tcg_temp_free_i32(t2);
|
|
| 590 |
tcg_temp_free(t0);
|
|
| 591 | 591 |
} |
| 592 | 592 |
} |
| 593 | 593 |
|
| ... | ... | |
| 887 | 887 |
} |
| 888 | 888 |
|
| 889 | 889 |
/* load/store instructions. */ |
| 890 |
#define OP_LD(insn,fname) \ |
|
| 891 |
static inline void op_ldst_##insn(TCGv t0, DisasContext *ctx) \
|
|
| 892 |
{ \
|
|
| 893 |
tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \
|
|
| 890 |
#define OP_LD(insn,fname) \
|
|
| 891 |
static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
|
|
| 892 |
{ \
|
|
| 893 |
tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
|
|
| 894 | 894 |
} |
| 895 | 895 |
OP_LD(lb,ld8s); |
| 896 | 896 |
OP_LD(lbu,ld8u); |
| ... | ... | |
| 903 | 903 |
#endif |
| 904 | 904 |
#undef OP_LD |
| 905 | 905 |
|
| 906 |
#define OP_ST(insn,fname) \ |
|
| 907 |
static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
|
|
| 908 |
{ \
|
|
| 909 |
tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
|
|
| 906 |
#define OP_ST(insn,fname) \
|
|
| 907 |
static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, DisasContext *ctx) \
|
|
| 908 |
{ \
|
|
| 909 |
tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \
|
|
| 910 | 910 |
} |
| 911 | 911 |
OP_ST(sb,st8); |
| 912 | 912 |
OP_ST(sh,st16); |
| ... | ... | |
| 916 | 916 |
#endif |
| 917 | 917 |
#undef OP_ST |
| 918 | 918 |
|
| 919 |
#define OP_LD_ATOMIC(insn,fname) \ |
|
| 920 |
static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \ |
|
| 921 |
{ \
|
|
| 922 |
tcg_gen_mov_tl(t1, t0); \ |
|
| 923 |
tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx); \ |
|
| 924 |
tcg_gen_st_tl(t1, cpu_env, offsetof(CPUState, CP0_LLAddr)); \ |
|
| 919 |
#define OP_LD_ATOMIC(insn,fname) \ |
|
| 920 |
static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \ |
|
| 921 |
{ \
|
|
| 922 |
TCGv t0 = tcg_temp_new(); \ |
|
| 923 |
tcg_gen_mov_tl(t0, arg1); \ |
|
| 924 |
tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \ |
|
| 925 |
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_LLAddr)); \ |
|
| 926 |
tcg_temp_free(t0); \ |
|
| 925 | 927 |
} |
| 926 | 928 |
OP_LD_ATOMIC(ll,ld32s); |
| 927 | 929 |
#if defined(TARGET_MIPS64) |
| ... | ... | |
| 929 | 931 |
#endif |
| 930 | 932 |
#undef OP_LD_ATOMIC |
| 931 | 933 |
|
| 932 |
#define OP_ST_ATOMIC(insn,fname,almask) \ |
|
| 933 |
static inline void op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx) \
|
|
| 934 |
{ \
|
|
| 935 |
TCGv r_tmp = tcg_temp_new(); \
|
|
| 936 |
int l1 = gen_new_label(); \ |
|
| 937 |
int l2 = gen_new_label(); \ |
|
| 938 |
int l3 = gen_new_label(); \ |
|
| 939 |
\ |
|
| 940 |
tcg_gen_andi_tl(r_tmp, t0, almask); \
|
|
| 941 |
tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp, 0, l1); \
|
|
| 942 |
tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
|
|
| 943 |
generate_exception(ctx, EXCP_AdES); \ |
|
| 944 |
gen_set_label(l1); \ |
|
| 945 |
tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
|
|
| 946 |
tcg_gen_brcond_tl(TCG_COND_NE, t0, r_tmp, l2); \
|
|
| 947 |
tcg_temp_free(r_tmp); \
|
|
| 948 |
tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx); \
|
|
| 949 |
tcg_gen_movi_tl(t0, 1); \
|
|
| 950 |
tcg_gen_br(l3); \ |
|
| 951 |
gen_set_label(l2); \ |
|
| 952 |
tcg_gen_movi_tl(t0, 0); \
|
|
| 953 |
gen_set_label(l3); \ |
|
| 934 |
#define OP_ST_ATOMIC(insn,fname,almask) \
|
|
| 935 |
static inline void op_ldst_##insn(TCGv ret, TCGv arg1, TCGv arg2, DisasContext *ctx) \
|
|
| 936 |
{ \
|
|
| 937 |
TCGv t0 = tcg_temp_new(); \
|
|
| 938 |
int l1 = gen_new_label(); \
|
|
| 939 |
int l2 = gen_new_label(); \
|
|
| 940 |
int l3 = gen_new_label(); \
|
|
| 941 |
\
|
|
| 942 |
tcg_gen_andi_tl(t0, arg2, almask); \
|
|
| 943 |
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \
|
|
| 944 |
tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
|
|
| 945 |
generate_exception(ctx, EXCP_AdES); \
|
|
| 946 |
gen_set_label(l1); \
|
|
| 947 |
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_LLAddr)); \
|
|
| 948 |
tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
|
|
| 949 |
tcg_temp_free(t0); \
|
|
| 950 |
tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \
|
|
| 951 |
tcg_gen_movi_tl(ret, 1); \
|
|
| 952 |
tcg_gen_br(l3); \
|
|
| 953 |
gen_set_label(l2); \
|
|
| 954 |
tcg_gen_movi_tl(ret, 0); \
|
|
| 955 |
gen_set_label(l3); \
|
|
| 954 | 956 |
} |
| 955 | 957 |
OP_ST_ATOMIC(sc,st32,0x3); |
| 956 | 958 |
#if defined(TARGET_MIPS64) |
| ... | ... | |
| 980 | 982 |
#if defined(TARGET_MIPS64) |
| 981 | 983 |
case OPC_LWU: |
| 982 | 984 |
save_cpu_state(ctx, 0); |
| 983 |
op_ldst_lwu(t0, ctx); |
|
| 985 |
op_ldst_lwu(t0, t0, ctx);
|
|
| 984 | 986 |
gen_store_gpr(t0, rt); |
| 985 | 987 |
opn = "lwu"; |
| 986 | 988 |
break; |
| 987 | 989 |
case OPC_LD: |
| 988 | 990 |
save_cpu_state(ctx, 0); |
| 989 |
op_ldst_ld(t0, ctx); |
|
| 991 |
op_ldst_ld(t0, t0, ctx);
|
|
| 990 | 992 |
gen_store_gpr(t0, rt); |
| 991 | 993 |
opn = "ld"; |
| 992 | 994 |
break; |
| 993 | 995 |
case OPC_LLD: |
| 994 | 996 |
save_cpu_state(ctx, 0); |
| 995 |
op_ldst_lld(t0, t1, ctx);
|
|
| 997 |
op_ldst_lld(t0, t0, ctx);
|
|
| 996 | 998 |
gen_store_gpr(t0, rt); |
| 997 | 999 |
opn = "lld"; |
| 998 | 1000 |
break; |
| 999 | 1001 |
case OPC_SD: |
| 1000 | 1002 |
save_cpu_state(ctx, 0); |
| 1001 | 1003 |
gen_load_gpr(t1, rt); |
| 1002 |
op_ldst_sd(t0, t1, ctx);
|
|
| 1004 |
op_ldst_sd(t1, t0, ctx);
|
|
| 1003 | 1005 |
opn = "sd"; |
| 1004 | 1006 |
break; |
| 1005 | 1007 |
case OPC_LDL: |
| 1006 | 1008 |
save_cpu_state(ctx, 1); |
| 1007 | 1009 |
gen_load_gpr(t1, rt); |
| 1008 |
gen_helper_3i(ldl, t1, t0, t1, ctx->mem_idx);
|
|
| 1010 |
gen_helper_3i(ldl, t1, t1, t0, ctx->mem_idx);
|
|
| 1009 | 1011 |
gen_store_gpr(t1, rt); |
| 1010 | 1012 |
opn = "ldl"; |
| 1011 | 1013 |
break; |
| 1012 | 1014 |
case OPC_SDL: |
| 1013 | 1015 |
save_cpu_state(ctx, 1); |
| 1014 | 1016 |
gen_load_gpr(t1, rt); |
| 1015 |
gen_helper_2i(sdl, t0, t1, ctx->mem_idx);
|
|
| 1017 |
gen_helper_2i(sdl, t1, t0, ctx->mem_idx);
|
|
| 1016 | 1018 |
opn = "sdl"; |
| 1017 | 1019 |
break; |
| 1018 | 1020 |
case OPC_LDR: |
| 1019 | 1021 |
save_cpu_state(ctx, 1); |
| 1020 | 1022 |
gen_load_gpr(t1, rt); |
| 1021 |
gen_helper_3i(ldr, t1, t0, t1, ctx->mem_idx);
|
|
| 1023 |
gen_helper_3i(ldr, t1, t1, t0, ctx->mem_idx);
|
|
| 1022 | 1024 |
gen_store_gpr(t1, rt); |
| 1023 | 1025 |
opn = "ldr"; |
| 1024 | 1026 |
break; |
| 1025 | 1027 |
case OPC_SDR: |
| 1026 | 1028 |
save_cpu_state(ctx, 1); |
| 1027 | 1029 |
gen_load_gpr(t1, rt); |
| 1028 |
gen_helper_2i(sdr, t0, t1, ctx->mem_idx);
|
|
| 1030 |
gen_helper_2i(sdr, t1, t0, ctx->mem_idx);
|
|
| 1029 | 1031 |
opn = "sdr"; |
| 1030 | 1032 |
break; |
| 1031 | 1033 |
#endif |
| 1032 | 1034 |
case OPC_LW: |
| 1033 | 1035 |
save_cpu_state(ctx, 0); |
| 1034 |
op_ldst_lw(t0, ctx); |
|
| 1036 |
op_ldst_lw(t0, t0, ctx);
|
|
| 1035 | 1037 |
gen_store_gpr(t0, rt); |
| 1036 | 1038 |
opn = "lw"; |
| 1037 | 1039 |
break; |
| 1038 | 1040 |
case OPC_SW: |
| 1039 | 1041 |
save_cpu_state(ctx, 0); |
| 1040 | 1042 |
gen_load_gpr(t1, rt); |
| 1041 |
op_ldst_sw(t0, t1, ctx);
|
|
| 1043 |
op_ldst_sw(t1, t0, ctx);
|
|
| 1042 | 1044 |
opn = "sw"; |
| 1043 | 1045 |
break; |
| 1044 | 1046 |
case OPC_LH: |
| 1045 | 1047 |
save_cpu_state(ctx, 0); |
| 1046 |
op_ldst_lh(t0, ctx); |
|
| 1048 |
op_ldst_lh(t0, t0, ctx);
|
|
| 1047 | 1049 |
gen_store_gpr(t0, rt); |
| 1048 | 1050 |
opn = "lh"; |
| 1049 | 1051 |
break; |
| 1050 | 1052 |
case OPC_SH: |
| 1051 | 1053 |
save_cpu_state(ctx, 0); |
| 1052 | 1054 |
gen_load_gpr(t1, rt); |
| 1053 |
op_ldst_sh(t0, t1, ctx);
|
|
| 1055 |
op_ldst_sh(t1, t0, ctx);
|
|
| 1054 | 1056 |
opn = "sh"; |
| 1055 | 1057 |
break; |
| 1056 | 1058 |
case OPC_LHU: |
| 1057 | 1059 |
save_cpu_state(ctx, 0); |
| 1058 |
op_ldst_lhu(t0, ctx); |
|
| 1060 |
op_ldst_lhu(t0, t0, ctx);
|
|
| 1059 | 1061 |
gen_store_gpr(t0, rt); |
| 1060 | 1062 |
opn = "lhu"; |
| 1061 | 1063 |
break; |
| 1062 | 1064 |
case OPC_LB: |
| 1063 | 1065 |
save_cpu_state(ctx, 0); |
| 1064 |
op_ldst_lb(t0, ctx); |
|
| 1066 |
op_ldst_lb(t0, t0, ctx);
|
|
| 1065 | 1067 |
gen_store_gpr(t0, rt); |
| 1066 | 1068 |
opn = "lb"; |
| 1067 | 1069 |
break; |
| 1068 | 1070 |
case OPC_SB: |
| 1069 | 1071 |
save_cpu_state(ctx, 0); |
| 1070 | 1072 |
gen_load_gpr(t1, rt); |
| 1071 |
op_ldst_sb(t0, t1, ctx);
|
|
| 1073 |
op_ldst_sb(t1, t0, ctx);
|
|
| 1072 | 1074 |
opn = "sb"; |
| 1073 | 1075 |
break; |
| 1074 | 1076 |
case OPC_LBU: |
| 1075 | 1077 |
save_cpu_state(ctx, 0); |
| 1076 |
op_ldst_lbu(t0, ctx); |
|
| 1078 |
op_ldst_lbu(t0, t0, ctx);
|
|
| 1077 | 1079 |
gen_store_gpr(t0, rt); |
| 1078 | 1080 |
opn = "lbu"; |
| 1079 | 1081 |
break; |
| 1080 | 1082 |
case OPC_LWL: |
| 1081 | 1083 |
save_cpu_state(ctx, 1); |
| 1082 | 1084 |
gen_load_gpr(t1, rt); |
| 1083 |
gen_helper_3i(lwl, t1, t0, t1, ctx->mem_idx);
|
|
| 1085 |
gen_helper_3i(lwl, t1, t1, t0, ctx->mem_idx);
|
|
| 1084 | 1086 |
gen_store_gpr(t1, rt); |
| 1085 | 1087 |
opn = "lwl"; |
| 1086 | 1088 |
break; |
| 1087 | 1089 |
case OPC_SWL: |
| 1088 | 1090 |
save_cpu_state(ctx, 1); |
| 1089 | 1091 |
gen_load_gpr(t1, rt); |
| 1090 |
gen_helper_2i(swl, t0, t1, ctx->mem_idx);
|
|
| 1092 |
gen_helper_2i(swl, t1, t0, ctx->mem_idx);
|
|
| 1091 | 1093 |
opn = "swr"; |
| 1092 | 1094 |
break; |
| 1093 | 1095 |
case OPC_LWR: |
| 1094 | 1096 |
save_cpu_state(ctx, 1); |
| 1095 | 1097 |
gen_load_gpr(t1, rt); |
| 1096 |
gen_helper_3i(lwr, t1, t0, t1, ctx->mem_idx);
|
|
| 1098 |
gen_helper_3i(lwr, t1, t1, t0, ctx->mem_idx);
|
|
| 1097 | 1099 |
gen_store_gpr(t1, rt); |
| 1098 | 1100 |
opn = "lwr"; |
| 1099 | 1101 |
break; |
| 1100 | 1102 |
case OPC_SWR: |
| 1101 | 1103 |
save_cpu_state(ctx, 1); |
| 1102 | 1104 |
gen_load_gpr(t1, rt); |
| 1103 |
gen_helper_2i(swr, t0, t1, ctx->mem_idx);
|
|
| 1105 |
gen_helper_2i(swr, t1, t0, ctx->mem_idx);
|
|
| 1104 | 1106 |
opn = "swr"; |
| 1105 | 1107 |
break; |
| 1106 | 1108 |
case OPC_LL: |
| 1107 | 1109 |
save_cpu_state(ctx, 0); |
| 1108 |
op_ldst_ll(t0, t1, ctx);
|
|
| 1110 |
op_ldst_ll(t0, t0, ctx);
|
|
| 1109 | 1111 |
gen_store_gpr(t0, rt); |
| 1110 | 1112 |
opn = "ll"; |
| 1111 | 1113 |
break; |
| ... | ... | |
| 1141 | 1143 |
#if defined(TARGET_MIPS64) |
| 1142 | 1144 |
case OPC_SCD: |
| 1143 | 1145 |
save_cpu_state(ctx, 0); |
| 1144 |
op_ldst_scd(t0, t1, ctx); |
|
| 1146 |
op_ldst_scd(t0, t1, t0, ctx);
|
|
| 1145 | 1147 |
opn = "scd"; |
| 1146 | 1148 |
break; |
| 1147 | 1149 |
#endif |
| 1148 | 1150 |
case OPC_SC: |
| 1149 | 1151 |
save_cpu_state(ctx, 0); |
| 1150 |
op_ldst_sc(t0, t1, ctx); |
|
| 1152 |
op_ldst_sc(t0, t1, t0, ctx);
|
|
| 1151 | 1153 |
opn = "sc"; |
| 1152 | 1154 |
break; |
| 1153 | 1155 |
} |
| ... | ... | |
| 1430 | 1432 |
/* rotr is decoded as srl on non-R2 CPUs */ |
| 1431 | 1433 |
if (env->insn_flags & ISA_MIPS32R2) {
|
| 1432 | 1434 |
if (uimm != 0) {
|
| 1433 |
TCGv_i32 r_tmp1 = tcg_temp_new_i32();
|
|
| 1435 |
TCGv_i32 t1 = tcg_temp_new_i32();
|
|
| 1434 | 1436 |
|
| 1435 |
tcg_gen_trunc_tl_i32(r_tmp1, t0);
|
|
| 1436 |
tcg_gen_rotri_i32(r_tmp1, r_tmp1, uimm);
|
|
| 1437 |
tcg_gen_ext_i32_tl(cpu_gpr[rt], r_tmp1);
|
|
| 1438 |
tcg_temp_free_i32(r_tmp1);
|
|
| 1437 |
tcg_gen_trunc_tl_i32(t1, t0);
|
|
| 1438 |
tcg_gen_rotri_i32(t1, t1, uimm);
|
|
| 1439 |
tcg_gen_ext_i32_tl(cpu_gpr[rt], t1);
|
|
| 1440 |
tcg_temp_free_i32(t1);
|
|
| 1439 | 1441 |
} |
| 1440 | 1442 |
opn = "rotr"; |
| 1441 | 1443 |
} else {
|
| ... | ... | |
| 2840 | 2842 |
|
| 2841 | 2843 |
#ifndef CONFIG_USER_ONLY |
| 2842 | 2844 |
/* CP0 (MMU and control) */ |
| 2843 |
static inline void gen_mfc0_load32 (TCGv t, target_ulong off)
|
|
| 2845 |
static inline void gen_mfc0_load32 (TCGv arg, target_ulong off)
|
|
| 2844 | 2846 |
{
|
| 2845 |
TCGv_i32 r_tmp = tcg_temp_new_i32();
|
|
| 2847 |
TCGv_i32 t0 = tcg_temp_new_i32();
|
|
| 2846 | 2848 |
|
| 2847 |
tcg_gen_ld_i32(r_tmp, cpu_env, off);
|
|
| 2848 |
tcg_gen_ext_i32_tl(t, r_tmp);
|
|
| 2849 |
tcg_temp_free_i32(r_tmp);
|
|
| 2849 |
tcg_gen_ld_i32(t0, cpu_env, off);
|
|
| 2850 |
tcg_gen_ext_i32_tl(arg, t0);
|
|
| 2851 |
tcg_temp_free_i32(t0);
|
|
| 2850 | 2852 |
} |
| 2851 | 2853 |
|
| 2852 |
static inline void gen_mfc0_load64 (TCGv t, target_ulong off)
|
|
| 2854 |
static inline void gen_mfc0_load64 (TCGv arg, target_ulong off)
|
|
| 2853 | 2855 |
{
|
| 2854 |
tcg_gen_ld_tl(t, cpu_env, off);
|
|
| 2855 |
tcg_gen_ext32s_tl(t, t);
|
|
| 2856 |
tcg_gen_ld_tl(arg, cpu_env, off);
|
|
| 2857 |
tcg_gen_ext32s_tl(arg, arg);
|
|
| 2856 | 2858 |
} |
| 2857 | 2859 |
|
| 2858 |
static inline void gen_mtc0_store32 (TCGv t, target_ulong off)
|
|
| 2860 |
static inline void gen_mtc0_store32 (TCGv arg, target_ulong off)
|
|
| 2859 | 2861 |
{
|
| 2860 |
TCGv_i32 r_tmp = tcg_temp_new_i32();
|
|
| 2862 |
TCGv_i32 t0 = tcg_temp_new_i32();
|
|
| 2861 | 2863 |
|
| 2862 |
tcg_gen_trunc_tl_i32(r_tmp, t);
|
|
| 2863 |
tcg_gen_st_i32(r_tmp, cpu_env, off);
|
|
| 2864 |
tcg_temp_free_i32(r_tmp);
|
|
| 2864 |
tcg_gen_trunc_tl_i32(t0, arg);
|
|
| 2865 |
tcg_gen_st_i32(t0, cpu_env, off);
|
|
| 2866 |
tcg_temp_free_i32(t0);
|
|
| 2865 | 2867 |
} |
| 2866 | 2868 |
|
| 2867 |
static inline void gen_mtc0_store64 (TCGv t, target_ulong off)
|
|
| 2869 |
static inline void gen_mtc0_store64 (TCGv arg, target_ulong off)
|
|
| 2868 | 2870 |
{
|
| 2869 |
tcg_gen_ext32s_tl(t, t);
|
|
| 2870 |
tcg_gen_st_tl(t, cpu_env, off);
|
|
| 2871 |
tcg_gen_ext32s_tl(arg, arg);
|
|
| 2872 |
tcg_gen_st_tl(arg, cpu_env, off);
|
|
| 2871 | 2873 |
} |
| 2872 | 2874 |
|
| 2873 |
static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
|
|
| 2875 |
static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
|
|
| 2874 | 2876 |
{
|
| 2875 | 2877 |
const char *rn = "invalid"; |
| 2876 | 2878 |
|
| ... | ... | |
| 2881 | 2883 |
case 0: |
| 2882 | 2884 |
switch (sel) {
|
| 2883 | 2885 |
case 0: |
| 2884 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_Index));
|
|
| 2886 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_Index));
|
|
| 2885 | 2887 |
rn = "Index"; |
| 2886 | 2888 |
break; |
| 2887 | 2889 |
case 1: |
| 2888 | 2890 |
check_insn(env, ctx, ASE_MT); |
| 2889 |
gen_helper_mfc0_mvpcontrol(t0);
|
|
| 2891 |
gen_helper_mfc0_mvpcontrol(arg);
|
|
| 2890 | 2892 |
rn = "MVPControl"; |
| 2891 | 2893 |
break; |
| 2892 | 2894 |
case 2: |
| 2893 | 2895 |
check_insn(env, ctx, ASE_MT); |
| 2894 |
gen_helper_mfc0_mvpconf0(t0);
|
|
| 2896 |
gen_helper_mfc0_mvpconf0(arg);
|
|
| 2895 | 2897 |
rn = "MVPConf0"; |
| 2896 | 2898 |
break; |
| 2897 | 2899 |
case 3: |
| 2898 | 2900 |
check_insn(env, ctx, ASE_MT); |
| 2899 |
gen_helper_mfc0_mvpconf1(t0);
|
|
| 2901 |
gen_helper_mfc0_mvpconf1(arg);
|
|
| 2900 | 2902 |
rn = "MVPConf1"; |
| 2901 | 2903 |
break; |
| 2902 | 2904 |
default: |
| ... | ... | |
| 2906 | 2908 |
case 1: |
| 2907 | 2909 |
switch (sel) {
|
| 2908 | 2910 |
case 0: |
| 2909 |
gen_helper_mfc0_random(t0);
|
|
| 2911 |
gen_helper_mfc0_random(arg);
|
|
| 2910 | 2912 |
rn = "Random"; |
| 2911 | 2913 |
break; |
| 2912 | 2914 |
case 1: |
| 2913 | 2915 |
check_insn(env, ctx, ASE_MT); |
| 2914 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEControl));
|
|
| 2916 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEControl));
|
|
| 2915 | 2917 |
rn = "VPEControl"; |
| 2916 | 2918 |
break; |
| 2917 | 2919 |
case 2: |
| 2918 | 2920 |
check_insn(env, ctx, ASE_MT); |
| 2919 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf0));
|
|
| 2921 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf0));
|
|
| 2920 | 2922 |
rn = "VPEConf0"; |
| 2921 | 2923 |
break; |
| 2922 | 2924 |
case 3: |
| 2923 | 2925 |
check_insn(env, ctx, ASE_MT); |
| 2924 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEConf1));
|
|
| 2926 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEConf1));
|
|
| 2925 | 2927 |
rn = "VPEConf1"; |
| 2926 | 2928 |
break; |
| 2927 | 2929 |
case 4: |
| 2928 | 2930 |
check_insn(env, ctx, ASE_MT); |
| 2929 |
gen_mfc0_load64(t0, offsetof(CPUState, CP0_YQMask));
|
|
| 2931 |
gen_mfc0_load64(arg, offsetof(CPUState, CP0_YQMask));
|
|
| 2930 | 2932 |
rn = "YQMask"; |
| 2931 | 2933 |
break; |
| 2932 | 2934 |
case 5: |
| 2933 | 2935 |
check_insn(env, ctx, ASE_MT); |
| 2934 |
gen_mfc0_load64(t0, offsetof(CPUState, CP0_VPESchedule));
|
|
| 2936 |
gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPESchedule));
|
|
| 2935 | 2937 |
rn = "VPESchedule"; |
| 2936 | 2938 |
break; |
| 2937 | 2939 |
case 6: |
| 2938 | 2940 |
check_insn(env, ctx, ASE_MT); |
| 2939 |
gen_mfc0_load64(t0, offsetof(CPUState, CP0_VPEScheFBack));
|
|
| 2941 |
gen_mfc0_load64(arg, offsetof(CPUState, CP0_VPEScheFBack));
|
|
| 2940 | 2942 |
rn = "VPEScheFBack"; |
| 2941 | 2943 |
break; |
| 2942 | 2944 |
case 7: |
| 2943 | 2945 |
check_insn(env, ctx, ASE_MT); |
| 2944 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_VPEOpt));
|
|
| 2946 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_VPEOpt));
|
|
| 2945 | 2947 |
rn = "VPEOpt"; |
| 2946 | 2948 |
break; |
| 2947 | 2949 |
default: |
| ... | ... | |
| 2951 | 2953 |
case 2: |
| 2952 | 2954 |
switch (sel) {
|
| 2953 | 2955 |
case 0: |
| 2954 |
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo0));
|
|
| 2955 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 2956 |
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo0));
|
|
| 2957 |
tcg_gen_ext32s_tl(arg, arg);
|
|
| 2956 | 2958 |
rn = "EntryLo0"; |
| 2957 | 2959 |
break; |
| 2958 | 2960 |
case 1: |
| 2959 | 2961 |
check_insn(env, ctx, ASE_MT); |
| 2960 |
gen_helper_mfc0_tcstatus(t0);
|
|
| 2962 |
gen_helper_mfc0_tcstatus(arg);
|
|
| 2961 | 2963 |
rn = "TCStatus"; |
| 2962 | 2964 |
break; |
| 2963 | 2965 |
case 2: |
| 2964 | 2966 |
check_insn(env, ctx, ASE_MT); |
| 2965 |
gen_helper_mfc0_tcbind(t0);
|
|
| 2967 |
gen_helper_mfc0_tcbind(arg);
|
|
| 2966 | 2968 |
rn = "TCBind"; |
| 2967 | 2969 |
break; |
| 2968 | 2970 |
case 3: |
| 2969 | 2971 |
check_insn(env, ctx, ASE_MT); |
| 2970 |
gen_helper_mfc0_tcrestart(t0);
|
|
| 2972 |
gen_helper_mfc0_tcrestart(arg);
|
|
| 2971 | 2973 |
rn = "TCRestart"; |
| 2972 | 2974 |
break; |
| 2973 | 2975 |
case 4: |
| 2974 | 2976 |
check_insn(env, ctx, ASE_MT); |
| 2975 |
gen_helper_mfc0_tchalt(t0);
|
|
| 2977 |
gen_helper_mfc0_tchalt(arg);
|
|
| 2976 | 2978 |
rn = "TCHalt"; |
| 2977 | 2979 |
break; |
| 2978 | 2980 |
case 5: |
| 2979 | 2981 |
check_insn(env, ctx, ASE_MT); |
| 2980 |
gen_helper_mfc0_tccontext(t0);
|
|
| 2982 |
gen_helper_mfc0_tccontext(arg);
|
|
| 2981 | 2983 |
rn = "TCContext"; |
| 2982 | 2984 |
break; |
| 2983 | 2985 |
case 6: |
| 2984 | 2986 |
check_insn(env, ctx, ASE_MT); |
| 2985 |
gen_helper_mfc0_tcschedule(t0);
|
|
| 2987 |
gen_helper_mfc0_tcschedule(arg);
|
|
| 2986 | 2988 |
rn = "TCSchedule"; |
| 2987 | 2989 |
break; |
| 2988 | 2990 |
case 7: |
| 2989 | 2991 |
check_insn(env, ctx, ASE_MT); |
| 2990 |
gen_helper_mfc0_tcschefback(t0);
|
|
| 2992 |
gen_helper_mfc0_tcschefback(arg);
|
|
| 2991 | 2993 |
rn = "TCScheFBack"; |
| 2992 | 2994 |
break; |
| 2993 | 2995 |
default: |
| ... | ... | |
| 2997 | 2999 |
case 3: |
| 2998 | 3000 |
switch (sel) {
|
| 2999 | 3001 |
case 0: |
| 3000 |
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryLo1));
|
|
| 3001 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 3002 |
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryLo1));
|
|
| 3003 |
tcg_gen_ext32s_tl(arg, arg);
|
|
| 3002 | 3004 |
rn = "EntryLo1"; |
| 3003 | 3005 |
break; |
| 3004 | 3006 |
default: |
| ... | ... | |
| 3008 | 3010 |
case 4: |
| 3009 | 3011 |
switch (sel) {
|
| 3010 | 3012 |
case 0: |
| 3011 |
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_Context));
|
|
| 3012 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 3013 |
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_Context));
|
|
| 3014 |
tcg_gen_ext32s_tl(arg, arg);
|
|
| 3013 | 3015 |
rn = "Context"; |
| 3014 | 3016 |
break; |
| 3015 | 3017 |
case 1: |
| 3016 |
// gen_helper_mfc0_contextconfig(t0); /* SmartMIPS ASE */
|
|
| 3018 |
// gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */
|
|
| 3017 | 3019 |
rn = "ContextConfig"; |
| 3018 | 3020 |
// break; |
| 3019 | 3021 |
default: |
| ... | ... | |
| 3023 | 3025 |
case 5: |
| 3024 | 3026 |
switch (sel) {
|
| 3025 | 3027 |
case 0: |
| 3026 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageMask));
|
|
| 3028 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageMask));
|
|
| 3027 | 3029 |
rn = "PageMask"; |
| 3028 | 3030 |
break; |
| 3029 | 3031 |
case 1: |
| 3030 | 3032 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3031 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_PageGrain));
|
|
| 3033 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_PageGrain));
|
|
| 3032 | 3034 |
rn = "PageGrain"; |
| 3033 | 3035 |
break; |
| 3034 | 3036 |
default: |
| ... | ... | |
| 3038 | 3040 |
case 6: |
| 3039 | 3041 |
switch (sel) {
|
| 3040 | 3042 |
case 0: |
| 3041 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_Wired));
|
|
| 3043 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_Wired));
|
|
| 3042 | 3044 |
rn = "Wired"; |
| 3043 | 3045 |
break; |
| 3044 | 3046 |
case 1: |
| 3045 | 3047 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3046 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf0));
|
|
| 3048 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf0));
|
|
| 3047 | 3049 |
rn = "SRSConf0"; |
| 3048 | 3050 |
break; |
| 3049 | 3051 |
case 2: |
| 3050 | 3052 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3051 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf1));
|
|
| 3053 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf1));
|
|
| 3052 | 3054 |
rn = "SRSConf1"; |
| 3053 | 3055 |
break; |
| 3054 | 3056 |
case 3: |
| 3055 | 3057 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3056 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf2));
|
|
| 3058 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf2));
|
|
| 3057 | 3059 |
rn = "SRSConf2"; |
| 3058 | 3060 |
break; |
| 3059 | 3061 |
case 4: |
| 3060 | 3062 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3061 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf3));
|
|
| 3063 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf3));
|
|
| 3062 | 3064 |
rn = "SRSConf3"; |
| 3063 | 3065 |
break; |
| 3064 | 3066 |
case 5: |
| 3065 | 3067 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3066 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSConf4));
|
|
| 3068 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSConf4));
|
|
| 3067 | 3069 |
rn = "SRSConf4"; |
| 3068 | 3070 |
break; |
| 3069 | 3071 |
default: |
| ... | ... | |
| 3074 | 3076 |
switch (sel) {
|
| 3075 | 3077 |
case 0: |
| 3076 | 3078 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3077 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_HWREna));
|
|
| 3079 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_HWREna));
|
|
| 3078 | 3080 |
rn = "HWREna"; |
| 3079 | 3081 |
break; |
| 3080 | 3082 |
default: |
| ... | ... | |
| 3084 | 3086 |
case 8: |
| 3085 | 3087 |
switch (sel) {
|
| 3086 | 3088 |
case 0: |
| 3087 |
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr));
|
|
| 3088 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 3089 |
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_BadVAddr));
|
|
| 3090 |
tcg_gen_ext32s_tl(arg, arg);
|
|
| 3089 | 3091 |
rn = "BadVAddr"; |
| 3090 | 3092 |
break; |
| 3091 | 3093 |
default: |
| ... | ... | |
| 3098 | 3100 |
/* Mark as an IO operation because we read the time. */ |
| 3099 | 3101 |
if (use_icount) |
| 3100 | 3102 |
gen_io_start(); |
| 3101 |
gen_helper_mfc0_count(t0);
|
|
| 3103 |
gen_helper_mfc0_count(arg);
|
|
| 3102 | 3104 |
if (use_icount) {
|
| 3103 | 3105 |
gen_io_end(); |
| 3104 | 3106 |
ctx->bstate = BS_STOP; |
| ... | ... | |
| 3113 | 3115 |
case 10: |
| 3114 | 3116 |
switch (sel) {
|
| 3115 | 3117 |
case 0: |
| 3116 |
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EntryHi));
|
|
| 3117 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 3118 |
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EntryHi));
|
|
| 3119 |
tcg_gen_ext32s_tl(arg, arg);
|
|
| 3118 | 3120 |
rn = "EntryHi"; |
| 3119 | 3121 |
break; |
| 3120 | 3122 |
default: |
| ... | ... | |
| 3124 | 3126 |
case 11: |
| 3125 | 3127 |
switch (sel) {
|
| 3126 | 3128 |
case 0: |
| 3127 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_Compare));
|
|
| 3129 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_Compare));
|
|
| 3128 | 3130 |
rn = "Compare"; |
| 3129 | 3131 |
break; |
| 3130 | 3132 |
/* 6,7 are implementation dependent */ |
| ... | ... | |
| 3135 | 3137 |
case 12: |
| 3136 | 3138 |
switch (sel) {
|
| 3137 | 3139 |
case 0: |
| 3138 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_Status));
|
|
| 3140 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_Status));
|
|
| 3139 | 3141 |
rn = "Status"; |
| 3140 | 3142 |
break; |
| 3141 | 3143 |
case 1: |
| 3142 | 3144 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3143 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_IntCtl));
|
|
| 3145 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_IntCtl));
|
|
| 3144 | 3146 |
rn = "IntCtl"; |
| 3145 | 3147 |
break; |
| 3146 | 3148 |
case 2: |
| 3147 | 3149 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3148 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSCtl));
|
|
| 3150 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSCtl));
|
|
| 3149 | 3151 |
rn = "SRSCtl"; |
| 3150 | 3152 |
break; |
| 3151 | 3153 |
case 3: |
| 3152 | 3154 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3153 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_SRSMap));
|
|
| 3155 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_SRSMap));
|
|
| 3154 | 3156 |
rn = "SRSMap"; |
| 3155 | 3157 |
break; |
| 3156 | 3158 |
default: |
| ... | ... | |
| 3160 | 3162 |
case 13: |
| 3161 | 3163 |
switch (sel) {
|
| 3162 | 3164 |
case 0: |
| 3163 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_Cause));
|
|
| 3165 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_Cause));
|
|
| 3164 | 3166 |
rn = "Cause"; |
| 3165 | 3167 |
break; |
| 3166 | 3168 |
default: |
| ... | ... | |
| 3170 | 3172 |
case 14: |
| 3171 | 3173 |
switch (sel) {
|
| 3172 | 3174 |
case 0: |
| 3173 |
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_EPC));
|
|
| 3174 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 3175 |
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_EPC));
|
|
| 3176 |
tcg_gen_ext32s_tl(arg, arg);
|
|
| 3175 | 3177 |
rn = "EPC"; |
| 3176 | 3178 |
break; |
| 3177 | 3179 |
default: |
| ... | ... | |
| 3181 | 3183 |
case 15: |
| 3182 | 3184 |
switch (sel) {
|
| 3183 | 3185 |
case 0: |
| 3184 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_PRid));
|
|
| 3186 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_PRid));
|
|
| 3185 | 3187 |
rn = "PRid"; |
| 3186 | 3188 |
break; |
| 3187 | 3189 |
case 1: |
| 3188 | 3190 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3189 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_EBase));
|
|
| 3191 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_EBase));
|
|
| 3190 | 3192 |
rn = "EBase"; |
| 3191 | 3193 |
break; |
| 3192 | 3194 |
default: |
| ... | ... | |
| 3196 | 3198 |
case 16: |
| 3197 | 3199 |
switch (sel) {
|
| 3198 | 3200 |
case 0: |
| 3199 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config0));
|
|
| 3201 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config0));
|
|
| 3200 | 3202 |
rn = "Config"; |
| 3201 | 3203 |
break; |
| 3202 | 3204 |
case 1: |
| 3203 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config1));
|
|
| 3205 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config1));
|
|
| 3204 | 3206 |
rn = "Config1"; |
| 3205 | 3207 |
break; |
| 3206 | 3208 |
case 2: |
| 3207 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config2));
|
|
| 3209 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config2));
|
|
| 3208 | 3210 |
rn = "Config2"; |
| 3209 | 3211 |
break; |
| 3210 | 3212 |
case 3: |
| 3211 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config3));
|
|
| 3213 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config3));
|
|
| 3212 | 3214 |
rn = "Config3"; |
| 3213 | 3215 |
break; |
| 3214 | 3216 |
/* 4,5 are reserved */ |
| 3215 | 3217 |
/* 6,7 are implementation dependent */ |
| 3216 | 3218 |
case 6: |
| 3217 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config6));
|
|
| 3219 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config6));
|
|
| 3218 | 3220 |
rn = "Config6"; |
| 3219 | 3221 |
break; |
| 3220 | 3222 |
case 7: |
| 3221 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_Config7));
|
|
| 3223 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_Config7));
|
|
| 3222 | 3224 |
rn = "Config7"; |
| 3223 | 3225 |
break; |
| 3224 | 3226 |
default: |
| ... | ... | |
| 3228 | 3230 |
case 17: |
| 3229 | 3231 |
switch (sel) {
|
| 3230 | 3232 |
case 0: |
| 3231 |
gen_helper_mfc0_lladdr(t0);
|
|
| 3233 |
gen_helper_mfc0_lladdr(arg);
|
|
| 3232 | 3234 |
rn = "LLAddr"; |
| 3233 | 3235 |
break; |
| 3234 | 3236 |
default: |
| ... | ... | |
| 3238 | 3240 |
case 18: |
| 3239 | 3241 |
switch (sel) {
|
| 3240 | 3242 |
case 0 ... 7: |
| 3241 |
gen_helper_1i(mfc0_watchlo, t0, sel);
|
|
| 3243 |
gen_helper_1i(mfc0_watchlo, arg, sel);
|
|
| 3242 | 3244 |
rn = "WatchLo"; |
| 3243 | 3245 |
break; |
| 3244 | 3246 |
default: |
| ... | ... | |
| 3248 | 3250 |
case 19: |
| 3249 | 3251 |
switch (sel) {
|
| 3250 | 3252 |
case 0 ...7: |
| 3251 |
gen_helper_1i(mfc0_watchhi, t0, sel);
|
|
| 3253 |
gen_helper_1i(mfc0_watchhi, arg, sel);
|
|
| 3252 | 3254 |
rn = "WatchHi"; |
| 3253 | 3255 |
break; |
| 3254 | 3256 |
default: |
| ... | ... | |
| 3260 | 3262 |
case 0: |
| 3261 | 3263 |
#if defined(TARGET_MIPS64) |
| 3262 | 3264 |
check_insn(env, ctx, ISA_MIPS3); |
| 3263 |
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_XContext));
|
|
| 3264 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 3265 |
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_XContext));
|
|
| 3266 |
tcg_gen_ext32s_tl(arg, arg);
|
|
| 3265 | 3267 |
rn = "XContext"; |
| 3266 | 3268 |
break; |
| 3267 | 3269 |
#endif |
| ... | ... | |
| 3273 | 3275 |
/* Officially reserved, but sel 0 is used for R1x000 framemask */ |
| 3274 | 3276 |
switch (sel) {
|
| 3275 | 3277 |
case 0: |
| 3276 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_Framemask));
|
|
| 3278 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_Framemask));
|
|
| 3277 | 3279 |
rn = "Framemask"; |
| 3278 | 3280 |
break; |
| 3279 | 3281 |
default: |
| ... | ... | |
| 3281 | 3283 |
} |
| 3282 | 3284 |
break; |
| 3283 | 3285 |
case 22: |
| 3284 |
tcg_gen_movi_tl(t0, 0); /* unimplemented */
|
|
| 3286 |
tcg_gen_movi_tl(arg, 0); /* unimplemented */
|
|
| 3285 | 3287 |
rn = "'Diagnostic"; /* implementation dependent */ |
| 3286 | 3288 |
break; |
| 3287 | 3289 |
case 23: |
| 3288 | 3290 |
switch (sel) {
|
| 3289 | 3291 |
case 0: |
| 3290 |
gen_helper_mfc0_debug(t0); /* EJTAG support */
|
|
| 3292 |
gen_helper_mfc0_debug(arg); /* EJTAG support */
|
|
| 3291 | 3293 |
rn = "Debug"; |
| 3292 | 3294 |
break; |
| 3293 | 3295 |
case 1: |
| 3294 |
// gen_helper_mfc0_tracecontrol(t0); /* PDtrace support */
|
|
| 3296 |
// gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
|
|
| 3295 | 3297 |
rn = "TraceControl"; |
| 3296 | 3298 |
// break; |
| 3297 | 3299 |
case 2: |
| 3298 |
// gen_helper_mfc0_tracecontrol2(t0); /* PDtrace support */
|
|
| 3300 |
// gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
|
|
| 3299 | 3301 |
rn = "TraceControl2"; |
| 3300 | 3302 |
// break; |
| 3301 | 3303 |
case 3: |
| 3302 |
// gen_helper_mfc0_usertracedata(t0); /* PDtrace support */
|
|
| 3304 |
// gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
|
|
| 3303 | 3305 |
rn = "UserTraceData"; |
| 3304 | 3306 |
// break; |
| 3305 | 3307 |
case 4: |
| 3306 |
// gen_helper_mfc0_tracebpc(t0); /* PDtrace support */
|
|
| 3308 |
// gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
|
|
| 3307 | 3309 |
rn = "TraceBPC"; |
| 3308 | 3310 |
// break; |
| 3309 | 3311 |
default: |
| ... | ... | |
| 3314 | 3316 |
switch (sel) {
|
| 3315 | 3317 |
case 0: |
| 3316 | 3318 |
/* EJTAG support */ |
| 3317 |
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_DEPC));
|
|
| 3318 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 3319 |
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_DEPC));
|
|
| 3320 |
tcg_gen_ext32s_tl(arg, arg);
|
|
| 3319 | 3321 |
rn = "DEPC"; |
| 3320 | 3322 |
break; |
| 3321 | 3323 |
default: |
| ... | ... | |
| 3325 | 3327 |
case 25: |
| 3326 | 3328 |
switch (sel) {
|
| 3327 | 3329 |
case 0: |
| 3328 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_Performance0));
|
|
| 3330 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_Performance0));
|
|
| 3329 | 3331 |
rn = "Performance0"; |
| 3330 | 3332 |
break; |
| 3331 | 3333 |
case 1: |
| 3332 |
// gen_helper_mfc0_performance1(t0);
|
|
| 3334 |
// gen_helper_mfc0_performance1(arg);
|
|
| 3333 | 3335 |
rn = "Performance1"; |
| 3334 | 3336 |
// break; |
| 3335 | 3337 |
case 2: |
| 3336 |
// gen_helper_mfc0_performance2(t0);
|
|
| 3338 |
// gen_helper_mfc0_performance2(arg);
|
|
| 3337 | 3339 |
rn = "Performance2"; |
| 3338 | 3340 |
// break; |
| 3339 | 3341 |
case 3: |
| 3340 |
// gen_helper_mfc0_performance3(t0);
|
|
| 3342 |
// gen_helper_mfc0_performance3(arg);
|
|
| 3341 | 3343 |
rn = "Performance3"; |
| 3342 | 3344 |
// break; |
| 3343 | 3345 |
case 4: |
| 3344 |
// gen_helper_mfc0_performance4(t0);
|
|
| 3346 |
// gen_helper_mfc0_performance4(arg);
|
|
| 3345 | 3347 |
rn = "Performance4"; |
| 3346 | 3348 |
// break; |
| 3347 | 3349 |
case 5: |
| 3348 |
// gen_helper_mfc0_performance5(t0);
|
|
| 3350 |
// gen_helper_mfc0_performance5(arg);
|
|
| 3349 | 3351 |
rn = "Performance5"; |
| 3350 | 3352 |
// break; |
| 3351 | 3353 |
case 6: |
| 3352 |
// gen_helper_mfc0_performance6(t0);
|
|
| 3354 |
// gen_helper_mfc0_performance6(arg);
|
|
| 3353 | 3355 |
rn = "Performance6"; |
| 3354 | 3356 |
// break; |
| 3355 | 3357 |
case 7: |
| 3356 |
// gen_helper_mfc0_performance7(t0);
|
|
| 3358 |
// gen_helper_mfc0_performance7(arg);
|
|
| 3357 | 3359 |
rn = "Performance7"; |
| 3358 | 3360 |
// break; |
| 3359 | 3361 |
default: |
| ... | ... | |
| 3361 | 3363 |
} |
| 3362 | 3364 |
break; |
| 3363 | 3365 |
case 26: |
| 3364 |
tcg_gen_movi_tl(t0, 0); /* unimplemented */
|
|
| 3366 |
tcg_gen_movi_tl(arg, 0); /* unimplemented */
|
|
| 3365 | 3367 |
rn = "ECC"; |
| 3366 | 3368 |
break; |
| 3367 | 3369 |
case 27: |
| 3368 | 3370 |
switch (sel) {
|
| 3369 | 3371 |
case 0 ... 3: |
| 3370 |
tcg_gen_movi_tl(t0, 0); /* unimplemented */
|
|
| 3372 |
tcg_gen_movi_tl(arg, 0); /* unimplemented */
|
|
| 3371 | 3373 |
rn = "CacheErr"; |
| 3372 | 3374 |
break; |
| 3373 | 3375 |
default: |
| ... | ... | |
| 3380 | 3382 |
case 2: |
| 3381 | 3383 |
case 4: |
| 3382 | 3384 |
case 6: |
| 3383 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagLo));
|
|
| 3385 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagLo));
|
|
| 3384 | 3386 |
rn = "TagLo"; |
| 3385 | 3387 |
break; |
| 3386 | 3388 |
case 1: |
| 3387 | 3389 |
case 3: |
| 3388 | 3390 |
case 5: |
| 3389 | 3391 |
case 7: |
| 3390 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataLo));
|
|
| 3392 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataLo));
|
|
| 3391 | 3393 |
rn = "DataLo"; |
| 3392 | 3394 |
break; |
| 3393 | 3395 |
default: |
| ... | ... | |
| 3400 | 3402 |
case 2: |
| 3401 | 3403 |
case 4: |
| 3402 | 3404 |
case 6: |
| 3403 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_TagHi));
|
|
| 3405 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_TagHi));
|
|
| 3404 | 3406 |
rn = "TagHi"; |
| 3405 | 3407 |
break; |
| 3406 | 3408 |
case 1: |
| 3407 | 3409 |
case 3: |
| 3408 | 3410 |
case 5: |
| 3409 | 3411 |
case 7: |
| 3410 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_DataHi));
|
|
| 3412 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_DataHi));
|
|
| 3411 | 3413 |
rn = "DataHi"; |
| 3412 | 3414 |
break; |
| 3413 | 3415 |
default: |
| ... | ... | |
| 3417 | 3419 |
case 30: |
| 3418 | 3420 |
switch (sel) {
|
| 3419 | 3421 |
case 0: |
| 3420 |
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
|
|
| 3421 |
tcg_gen_ext32s_tl(t0, t0);
|
|
| 3422 |
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUState, CP0_ErrorEPC));
|
|
| 3423 |
tcg_gen_ext32s_tl(arg, arg);
|
|
| 3422 | 3424 |
rn = "ErrorEPC"; |
| 3423 | 3425 |
break; |
| 3424 | 3426 |
default: |
| ... | ... | |
| 3429 | 3431 |
switch (sel) {
|
| 3430 | 3432 |
case 0: |
| 3431 | 3433 |
/* EJTAG support */ |
| 3432 |
gen_mfc0_load32(t0, offsetof(CPUState, CP0_DESAVE));
|
|
| 3434 |
gen_mfc0_load32(arg, offsetof(CPUState, CP0_DESAVE));
|
|
| 3433 | 3435 |
rn = "DESAVE"; |
| 3434 | 3436 |
break; |
| 3435 | 3437 |
default: |
| ... | ... | |
| 3447 | 3449 |
generate_exception(ctx, EXCP_RI); |
| 3448 | 3450 |
} |
| 3449 | 3451 |
|
| 3450 |
static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel)
|
|
| 3452 |
static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv arg, int reg, int sel)
|
|
| 3451 | 3453 |
{
|
| 3452 | 3454 |
const char *rn = "invalid"; |
| 3453 | 3455 |
|
| ... | ... | |
| 3461 | 3463 |
case 0: |
| 3462 | 3464 |
switch (sel) {
|
| 3463 | 3465 |
case 0: |
| 3464 |
gen_helper_mtc0_index(t0);
|
|
| 3466 |
gen_helper_mtc0_index(arg);
|
|
| 3465 | 3467 |
rn = "Index"; |
| 3466 | 3468 |
break; |
| 3467 | 3469 |
case 1: |
| 3468 | 3470 |
check_insn(env, ctx, ASE_MT); |
| 3469 |
gen_helper_mtc0_mvpcontrol(t0);
|
|
| 3471 |
gen_helper_mtc0_mvpcontrol(arg);
|
|
| 3470 | 3472 |
rn = "MVPControl"; |
| 3471 | 3473 |
break; |
| 3472 | 3474 |
case 2: |
| ... | ... | |
| 3491 | 3493 |
break; |
| 3492 | 3494 |
case 1: |
| 3493 | 3495 |
check_insn(env, ctx, ASE_MT); |
| 3494 |
gen_helper_mtc0_vpecontrol(t0);
|
|
| 3496 |
gen_helper_mtc0_vpecontrol(arg);
|
|
| 3495 | 3497 |
rn = "VPEControl"; |
| 3496 | 3498 |
break; |
| 3497 | 3499 |
case 2: |
| 3498 | 3500 |
check_insn(env, ctx, ASE_MT); |
| 3499 |
gen_helper_mtc0_vpeconf0(t0);
|
|
| 3501 |
gen_helper_mtc0_vpeconf0(arg);
|
|
| 3500 | 3502 |
rn = "VPEConf0"; |
| 3501 | 3503 |
break; |
| 3502 | 3504 |
case 3: |
| 3503 | 3505 |
check_insn(env, ctx, ASE_MT); |
| 3504 |
gen_helper_mtc0_vpeconf1(t0);
|
|
| 3506 |
gen_helper_mtc0_vpeconf1(arg);
|
|
| 3505 | 3507 |
rn = "VPEConf1"; |
| 3506 | 3508 |
break; |
| 3507 | 3509 |
case 4: |
| 3508 | 3510 |
check_insn(env, ctx, ASE_MT); |
| 3509 |
gen_helper_mtc0_yqmask(t0);
|
|
| 3511 |
gen_helper_mtc0_yqmask(arg);
|
|
| 3510 | 3512 |
rn = "YQMask"; |
| 3511 | 3513 |
break; |
| 3512 | 3514 |
case 5: |
| 3513 | 3515 |
check_insn(env, ctx, ASE_MT); |
| 3514 |
gen_mtc0_store64(t0, offsetof(CPUState, CP0_VPESchedule));
|
|
| 3516 |
gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPESchedule));
|
|
| 3515 | 3517 |
rn = "VPESchedule"; |
| 3516 | 3518 |
break; |
| 3517 | 3519 |
case 6: |
| 3518 | 3520 |
check_insn(env, ctx, ASE_MT); |
| 3519 |
gen_mtc0_store64(t0, offsetof(CPUState, CP0_VPEScheFBack));
|
|
| 3521 |
gen_mtc0_store64(arg, offsetof(CPUState, CP0_VPEScheFBack));
|
|
| 3520 | 3522 |
rn = "VPEScheFBack"; |
| 3521 | 3523 |
break; |
| 3522 | 3524 |
case 7: |
| 3523 | 3525 |
check_insn(env, ctx, ASE_MT); |
| 3524 |
gen_helper_mtc0_vpeopt(t0);
|
|
| 3526 |
gen_helper_mtc0_vpeopt(arg);
|
|
| 3525 | 3527 |
rn = "VPEOpt"; |
| 3526 | 3528 |
break; |
| 3527 | 3529 |
default: |
| ... | ... | |
| 3531 | 3533 |
case 2: |
| 3532 | 3534 |
switch (sel) {
|
| 3533 | 3535 |
case 0: |
| 3534 |
gen_helper_mtc0_entrylo0(t0);
|
|
| 3536 |
gen_helper_mtc0_entrylo0(arg);
|
|
| 3535 | 3537 |
rn = "EntryLo0"; |
| 3536 | 3538 |
break; |
| 3537 | 3539 |
case 1: |
| 3538 | 3540 |
check_insn(env, ctx, ASE_MT); |
| 3539 |
gen_helper_mtc0_tcstatus(t0);
|
|
| 3541 |
gen_helper_mtc0_tcstatus(arg);
|
|
| 3540 | 3542 |
rn = "TCStatus"; |
| 3541 | 3543 |
break; |
| 3542 | 3544 |
case 2: |
| 3543 | 3545 |
check_insn(env, ctx, ASE_MT); |
| 3544 |
gen_helper_mtc0_tcbind(t0);
|
|
| 3546 |
gen_helper_mtc0_tcbind(arg);
|
|
| 3545 | 3547 |
rn = "TCBind"; |
| 3546 | 3548 |
break; |
| 3547 | 3549 |
case 3: |
| 3548 | 3550 |
check_insn(env, ctx, ASE_MT); |
| 3549 |
gen_helper_mtc0_tcrestart(t0);
|
|
| 3551 |
gen_helper_mtc0_tcrestart(arg);
|
|
| 3550 | 3552 |
rn = "TCRestart"; |
| 3551 | 3553 |
break; |
| 3552 | 3554 |
case 4: |
| 3553 | 3555 |
check_insn(env, ctx, ASE_MT); |
| 3554 |
gen_helper_mtc0_tchalt(t0);
|
|
| 3556 |
gen_helper_mtc0_tchalt(arg);
|
|
| 3555 | 3557 |
rn = "TCHalt"; |
| 3556 | 3558 |
break; |
| 3557 | 3559 |
case 5: |
| 3558 | 3560 |
check_insn(env, ctx, ASE_MT); |
| 3559 |
gen_helper_mtc0_tccontext(t0);
|
|
| 3561 |
gen_helper_mtc0_tccontext(arg);
|
|
| 3560 | 3562 |
rn = "TCContext"; |
| 3561 | 3563 |
break; |
| 3562 | 3564 |
case 6: |
| 3563 | 3565 |
check_insn(env, ctx, ASE_MT); |
| 3564 |
gen_helper_mtc0_tcschedule(t0);
|
|
| 3566 |
gen_helper_mtc0_tcschedule(arg);
|
|
| 3565 | 3567 |
rn = "TCSchedule"; |
| 3566 | 3568 |
break; |
| 3567 | 3569 |
case 7: |
| 3568 | 3570 |
check_insn(env, ctx, ASE_MT); |
| 3569 |
gen_helper_mtc0_tcschefback(t0);
|
|
| 3571 |
gen_helper_mtc0_tcschefback(arg);
|
|
| 3570 | 3572 |
rn = "TCScheFBack"; |
| 3571 | 3573 |
break; |
| 3572 | 3574 |
default: |
| ... | ... | |
| 3576 | 3578 |
case 3: |
| 3577 | 3579 |
switch (sel) {
|
| 3578 | 3580 |
case 0: |
| 3579 |
gen_helper_mtc0_entrylo1(t0);
|
|
| 3581 |
gen_helper_mtc0_entrylo1(arg);
|
|
| 3580 | 3582 |
rn = "EntryLo1"; |
| 3581 | 3583 |
break; |
| 3582 | 3584 |
default: |
| ... | ... | |
| 3586 | 3588 |
case 4: |
| 3587 | 3589 |
switch (sel) {
|
| 3588 | 3590 |
case 0: |
| 3589 |
gen_helper_mtc0_context(t0);
|
|
| 3591 |
gen_helper_mtc0_context(arg);
|
|
| 3590 | 3592 |
rn = "Context"; |
| 3591 | 3593 |
break; |
| 3592 | 3594 |
case 1: |
| 3593 |
// gen_helper_mtc0_contextconfig(t0); /* SmartMIPS ASE */
|
|
| 3595 |
// gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
|
|
| 3594 | 3596 |
rn = "ContextConfig"; |
| 3595 | 3597 |
// break; |
| 3596 | 3598 |
default: |
| ... | ... | |
| 3600 | 3602 |
case 5: |
| 3601 | 3603 |
switch (sel) {
|
| 3602 | 3604 |
case 0: |
| 3603 |
gen_helper_mtc0_pagemask(t0);
|
|
| 3605 |
gen_helper_mtc0_pagemask(arg);
|
|
| 3604 | 3606 |
rn = "PageMask"; |
| 3605 | 3607 |
break; |
| 3606 | 3608 |
case 1: |
| 3607 | 3609 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3608 |
gen_helper_mtc0_pagegrain(t0);
|
|
| 3610 |
gen_helper_mtc0_pagegrain(arg);
|
|
| 3609 | 3611 |
rn = "PageGrain"; |
| 3610 | 3612 |
break; |
| 3611 | 3613 |
default: |
| ... | ... | |
| 3615 | 3617 |
case 6: |
| 3616 | 3618 |
switch (sel) {
|
| 3617 | 3619 |
case 0: |
| 3618 |
gen_helper_mtc0_wired(t0);
|
|
| 3620 |
gen_helper_mtc0_wired(arg);
|
|
| 3619 | 3621 |
rn = "Wired"; |
| 3620 | 3622 |
break; |
| 3621 | 3623 |
case 1: |
| 3622 | 3624 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3623 |
gen_helper_mtc0_srsconf0(t0);
|
|
| 3625 |
gen_helper_mtc0_srsconf0(arg);
|
|
| 3624 | 3626 |
rn = "SRSConf0"; |
| 3625 | 3627 |
break; |
| 3626 | 3628 |
case 2: |
| 3627 | 3629 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3628 |
gen_helper_mtc0_srsconf1(t0);
|
|
| 3630 |
gen_helper_mtc0_srsconf1(arg);
|
|
| 3629 | 3631 |
rn = "SRSConf1"; |
| 3630 | 3632 |
break; |
| 3631 | 3633 |
case 3: |
| 3632 | 3634 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3633 |
gen_helper_mtc0_srsconf2(t0);
|
|
| 3635 |
gen_helper_mtc0_srsconf2(arg);
|
|
| 3634 | 3636 |
rn = "SRSConf2"; |
| 3635 | 3637 |
break; |
| 3636 | 3638 |
case 4: |
| 3637 | 3639 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3638 |
gen_helper_mtc0_srsconf3(t0);
|
|
| 3640 |
gen_helper_mtc0_srsconf3(arg);
|
|
| 3639 | 3641 |
rn = "SRSConf3"; |
| 3640 | 3642 |
break; |
| 3641 | 3643 |
case 5: |
| 3642 | 3644 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3643 |
gen_helper_mtc0_srsconf4(t0);
|
|
| 3645 |
gen_helper_mtc0_srsconf4(arg);
|
|
| 3644 | 3646 |
rn = "SRSConf4"; |
| 3645 | 3647 |
break; |
| 3646 | 3648 |
default: |
| ... | ... | |
| 3651 | 3653 |
switch (sel) {
|
| 3652 | 3654 |
case 0: |
| 3653 | 3655 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3654 |
gen_helper_mtc0_hwrena(t0);
|
|
| 3656 |
gen_helper_mtc0_hwrena(arg);
|
|
| 3655 | 3657 |
rn = "HWREna"; |
| 3656 | 3658 |
break; |
| 3657 | 3659 |
default: |
| ... | ... | |
| 3665 | 3667 |
case 9: |
| 3666 | 3668 |
switch (sel) {
|
| 3667 | 3669 |
case 0: |
| 3668 |
gen_helper_mtc0_count(t0);
|
|
| 3670 |
gen_helper_mtc0_count(arg);
|
|
| 3669 | 3671 |
rn = "Count"; |
| 3670 | 3672 |
break; |
| 3671 | 3673 |
/* 6,7 are implementation dependent */ |
| ... | ... | |
| 3676 | 3678 |
case 10: |
| 3677 | 3679 |
switch (sel) {
|
| 3678 | 3680 |
case 0: |
| 3679 |
gen_helper_mtc0_entryhi(t0);
|
|
| 3681 |
gen_helper_mtc0_entryhi(arg);
|
|
| 3680 | 3682 |
rn = "EntryHi"; |
| 3681 | 3683 |
break; |
| 3682 | 3684 |
default: |
| ... | ... | |
| 3686 | 3688 |
case 11: |
| 3687 | 3689 |
switch (sel) {
|
| 3688 | 3690 |
case 0: |
| 3689 |
gen_helper_mtc0_compare(t0);
|
|
| 3691 |
gen_helper_mtc0_compare(arg);
|
|
| 3690 | 3692 |
rn = "Compare"; |
| 3691 | 3693 |
break; |
| 3692 | 3694 |
/* 6,7 are implementation dependent */ |
| ... | ... | |
| 3698 | 3700 |
switch (sel) {
|
| 3699 | 3701 |
case 0: |
| 3700 | 3702 |
save_cpu_state(ctx, 1); |
| 3701 |
gen_helper_mtc0_status(t0);
|
|
| 3703 |
gen_helper_mtc0_status(arg);
|
|
| 3702 | 3704 |
/* BS_STOP isn't good enough here, hflags may have changed. */ |
| 3703 | 3705 |
gen_save_pc(ctx->pc + 4); |
| 3704 | 3706 |
ctx->bstate = BS_EXCP; |
| ... | ... | |
| 3706 | 3708 |
break; |
| 3707 | 3709 |
case 1: |
| 3708 | 3710 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3709 |
gen_helper_mtc0_intctl(t0);
|
|
| 3711 |
gen_helper_mtc0_intctl(arg);
|
|
| 3710 | 3712 |
/* Stop translation as we may have switched the execution mode */ |
| 3711 | 3713 |
ctx->bstate = BS_STOP; |
| 3712 | 3714 |
rn = "IntCtl"; |
| 3713 | 3715 |
break; |
| 3714 | 3716 |
case 2: |
| 3715 | 3717 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3716 |
gen_helper_mtc0_srsctl(t0);
|
|
| 3718 |
gen_helper_mtc0_srsctl(arg);
|
|
| 3717 | 3719 |
/* Stop translation as we may have switched the execution mode */ |
| 3718 | 3720 |
ctx->bstate = BS_STOP; |
| 3719 | 3721 |
rn = "SRSCtl"; |
| 3720 | 3722 |
break; |
| 3721 | 3723 |
case 3: |
| 3722 | 3724 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3723 |
gen_mtc0_store32(t0, offsetof(CPUState, CP0_SRSMap));
|
|
| 3725 |
gen_mtc0_store32(arg, offsetof(CPUState, CP0_SRSMap));
|
|
| 3724 | 3726 |
/* Stop translation as we may have switched the execution mode */ |
| 3725 | 3727 |
ctx->bstate = BS_STOP; |
| 3726 | 3728 |
rn = "SRSMap"; |
| ... | ... | |
| 3733 | 3735 |
switch (sel) {
|
| 3734 | 3736 |
case 0: |
| 3735 | 3737 |
save_cpu_state(ctx, 1); |
| 3736 |
gen_helper_mtc0_cause(t0);
|
|
| 3738 |
gen_helper_mtc0_cause(arg);
|
|
| 3737 | 3739 |
rn = "Cause"; |
| 3738 | 3740 |
break; |
| 3739 | 3741 |
default: |
| ... | ... | |
| 3743 | 3745 |
case 14: |
| 3744 | 3746 |
switch (sel) {
|
| 3745 | 3747 |
case 0: |
| 3746 |
gen_mtc0_store64(t0, offsetof(CPUState, CP0_EPC));
|
|
| 3748 |
gen_mtc0_store64(arg, offsetof(CPUState, CP0_EPC));
|
|
| 3747 | 3749 |
rn = "EPC"; |
| 3748 | 3750 |
break; |
| 3749 | 3751 |
default: |
| ... | ... | |
| 3758 | 3760 |
break; |
| 3759 | 3761 |
case 1: |
| 3760 | 3762 |
check_insn(env, ctx, ISA_MIPS32R2); |
| 3761 |
gen_helper_mtc0_ebase(t0);
|
|
| 3763 |
gen_helper_mtc0_ebase(arg);
|
|
| 3762 | 3764 |
rn = "EBase"; |
| 3763 | 3765 |
break; |
| 3764 | 3766 |
default: |
| ... | ... | |
| 3768 | 3770 |
case 16: |
| 3769 | 3771 |
switch (sel) {
|
| 3770 | 3772 |
case 0: |
| 3771 |
gen_helper_mtc0_config0(t0);
|
|
| 3773 |
gen_helper_mtc0_config0(arg);
|
|
| 3772 | 3774 |
rn = "Config"; |
| 3773 | 3775 |
/* Stop translation as we may have switched the execution mode */ |
| 3774 | 3776 |
ctx->bstate = BS_STOP; |
| ... | ... | |
| 3778 | 3780 |
rn = "Config1"; |
| 3779 | 3781 |
break; |
| 3780 | 3782 |
case 2: |
| 3781 |
gen_helper_mtc0_config2(t0);
|
|
| 3783 |
gen_helper_mtc0_config2(arg);
|
|
| 3782 | 3784 |
rn = "Config2"; |
| 3783 | 3785 |
/* Stop translation as we may have switched the execution mode */ |
| 3784 | 3786 |
ctx->bstate = BS_STOP; |
| ... | ... | |
| 3815 | 3817 |
case 18: |
| 3816 | 3818 |
switch (sel) {
|
| 3817 | 3819 |
case 0 ... 7: |
| 3818 |
gen_helper_1i(mtc0_watchlo, t0, sel);
|
|
| 3820 |
gen_helper_1i(mtc0_watchlo, arg, sel);
|
|
| 3819 | 3821 |
rn = "WatchLo"; |
| 3820 | 3822 |
break; |
| 3821 | 3823 |
default: |
| ... | ... | |
| 3825 | 3827 |
case 19: |
| 3826 | 3828 |
switch (sel) {
|
| 3827 | 3829 |
case 0 ... 7: |
| 3828 |
gen_helper_1i(mtc0_watchhi, t0, sel);
|
|
| 3830 |
gen_helper_1i(mtc0_watchhi, arg, sel);
|
|
| 3829 | 3831 |
rn = "WatchHi"; |
| 3830 | 3832 |
break; |
| 3831 | 3833 |
default: |
| ... | ... | |
| 3837 | 3839 |
case 0: |
| 3838 | 3840 |
#if defined(TARGET_MIPS64) |
| 3839 | 3841 |
check_insn(env, ctx, ISA_MIPS3); |
| 3840 |
gen_helper_mtc0_xcontext(t0);
|
|
| 3842 |
gen_helper_mtc0_xcontext(arg);
|
|
| 3841 | 3843 |
rn = "XContext"; |
| 3842 | 3844 |
break; |
| 3843 | 3845 |
#endif |
| ... | ... | |
| 3849 | 3851 |
/* Officially reserved, but sel 0 is used for R1x000 framemask */ |
| 3850 | 3852 |
switch (sel) {
|
| 3851 | 3853 |
case 0: |
| 3852 |
gen_helper_mtc0_framemask(t0);
|
|
| 3854 |
gen_helper_mtc0_framemask(arg);
|
|
| 3853 | 3855 |
rn = "Framemask"; |
| 3854 | 3856 |
break; |
| 3855 | 3857 |
default: |
| ... | ... | |
| 3863 | 3865 |
case 23: |
| 3864 | 3866 |
switch (sel) {
|
| 3865 | 3867 |
case 0: |
| 3866 |
gen_helper_mtc0_debug(t0); /* EJTAG support */
|
|
| 3868 |
gen_helper_mtc0_debug(arg); /* EJTAG support */
|
|
| 3867 | 3869 |
/* BS_STOP isn't good enough here, hflags may have changed. */ |
| 3868 | 3870 |
gen_save_pc(ctx->pc + 4); |
| 3869 | 3871 |
ctx->bstate = BS_EXCP; |
| 3870 | 3872 |
rn = "Debug"; |
| 3871 | 3873 |
break; |
| 3872 | 3874 |
case 1: |
| 3873 |
// gen_helper_mtc0_tracecontrol(t0); /* PDtrace support */
|
|
| 3875 |
// gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
|
|
| 3874 | 3876 |
rn = "TraceControl"; |
| 3875 | 3877 |
/* Stop translation as we may have switched the execution mode */ |
| 3876 | 3878 |
ctx->bstate = BS_STOP; |
| 3877 | 3879 |
// break; |
| 3878 | 3880 |
case 2: |
| 3879 |
// gen_helper_mtc0_tracecontrol2(t0); /* PDtrace support */
|
|
| 3881 |
// gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
|
|
| 3880 | 3882 |
rn = "TraceControl2"; |
| 3881 | 3883 |
/* Stop translation as we may have switched the execution mode */ |
| 3882 | 3884 |
ctx->bstate = BS_STOP; |
| ... | ... | |
| 3884 | 3886 |
case 3: |
| 3885 | 3887 |
/* Stop translation as we may have switched the execution mode */ |
| 3886 | 3888 |
ctx->bstate = BS_STOP; |
| 3887 |
// gen_helper_mtc0_usertracedata(t0); /* PDtrace support */
|
|
| 3889 |
// gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
|
|
| 3888 | 3890 |
rn = "UserTraceData"; |
| 3889 | 3891 |
/* Stop translation as we may have switched the execution mode */ |
| 3890 | 3892 |
ctx->bstate = BS_STOP; |
| 3891 | 3893 |
// break; |
| 3892 | 3894 |
case 4: |
| 3893 |
// gen_helper_mtc0_tracebpc(t0); /* PDtrace support */
|
|
| 3895 |
// gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
|
|
| 3894 | 3896 |
/* Stop translation as we may have switched the execution mode */ |
| 3895 | 3897 |
ctx->bstate = BS_STOP; |
| 3896 | 3898 |
rn = "TraceBPC"; |
| ... | ... | |
| 3903 | 3905 |
switch (sel) {
|
| 3904 | 3906 |
case 0: |
| 3905 | 3907 |
/* EJTAG support */ |
| 3906 |
gen_mtc0_store64(t0, offsetof(CPUState, CP0_DEPC));
|
|
| 3908 |
gen_mtc0_store64(arg, offsetof(CPUState, CP0_DEPC));
|
|
| 3907 | 3909 |
rn = "DEPC"; |
| 3908 | 3910 |
break; |
| 3909 | 3911 |
default: |
| ... | ... | |
| 3913 | 3915 |
case 25: |
| 3914 | 3916 |
switch (sel) {
|
| 3915 | 3917 |
case 0: |
| 3916 |
gen_helper_mtc0_performance0(t0);
|
|
| 3918 |
gen_helper_mtc0_performance0(arg);
|
|
| 3917 | 3919 |
rn = "Performance0"; |
| 3918 | 3920 |
break; |
| 3919 | 3921 |
case 1: |
| 3920 |
// gen_helper_mtc0_performance1(t0);
|
|
| 3922 |
// gen_helper_mtc0_performance1(arg);
|
|
| 3921 | 3923 |
rn = "Performance1"; |
| 3922 | 3924 |
// break; |
| 3923 | 3925 |
case 2: |
| 3924 |
// gen_helper_mtc0_performance2(t0);
|
|
| 3926 |
// gen_helper_mtc0_performance2(arg);
|
|
| 3925 | 3927 |
rn = "Performance2"; |
| 3926 | 3928 |
// break; |
| 3927 | 3929 |
case 3: |
| 3928 |
// gen_helper_mtc0_performance3(t0);
|
|
| 3930 |
// gen_helper_mtc0_performance3(arg);
|
|
| 3929 | 3931 |
rn = "Performance3"; |
| 3930 | 3932 |
// break; |
| 3931 | 3933 |
case 4: |
| 3932 |
// gen_helper_mtc0_performance4(t0);
|
|
| 3934 |
// gen_helper_mtc0_performance4(arg);
|
|
| 3933 | 3935 |
rn = "Performance4"; |
| 3934 | 3936 |
// break; |
| 3935 | 3937 |
case 5: |
| 3936 |
// gen_helper_mtc0_performance5(t0);
|
|
| 3938 |
// gen_helper_mtc0_performance5(arg);
|
|
| 3937 | 3939 |
rn = "Performance5"; |
| 3938 | 3940 |
// break; |
| 3939 | 3941 |
case 6: |
| 3940 |
// gen_helper_mtc0_performance6(t0);
|
|
| 3942 |
// gen_helper_mtc0_performance6(arg);
|
|
| 3941 | 3943 |
rn = "Performance6"; |
| 3942 | 3944 |
// break; |
| 3943 | 3945 |
case 7: |
| 3944 |
// gen_helper_mtc0_performance7(t0);
|
|
| 3946 |
// gen_helper_mtc0_performance7(arg);
|
|
| 3945 | 3947 |
rn = "Performance7"; |
| 3946 | 3948 |
// break; |
| 3947 | 3949 |
default: |
| ... | ... | |
| 3968 | 3970 |
case 2: |
| 3969 | 3971 |
case 4: |
| 3970 | 3972 |
case 6: |
| 3971 |
gen_helper_mtc0_taglo(t0);
|
|
| 3973 |
gen_helper_mtc0_taglo(arg);
|
|
| 3972 | 3974 |
rn = "TagLo"; |
| 3973 | 3975 |
break; |
| 3974 | 3976 |
case 1: |
| 3975 | 3977 |
case 3: |
| 3976 | 3978 |
case 5: |
| 3977 | 3979 |
case 7: |
| 3978 |
gen_helper_mtc0_datalo(t0);
|
|
| 3980 |
gen_helper_mtc0_datalo(arg);
|
|
| 3979 | 3981 |
rn = "DataLo"; |
| 3980 | 3982 |
break; |
| 3981 | 3983 |
default: |
| ... | ... | |
| 3988 | 3990 |
case 2: |
| 3989 | 3991 |
case 4: |
| 3990 | 3992 |
case 6: |
| 3991 |
gen_helper_mtc0_taghi(t0);
|
|
| 3993 |
gen_helper_mtc0_taghi(arg);
|
|
| 3992 | 3994 |
rn = "TagHi"; |
| 3993 | 3995 |
break; |
| 3994 | 3996 |
case 1: |
| 3995 | 3997 |
case 3: |
| 3996 | 3998 |
case 5: |
| 3997 | 3999 |
case 7: |
| 3998 |
gen_helper_mtc0_datahi(t0);
|
|
| 4000 |
gen_helper_mtc0_datahi(arg);
|
|
| 3999 | 4001 |
rn = "DataHi"; |
| 4000 | 4002 |
break; |
| 4001 | 4003 |
default: |
| ... | ... | |
| 4006 | 4008 |
case 30: |
| 4007 | 4009 |
switch (sel) {
|
| 4008 | 4010 |
case 0: |
| 4009 |
gen_mtc0_store64(t0, offsetof(CPUState, CP0_ErrorEPC));
|
|
| 4011 |
gen_mtc0_store64(arg, offsetof(CPUState, CP0_ErrorEPC));
|
|
| 4010 | 4012 |
rn = "ErrorEPC"; |
| 4011 | 4013 |
break; |
| 4012 | 4014 |
default: |
| ... | ... | |
| 4017 | 4019 |
switch (sel) {
|
| 4018 | 4020 |
case 0: |
| 4019 | 4021 |
/* EJTAG support */ |
| 4020 |
gen_mtc0_store32(t0, offsetof(CPUState, CP0_DESAVE));
|
|
| 4022 |
gen_mtc0_store32(arg, offsetof(CPUState, CP0_DESAVE));
|
|
| 4021 | 4023 |
rn = "DESAVE"; |
| 4022 | 4024 |
break; |
| 4023 | 4025 |
default: |
| ... | ... | |
| 4043 | 4045 |
} |
| 4044 | 4046 |
|
| 4045 | 4047 |
#if defined(TARGET_MIPS64) |
| 4046 |
static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int sel) |
|
Also available in: Unified diff