Revision d9c32310
| b/hw/acpi.c | ||
|---|---|---|
| 496 | 496 |
} |
| 497 | 497 |
} |
| 498 | 498 |
|
| 499 |
static void piix4_powerdown(void *opaque, int irq, int power_failing) |
|
| 500 |
{
|
|
| 501 |
#if defined(TARGET_I386) |
|
| 502 |
PIIX4PMState *s = opaque; |
|
| 503 |
|
|
| 504 |
if (!s) {
|
|
| 505 |
qemu_system_shutdown_request(); |
|
| 506 |
} else if (s->pmen & PWRBTN_EN) {
|
|
| 507 |
s->pmsts |= PWRBTN_EN; |
|
| 508 |
pm_update_sci(s); |
|
| 509 |
} |
|
| 510 |
#endif |
|
| 511 |
} |
|
| 512 |
|
|
| 499 | 513 |
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, |
| 500 | 514 |
qemu_irq sci_irq) |
| 501 | 515 |
{
|
| ... | ... | |
| 545 | 559 |
|
| 546 | 560 |
s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s); |
| 547 | 561 |
|
| 562 |
qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1); |
|
| 563 |
|
|
| 548 | 564 |
register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
|
| 549 | 565 |
|
| 550 | 566 |
s->smbus = i2c_init_bus(NULL, "i2c"); |
| ... | ... | |
| 554 | 570 |
return s->smbus; |
| 555 | 571 |
} |
| 556 | 572 |
|
| 557 |
#if defined(TARGET_I386) |
|
| 558 |
void qemu_system_powerdown(void) |
|
| 559 |
{
|
|
| 560 |
if (!pm_state) {
|
|
| 561 |
qemu_system_shutdown_request(); |
|
| 562 |
} else if (pm_state->pmen & PWRBTN_EN) {
|
|
| 563 |
pm_state->pmsts |= PWRBTN_EN; |
|
| 564 |
pm_update_sci(pm_state); |
|
| 565 |
} |
|
| 566 |
} |
|
| 567 |
#endif |
|
| 568 |
|
|
| 569 | 573 |
#define GPE_BASE 0xafe0 |
| 570 | 574 |
#define PCI_BASE 0xae00 |
| 571 | 575 |
#define PCI_EJ_BASE 0xae08 |
| b/hw/sun4m.c | ||
|---|---|---|
| 451 | 451 |
#define MISC_MDM 0x01b00000 |
| 452 | 452 |
#define MISC_SYS 0x01f00000 |
| 453 | 453 |
|
| 454 |
static qemu_irq slavio_powerdown; |
|
| 455 |
|
|
| 456 |
void qemu_system_powerdown(void) |
|
| 457 |
{
|
|
| 458 |
qemu_irq_raise(slavio_powerdown); |
|
| 459 |
} |
|
| 460 |
|
|
| 461 | 454 |
static void slavio_misc_init(target_phys_addr_t base, |
| 462 | 455 |
target_phys_addr_t aux1_base, |
| 463 | 456 |
target_phys_addr_t aux2_base, qemu_irq irq, |
| ... | ... | |
| 494 | 487 |
} |
| 495 | 488 |
sysbus_connect_irq(s, 0, irq); |
| 496 | 489 |
sysbus_connect_irq(s, 1, fdc_tc); |
| 497 |
slavio_powerdown = qdev_get_gpio_in(dev, 0);
|
|
| 490 |
qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
|
|
| 498 | 491 |
} |
| 499 | 492 |
|
| 500 | 493 |
static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version) |
| b/hw/sun4u.c | ||
|---|---|---|
| 254 | 254 |
} |
| 255 | 255 |
} |
| 256 | 256 |
|
| 257 |
void qemu_system_powerdown(void) |
|
| 258 |
{
|
|
| 259 |
} |
|
| 260 |
|
|
| 261 | 257 |
typedef struct ResetData {
|
| 262 | 258 |
CPUState *env; |
| 263 | 259 |
uint64_t reset_addr; |
| b/sysemu.h | ||
|---|---|---|
| 47 | 47 |
int qemu_shutdown_requested(void); |
| 48 | 48 |
int qemu_reset_requested(void); |
| 49 | 49 |
int qemu_powerdown_requested(void); |
| 50 |
#ifdef NEED_CPU_H |
|
| 51 |
#if !defined(TARGET_SPARC) && !defined(TARGET_I386) |
|
| 52 |
// Please implement a power failure function to signal the OS |
|
| 53 |
#define qemu_system_powerdown() do{}while(0)
|
|
| 54 |
#else |
|
| 55 |
void qemu_system_powerdown(void); |
|
| 56 |
#endif |
|
| 57 |
#endif |
|
| 50 |
extern qemu_irq qemu_system_powerdown; |
|
| 58 | 51 |
void qemu_system_reset(void); |
| 59 | 52 |
|
| 60 | 53 |
void do_savevm(Monitor *mon, const char *name); |
| b/vl.c | ||
|---|---|---|
| 4281 | 4281 |
return 1; |
| 4282 | 4282 |
} |
| 4283 | 4283 |
|
| 4284 |
qemu_irq qemu_system_powerdown; |
|
| 4285 |
|
|
| 4284 | 4286 |
static void main_loop(void) |
| 4285 | 4287 |
{
|
| 4286 | 4288 |
int r; |
| ... | ... | |
| 4321 | 4323 |
qemu_system_reset(); |
| 4322 | 4324 |
resume_all_vcpus(); |
| 4323 | 4325 |
} |
| 4324 |
if (qemu_powerdown_requested()) |
|
| 4325 |
qemu_system_powerdown(); |
|
| 4326 |
if (qemu_powerdown_requested()) {
|
|
| 4327 |
qemu_irq_raise(qemu_system_powerdown); |
|
| 4328 |
} |
|
| 4326 | 4329 |
if ((r = qemu_vmstop_requested())) |
| 4327 | 4330 |
vm_stop(r); |
| 4328 | 4331 |
} |
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