Revision d9c32310 hw/acpi.c
b/hw/acpi.c | ||
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} |
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} |
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static void piix4_powerdown(void *opaque, int irq, int power_failing) |
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{ |
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#if defined(TARGET_I386) |
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PIIX4PMState *s = opaque; |
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|
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if (!s) { |
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qemu_system_shutdown_request(); |
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} else if (s->pmen & PWRBTN_EN) { |
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s->pmsts |= PWRBTN_EN; |
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pm_update_sci(s); |
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} |
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#endif |
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} |
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i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, |
500 | 514 |
qemu_irq sci_irq) |
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{ |
... | ... | |
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s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s); |
547 | 561 |
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qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1); |
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register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s); |
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s->smbus = i2c_init_bus(NULL, "i2c"); |
... | ... | |
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return s->smbus; |
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} |
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#if defined(TARGET_I386) |
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void qemu_system_powerdown(void) |
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{ |
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if (!pm_state) { |
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qemu_system_shutdown_request(); |
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} else if (pm_state->pmen & PWRBTN_EN) { |
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pm_state->pmsts |= PWRBTN_EN; |
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pm_update_sci(pm_state); |
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} |
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} |
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#endif |
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#define GPE_BASE 0xafe0 |
570 | 574 |
#define PCI_BASE 0xae00 |
571 | 575 |
#define PCI_EJ_BASE 0xae08 |
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