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Revision d9f4bb27

IDd9f4bb27dbff2e40ec2e36eb8017c9dedce77f30

Added by Andre Przywara almost 12 years ago

target-i386: add SSE4a instruction support

This adds support for the AMD Phenom/Barcelona's SSE4a instructions.
Those include insertq and extrq, which are doing shift and mask on
XMM registers, in two versions (immediate shift/length values and
stored in another XMM register).
Additionally it implements movntss, movntsd, which are scalar
non-temporal stores (avoiding cache trashing). These are implemented
as normal stores, though.
SSE4a is guarded by the SSE4A CPUID bit (Fn8000_0001:ECX6).

Signed-off-by: Andre Przywara <>
Signed-off-by: Aurelien Jarno <>

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