Revision dac454af target-ppc/translate.c
| b/target-ppc/translate.c | ||
|---|---|---|
| 3618 | 3618 |
} |
| 3619 | 3619 |
|
| 3620 | 3620 |
/*** Cache management ***/ |
| 3621 |
/* For now, all those will be implemented as nop: |
|
| 3622 |
* this is valid, regarding the PowerPC specs... |
|
| 3623 |
* We just have to flush tb while invalidating instruction cache lines... |
|
| 3624 |
*/ |
|
| 3625 | 3621 |
/* dcbf */ |
| 3626 | 3622 |
GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE) |
| 3627 | 3623 |
{
|
| 3624 |
/* XXX: specification says this is treated as a load by the MMU */ |
|
| 3628 | 3625 |
gen_addr_reg_index(ctx); |
| 3629 | 3626 |
op_ldst(lbz); |
| 3630 | 3627 |
} |
| ... | ... | |
| 3641 | 3638 |
} |
| 3642 | 3639 |
gen_addr_reg_index(ctx); |
| 3643 | 3640 |
/* XXX: specification says this should be treated as a store by the MMU */ |
| 3644 |
//op_ldst(lbz);
|
|
| 3641 |
op_ldst(lbz); |
|
| 3645 | 3642 |
op_ldst(stb); |
| 3646 | 3643 |
#endif |
| 3647 | 3644 |
} |
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