Revision dad081ee
| b/linux-user/main.c | ||
|---|---|---|
| 3054 | 3054 |
for(i = 0; i < 28; i++) {
|
| 3055 | 3055 |
env->ir[i] = ((abi_ulong *)regs)[i]; |
| 3056 | 3056 |
} |
| 3057 |
env->ipr[IPR_USP] = regs->usp; |
|
| 3058 |
env->ir[30] = regs->usp; |
|
| 3057 |
env->ir[IR_SP] = regs->usp; |
|
| 3059 | 3058 |
env->pc = regs->pc; |
| 3060 |
env->unique = regs->unique; |
|
| 3061 | 3059 |
} |
| 3062 | 3060 |
#elif defined(TARGET_CRIS) |
| 3063 | 3061 |
{
|
| b/target-alpha/cpu.h | ||
|---|---|---|
| 193 | 193 |
/* Internal processor registers */ |
| 194 | 194 |
/* XXX: TOFIX: most of those registers are implementation dependant */ |
| 195 | 195 |
enum {
|
| 196 |
#if defined(CONFIG_USER_ONLY) |
|
| 197 |
IPR_EXC_ADDR, |
|
| 198 |
IPR_EXC_SUM, |
|
| 199 |
IPR_EXC_MASK, |
|
| 200 |
#else |
|
| 196 | 201 |
/* Ebox IPRs */ |
| 197 | 202 |
IPR_CC = 0xC0, /* 21264 */ |
| 198 | 203 |
IPR_CC_CTL = 0xC1, /* 21264 */ |
| ... | ... | |
| 306 | 311 |
IPR_VPTB, |
| 307 | 312 |
IPR_WHAMI, |
| 308 | 313 |
IPR_ALT_MODE, |
| 314 |
#endif |
|
| 309 | 315 |
IPR_LAST, |
| 310 | 316 |
}; |
| 311 | 317 |
|
| b/target-alpha/translate.c | ||
|---|---|---|
| 2721 | 2721 |
CPUAlphaState * cpu_alpha_init (const char *cpu_model) |
| 2722 | 2722 |
{
|
| 2723 | 2723 |
CPUAlphaState *env; |
| 2724 |
uint64_t hwpcb; |
|
| 2725 | 2724 |
int implver, amask, i, max; |
| 2726 | 2725 |
|
| 2727 | 2726 |
env = qemu_mallocz(sizeof(CPUAlphaState)); |
| ... | ... | |
| 2752 | 2751 |
| FPCR_UNFD | FPCR_INED | FPCR_DNOD)); |
| 2753 | 2752 |
#endif |
| 2754 | 2753 |
pal_init(env); |
| 2754 |
|
|
| 2755 | 2755 |
/* Initialize IPR */ |
| 2756 |
hwpcb = env->ipr[IPR_PCBB]; |
|
| 2757 |
env->ipr[IPR_ASN] = 0; |
|
| 2758 |
env->ipr[IPR_ASTEN] = 0; |
|
| 2759 |
env->ipr[IPR_ASTSR] = 0; |
|
| 2760 |
env->ipr[IPR_DATFX] = 0; |
|
| 2761 |
/* XXX: fix this */ |
|
| 2762 |
// env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8); |
|
| 2763 |
// env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0); |
|
| 2764 |
// env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16); |
|
| 2765 |
// env->ipr[IPR_USP] = ldq_raw(hwpcb + 24); |
|
| 2766 |
env->ipr[IPR_FEN] = 0; |
|
| 2767 |
env->ipr[IPR_IPL] = 31; |
|
| 2768 |
env->ipr[IPR_MCES] = 0; |
|
| 2769 |
env->ipr[IPR_PERFMON] = 0; /* Implementation specific */ |
|
| 2770 |
// env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32); |
|
| 2771 |
env->ipr[IPR_SISR] = 0; |
|
| 2772 |
env->ipr[IPR_VIRBND] = -1ULL; |
|
| 2756 |
#if defined (CONFIG_USER_ONLY) |
|
| 2757 |
env->ipr[IPR_EXC_ADDR] = 0; |
|
| 2758 |
env->ipr[IPR_EXC_SUM] = 0; |
|
| 2759 |
env->ipr[IPR_EXC_MASK] = 0; |
|
| 2760 |
#else |
|
| 2761 |
{
|
|
| 2762 |
uint64_t hwpcb; |
|
| 2763 |
hwpcb = env->ipr[IPR_PCBB]; |
|
| 2764 |
env->ipr[IPR_ASN] = 0; |
|
| 2765 |
env->ipr[IPR_ASTEN] = 0; |
|
| 2766 |
env->ipr[IPR_ASTSR] = 0; |
|
| 2767 |
env->ipr[IPR_DATFX] = 0; |
|
| 2768 |
/* XXX: fix this */ |
|
| 2769 |
// env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8); |
|
| 2770 |
// env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0); |
|
| 2771 |
// env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16); |
|
| 2772 |
// env->ipr[IPR_USP] = ldq_raw(hwpcb + 24); |
|
| 2773 |
env->ipr[IPR_FEN] = 0; |
|
| 2774 |
env->ipr[IPR_IPL] = 31; |
|
| 2775 |
env->ipr[IPR_MCES] = 0; |
|
| 2776 |
env->ipr[IPR_PERFMON] = 0; /* Implementation specific */ |
|
| 2777 |
// env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32); |
|
| 2778 |
env->ipr[IPR_SISR] = 0; |
|
| 2779 |
env->ipr[IPR_VIRBND] = -1ULL; |
|
| 2780 |
} |
|
| 2781 |
#endif |
|
| 2773 | 2782 |
|
| 2774 | 2783 |
qemu_init_vcpu(env); |
| 2775 | 2784 |
return env; |
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