Revision dad081ee target-alpha/translate.c
| b/target-alpha/translate.c | ||
|---|---|---|
| 2721 | 2721 |
CPUAlphaState * cpu_alpha_init (const char *cpu_model) |
| 2722 | 2722 |
{
|
| 2723 | 2723 |
CPUAlphaState *env; |
| 2724 |
uint64_t hwpcb; |
|
| 2725 | 2724 |
int implver, amask, i, max; |
| 2726 | 2725 |
|
| 2727 | 2726 |
env = qemu_mallocz(sizeof(CPUAlphaState)); |
| ... | ... | |
| 2752 | 2751 |
| FPCR_UNFD | FPCR_INED | FPCR_DNOD)); |
| 2753 | 2752 |
#endif |
| 2754 | 2753 |
pal_init(env); |
| 2754 |
|
|
| 2755 | 2755 |
/* Initialize IPR */ |
| 2756 |
hwpcb = env->ipr[IPR_PCBB]; |
|
| 2757 |
env->ipr[IPR_ASN] = 0; |
|
| 2758 |
env->ipr[IPR_ASTEN] = 0; |
|
| 2759 |
env->ipr[IPR_ASTSR] = 0; |
|
| 2760 |
env->ipr[IPR_DATFX] = 0; |
|
| 2761 |
/* XXX: fix this */ |
|
| 2762 |
// env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8); |
|
| 2763 |
// env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0); |
|
| 2764 |
// env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16); |
|
| 2765 |
// env->ipr[IPR_USP] = ldq_raw(hwpcb + 24); |
|
| 2766 |
env->ipr[IPR_FEN] = 0; |
|
| 2767 |
env->ipr[IPR_IPL] = 31; |
|
| 2768 |
env->ipr[IPR_MCES] = 0; |
|
| 2769 |
env->ipr[IPR_PERFMON] = 0; /* Implementation specific */ |
|
| 2770 |
// env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32); |
|
| 2771 |
env->ipr[IPR_SISR] = 0; |
|
| 2772 |
env->ipr[IPR_VIRBND] = -1ULL; |
|
| 2756 |
#if defined (CONFIG_USER_ONLY) |
|
| 2757 |
env->ipr[IPR_EXC_ADDR] = 0; |
|
| 2758 |
env->ipr[IPR_EXC_SUM] = 0; |
|
| 2759 |
env->ipr[IPR_EXC_MASK] = 0; |
|
| 2760 |
#else |
|
| 2761 |
{
|
|
| 2762 |
uint64_t hwpcb; |
|
| 2763 |
hwpcb = env->ipr[IPR_PCBB]; |
|
| 2764 |
env->ipr[IPR_ASN] = 0; |
|
| 2765 |
env->ipr[IPR_ASTEN] = 0; |
|
| 2766 |
env->ipr[IPR_ASTSR] = 0; |
|
| 2767 |
env->ipr[IPR_DATFX] = 0; |
|
| 2768 |
/* XXX: fix this */ |
|
| 2769 |
// env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8); |
|
| 2770 |
// env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0); |
|
| 2771 |
// env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16); |
|
| 2772 |
// env->ipr[IPR_USP] = ldq_raw(hwpcb + 24); |
|
| 2773 |
env->ipr[IPR_FEN] = 0; |
|
| 2774 |
env->ipr[IPR_IPL] = 31; |
|
| 2775 |
env->ipr[IPR_MCES] = 0; |
|
| 2776 |
env->ipr[IPR_PERFMON] = 0; /* Implementation specific */ |
|
| 2777 |
// env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32); |
|
| 2778 |
env->ipr[IPR_SISR] = 0; |
|
| 2779 |
env->ipr[IPR_VIRBND] = -1ULL; |
|
| 2780 |
} |
|
| 2781 |
#endif |
|
| 2773 | 2782 |
|
| 2774 | 2783 |
qemu_init_vcpu(env); |
| 2775 | 2784 |
return env; |
Also available in: Unified diff