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1
/*
2
 *  PowerPC emulation helpers for qemu.
3
 *
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
6
 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
11
 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
16
 * You should have received a copy of the GNU Lesser General Public
17
 * License along with this library; if not, write to the Free Software
18
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
 */
20
#include <stdarg.h>
21
#include <stdlib.h>
22
#include <stdio.h>
23
#include <string.h>
24
#include <inttypes.h>
25
#include <signal.h>
26
#include <assert.h>
27

    
28
#include "cpu.h"
29
#include "exec-all.h"
30

    
31
//#define DEBUG_MMU
32
//#define DEBUG_BATS
33
//#define DEBUG_SOFTWARE_TLB
34
//#define DEBUG_EXCEPTIONS
35
//#define FLUSH_ALL_TLBS
36

    
37
/*****************************************************************************/
38
/* PowerPC MMU emulation */
39

    
40
#if defined(CONFIG_USER_ONLY)
41
int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
42
                              int is_user, int is_softmmu)
43
{
44
    int exception, error_code;
45

    
46
    if (rw == 2) {
47
        exception = POWERPC_EXCP_ISI;
48
        error_code = 0;
49
    } else {
50
        exception = POWERPC_EXCP_DSI;
51
        error_code = 0;
52
        if (rw)
53
            error_code |= 0x02000000;
54
        env->spr[SPR_DAR] = address;
55
        env->spr[SPR_DSISR] = error_code;
56
    }
57
    env->exception_index = exception;
58
    env->error_code = error_code;
59

    
60
    return 1;
61
}
62

    
63
target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
64
{
65
    return addr;
66
}
67

    
68
#else
69
/* Common routines used by software and hardware TLBs emulation */
70
static inline int pte_is_valid (target_ulong pte0)
71
{
72
    return pte0 & 0x80000000 ? 1 : 0;
73
}
74

    
75
static inline void pte_invalidate (target_ulong *pte0)
76
{
77
    *pte0 &= ~0x80000000;
78
}
79

    
80
#if defined(TARGET_PPC64)
81
static inline int pte64_is_valid (target_ulong pte0)
82
{
83
    return pte0 & 0x0000000000000001ULL ? 1 : 0;
84
}
85

    
86
static inline void pte64_invalidate (target_ulong *pte0)
87
{
88
    *pte0 &= ~0x0000000000000001ULL;
89
}
90
#endif
91

    
92
#define PTE_PTEM_MASK 0x7FFFFFBF
93
#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
94
#if defined(TARGET_PPC64)
95
#define PTE64_PTEM_MASK 0xFFFFFFFFFFFFFF80ULL
96
#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
97
#endif
98

    
99
static inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
100
                              target_ulong pte0, target_ulong pte1,
101
                              int h, int rw)
102
{
103
    target_ulong ptem, mmask;
104
    int access, ret, pteh, ptev;
105

    
106
    access = 0;
107
    ret = -1;
108
    /* Check validity and table match */
109
#if defined(TARGET_PPC64)
110
    if (is_64b) {
111
        ptev = pte64_is_valid(pte0);
112
        pteh = (pte0 >> 1) & 1;
113
    } else
114
#endif
115
    {
116
        ptev = pte_is_valid(pte0);
117
        pteh = (pte0 >> 6) & 1;
118
    }
119
    if (ptev && h == pteh) {
120
        /* Check vsid & api */
121
#if defined(TARGET_PPC64)
122
        if (is_64b) {
123
            ptem = pte0 & PTE64_PTEM_MASK;
124
            mmask = PTE64_CHECK_MASK;
125
        } else
126
#endif
127
        {
128
            ptem = pte0 & PTE_PTEM_MASK;
129
            mmask = PTE_CHECK_MASK;
130
        }
131
        if (ptem == ctx->ptem) {
132
            if (ctx->raddr != (target_ulong)-1) {
133
                /* all matches should have equal RPN, WIMG & PP */
134
                if ((ctx->raddr & mmask) != (pte1 & mmask)) {
135
                    if (loglevel != 0)
136
                        fprintf(logfile, "Bad RPN/WIMG/PP\n");
137
                    return -3;
138
                }
139
            }
140
            /* Compute access rights */
141
            if (ctx->key == 0) {
142
                access = PAGE_READ;
143
                if ((pte1 & 0x00000003) != 0x3)
144
                    access |= PAGE_WRITE;
145
            } else {
146
                switch (pte1 & 0x00000003) {
147
                case 0x0:
148
                    access = 0;
149
                    break;
150
                case 0x1:
151
                case 0x3:
152
                    access = PAGE_READ;
153
                    break;
154
                case 0x2:
155
                    access = PAGE_READ | PAGE_WRITE;
156
                    break;
157
                }
158
            }
159
            /* Keep the matching PTE informations */
160
            ctx->raddr = pte1;
161
            ctx->prot = access;
162
            if ((rw == 0 && (access & PAGE_READ)) ||
163
                (rw == 1 && (access & PAGE_WRITE))) {
164
                /* Access granted */
165
#if defined (DEBUG_MMU)
166
                if (loglevel != 0)
167
                    fprintf(logfile, "PTE access granted !\n");
168
#endif
169
                ret = 0;
170
            } else {
171
                /* Access right violation */
172
#if defined (DEBUG_MMU)
173
                if (loglevel != 0)
174
                    fprintf(logfile, "PTE access rejected\n");
175
#endif
176
                ret = -2;
177
            }
178
        }
179
    }
180

    
181
    return ret;
182
}
183

    
184
static int pte32_check (mmu_ctx_t *ctx,
185
                        target_ulong pte0, target_ulong pte1, int h, int rw)
186
{
187
    return _pte_check(ctx, 0, pte0, pte1, h, rw);
188
}
189

    
190
#if defined(TARGET_PPC64)
191
static int pte64_check (mmu_ctx_t *ctx,
192
                        target_ulong pte0, target_ulong pte1, int h, int rw)
193
{
194
    return _pte_check(ctx, 1, pte0, pte1, h, rw);
195
}
196
#endif
197

    
198
static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
199
                             int ret, int rw)
200
{
201
    int store = 0;
202

    
203
    /* Update page flags */
204
    if (!(*pte1p & 0x00000100)) {
205
        /* Update accessed flag */
206
        *pte1p |= 0x00000100;
207
        store = 1;
208
    }
209
    if (!(*pte1p & 0x00000080)) {
210
        if (rw == 1 && ret == 0) {
211
            /* Update changed flag */
212
            *pte1p |= 0x00000080;
213
            store = 1;
214
        } else {
215
            /* Force page fault for first write access */
216
            ctx->prot &= ~PAGE_WRITE;
217
        }
218
    }
219

    
220
    return store;
221
}
222

    
223
/* Software driven TLB helpers */
224
static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
225
                              int way, int is_code)
226
{
227
    int nr;
228

    
229
    /* Select TLB num in a way from address */
230
    nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
231
    /* Select TLB way */
232
    nr += env->tlb_per_way * way;
233
    /* 6xx have separate TLBs for instructions and data */
234
    if (is_code && env->id_tlbs == 1)
235
        nr += env->nb_tlb;
236

    
237
    return nr;
238
}
239

    
240
static void ppc6xx_tlb_invalidate_all (CPUState *env)
241
{
242
    ppc6xx_tlb_t *tlb;
243
    int nr, max;
244

    
245
#if defined (DEBUG_SOFTWARE_TLB) && 0
246
    if (loglevel != 0) {
247
        fprintf(logfile, "Invalidate all TLBs\n");
248
    }
249
#endif
250
    /* Invalidate all defined software TLB */
251
    max = env->nb_tlb;
252
    if (env->id_tlbs == 1)
253
        max *= 2;
254
    for (nr = 0; nr < max; nr++) {
255
        tlb = &env->tlb[nr].tlb6;
256
        pte_invalidate(&tlb->pte0);
257
    }
258
    tlb_flush(env, 1);
259
}
260

    
261
static inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
262
                                                 target_ulong eaddr,
263
                                                 int is_code, int match_epn)
264
{
265
#if !defined(FLUSH_ALL_TLBS)
266
    ppc6xx_tlb_t *tlb;
267
    int way, nr;
268

    
269
    /* Invalidate ITLB + DTLB, all ways */
270
    for (way = 0; way < env->nb_ways; way++) {
271
        nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
272
        tlb = &env->tlb[nr].tlb6;
273
        if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
274
#if defined (DEBUG_SOFTWARE_TLB)
275
            if (loglevel != 0) {
276
                fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n",
277
                        nr, env->nb_tlb, eaddr);
278
            }
279
#endif
280
            pte_invalidate(&tlb->pte0);
281
            tlb_flush_page(env, tlb->EPN);
282
        }
283
    }
284
#else
285
    /* XXX: PowerPC specification say this is valid as well */
286
    ppc6xx_tlb_invalidate_all(env);
287
#endif
288
}
289

    
290
static void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
291
                                        int is_code)
292
{
293
    __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
294
}
295

    
296
void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
297
                       target_ulong pte0, target_ulong pte1)
298
{
299
    ppc6xx_tlb_t *tlb;
300
    int nr;
301

    
302
    nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
303
    tlb = &env->tlb[nr].tlb6;
304
#if defined (DEBUG_SOFTWARE_TLB)
305
    if (loglevel != 0) {
306
        fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
307
                " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
308
    }
309
#endif
310
    /* Invalidate any pending reference in Qemu for this virtual address */
311
    __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
312
    tlb->pte0 = pte0;
313
    tlb->pte1 = pte1;
314
    tlb->EPN = EPN;
315
    /* Store last way for LRU mechanism */
316
    env->last_way = way;
317
}
318

    
319
static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
320
                             target_ulong eaddr, int rw, int access_type)
321
{
322
    ppc6xx_tlb_t *tlb;
323
    int nr, best, way;
324
    int ret;
325

    
326
    best = -1;
327
    ret = -1; /* No TLB found */
328
    for (way = 0; way < env->nb_ways; way++) {
329
        nr = ppc6xx_tlb_getnum(env, eaddr, way,
330
                               access_type == ACCESS_CODE ? 1 : 0);
331
        tlb = &env->tlb[nr].tlb6;
332
        /* This test "emulates" the PTE index match for hardware TLBs */
333
        if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
334
#if defined (DEBUG_SOFTWARE_TLB)
335
            if (loglevel != 0) {
336
                fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX
337
                        "] <> " ADDRX "\n",
338
                        nr, env->nb_tlb,
339
                        pte_is_valid(tlb->pte0) ? "valid" : "inval",
340
                        tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
341
            }
342
#endif
343
            continue;
344
        }
345
#if defined (DEBUG_SOFTWARE_TLB)
346
        if (loglevel != 0) {
347
            fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
348
                    " %c %c\n",
349
                    nr, env->nb_tlb,
350
                    pte_is_valid(tlb->pte0) ? "valid" : "inval",
351
                    tlb->EPN, eaddr, tlb->pte1,
352
                    rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
353
        }
354
#endif
355
        switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) {
356
        case -3:
357
            /* TLB inconsistency */
358
            return -1;
359
        case -2:
360
            /* Access violation */
361
            ret = -2;
362
            best = nr;
363
            break;
364
        case -1:
365
        default:
366
            /* No match */
367
            break;
368
        case 0:
369
            /* access granted */
370
            /* XXX: we should go on looping to check all TLBs consistency
371
             *      but we can speed-up the whole thing as the
372
             *      result would be undefined if TLBs are not consistent.
373
             */
374
            ret = 0;
375
            best = nr;
376
            goto done;
377
        }
378
    }
379
    if (best != -1) {
380
    done:
381
#if defined (DEBUG_SOFTWARE_TLB)
382
        if (loglevel != 0) {
383
            fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
384
                    ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
385
        }
386
#endif
387
        /* Update page flags */
388
        pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
389
    }
390

    
391
    return ret;
392
}
393

    
394
/* Perform BAT hit & translation */
395
static int get_bat (CPUState *env, mmu_ctx_t *ctx,
396
                    target_ulong virtual, int rw, int type)
397
{
398
    target_ulong *BATlt, *BATut, *BATu, *BATl;
399
    target_ulong base, BEPIl, BEPIu, bl;
400
    int i;
401
    int ret = -1;
402

    
403
#if defined (DEBUG_BATS)
404
    if (loglevel != 0) {
405
        fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__,
406
                type == ACCESS_CODE ? 'I' : 'D', virtual);
407
    }
408
#endif
409
    switch (type) {
410
    case ACCESS_CODE:
411
        BATlt = env->IBAT[1];
412
        BATut = env->IBAT[0];
413
        break;
414
    default:
415
        BATlt = env->DBAT[1];
416
        BATut = env->DBAT[0];
417
        break;
418
    }
419
#if defined (DEBUG_BATS)
420
    if (loglevel != 0) {
421
        fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__,
422
                type == ACCESS_CODE ? 'I' : 'D', virtual);
423
    }
424
#endif
425
    base = virtual & 0xFFFC0000;
426
    for (i = 0; i < 4; i++) {
427
        BATu = &BATut[i];
428
        BATl = &BATlt[i];
429
        BEPIu = *BATu & 0xF0000000;
430
        BEPIl = *BATu & 0x0FFE0000;
431
        bl = (*BATu & 0x00001FFC) << 15;
432
#if defined (DEBUG_BATS)
433
        if (loglevel != 0) {
434
            fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
435
                    " BATl 0x" ADDRX "\n",
436
                    __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
437
                    *BATu, *BATl);
438
        }
439
#endif
440
        if ((virtual & 0xF0000000) == BEPIu &&
441
            ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
442
            /* BAT matches */
443
            if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
444
                (msr_pr == 1 && (*BATu & 0x00000001))) {
445
                /* Get physical address */
446
                ctx->raddr = (*BATl & 0xF0000000) |
447
                    ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
448
                    (virtual & 0x0001F000);
449
                if (*BATl & 0x00000001)
450
                    ctx->prot = PAGE_READ;
451
                if (*BATl & 0x00000002)
452
                    ctx->prot = PAGE_WRITE | PAGE_READ;
453
#if defined (DEBUG_BATS)
454
                if (loglevel != 0) {
455
                    fprintf(logfile, "BAT %d match: r 0x" PADDRX
456
                            " prot=%c%c\n",
457
                            i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
458
                            ctx->prot & PAGE_WRITE ? 'W' : '-');
459
                }
460
#endif
461
                ret = 0;
462
                break;
463
            }
464
        }
465
    }
466
    if (ret < 0) {
467
#if defined (DEBUG_BATS)
468
        if (loglevel != 0) {
469
            fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual);
470
            for (i = 0; i < 4; i++) {
471
                BATu = &BATut[i];
472
                BATl = &BATlt[i];
473
                BEPIu = *BATu & 0xF0000000;
474
                BEPIl = *BATu & 0x0FFE0000;
475
                bl = (*BATu & 0x00001FFC) << 15;
476
                fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX
477
                        " BATl 0x" ADDRX " \n\t"
478
                        "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",
479
                        __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
480
                        *BATu, *BATl, BEPIu, BEPIl, bl);
481
            }
482
        }
483
#endif
484
    }
485
    /* No hit */
486
    return ret;
487
}
488

    
489
/* PTE table lookup */
490
static inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h, int rw)
491
{
492
    target_ulong base, pte0, pte1;
493
    int i, good = -1;
494
    int ret, r;
495

    
496
    ret = -1; /* No entry found */
497
    base = ctx->pg_addr[h];
498
    for (i = 0; i < 8; i++) {
499
#if defined(TARGET_PPC64)
500
        if (is_64b) {
501
            pte0 = ldq_phys(base + (i * 16));
502
            pte1 =  ldq_phys(base + (i * 16) + 8);
503
            r = pte64_check(ctx, pte0, pte1, h, rw);
504
        } else
505
#endif
506
        {
507
            pte0 = ldl_phys(base + (i * 8));
508
            pte1 =  ldl_phys(base + (i * 8) + 4);
509
            r = pte32_check(ctx, pte0, pte1, h, rw);
510
        }
511
#if defined (DEBUG_MMU)
512
        if (loglevel != 0) {
513
            fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX
514
                    " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",
515
                    base + (i * 8), pte0, pte1,
516
                    (int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1), ctx->ptem);
517
        }
518
#endif
519
        switch (r) {
520
        case -3:
521
            /* PTE inconsistency */
522
            return -1;
523
        case -2:
524
            /* Access violation */
525
            ret = -2;
526
            good = i;
527
            break;
528
        case -1:
529
        default:
530
            /* No PTE match */
531
            break;
532
        case 0:
533
            /* access granted */
534
            /* XXX: we should go on looping to check all PTEs consistency
535
             *      but if we can speed-up the whole thing as the
536
             *      result would be undefined if PTEs are not consistent.
537
             */
538
            ret = 0;
539
            good = i;
540
            goto done;
541
        }
542
    }
543
    if (good != -1) {
544
    done:
545
#if defined (DEBUG_MMU)
546
        if (loglevel != 0) {
547
            fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x "
548
                    "ret=%d\n",
549
                    ctx->raddr, ctx->prot, ret);
550
        }
551
#endif
552
        /* Update page flags */
553
        pte1 = ctx->raddr;
554
        if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
555
#if defined(TARGET_PPC64)
556
            if (is_64b) {
557
                stq_phys_notdirty(base + (good * 16) + 8, pte1);
558
            } else
559
#endif
560
            {
561
                stl_phys_notdirty(base + (good * 8) + 4, pte1);
562
            }
563
        }
564
    }
565

    
566
    return ret;
567
}
568

    
569
static int find_pte32 (mmu_ctx_t *ctx, int h, int rw)
570
{
571
    return _find_pte(ctx, 0, h, rw);
572
}
573

    
574
#if defined(TARGET_PPC64)
575
static int find_pte64 (mmu_ctx_t *ctx, int h, int rw)
576
{
577
    return _find_pte(ctx, 1, h, rw);
578
}
579
#endif
580

    
581
static inline int find_pte (CPUState *env, mmu_ctx_t *ctx, int h, int rw)
582
{
583
#if defined(TARGET_PPC64)
584
    if (env->mmu_model == POWERPC_MMU_64B ||
585
        env->mmu_model == POWERPC_MMU_64BRIDGE)
586
        return find_pte64(ctx, h, rw);
587
#endif
588

    
589
    return find_pte32(ctx, h, rw);
590
}
591

    
592
static inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
593
                                             int sdr_sh,
594
                                             target_phys_addr_t hash,
595
                                             target_phys_addr_t mask)
596
{
597
    return (sdr1 & ((target_ulong)(-1ULL) << sdr_sh)) | (hash & mask);
598
}
599

    
600
#if defined(TARGET_PPC64)
601
static int slb_lookup (CPUState *env, target_ulong eaddr,
602
                       target_ulong *vsid, target_ulong *page_mask, int *attr)
603
{
604
    target_phys_addr_t sr_base;
605
    target_ulong mask;
606
    uint64_t tmp64;
607
    uint32_t tmp;
608
    int n, ret;
609
    int slb_nr;
610

    
611
    ret = -5;
612
    sr_base = env->spr[SPR_ASR];
613
    mask = 0x0000000000000000ULL; /* Avoid gcc warning */
614
#if 0 /* XXX: Fix this */
615
    slb_nr = env->slb_nr;
616
#else
617
    slb_nr = 32;
618
#endif
619
    for (n = 0; n < slb_nr; n++) {
620
        tmp64 = ldq_phys(sr_base);
621
        if (tmp64 & 0x0000000008000000ULL) {
622
            /* SLB entry is valid */
623
            switch (tmp64 & 0x0000000006000000ULL) {
624
            case 0x0000000000000000ULL:
625
                /* 256 MB segment */
626
                mask = 0xFFFFFFFFF0000000ULL;
627
                break;
628
            case 0x0000000002000000ULL:
629
                /* 1 TB segment */
630
                mask = 0xFFFF000000000000ULL;
631
                break;
632
            case 0x0000000004000000ULL:
633
            case 0x0000000006000000ULL:
634
                /* Reserved => segment is invalid */
635
                continue;
636
            }
637
            if ((eaddr & mask) == (tmp64 & mask)) {
638
                /* SLB match */
639
                tmp = ldl_phys(sr_base + 8);
640
                *vsid = ((tmp64 << 24) | (tmp >> 8)) & 0x0003FFFFFFFFFFFFULL;
641
                *page_mask = ~mask;
642
                *attr = tmp & 0xFF;
643
                ret = 0;
644
                break;
645
            }
646
        }
647
        sr_base += 12;
648
    }
649

    
650
    return ret;
651
}
652
#endif /* defined(TARGET_PPC64) */
653

    
654
/* Perform segment based translation */
655
static int get_segment (CPUState *env, mmu_ctx_t *ctx,
656
                        target_ulong eaddr, int rw, int type)
657
{
658
    target_phys_addr_t sdr, hash, mask, sdr_mask;
659
    target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
660
#if defined(TARGET_PPC64)
661
    int attr;
662
#endif
663
    int ds, nx, vsid_sh, sdr_sh;
664
    int ret, ret2;
665

    
666
#if defined(TARGET_PPC64)
667
    if (env->mmu_model == POWERPC_MMU_64B) {
668
        ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr);
669
        if (ret < 0)
670
            return ret;
671
        ctx->key = ((attr & 0x40) && msr_pr == 1) ||
672
            ((attr & 0x80) && msr_pr == 0) ? 1 : 0;
673
        ds = 0;
674
        nx = attr & 0x20 ? 1 : 0;
675
        vsid_mask = 0x00003FFFFFFFFF80ULL;
676
        vsid_sh = 7;
677
        sdr_sh = 18;
678
        sdr_mask = 0x3FF80;
679
    } else
680
#endif /* defined(TARGET_PPC64) */
681
    {
682
        sr = env->sr[eaddr >> 28];
683
        page_mask = 0x0FFFFFFF;
684
        ctx->key = (((sr & 0x20000000) && msr_pr == 1) ||
685
                    ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
686
        ds = sr & 0x80000000 ? 1 : 0;
687
        nx = sr & 0x10000000 ? 1 : 0;
688
        vsid = sr & 0x00FFFFFF;
689
        vsid_mask = 0x01FFFFC0;
690
        vsid_sh = 6;
691
        sdr_sh = 16;
692
        sdr_mask = 0xFFC0;
693
#if defined (DEBUG_MMU)
694
        if (loglevel != 0) {
695
            fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX
696
                    " nip=0x" ADDRX " lr=0x" ADDRX
697
                    " ir=%d dr=%d pr=%d %d t=%d\n",
698
                    eaddr, (int)(eaddr >> 28), sr, env->nip,
699
                    env->lr, msr_ir, msr_dr, msr_pr, rw, type);
700
        }
701
        if (!ds && loglevel != 0) {
702
            fprintf(logfile, "pte segment: key=%d n=0x" ADDRX "\n",
703
                    ctx->key, sr & 0x10000000);
704
        }
705
#endif
706
    }
707
    ret = -1;
708
    if (!ds) {
709
        /* Check if instruction fetch is allowed, if needed */
710
        if (type != ACCESS_CODE || nx == 0) {
711
            /* Page address translation */
712
            pgidx = (eaddr & page_mask) >> TARGET_PAGE_BITS;
713
            hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
714
            /* Primary table address */
715
            sdr = env->sdr1;
716
            mask = ((sdr & 0x000001FF) << sdr_sh) | sdr_mask;
717
            ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
718
            /* Secondary table address */
719
            hash = (~hash) & vsid_mask;
720
            ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
721
#if defined(TARGET_PPC64)
722
            if (env->mmu_model == POWERPC_MMU_64B ||
723
                env->mmu_model == POWERPC_MMU_64BRIDGE) {
724
                /* Only 5 bits of the page index are used in the AVPN */
725
                ctx->ptem = (vsid << 12) | ((pgidx >> 4) & 0x0F80);
726
            } else
727
#endif
728
            {
729
                ctx->ptem = (vsid << 7) | (pgidx >> 10);
730
            }
731
            /* Initialize real address with an invalid value */
732
            ctx->raddr = (target_ulong)-1;
733
            if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx)) {
734
                /* Software TLB search */
735
                ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
736
            } else {
737
#if defined (DEBUG_MMU)
738
                if (loglevel != 0) {
739
                    fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x "
740
                            "api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n",
741
                            sdr, (uint32_t)vsid, (uint32_t)pgidx,
742
                            (uint32_t)hash, ctx->pg_addr[0]);
743
                }
744
#endif
745
                /* Primary table lookup */
746
                ret = find_pte(env, ctx, 0, rw);
747
                if (ret < 0) {
748
                    /* Secondary table lookup */
749
#if defined (DEBUG_MMU)
750
                    if (eaddr != 0xEFFFFFFF && loglevel != 0) {
751
                        fprintf(logfile,
752
                                "1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x "
753
                                "hash=0x%05x pg_addr=0x" PADDRX "\n",
754
                                sdr, (uint32_t)vsid, (uint32_t)pgidx,
755
                                (uint32_t)hash, ctx->pg_addr[1]);
756
                    }
757
#endif
758
                    ret2 = find_pte(env, ctx, 1, rw);
759
                    if (ret2 != -1)
760
                        ret = ret2;
761
                }
762
            }
763
        } else {
764
#if defined (DEBUG_MMU)
765
            if (loglevel != 0)
766
                fprintf(logfile, "No access allowed\n");
767
#endif
768
            ret = -3;
769
        }
770
    } else {
771
#if defined (DEBUG_MMU)
772
        if (loglevel != 0)
773
            fprintf(logfile, "direct store...\n");
774
#endif
775
        /* Direct-store segment : absolutely *BUGGY* for now */
776
        switch (type) {
777
        case ACCESS_INT:
778
            /* Integer load/store : only access allowed */
779
            break;
780
        case ACCESS_CODE:
781
            /* No code fetch is allowed in direct-store areas */
782
            return -4;
783
        case ACCESS_FLOAT:
784
            /* Floating point load/store */
785
            return -4;
786
        case ACCESS_RES:
787
            /* lwarx, ldarx or srwcx. */
788
            return -4;
789
        case ACCESS_CACHE:
790
            /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
791
            /* Should make the instruction do no-op.
792
             * As it already do no-op, it's quite easy :-)
793
             */
794
            ctx->raddr = eaddr;
795
            return 0;
796
        case ACCESS_EXT:
797
            /* eciwx or ecowx */
798
            return -4;
799
        default:
800
            if (logfile) {
801
                fprintf(logfile, "ERROR: instruction should not need "
802
                        "address translation\n");
803
            }
804
            return -4;
805
        }
806
        if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
807
            ctx->raddr = eaddr;
808
            ret = 2;
809
        } else {
810
            ret = -2;
811
        }
812
    }
813

    
814
    return ret;
815
}
816

    
817
/* Generic TLB check function for embedded PowerPC implementations */
818
static int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
819
                             target_phys_addr_t *raddrp,
820
                             target_ulong address,
821
                             uint32_t pid, int ext, int i)
822
{
823
    target_ulong mask;
824

    
825
    /* Check valid flag */
826
    if (!(tlb->prot & PAGE_VALID)) {
827
        if (loglevel != 0)
828
            fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);
829
        return -1;
830
    }
831
    mask = ~(tlb->size - 1);
832
#if defined (DEBUG_SOFTWARE_TLB)
833
    if (loglevel != 0) {
834
        fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> "
835
                ADDRX " " ADDRX " %d\n",
836
                __func__, i, address, pid, tlb->EPN, mask, (int)tlb->PID);
837
    }
838
#endif
839
    /* Check PID */
840
    if (tlb->PID != 0 && tlb->PID != pid)
841
        return -1;
842
    /* Check effective address */
843
    if ((address & mask) != tlb->EPN)
844
        return -1;
845
    *raddrp = (tlb->RPN & mask) | (address & ~mask);
846
#if (TARGET_PHYS_ADDR_BITS >= 36)
847
    if (ext) {
848
        /* Extend the physical address to 36 bits */
849
        *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32;
850
    }
851
#endif
852

    
853
    return 0;
854
}
855

    
856
/* Generic TLB search function for PowerPC embedded implementations */
857
int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)
858
{
859
    ppcemb_tlb_t *tlb;
860
    target_phys_addr_t raddr;
861
    int i, ret;
862

    
863
    /* Default return value is no match */
864
    ret = -1;
865
    for (i = 0; i < env->nb_tlb; i++) {
866
        tlb = &env->tlb[i].tlbe;
867
        if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {
868
            ret = i;
869
            break;
870
        }
871
    }
872

    
873
    return ret;
874
}
875

    
876
/* Helpers specific to PowerPC 40x implementations */
877
static void ppc4xx_tlb_invalidate_all (CPUState *env)
878
{
879
    ppcemb_tlb_t *tlb;
880
    int i;
881

    
882
    for (i = 0; i < env->nb_tlb; i++) {
883
        tlb = &env->tlb[i].tlbe;
884
        tlb->prot &= ~PAGE_VALID;
885
    }
886
    tlb_flush(env, 1);
887
}
888

    
889
static void ppc4xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
890
                                        uint32_t pid)
891
{
892
#if !defined(FLUSH_ALL_TLBS)
893
    ppcemb_tlb_t *tlb;
894
    target_phys_addr_t raddr;
895
    target_ulong page, end;
896
    int i;
897

    
898
    for (i = 0; i < env->nb_tlb; i++) {
899
        tlb = &env->tlb[i].tlbe;
900
        if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
901
            end = tlb->EPN + tlb->size;
902
            for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
903
                tlb_flush_page(env, page);
904
            tlb->prot &= ~PAGE_VALID;
905
            break;
906
        }
907
    }
908
#else
909
    ppc4xx_tlb_invalidate_all(env);
910
#endif
911
}
912

    
913
int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
914
                                 target_ulong address, int rw, int access_type)
915
{
916
    ppcemb_tlb_t *tlb;
917
    target_phys_addr_t raddr;
918
    int i, ret, zsel, zpr;
919

    
920
    ret = -1;
921
    raddr = -1;
922
    for (i = 0; i < env->nb_tlb; i++) {
923
        tlb = &env->tlb[i].tlbe;
924
        if (ppcemb_tlb_check(env, tlb, &raddr, address,
925
                             env->spr[SPR_40x_PID], 0, i) < 0)
926
            continue;
927
        zsel = (tlb->attr >> 4) & 0xF;
928
        zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
929
#if defined (DEBUG_SOFTWARE_TLB)
930
        if (loglevel != 0) {
931
            fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
932
                    __func__, i, zsel, zpr, rw, tlb->attr);
933
        }
934
#endif
935
        if (access_type == ACCESS_CODE) {
936
            /* Check execute enable bit */
937
            switch (zpr) {
938
            case 0x2:
939
                if (msr_pr)
940
                    goto check_exec_perm;
941
                goto exec_granted;
942
            case 0x0:
943
                if (msr_pr) {
944
                    ctx->prot = 0;
945
                    ret = -3;
946
                    break;
947
                }
948
                /* No break here */
949
            case 0x1:
950
            check_exec_perm:
951
                /* Check from TLB entry */
952
                if (!(tlb->prot & PAGE_EXEC)) {
953
                    ret = -3;
954
                } else {
955
                    if (tlb->prot & PAGE_WRITE) {
956
                        ctx->prot = PAGE_READ | PAGE_WRITE;
957
                    } else {
958
                        ctx->prot = PAGE_READ;
959
                    }
960
                    ret = 0;
961
                }
962
                break;
963
            case 0x3:
964
            exec_granted:
965
                /* All accesses granted */
966
                ctx->prot = PAGE_READ | PAGE_WRITE;
967
                ret = 0;
968
                break;
969
            }
970
        } else {
971
            switch (zpr) {
972
            case 0x2:
973
                if (msr_pr)
974
                    goto check_rw_perm;
975
                goto rw_granted;
976
            case 0x0:
977
                if (msr_pr) {
978
                    ctx->prot = 0;
979
                    ret = -2;
980
                    break;
981
                }
982
                /* No break here */
983
            case 0x1:
984
            check_rw_perm:
985
                /* Check from TLB entry */
986
                /* Check write protection bit */
987
                if (tlb->prot & PAGE_WRITE) {
988
                    ctx->prot = PAGE_READ | PAGE_WRITE;
989
                    ret = 0;
990
                } else {
991
                    ctx->prot = PAGE_READ;
992
                    if (rw)
993
                        ret = -2;
994
                    else
995
                        ret = 0;
996
                }
997
                break;
998
            case 0x3:
999
            rw_granted:
1000
                /* All accesses granted */
1001
                ctx->prot = PAGE_READ | PAGE_WRITE;
1002
                ret = 0;
1003
                break;
1004
            }
1005
        }
1006
        if (ret >= 0) {
1007
            ctx->raddr = raddr;
1008
#if defined (DEBUG_SOFTWARE_TLB)
1009
            if (loglevel != 0) {
1010
                fprintf(logfile, "%s: access granted " ADDRX " => " REGX
1011
                        " %d %d\n", __func__, address, ctx->raddr, ctx->prot,
1012
                        ret);
1013
            }
1014
#endif
1015
            return 0;
1016
        }
1017
    }
1018
#if defined (DEBUG_SOFTWARE_TLB)
1019
    if (loglevel != 0) {
1020
        fprintf(logfile, "%s: access refused " ADDRX " => " REGX
1021
                " %d %d\n", __func__, address, raddr, ctx->prot,
1022
                ret);
1023
    }
1024
#endif
1025

    
1026
    return ret;
1027
}
1028

    
1029
void store_40x_sler (CPUPPCState *env, uint32_t val)
1030
{
1031
    /* XXX: TO BE FIXED */
1032
    if (val != 0x00000000) {
1033
        cpu_abort(env, "Little-endian regions are not supported by now\n");
1034
    }
1035
    env->spr[SPR_405_SLER] = val;
1036
}
1037

    
1038
int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
1039
                                   target_ulong address, int rw,
1040
                                   int access_type)
1041
{
1042
    ppcemb_tlb_t *tlb;
1043
    target_phys_addr_t raddr;
1044
    int i, prot, ret;
1045

    
1046
    ret = -1;
1047
    raddr = -1;
1048
    for (i = 0; i < env->nb_tlb; i++) {
1049
        tlb = &env->tlb[i].tlbe;
1050
        if (ppcemb_tlb_check(env, tlb, &raddr, address,
1051
                             env->spr[SPR_BOOKE_PID], 1, i) < 0)
1052
            continue;
1053
        if (msr_pr)
1054
            prot = tlb->prot & 0xF;
1055
        else
1056
            prot = (tlb->prot >> 4) & 0xF;
1057
        /* Check the address space */
1058
        if (access_type == ACCESS_CODE) {
1059
            if (msr_is != (tlb->attr & 1))
1060
                continue;
1061
            ctx->prot = prot;
1062
            if (prot & PAGE_EXEC) {
1063
                ret = 0;
1064
                break;
1065
            }
1066
            ret = -3;
1067
        } else {
1068
            if (msr_ds != (tlb->attr & 1))
1069
                continue;
1070
            ctx->prot = prot;
1071
            if ((!rw && prot & PAGE_READ) || (rw && (prot & PAGE_WRITE))) {
1072
                ret = 0;
1073
                break;
1074
            }
1075
            ret = -2;
1076
        }
1077
    }
1078
    if (ret >= 0)
1079
        ctx->raddr = raddr;
1080

    
1081
    return ret;
1082
}
1083

    
1084
static int check_physical (CPUState *env, mmu_ctx_t *ctx,
1085
                           target_ulong eaddr, int rw)
1086
{
1087
    int in_plb, ret;
1088

    
1089
    ctx->raddr = eaddr;
1090
    ctx->prot = PAGE_READ;
1091
    ret = 0;
1092
    switch (env->mmu_model) {
1093
    case POWERPC_MMU_32B:
1094
    case POWERPC_MMU_SOFT_6xx:
1095
    case POWERPC_MMU_601:
1096
    case POWERPC_MMU_SOFT_4xx:
1097
    case POWERPC_MMU_REAL_4xx:
1098
        ctx->prot |= PAGE_WRITE;
1099
        break;
1100
#if defined(TARGET_PPC64)
1101
    case POWERPC_MMU_64B:
1102
    case POWERPC_MMU_64BRIDGE:
1103
        /* Real address are 60 bits long */
1104
        ctx->raddr &= 0x0FFFFFFFFFFFFFFFULL;
1105
        ctx->prot |= PAGE_WRITE;
1106
        break;
1107
#endif
1108
    case POWERPC_MMU_SOFT_4xx_Z:
1109
        if (unlikely(msr_pe != 0)) {
1110
            /* 403 family add some particular protections,
1111
             * using PBL/PBU registers for accesses with no translation.
1112
             */
1113
            in_plb =
1114
                /* Check PLB validity */
1115
                (env->pb[0] < env->pb[1] &&
1116
                 /* and address in plb area */
1117
                 eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
1118
                (env->pb[2] < env->pb[3] &&
1119
                 eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
1120
            if (in_plb ^ msr_px) {
1121
                /* Access in protected area */
1122
                if (rw == 1) {
1123
                    /* Access is not allowed */
1124
                    ret = -2;
1125
                }
1126
            } else {
1127
                /* Read-write access is allowed */
1128
                ctx->prot |= PAGE_WRITE;
1129
            }
1130
        }
1131
        break;
1132
    case POWERPC_MMU_BOOKE:
1133
        ctx->prot |= PAGE_WRITE;
1134
        break;
1135
    case POWERPC_MMU_BOOKE_FSL:
1136
        /* XXX: TODO */
1137
        cpu_abort(env, "BookE FSL MMU model not implemented\n");
1138
        break;
1139
    default:
1140
        cpu_abort(env, "Unknown or invalid MMU model\n");
1141
        return -1;
1142
    }
1143

    
1144
    return ret;
1145
}
1146

    
1147
int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
1148
                          int rw, int access_type, int check_BATs)
1149
{
1150
    int ret;
1151
#if 0
1152
    if (loglevel != 0) {
1153
        fprintf(logfile, "%s\n", __func__);
1154
    }
1155
#endif
1156
    if ((access_type == ACCESS_CODE && msr_ir == 0) ||
1157
        (access_type != ACCESS_CODE && msr_dr == 0)) {
1158
        /* No address translation */
1159
        ret = check_physical(env, ctx, eaddr, rw);
1160
    } else {
1161
        ret = -1;
1162
        switch (env->mmu_model) {
1163
        case POWERPC_MMU_32B:
1164
        case POWERPC_MMU_SOFT_6xx:
1165
            /* Try to find a BAT */
1166
            if (check_BATs)
1167
                ret = get_bat(env, ctx, eaddr, rw, access_type);
1168
            /* No break here */
1169
#if defined(TARGET_PPC64)
1170
        case POWERPC_MMU_64B:
1171
        case POWERPC_MMU_64BRIDGE:
1172
#endif
1173
            if (ret < 0) {
1174
                /* We didn't match any BAT entry or don't have BATs */
1175
                ret = get_segment(env, ctx, eaddr, rw, access_type);
1176
            }
1177
            break;
1178
        case POWERPC_MMU_SOFT_4xx:
1179
        case POWERPC_MMU_SOFT_4xx_Z:
1180
            ret = mmu40x_get_physical_address(env, ctx, eaddr,
1181
                                              rw, access_type);
1182
            break;
1183
        case POWERPC_MMU_601:
1184
            /* XXX: TODO */
1185
            cpu_abort(env, "601 MMU model not implemented\n");
1186
            return -1;
1187
        case POWERPC_MMU_BOOKE:
1188
            ret = mmubooke_get_physical_address(env, ctx, eaddr,
1189
                                                rw, access_type);
1190
            break;
1191
        case POWERPC_MMU_BOOKE_FSL:
1192
            /* XXX: TODO */
1193
            cpu_abort(env, "BookE FSL MMU model not implemented\n");
1194
            return -1;
1195
        case POWERPC_MMU_REAL_4xx:
1196
            cpu_abort(env, "PowerPC 401 does not do any translation\n");
1197
            return -1;
1198
        default:
1199
            cpu_abort(env, "Unknown or invalid MMU model\n");
1200
            return -1;
1201
        }
1202
    }
1203
#if 0
1204
    if (loglevel != 0) {
1205
        fprintf(logfile, "%s address " ADDRX " => %d " PADDRX "\n",
1206
                __func__, eaddr, ret, ctx->raddr);
1207
    }
1208
#endif
1209

    
1210
    return ret;
1211
}
1212

    
1213
target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
1214
{
1215
    mmu_ctx_t ctx;
1216

    
1217
    if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0))
1218
        return -1;
1219

    
1220
    return ctx.raddr & TARGET_PAGE_MASK;
1221
}
1222

    
1223
/* Perform address translation */
1224
int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
1225
                              int is_user, int is_softmmu)
1226
{
1227
    mmu_ctx_t ctx;
1228
    int exception = 0, error_code = 0;
1229
    int access_type;
1230
    int ret = 0;
1231

    
1232
    if (rw == 2) {
1233
        /* code access */
1234
        rw = 0;
1235
        access_type = ACCESS_CODE;
1236
    } else {
1237
        /* data access */
1238
        /* XXX: put correct access by using cpu_restore_state()
1239
           correctly */
1240
        access_type = ACCESS_INT;
1241
        //        access_type = env->access_type;
1242
    }
1243
    ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
1244
    if (ret == 0) {
1245
        ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
1246
                           ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
1247
                           is_user, is_softmmu);
1248
    } else if (ret < 0) {
1249
#if defined (DEBUG_MMU)
1250
        if (loglevel != 0)
1251
            cpu_dump_state(env, logfile, fprintf, 0);
1252
#endif
1253
        if (access_type == ACCESS_CODE) {
1254
            exception = POWERPC_EXCP_ISI;
1255
            switch (ret) {
1256
            case -1:
1257
                /* No matches in page tables or TLB */
1258
                switch (env->mmu_model) {
1259
                case POWERPC_MMU_SOFT_6xx:
1260
                    exception = POWERPC_EXCP_IFTLB;
1261
                    env->spr[SPR_IMISS] = address;
1262
                    env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
1263
                    error_code = 1 << 18;
1264
                    goto tlb_miss;
1265
                case POWERPC_MMU_SOFT_4xx:
1266
                case POWERPC_MMU_SOFT_4xx_Z:
1267
                    exception = POWERPC_EXCP_ITLB;
1268
                    error_code = 0;
1269
                    env->spr[SPR_40x_DEAR] = address;
1270
                    env->spr[SPR_40x_ESR] = 0x00000000;
1271
                    break;
1272
                case POWERPC_MMU_32B:
1273
                    error_code = 0x40000000;
1274
                    break;
1275
#if defined(TARGET_PPC64)
1276
                case POWERPC_MMU_64B:
1277
                    /* XXX: TODO */
1278
                    cpu_abort(env, "MMU model not implemented\n");
1279
                    return -1;
1280
                case POWERPC_MMU_64BRIDGE:
1281
                    /* XXX: TODO */
1282
                    cpu_abort(env, "MMU model not implemented\n");
1283
                    return -1;
1284
#endif
1285
                case POWERPC_MMU_601:
1286
                    /* XXX: TODO */
1287
                    cpu_abort(env, "MMU model not implemented\n");
1288
                    return -1;
1289
                case POWERPC_MMU_BOOKE:
1290
                    /* XXX: TODO */
1291
                    cpu_abort(env, "MMU model not implemented\n");
1292
                    return -1;
1293
                case POWERPC_MMU_BOOKE_FSL:
1294
                    /* XXX: TODO */
1295
                    cpu_abort(env, "MMU model not implemented\n");
1296
                    return -1;
1297
                case POWERPC_MMU_REAL_4xx:
1298
                    cpu_abort(env, "PowerPC 401 should never raise any MMU "
1299
                              "exceptions\n");
1300
                    return -1;
1301
                default:
1302
                    cpu_abort(env, "Unknown or invalid MMU model\n");
1303
                    return -1;
1304
                }
1305
                break;
1306
            case -2:
1307
                /* Access rights violation */
1308
                error_code = 0x08000000;
1309
                break;
1310
            case -3:
1311
                /* No execute protection violation */
1312
                error_code = 0x10000000;
1313
                break;
1314
            case -4:
1315
                /* Direct store exception */
1316
                /* No code fetch is allowed in direct-store areas */
1317
                error_code = 0x10000000;
1318
                break;
1319
#if defined(TARGET_PPC64)
1320
            case -5:
1321
                /* No match in segment table */
1322
                exception = POWERPC_EXCP_ISEG;
1323
                error_code = 0;
1324
                break;
1325
#endif
1326
            }
1327
        } else {
1328
            exception = POWERPC_EXCP_DSI;
1329
            switch (ret) {
1330
            case -1:
1331
                /* No matches in page tables or TLB */
1332
                switch (env->mmu_model) {
1333
                case POWERPC_MMU_SOFT_6xx:
1334
                    if (rw == 1) {
1335
                        exception = POWERPC_EXCP_DSTLB;
1336
                        error_code = 1 << 16;
1337
                    } else {
1338
                        exception = POWERPC_EXCP_DLTLB;
1339
                        error_code = 0;
1340
                    }
1341
                    env->spr[SPR_DMISS] = address;
1342
                    env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
1343
                tlb_miss:
1344
                    error_code |= ctx.key << 19;
1345
                    env->spr[SPR_HASH1] = ctx.pg_addr[0];
1346
                    env->spr[SPR_HASH2] = ctx.pg_addr[1];
1347
                    /* Do not alter DAR nor DSISR */
1348
                    goto out;
1349
                case POWERPC_MMU_SOFT_4xx:
1350
                case POWERPC_MMU_SOFT_4xx_Z:
1351
                    exception = POWERPC_EXCP_DTLB;
1352
                    error_code = 0;
1353
                    env->spr[SPR_40x_DEAR] = address;
1354
                    if (rw)
1355
                        env->spr[SPR_40x_ESR] = 0x00800000;
1356
                    else
1357
                        env->spr[SPR_40x_ESR] = 0x00000000;
1358
                    break;
1359
                case POWERPC_MMU_32B:
1360
                    error_code = 0x40000000;
1361
                    break;
1362
#if defined(TARGET_PPC64)
1363
                case POWERPC_MMU_64B:
1364
                    /* XXX: TODO */
1365
                    cpu_abort(env, "MMU model not implemented\n");
1366
                    return -1;
1367
                case POWERPC_MMU_64BRIDGE:
1368
                    /* XXX: TODO */
1369
                    cpu_abort(env, "MMU model not implemented\n");
1370
                    return -1;
1371
#endif
1372
                case POWERPC_MMU_601:
1373
                    /* XXX: TODO */
1374
                    cpu_abort(env, "MMU model not implemented\n");
1375
                    return -1;
1376
                case POWERPC_MMU_BOOKE:
1377
                    /* XXX: TODO */
1378
                    cpu_abort(env, "MMU model not implemented\n");
1379
                    return -1;
1380
                case POWERPC_MMU_BOOKE_FSL:
1381
                    /* XXX: TODO */
1382
                    cpu_abort(env, "MMU model not implemented\n");
1383
                    return -1;
1384
                case POWERPC_MMU_REAL_4xx:
1385
                    cpu_abort(env, "PowerPC 401 should never raise any MMU "
1386
                              "exceptions\n");
1387
                    return -1;
1388
                default:
1389
                    cpu_abort(env, "Unknown or invalid MMU model\n");
1390
                    return -1;
1391
                }
1392
                break;
1393
            case -2:
1394
                /* Access rights violation */
1395
                error_code = 0x08000000;
1396
                break;
1397
            case -4:
1398
                /* Direct store exception */
1399
                switch (access_type) {
1400
                case ACCESS_FLOAT:
1401
                    /* Floating point load/store */
1402
                    exception = POWERPC_EXCP_ALIGN;
1403
                    error_code = POWERPC_EXCP_ALIGN_FP;
1404
                    break;
1405
                case ACCESS_RES:
1406
                    /* lwarx, ldarx or srwcx. */
1407
                    error_code = 0x04000000;
1408
                    break;
1409
                case ACCESS_EXT:
1410
                    /* eciwx or ecowx */
1411
                    error_code = 0x04100000;
1412
                    break;
1413
                default:
1414
                    printf("DSI: invalid exception (%d)\n", ret);
1415
                    exception = POWERPC_EXCP_PROGRAM;
1416
                    error_code = POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
1417
                    break;
1418
                }
1419
                break;
1420
#if defined(TARGET_PPC64)
1421
            case -5:
1422
                /* No match in segment table */
1423
                exception = POWERPC_EXCP_DSEG;
1424
                error_code = 0;
1425
                break;
1426
#endif
1427
            }
1428
            if (exception == POWERPC_EXCP_DSI && rw == 1)
1429
                error_code |= 0x02000000;
1430
            /* Store fault address */
1431
            env->spr[SPR_DAR] = address;
1432
            env->spr[SPR_DSISR] = error_code;
1433
        }
1434
    out:
1435
#if 0
1436
        printf("%s: set exception to %d %02x\n",
1437
               __func__, exception, error_code);
1438
#endif
1439
        env->exception_index = exception;
1440
        env->error_code = error_code;
1441
        ret = 1;
1442
    }
1443

    
1444
    return ret;
1445
}
1446

    
1447
/*****************************************************************************/
1448
/* BATs management */
1449
#if !defined(FLUSH_ALL_TLBS)
1450
static inline void do_invalidate_BAT (CPUPPCState *env,
1451
                                      target_ulong BATu, target_ulong mask)
1452
{
1453
    target_ulong base, end, page;
1454

    
1455
    base = BATu & ~0x0001FFFF;
1456
    end = base + mask + 0x00020000;
1457
#if defined (DEBUG_BATS)
1458
    if (loglevel != 0) {
1459
        fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
1460
                base, end, mask);
1461
    }
1462
#endif
1463
    for (page = base; page != end; page += TARGET_PAGE_SIZE)
1464
        tlb_flush_page(env, page);
1465
#if defined (DEBUG_BATS)
1466
    if (loglevel != 0)
1467
        fprintf(logfile, "Flush done\n");
1468
#endif
1469
}
1470
#endif
1471

    
1472
static inline void dump_store_bat (CPUPPCState *env, char ID, int ul, int nr,
1473
                                   target_ulong value)
1474
{
1475
#if defined (DEBUG_BATS)
1476
    if (loglevel != 0) {
1477
        fprintf(logfile, "Set %cBAT%d%c to 0x" ADDRX " (0x" ADDRX ")\n",
1478
                ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
1479
    }
1480
#endif
1481
}
1482

    
1483
target_ulong do_load_ibatu (CPUPPCState *env, int nr)
1484
{
1485
    return env->IBAT[0][nr];
1486
}
1487

    
1488
target_ulong do_load_ibatl (CPUPPCState *env, int nr)
1489
{
1490
    return env->IBAT[1][nr];
1491
}
1492

    
1493
void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
1494
{
1495
    target_ulong mask;
1496

    
1497
    dump_store_bat(env, 'I', 0, nr, value);
1498
    if (env->IBAT[0][nr] != value) {
1499
        mask = (value << 15) & 0x0FFE0000UL;
1500
#if !defined(FLUSH_ALL_TLBS)
1501
        do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1502
#endif
1503
        /* When storing valid upper BAT, mask BEPI and BRPN
1504
         * and invalidate all TLBs covered by this BAT
1505
         */
1506
        mask = (value << 15) & 0x0FFE0000UL;
1507
        env->IBAT[0][nr] = (value & 0x00001FFFUL) |
1508
            (value & ~0x0001FFFFUL & ~mask);
1509
        env->IBAT[1][nr] = (env->IBAT[1][nr] & 0x0000007B) |
1510
            (env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
1511
#if !defined(FLUSH_ALL_TLBS)
1512
        do_invalidate_BAT(env, env->IBAT[0][nr], mask);
1513
#else
1514
        tlb_flush(env, 1);
1515
#endif
1516
    }
1517
}
1518

    
1519
void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value)
1520
{
1521
    dump_store_bat(env, 'I', 1, nr, value);
1522
    env->IBAT[1][nr] = value;
1523
}
1524

    
1525
target_ulong do_load_dbatu (CPUPPCState *env, int nr)
1526
{
1527
    return env->DBAT[0][nr];
1528
}
1529

    
1530
target_ulong do_load_dbatl (CPUPPCState *env, int nr)
1531
{
1532
    return env->DBAT[1][nr];
1533
}
1534

    
1535
void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value)
1536
{
1537
    target_ulong mask;
1538

    
1539
    dump_store_bat(env, 'D', 0, nr, value);
1540
    if (env->DBAT[0][nr] != value) {
1541
        /* When storing valid upper BAT, mask BEPI and BRPN
1542
         * and invalidate all TLBs covered by this BAT
1543
         */
1544
        mask = (value << 15) & 0x0FFE0000UL;
1545
#if !defined(FLUSH_ALL_TLBS)
1546
        do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1547
#endif
1548
        mask = (value << 15) & 0x0FFE0000UL;
1549
        env->DBAT[0][nr] = (value & 0x00001FFFUL) |
1550
            (value & ~0x0001FFFFUL & ~mask);
1551
        env->DBAT[1][nr] = (env->DBAT[1][nr] & 0x0000007B) |
1552
            (env->DBAT[1][nr] & ~0x0001FFFF & ~mask);
1553
#if !defined(FLUSH_ALL_TLBS)
1554
        do_invalidate_BAT(env, env->DBAT[0][nr], mask);
1555
#else
1556
        tlb_flush(env, 1);
1557
#endif
1558
    }
1559
}
1560

    
1561
void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
1562
{
1563
    dump_store_bat(env, 'D', 1, nr, value);
1564
    env->DBAT[1][nr] = value;
1565
}
1566

    
1567

    
1568
/*****************************************************************************/
1569
/* TLB management */
1570
void ppc_tlb_invalidate_all (CPUPPCState *env)
1571
{
1572
    switch (env->mmu_model) {
1573
    case POWERPC_MMU_SOFT_6xx:
1574
        ppc6xx_tlb_invalidate_all(env);
1575
        break;
1576
    case POWERPC_MMU_SOFT_4xx:
1577
    case POWERPC_MMU_SOFT_4xx_Z:
1578
        ppc4xx_tlb_invalidate_all(env);
1579
        break;
1580
    default:
1581
        tlb_flush(env, 1);
1582
        break;
1583
    }
1584
}
1585

    
1586
void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr)
1587
{
1588
#if !defined(FLUSH_ALL_TLBS)
1589
    addr &= TARGET_PAGE_MASK;
1590
    switch (env->mmu_model) {
1591
    case POWERPC_MMU_SOFT_6xx:
1592
        ppc6xx_tlb_invalidate_virt(env, addr, 0);
1593
        if (env->id_tlbs == 1)
1594
            ppc6xx_tlb_invalidate_virt(env, addr, 1);
1595
        break;
1596
    case POWERPC_MMU_SOFT_4xx:
1597
    case POWERPC_MMU_SOFT_4xx_Z:
1598
        ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);
1599
        break;
1600
    default:
1601
        /* tlbie invalidate TLBs for all segments */
1602
        addr &= ~((target_ulong)-1 << 28);
1603
        /* XXX: this case should be optimized,
1604
         * giving a mask to tlb_flush_page
1605
         */
1606
        tlb_flush_page(env, addr | (0x0 << 28));
1607
        tlb_flush_page(env, addr | (0x1 << 28));
1608
        tlb_flush_page(env, addr | (0x2 << 28));
1609
        tlb_flush_page(env, addr | (0x3 << 28));
1610
        tlb_flush_page(env, addr | (0x4 << 28));
1611
        tlb_flush_page(env, addr | (0x5 << 28));
1612
        tlb_flush_page(env, addr | (0x6 << 28));
1613
        tlb_flush_page(env, addr | (0x7 << 28));
1614
        tlb_flush_page(env, addr | (0x8 << 28));
1615
        tlb_flush_page(env, addr | (0x9 << 28));
1616
        tlb_flush_page(env, addr | (0xA << 28));
1617
        tlb_flush_page(env, addr | (0xB << 28));
1618
        tlb_flush_page(env, addr | (0xC << 28));
1619
        tlb_flush_page(env, addr | (0xD << 28));
1620
        tlb_flush_page(env, addr | (0xE << 28));
1621
        tlb_flush_page(env, addr | (0xF << 28));
1622
    }
1623
#else
1624
    ppc_tlb_invalidate_all(env);
1625
#endif
1626
}
1627

    
1628
#if defined(TARGET_PPC64)
1629
void ppc_slb_invalidate_all (CPUPPCState *env)
1630
{
1631
    /* XXX: TODO */
1632
    tlb_flush(env, 1);
1633
}
1634

    
1635
void ppc_slb_invalidate_one (CPUPPCState *env, uint64_t T0)
1636
{
1637
    /* XXX: TODO */
1638
    tlb_flush(env, 1);
1639
}
1640
#endif
1641

    
1642

    
1643
/*****************************************************************************/
1644
/* Special registers manipulation */
1645
#if defined(TARGET_PPC64)
1646
target_ulong ppc_load_asr (CPUPPCState *env)
1647
{
1648
    return env->asr;
1649
}
1650

    
1651
void ppc_store_asr (CPUPPCState *env, target_ulong value)
1652
{
1653
    if (env->asr != value) {
1654
        env->asr = value;
1655
        tlb_flush(env, 1);
1656
    }
1657
}
1658
#endif
1659

    
1660
target_ulong do_load_sdr1 (CPUPPCState *env)
1661
{
1662
    return env->sdr1;
1663
}
1664

    
1665
void do_store_sdr1 (CPUPPCState *env, target_ulong value)
1666
{
1667
#if defined (DEBUG_MMU)
1668
    if (loglevel != 0) {
1669
        fprintf(logfile, "%s: 0x" ADDRX "\n", __func__, value);
1670
    }
1671
#endif
1672
    if (env->sdr1 != value) {
1673
        env->sdr1 = value;
1674
        tlb_flush(env, 1);
1675
    }
1676
}
1677

    
1678
target_ulong do_load_sr (CPUPPCState *env, int srnum)
1679
{
1680
    return env->sr[srnum];
1681
}
1682

    
1683
void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
1684
{
1685
#if defined (DEBUG_MMU)
1686
    if (loglevel != 0) {
1687
        fprintf(logfile, "%s: reg=%d 0x" ADDRX " " ADDRX "\n",
1688
                __func__, srnum, value, env->sr[srnum]);
1689
    }
1690
#endif
1691
    if (env->sr[srnum] != value) {
1692
        env->sr[srnum] = value;
1693
#if !defined(FLUSH_ALL_TLBS) && 0
1694
        {
1695
            target_ulong page, end;
1696
            /* Invalidate 256 MB of virtual memory */
1697
            page = (16 << 20) * srnum;
1698
            end = page + (16 << 20);
1699
            for (; page != end; page += TARGET_PAGE_SIZE)
1700
                tlb_flush_page(env, page);
1701
        }
1702
#else
1703
        tlb_flush(env, 1);
1704
#endif
1705
    }
1706
}
1707
#endif /* !defined (CONFIG_USER_ONLY) */
1708

    
1709
target_ulong ppc_load_xer (CPUPPCState *env)
1710
{
1711
    return (xer_so << XER_SO) |
1712
        (xer_ov << XER_OV) |
1713
        (xer_ca << XER_CA) |
1714
        (xer_bc << XER_BC) |
1715
        (xer_cmp << XER_CMP);
1716
}
1717

    
1718
void ppc_store_xer (CPUPPCState *env, target_ulong value)
1719
{
1720
    xer_so = (value >> XER_SO) & 0x01;
1721
    xer_ov = (value >> XER_OV) & 0x01;
1722
    xer_ca = (value >> XER_CA) & 0x01;
1723
    xer_cmp = (value >> XER_CMP) & 0xFF;
1724
    xer_bc = (value >> XER_BC) & 0x7F;
1725
}
1726

    
1727
/* Swap temporary saved registers with GPRs */
1728
static inline void swap_gpr_tgpr (CPUPPCState *env)
1729
{
1730
    ppc_gpr_t tmp;
1731

    
1732
    tmp = env->gpr[0];
1733
    env->gpr[0] = env->tgpr[0];
1734
    env->tgpr[0] = tmp;
1735
    tmp = env->gpr[1];
1736
    env->gpr[1] = env->tgpr[1];
1737
    env->tgpr[1] = tmp;
1738
    tmp = env->gpr[2];
1739
    env->gpr[2] = env->tgpr[2];
1740
    env->tgpr[2] = tmp;
1741
    tmp = env->gpr[3];
1742
    env->gpr[3] = env->tgpr[3];
1743
    env->tgpr[3] = tmp;
1744
}
1745

    
1746
/* GDBstub can read and write MSR... */
1747
target_ulong do_load_msr (CPUPPCState *env)
1748
{
1749
    return
1750
#if defined (TARGET_PPC64)
1751
        ((target_ulong)msr_sf   << MSR_SF)   |
1752
        ((target_ulong)msr_isf  << MSR_ISF)  |
1753
        ((target_ulong)msr_hv   << MSR_HV)   |
1754
#endif
1755
        ((target_ulong)msr_ucle << MSR_UCLE) |
1756
        ((target_ulong)msr_vr   << MSR_VR)   | /* VR / SPE */
1757
        ((target_ulong)msr_ap   << MSR_AP)   |
1758
        ((target_ulong)msr_sa   << MSR_SA)   |
1759
        ((target_ulong)msr_key  << MSR_KEY)  |
1760
        ((target_ulong)msr_pow  << MSR_POW)  | /* POW / WE */
1761
        ((target_ulong)msr_tlb  << MSR_TLB)  | /* TLB / TGPE / CE */
1762
        ((target_ulong)msr_ile  << MSR_ILE)  |
1763
        ((target_ulong)msr_ee   << MSR_EE)   |
1764
        ((target_ulong)msr_pr   << MSR_PR)   |
1765
        ((target_ulong)msr_fp   << MSR_FP)   |
1766
        ((target_ulong)msr_me   << MSR_ME)   |
1767
        ((target_ulong)msr_fe0  << MSR_FE0)  |
1768
        ((target_ulong)msr_se   << MSR_SE)   | /* SE / DWE / UBLE */
1769
        ((target_ulong)msr_be   << MSR_BE)   | /* BE / DE */
1770
        ((target_ulong)msr_fe1  << MSR_FE1)  |
1771
        ((target_ulong)msr_al   << MSR_AL)   |
1772
        ((target_ulong)msr_ip   << MSR_IP)   |
1773
        ((target_ulong)msr_ir   << MSR_IR)   | /* IR / IS */
1774
        ((target_ulong)msr_dr   << MSR_DR)   | /* DR / DS */
1775
        ((target_ulong)msr_pe   << MSR_PE)   | /* PE / EP */
1776
        ((target_ulong)msr_px   << MSR_PX)   | /* PX / PMM */
1777
        ((target_ulong)msr_ri   << MSR_RI)   |
1778
        ((target_ulong)msr_le   << MSR_LE);
1779
}
1780

    
1781
void do_store_msr (CPUPPCState *env, target_ulong value)
1782
{
1783
    int enter_pm;
1784

    
1785
    value &= env->msr_mask;
1786
    if (((value >> MSR_IR) & 1) != msr_ir ||
1787
        ((value >> MSR_DR) & 1) != msr_dr) {
1788
        /* Flush all tlb when changing translation mode */
1789
        tlb_flush(env, 1);
1790
        env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1791
    }
1792
#if 0
1793
    if (loglevel != 0) {
1794
        fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
1795
    }
1796
#endif
1797
    switch (env->excp_model) {
1798
    case POWERPC_EXCP_602:
1799
    case POWERPC_EXCP_603:
1800
    case POWERPC_EXCP_603E:
1801
    case POWERPC_EXCP_G2:
1802
        if (((value >> MSR_TGPR) & 1) != msr_tgpr) {
1803
            /* Swap temporary saved registers with GPRs */
1804
            swap_gpr_tgpr(env);
1805
        }
1806
        break;
1807
    default:
1808
        break;
1809
    }
1810
#if defined (TARGET_PPC64)
1811
    msr_sf   = (value >> MSR_SF)   & 1;
1812
    msr_isf  = (value >> MSR_ISF)  & 1;
1813
    msr_hv   = (value >> MSR_HV)   & 1;
1814
#endif
1815
    msr_ucle = (value >> MSR_UCLE) & 1;
1816
    msr_vr   = (value >> MSR_VR)   & 1; /* VR / SPE */
1817
    msr_ap   = (value >> MSR_AP)   & 1;
1818
    msr_sa   = (value >> MSR_SA)   & 1;
1819
    msr_key  = (value >> MSR_KEY)  & 1;
1820
    msr_pow  = (value >> MSR_POW)  & 1; /* POW / WE */
1821
    msr_tlb  = (value >> MSR_TLB)  & 1; /* TLB / TGPR / CE */
1822
    msr_ile  = (value >> MSR_ILE)  & 1;
1823
    msr_ee   = (value >> MSR_EE)   & 1;
1824
    msr_pr   = (value >> MSR_PR)   & 1;
1825
    msr_fp   = (value >> MSR_FP)   & 1;
1826
    msr_me   = (value >> MSR_ME)   & 1;
1827
    msr_fe0  = (value >> MSR_FE0)  & 1;
1828
    msr_se   = (value >> MSR_SE)   & 1; /* SE / DWE / UBLE */
1829
    msr_be   = (value >> MSR_BE)   & 1; /* BE / DE */
1830
    msr_fe1  = (value >> MSR_FE1)  & 1;
1831
    msr_al   = (value >> MSR_AL)   & 1;
1832
    msr_ip   = (value >> MSR_IP)   & 1;
1833
    msr_ir   = (value >> MSR_IR)   & 1; /* IR / IS */
1834
    msr_dr   = (value >> MSR_DR)   & 1; /* DR / DS */
1835
    msr_pe   = (value >> MSR_PE)   & 1; /* PE / EP */
1836
    msr_px   = (value >> MSR_PX)   & 1; /* PX / PMM */
1837
    msr_ri   = (value >> MSR_RI)   & 1;
1838
    msr_le   = (value >> MSR_LE)   & 1;
1839
    do_compute_hflags(env);
1840

    
1841
    enter_pm = 0;
1842
    switch (env->excp_model) {
1843
    case POWERPC_EXCP_603:
1844
    case POWERPC_EXCP_603E:
1845
    case POWERPC_EXCP_G2:
1846
        /* Don't handle SLEEP mode: we should disable all clocks...
1847
         * No dynamic power-management.
1848
         */
1849
        if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00C00000) != 0)
1850
            enter_pm = 1;
1851
        break;
1852
    case POWERPC_EXCP_604:
1853
        if (msr_pow == 1)
1854
            enter_pm = 1;
1855
        break;
1856
    case POWERPC_EXCP_7x0:
1857
        if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0)
1858
            enter_pm = 1;
1859
        break;
1860
    default:
1861
        break;
1862
    }
1863
    if (enter_pm) {
1864
        if (likely(!env->halted)) {
1865
            /* power save: exit cpu loop */
1866
            env->halted = 1;
1867
            env->exception_index = EXCP_HLT;
1868
            cpu_loop_exit();
1869
        }
1870
    }
1871
}
1872

    
1873
#if defined(TARGET_PPC64)
1874
void ppc_store_msr_32 (CPUPPCState *env, uint32_t value)
1875
{
1876
    do_store_msr(env,
1877
                 (do_load_msr(env) & ~0xFFFFFFFFULL) | (value & 0xFFFFFFFF));
1878
}
1879
#endif
1880

    
1881
void do_compute_hflags (CPUPPCState *env)
1882
{
1883
    /* Compute current hflags */
1884
    env->hflags = (msr_vr << MSR_VR) |
1885
        (msr_ap << MSR_AP) | (msr_sa << MSR_SA) | (msr_pr << MSR_PR) |
1886
        (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_se << MSR_SE) |
1887
        (msr_be << MSR_BE) | (msr_fe1 << MSR_FE1) | (msr_le << MSR_LE);
1888
#if defined (TARGET_PPC64)
1889
    env->hflags |= msr_cm << MSR_CM;
1890
    env->hflags |= (uint64_t)msr_sf << MSR_SF;
1891
    env->hflags |= (uint64_t)msr_hv << MSR_HV;
1892
#endif
1893
}
1894

    
1895
/*****************************************************************************/
1896
/* Exception processing */
1897
#if defined (CONFIG_USER_ONLY)
1898
void do_interrupt (CPUState *env)
1899
{
1900
    env->exception_index = POWERPC_EXCP_NONE;
1901
    env->error_code = 0;
1902
}
1903

    
1904
void ppc_hw_interrupt (CPUState *env)
1905
{
1906
    env->exception_index = POWERPC_EXCP_NONE;
1907
    env->error_code = 0;
1908
}
1909
#else /* defined (CONFIG_USER_ONLY) */
1910
static void dump_syscall (CPUState *env)
1911
{
1912
    fprintf(logfile, "syscall r0=0x" REGX " r3=0x" REGX " r4=0x" REGX
1913
            " r5=0x" REGX " r6=0x" REGX " nip=0x" ADDRX "\n",
1914
            env->gpr[0], env->gpr[3], env->gpr[4],
1915
            env->gpr[5], env->gpr[6], env->nip);
1916
}
1917

    
1918
/* Note that this function should be greatly optimized
1919
 * when called with a constant excp, from ppc_hw_interrupt
1920
 */
1921
static always_inline void powerpc_excp (CPUState *env,
1922
                                        int excp_model, int excp)
1923
{
1924
    target_ulong msr, vector;
1925
    int srr0, srr1, asrr0, asrr1;
1926

    
1927
    if (loglevel & CPU_LOG_INT) {
1928
        fprintf(logfile, "Raise exception at 0x" ADDRX " => 0x%08x (%02x)\n",
1929
                env->nip, excp, env->error_code);
1930
    }
1931
    msr = do_load_msr(env);
1932
    srr0 = SPR_SRR0;
1933
    srr1 = SPR_SRR1;
1934
    asrr0 = -1;
1935
    asrr1 = -1;
1936
    msr &= ~((target_ulong)0x783F0000);
1937
    switch (excp) {
1938
    case POWERPC_EXCP_NONE:
1939
        /* Should never happen */
1940
        return;
1941
    case POWERPC_EXCP_CRITICAL:    /* Critical input                         */
1942
        msr_ri = 0; /* XXX: check this */
1943
        switch (excp_model) {
1944
        case POWERPC_EXCP_40x:
1945
            srr0 = SPR_40x_SRR2;
1946
            srr1 = SPR_40x_SRR3;
1947
            break;
1948
        case POWERPC_EXCP_BOOKE:
1949
            srr0 = SPR_BOOKE_CSRR0;
1950
            srr1 = SPR_BOOKE_CSRR1;
1951
            break;
1952
        case POWERPC_EXCP_G2:
1953
            break;
1954
        default:
1955
            goto excp_invalid;
1956
        }
1957
        goto store_next;
1958
    case POWERPC_EXCP_MCHECK:    /* Machine check exception                  */
1959
        if (msr_me == 0) {
1960
            /* Machine check exception is not enabled */
1961
            /* XXX: we may just stop the processor here, to allow debugging */
1962
            excp = POWERPC_EXCP_RESET;
1963
            goto excp_reset;
1964
        }
1965
        msr_ri = 0;
1966
        msr_me = 0;
1967
#if defined(TARGET_PPC64H)
1968
        msr_hv = 1;
1969
#endif
1970
        /* XXX: should also have something loaded in DAR / DSISR */
1971
        switch (excp_model) {
1972
        case POWERPC_EXCP_40x:
1973
            srr0 = SPR_40x_SRR2;
1974
            srr1 = SPR_40x_SRR3;
1975
            break;
1976
        case POWERPC_EXCP_BOOKE:
1977
            srr0 = SPR_BOOKE_MCSRR0;
1978
            srr1 = SPR_BOOKE_MCSRR1;
1979
            asrr0 = SPR_BOOKE_CSRR0;
1980
            asrr1 = SPR_BOOKE_CSRR1;
1981
            break;
1982
        default:
1983
            break;
1984
        }
1985
        goto store_next;
1986
    case POWERPC_EXCP_DSI:       /* Data storage exception                   */
1987
#if defined (DEBUG_EXCEPTIONS)
1988
        if (loglevel != 0) {
1989
            fprintf(logfile, "DSI exception: DSISR=0x" ADDRX" DAR=0x" ADDRX
1990
                    "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]);
1991
        }
1992
#endif
1993
        msr_ri = 0;
1994
#if defined(TARGET_PPC64H)
1995
        if (lpes1 == 0)
1996
            msr_hv = 1;
1997
#endif
1998
        goto store_next;
1999
    case POWERPC_EXCP_ISI:       /* Instruction storage exception            */
2000
#if defined (DEBUG_EXCEPTIONS)
2001
        if (loglevel != 0) {
2002
            fprintf(logfile, "ISI exception: msr=0x" ADDRX ", nip=0x" ADDRX
2003
                    "\n", msr, env->nip);
2004
        }
2005
#endif
2006
        msr_ri = 0;
2007
#if defined(TARGET_PPC64H)
2008
        if (lpes1 == 0)
2009
            msr_hv = 1;
2010
#endif
2011
        msr |= env->error_code;
2012
        goto store_next;
2013
    case POWERPC_EXCP_EXTERNAL:  /* External input                           */
2014
        msr_ri = 0;
2015
#if defined(TARGET_PPC64H)
2016
        if (lpes0 == 1)
2017
            msr_hv = 1;
2018
#endif
2019
        goto store_next;
2020
    case POWERPC_EXCP_ALIGN:     /* Alignment exception                      */
2021
        msr_ri = 0;
2022
#if defined(TARGET_PPC64H)
2023
        if (lpes1 == 0)
2024
            msr_hv = 1;
2025
#endif
2026
        /* XXX: this is false */
2027
        /* Get rS/rD and rA from faulting opcode */
2028
        env->spr[SPR_DSISR] |= (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
2029
        goto store_current;
2030
    case POWERPC_EXCP_PROGRAM:   /* Program exception                        */
2031
        switch (env->error_code & ~0xF) {
2032
        case POWERPC_EXCP_FP:
2033
            if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
2034
#if defined (DEBUG_EXCEPTIONS)
2035
                if (loglevel != 0) {
2036
                    fprintf(logfile, "Ignore floating point exception\n");
2037
                }
2038
#endif
2039
                return;
2040
            }
2041
            msr_ri = 0;
2042
#if defined(TARGET_PPC64H)
2043
            if (lpes1 == 0)
2044
                msr_hv = 1;
2045
#endif
2046
            msr |= 0x00100000;
2047
            /* Set FX */
2048
            env->fpscr[7] |= 0x8;
2049
            /* Finally, update FEX */
2050
            if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
2051
                ((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
2052
                env->fpscr[7] |= 0x4;
2053
            if (msr_fe0 != msr_fe1) {
2054
                msr |= 0x00010000;
2055
                goto store_current;
2056
            }
2057
            break;
2058
        case POWERPC_EXCP_INVAL:
2059
#if defined (DEBUG_EXCEPTIONS)
2060
            if (loglevel != 0) {
2061
                fprintf(logfile, "Invalid instruction at 0x" ADDRX "\n",
2062
                        env->nip);
2063
            }
2064
#endif
2065
            msr_ri = 0;
2066
#if defined(TARGET_PPC64H)
2067
            if (lpes1 == 0)
2068
                msr_hv = 1;
2069
#endif
2070
            msr |= 0x00080000;
2071
            break;
2072
        case POWERPC_EXCP_PRIV:
2073
            msr_ri = 0;
2074
#if defined(TARGET_PPC64H)
2075
            if (lpes1 == 0)
2076
                msr_hv = 1;
2077
#endif
2078
            msr |= 0x00040000;
2079
            break;
2080
        case POWERPC_EXCP_TRAP:
2081
            msr_ri = 0;
2082
#if defined(TARGET_PPC64H)
2083
            if (lpes1 == 0)
2084
                msr_hv = 1;
2085
#endif
2086
            msr |= 0x00020000;
2087
            break;
2088
        default:
2089
            /* Should never occur */
2090
            cpu_abort(env, "Invalid program exception %d. Aborting\n",
2091
                      env->error_code);
2092
            break;
2093
        }
2094
        goto store_next;
2095
    case POWERPC_EXCP_FPU:       /* Floating-point unavailable exception     */
2096
        msr_ri = 0;
2097
#if defined(TARGET_PPC64H)
2098
        if (lpes1 == 0)
2099
            msr_hv = 1;
2100
#endif
2101
        goto store_current;
2102
    case POWERPC_EXCP_SYSCALL:   /* System call exception                    */
2103
        /* NOTE: this is a temporary hack to support graphics OSI
2104
           calls from the MOL driver */
2105
        /* XXX: To be removed */
2106
        if (env->gpr[3] == 0x113724fa && env->gpr[4] == 0x77810f9b &&
2107
            env->osi_call) {
2108
            if (env->osi_call(env) != 0)
2109
                return;
2110
        }
2111
        if (loglevel & CPU_LOG_INT) {
2112
            dump_syscall(env);
2113
        }
2114
        msr_ri = 0;
2115
#if defined(TARGET_PPC64H)
2116
        if (lev == 1 || (lpes0 == 0 && lpes1 == 0))
2117
            msr_hv = 1;
2118
#endif
2119
        goto store_next;
2120
    case POWERPC_EXCP_APU:       /* Auxiliary processor unavailable          */
2121
        msr_ri = 0;
2122
        goto store_current;
2123
    case POWERPC_EXCP_DECR:      /* Decrementer exception                    */
2124
        msr_ri = 0;
2125
#if defined(TARGET_PPC64H)
2126
        if (lpes1 == 0)
2127
            msr_hv = 1;
2128
#endif
2129
        goto store_next;
2130
    case POWERPC_EXCP_FIT:       /* Fixed-interval timer interrupt           */
2131
        /* FIT on 4xx */
2132
#if defined (DEBUG_EXCEPTIONS)
2133
        if (loglevel != 0)
2134
            fprintf(logfile, "FIT exception\n");
2135
#endif
2136
        msr_ri = 0; /* XXX: check this */
2137
        goto store_next;
2138
    case POWERPC_EXCP_WDT:       /* Watchdog timer interrupt                 */
2139
#if defined (DEBUG_EXCEPTIONS)
2140
        if (loglevel != 0)
2141
            fprintf(logfile, "WDT exception\n");
2142
#endif
2143
        switch (excp_model) {
2144
        case POWERPC_EXCP_BOOKE:
2145
            srr0 = SPR_BOOKE_CSRR0;
2146
            srr1 = SPR_BOOKE_CSRR1;
2147
            break;
2148
        default:
2149
            break;
2150
        }
2151
        msr_ri = 0; /* XXX: check this */
2152
        goto store_next;
2153
    case POWERPC_EXCP_DTLB:      /* Data TLB error                           */
2154
        msr_ri = 0; /* XXX: check this */
2155
        goto store_next;
2156
    case POWERPC_EXCP_ITLB:      /* Instruction TLB error                    */
2157
        msr_ri = 0; /* XXX: check this */
2158
        goto store_next;
2159
    case POWERPC_EXCP_DEBUG:     /* Debug interrupt                          */
2160
        switch (excp_model) {
2161
        case POWERPC_EXCP_BOOKE:
2162
            srr0 = SPR_BOOKE_DSRR0;
2163
            srr1 = SPR_BOOKE_DSRR1;
2164
            asrr0 = SPR_BOOKE_CSRR0;
2165
            asrr1 = SPR_BOOKE_CSRR1;
2166
            break;
2167
        default:
2168
            break;
2169
        }
2170
        /* XXX: TODO */
2171
        cpu_abort(env, "Debug exception is not implemented yet !\n");
2172
        goto store_next;
2173
#if defined(TARGET_PPCEMB)
2174
    case POWERPC_EXCP_SPEU:      /* SPE/embedded floating-point unavailable  */
2175
        msr_ri = 0; /* XXX: check this */
2176
        goto store_current;
2177
    case POWERPC_EXCP_EFPDI:     /* Embedded floating-point data interrupt   */
2178
        /* XXX: TODO */
2179
        cpu_abort(env, "Embedded floating point data exception "
2180
                  "is not implemented yet !\n");
2181
        goto store_next;
2182
    case POWERPC_EXCP_EFPRI:     /* Embedded floating-point round interrupt  */
2183
        /* XXX: TODO */
2184
        cpu_abort(env, "Embedded floating point round exception "
2185
                  "is not implemented yet !\n");
2186
        goto store_next;
2187
    case POWERPC_EXCP_EPERFM:    /* Embedded performance monitor interrupt   */
2188
        msr_ri = 0;
2189
        /* XXX: TODO */
2190
        cpu_abort(env,
2191
                  "Performance counter exception is not implemented yet !\n");
2192
        goto store_next;
2193
    case POWERPC_EXCP_DOORI:     /* Embedded doorbell interrupt              */
2194
        /* XXX: TODO */
2195
        cpu_abort(env,
2196
                  "Embedded doorbell interrupt is not implemented yet !\n");
2197
        goto store_next;
2198
    case POWERPC_EXCP_DOORCI:    /* Embedded doorbell critical interrupt     */
2199
        switch (excp_model) {
2200
        case POWERPC_EXCP_BOOKE:
2201
            srr0 = SPR_BOOKE_CSRR0;
2202
            srr1 = SPR_BOOKE_CSRR1;
2203
            break;
2204
        default:
2205
            break;
2206
        }
2207
        /* XXX: TODO */
2208
        cpu_abort(env, "Embedded doorbell critical interrupt "
2209
                  "is not implemented yet !\n");
2210
        goto store_next;
2211
#endif /* defined(TARGET_PPCEMB) */
2212
    case POWERPC_EXCP_RESET:     /* System reset exception                   */
2213
        msr_ri = 0;
2214
#if defined(TARGET_PPC64H)
2215
        msr_hv = 1;
2216
#endif
2217
    excp_reset:
2218
        goto store_next;
2219
#if defined(TARGET_PPC64)
2220
    case POWERPC_EXCP_DSEG:      /* Data segment exception                   */
2221
        msr_ri = 0;
2222
#if defined(TARGET_PPC64H)
2223
        if (lpes1 == 0)
2224
            msr_hv = 1;
2225
#endif
2226
        /* XXX: TODO */
2227
        cpu_abort(env, "Data segment exception is not implemented yet !\n");
2228
        goto store_next;
2229
    case POWERPC_EXCP_ISEG:      /* Instruction segment exception            */
2230
        msr_ri = 0;
2231
#if defined(TARGET_PPC64H)
2232
        if (lpes1 == 0)
2233
            msr_hv = 1;
2234
#endif
2235
        /* XXX: TODO */
2236
        cpu_abort(env,
2237
                  "Instruction segment exception is not implemented yet !\n");
2238
        goto store_next;
2239
#endif /* defined(TARGET_PPC64) */
2240
#if defined(TARGET_PPC64H)
2241
    case POWERPC_EXCP_HDECR:     /* Hypervisor decrementer exception         */
2242
        srr0 = SPR_HSRR0;
2243
        srr1 = SPR_HSSR1;
2244
        msr_hv = 1;
2245
        goto store_next;
2246
#endif
2247
    case POWERPC_EXCP_TRACE:     /* Trace exception                          */
2248
        msr_ri = 0;
2249
#if defined(TARGET_PPC64H)
2250
        if (lpes1 == 0)
2251
            msr_hv = 1;
2252
#endif
2253
        goto store_next;
2254
#if defined(TARGET_PPC64H)
2255
    case POWERPC_EXCP_HDSI:      /* Hypervisor data storage exception        */
2256
        srr0 = SPR_HSRR0;
2257
        srr1 = SPR_HSSR1;
2258
        msr_hv = 1;
2259
        goto store_next;
2260
    case POWERPC_EXCP_HISI:      /* Hypervisor instruction storage exception */
2261
        srr0 = SPR_HSRR0;
2262
        srr1 = SPR_HSSR1;
2263
        msr_hv = 1;
2264
        /* XXX: TODO */
2265
        cpu_abort(env, "Hypervisor instruction storage exception "
2266
                  "is not implemented yet !\n");
2267
        goto store_next;
2268
    case POWERPC_EXCP_HDSEG:     /* Hypervisor data segment exception        */
2269
        srr0 = SPR_HSRR0;
2270
        srr1 = SPR_HSSR1;
2271
        msr_hv = 1;
2272
        goto store_next;
2273
    case POWERPC_EXCP_HISEG:     /* Hypervisor instruction segment exception */
2274
        srr0 = SPR_HSRR0;
2275
        srr1 = SPR_HSSR1;
2276
        msr_hv = 1;
2277
        goto store_next;
2278
#endif /* defined(TARGET_PPC64H) */
2279
    case POWERPC_EXCP_VPU:       /* Vector unavailable exception             */
2280
        msr_ri = 0;
2281
#if defined(TARGET_PPC64H)
2282
        if (lpes1 == 0)
2283
            msr_hv = 1;
2284
#endif
2285
        goto store_current;
2286
    case POWERPC_EXCP_PIT:       /* Programmable interval timer interrupt    */
2287
#if defined (DEBUG_EXCEPTIONS)
2288
        if (loglevel != 0)
2289
            fprintf(logfile, "PIT exception\n");
2290
#endif
2291
        msr_ri = 0; /* XXX: check this */
2292
        goto store_next;
2293
    case POWERPC_EXCP_IO:        /* IO error exception                       */
2294
        /* XXX: TODO */
2295
        cpu_abort(env, "601 IO error exception is not implemented yet !\n");
2296
        goto store_next;
2297
    case POWERPC_EXCP_RUNM:      /* Run mode exception                       */
2298
        /* XXX: TODO */
2299
        cpu_abort(env, "601 run mode exception is not implemented yet !\n");
2300
        goto store_next;
2301
    case POWERPC_EXCP_EMUL:      /* Emulation trap exception                 */
2302
        /* XXX: TODO */
2303
        cpu_abort(env, "602 emulation trap exception "
2304
                  "is not implemented yet !\n");
2305
        goto store_next;
2306
    case POWERPC_EXCP_IFTLB:     /* Instruction fetch TLB error              */
2307
        msr_ri = 0; /* XXX: check this */
2308
#if defined(TARGET_PPC64H) /* XXX: check this */
2309
        if (lpes1 == 0)
2310
            msr_hv = 1;
2311
#endif
2312
        switch (excp_model) {
2313
        case POWERPC_EXCP_602:
2314
        case POWERPC_EXCP_603:
2315
        case POWERPC_EXCP_603E:
2316
        case POWERPC_EXCP_G2:
2317
            goto tlb_miss_tgpr;
2318
        case POWERPC_EXCP_7x5:
2319
            goto tlb_miss;
2320
        default:
2321
            cpu_abort(env, "Invalid instruction TLB miss exception\n");
2322
            break;
2323
        }
2324
        break;
2325
    case POWERPC_EXCP_DLTLB:     /* Data load TLB miss                       */
2326
        msr_ri = 0; /* XXX: check this */
2327
#if defined(TARGET_PPC64H) /* XXX: check this */
2328
        if (lpes1 == 0)
2329
            msr_hv = 1;
2330
#endif
2331
        switch (excp_model) {
2332
        case POWERPC_EXCP_602:
2333
        case POWERPC_EXCP_603:
2334
        case POWERPC_EXCP_603E:
2335
        case POWERPC_EXCP_G2:
2336
            goto tlb_miss_tgpr;
2337
        case POWERPC_EXCP_7x5:
2338
            goto tlb_miss;
2339
        default:
2340
            cpu_abort(env, "Invalid data load TLB miss exception\n");
2341
            break;
2342
        }
2343
        break;
2344
    case POWERPC_EXCP_DSTLB:     /* Data store TLB miss                      */
2345
        msr_ri = 0; /* XXX: check this */
2346
#if defined(TARGET_PPC64H) /* XXX: check this */
2347
        if (lpes1 == 0)
2348
            msr_hv = 1;
2349
#endif
2350
        switch (excp_model) {
2351
        case POWERPC_EXCP_602:
2352
        case POWERPC_EXCP_603:
2353
        case POWERPC_EXCP_603E:
2354
        case POWERPC_EXCP_G2:
2355
        tlb_miss_tgpr:
2356
            /* Swap temporary saved registers with GPRs */
2357
            swap_gpr_tgpr(env);
2358
            msr_tgpr = 1;
2359
            goto tlb_miss;
2360
        case POWERPC_EXCP_7x5:
2361
        tlb_miss:
2362
#if defined (DEBUG_SOFTWARE_TLB)
2363
            if (loglevel != 0) {
2364
                const unsigned char *es;
2365
                target_ulong *miss, *cmp;
2366
                int en;
2367
                if (excp == POWERPC_EXCP_IFTLB) {
2368
                    es = "I";
2369
                    en = 'I';
2370
                    miss = &env->spr[SPR_IMISS];
2371
                    cmp = &env->spr[SPR_ICMP];
2372
                } else {
2373
                    if (excp == POWERPC_EXCP_DLTLB)
2374
                        es = "DL";
2375
                    else
2376
                        es = "DS";
2377
                    en = 'D';
2378
                    miss = &env->spr[SPR_DMISS];
2379
                    cmp = &env->spr[SPR_DCMP];
2380
                }
2381
                fprintf(logfile, "6xx %sTLB miss: %cM " ADDRX " %cC " ADDRX
2382
                        " H1 " ADDRX " H2 " ADDRX " %08x\n",
2383
                        es, en, *miss, en, *cmp,
2384
                        env->spr[SPR_HASH1], env->spr[SPR_HASH2],
2385
                        env->error_code);
2386
            }
2387
#endif
2388
            msr |= env->crf[0] << 28;
2389
            msr |= env->error_code; /* key, D/I, S/L bits */
2390
            /* Set way using a LRU mechanism */
2391
            msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
2392
            break;
2393
        default:
2394
            cpu_abort(env, "Invalid data store TLB miss exception\n");
2395
            break;
2396
        }
2397
        goto store_next;
2398
    case POWERPC_EXCP_FPA:       /* Floating-point assist exception          */
2399
        /* XXX: TODO */
2400
        cpu_abort(env, "Floating point assist exception "
2401
                  "is not implemented yet !\n");
2402
        goto store_next;
2403
    case POWERPC_EXCP_IABR:      /* Instruction address breakpoint           */
2404
        /* XXX: TODO */
2405
        cpu_abort(env, "IABR exception is not implemented yet !\n");
2406
        goto store_next;
2407
    case POWERPC_EXCP_SMI:       /* System management interrupt              */
2408
        /* XXX: TODO */
2409
        cpu_abort(env, "SMI exception is not implemented yet !\n");
2410
        goto store_next;
2411
    case POWERPC_EXCP_THERM:     /* Thermal interrupt                        */
2412
        /* XXX: TODO */
2413
        cpu_abort(env, "Thermal management exception "
2414
                  "is not implemented yet !\n");
2415
        goto store_next;
2416
    case POWERPC_EXCP_PERFM:     /* Embedded performance monitor interrupt   */
2417
        msr_ri = 0;
2418
#if defined(TARGET_PPC64H)
2419
        if (lpes1 == 0)
2420
            msr_hv = 1;
2421
#endif
2422
        /* XXX: TODO */
2423
        cpu_abort(env,
2424
                  "Performance counter exception is not implemented yet !\n");
2425
        goto store_next;
2426
    case POWERPC_EXCP_VPUA:      /* Vector assist exception                  */
2427
        /* XXX: TODO */
2428
        cpu_abort(env, "VPU assist exception is not implemented yet !\n");
2429
        goto store_next;
2430
    case POWERPC_EXCP_SOFTP:     /* Soft patch exception                     */
2431
        /* XXX: TODO */
2432
        cpu_abort(env,
2433
                  "970 soft-patch exception is not implemented yet !\n");
2434
        goto store_next;
2435
    case POWERPC_EXCP_MAINT:     /* Maintenance exception                    */
2436
        /* XXX: TODO */
2437
        cpu_abort(env,
2438
                  "970 maintenance exception is not implemented yet !\n");
2439
        goto store_next;
2440
    default:
2441
    excp_invalid:
2442
        cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
2443
        break;
2444
    store_current:
2445
        /* save current instruction location */
2446
        env->spr[srr0] = env->nip - 4;
2447
        break;
2448
    store_next:
2449
        /* save next instruction location */
2450
        env->spr[srr0] = env->nip;
2451
        break;
2452
    }
2453
    /* Save MSR */
2454
    env->spr[srr1] = msr;
2455
    /* If any alternate SRR register are defined, duplicate saved values */
2456
    if (asrr0 != -1)
2457
        env->spr[asrr0] = env->spr[srr0];
2458
    if (asrr1 != -1)
2459
        env->spr[asrr1] = env->spr[srr1];
2460
    /* If we disactivated any translation, flush TLBs */
2461
    if (msr_ir || msr_dr)
2462
        tlb_flush(env, 1);
2463
    /* reload MSR with correct bits */
2464
    msr_ee = 0;
2465
    msr_pr = 0;
2466
    msr_fp = 0;
2467
    msr_fe0 = 0;
2468
    msr_se = 0;
2469
    msr_be = 0;
2470
    msr_fe1 = 0;
2471
    msr_ir = 0;
2472
    msr_dr = 0;
2473
#if 0 /* Fix this: not on all targets */
2474
    msr_pmm = 0;
2475
#endif
2476
    msr_le = msr_ile;
2477
    do_compute_hflags(env);
2478
    /* Jump to handler */
2479
    vector = env->excp_vectors[excp];
2480
    if (vector == (target_ulong)-1) {
2481
        cpu_abort(env, "Raised an exception without defined vector %d\n",
2482
                  excp);
2483
    }
2484
    vector |= env->excp_prefix;
2485
#if defined(TARGET_PPC64)
2486
    if (excp_model == POWERPC_EXCP_BOOKE) {
2487
        msr_cm = msr_icm;
2488
        if (!msr_cm)
2489
            vector = (uint32_t)vector;
2490
    } else {
2491
        msr_sf = msr_isf;
2492
        if (!msr_sf)
2493
            vector = (uint32_t)vector;
2494
    }
2495
#endif
2496
    env->nip = vector;
2497
    /* Reset exception state */
2498
    env->exception_index = POWERPC_EXCP_NONE;
2499
    env->error_code = 0;
2500
}
2501

    
2502
void do_interrupt (CPUState *env)
2503
{
2504
    powerpc_excp(env, env->excp_model, env->exception_index);
2505
}
2506

    
2507
void ppc_hw_interrupt (CPUPPCState *env)
2508
{
2509
#if 1
2510
    if (loglevel & CPU_LOG_INT) {
2511
        fprintf(logfile, "%s: %p pending %08x req %08x me %d ee %d\n",
2512
                __func__, env, env->pending_interrupts,
2513
                env->interrupt_request, msr_me, msr_ee);
2514
    }
2515
#endif
2516
    /* External reset */
2517
    if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) {
2518
        env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET);
2519
        powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET);
2520
        return;
2521
    }
2522
    /* Machine check exception */
2523
    if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) {
2524
        env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK);
2525
        powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK);
2526
        return;
2527
    }
2528
#if 0 /* TODO */
2529
    /* External debug exception */
2530
    if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) {
2531
        env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG);
2532
        powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG);
2533
        return;
2534
    }
2535
#endif
2536
#if defined(TARGET_PPC64H)
2537
    if ((msr_ee != 0 || msr_hv == 0 || msr_pr == 1) & hdice != 0) {
2538
        /* Hypervisor decrementer exception */
2539
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
2540
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
2541
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR);
2542
            return;
2543
        }
2544
    }
2545
#endif
2546
    if (msr_ce != 0) {
2547
        /* External critical interrupt */
2548
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
2549
            /* Taking a critical external interrupt does not clear the external
2550
             * critical interrupt status
2551
             */
2552
#if 0
2553
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT);
2554
#endif
2555
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL);
2556
            return;
2557
        }
2558
    }
2559
    if (msr_ee != 0) {
2560
        /* Watchdog timer on embedded PowerPC */
2561
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) {
2562
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT);
2563
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT);
2564
            return;
2565
        }
2566
#if defined(TARGET_PPCEMB)
2567
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) {
2568
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL);
2569
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI);
2570
            return;
2571
        }
2572
#endif
2573
#if defined(TARGET_PPCEMB)
2574
        /* External interrupt */
2575
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2576
            /* Taking an external interrupt does not clear the external
2577
             * interrupt status
2578
             */
2579
#if 0
2580
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
2581
#endif
2582
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
2583
            return;
2584
        }
2585
#endif
2586
        /* Fixed interval timer on embedded PowerPC */
2587
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) {
2588
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT);
2589
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT);
2590
            return;
2591
        }
2592
        /* Programmable interval timer on embedded PowerPC */
2593
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) {
2594
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT);
2595
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT);
2596
            return;
2597
        }
2598
        /* Decrementer exception */
2599
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) {
2600
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR);
2601
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR);
2602
            return;
2603
        }
2604
#if !defined(TARGET_PPCEMB)
2605
        /* External interrupt */
2606
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) {
2607
            /* Taking an external interrupt does not clear the external
2608
             * interrupt status
2609
             */
2610
#if 0
2611
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT);
2612
#endif
2613
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL);
2614
            return;
2615
        }
2616
#endif
2617
#if defined(TARGET_PPCEMB)
2618
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
2619
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL);
2620
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI);
2621
            return;
2622
        }
2623
#endif
2624
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) {
2625
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM);
2626
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM);
2627
            return;
2628
        }
2629
        /* Thermal interrupt */
2630
        if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) {
2631
            env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM);
2632
            powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM);
2633
            return;
2634
        }
2635
    }
2636
}
2637
#endif /* !CONFIG_USER_ONLY */
2638

    
2639
void cpu_dump_EA (target_ulong EA)
2640
{
2641
    FILE *f;
2642

    
2643
    if (logfile) {
2644
        f = logfile;
2645
    } else {
2646
        f = stdout;
2647
        return;
2648
    }
2649
    fprintf(f, "Memory access at address " ADDRX "\n", EA);
2650
}
2651

    
2652
void cpu_dump_rfi (target_ulong RA, target_ulong msr)
2653
{
2654
    FILE *f;
2655

    
2656
    if (logfile) {
2657
        f = logfile;
2658
    } else {
2659
        f = stdout;
2660
        return;
2661
    }
2662
    fprintf(f, "Return from exception at " ADDRX " with flags " ADDRX "\n",
2663
            RA, msr);
2664
}
2665

    
2666
void cpu_ppc_reset (void *opaque)
2667
{
2668
    CPUPPCState *env;
2669
    int i;
2670

    
2671
    env = opaque;
2672
    /* XXX: some of those flags initialisation values could depend
2673
     *      on the actual PowerPC implementation
2674
     */
2675
    for (i = 0; i < 63; i++)
2676
        env->msr[i] = 0;
2677
#if defined(TARGET_PPC64)
2678
    msr_hv = 0; /* Should be 1... */
2679
#endif
2680
    msr_ap = 0; /* TO BE CHECKED */
2681
    msr_sa = 0; /* TO BE CHECKED */
2682
    msr_ip = 0; /* TO BE CHECKED */
2683
#if defined (DO_SINGLE_STEP) && 0
2684
    /* Single step trace mode */
2685
    msr_se = 1;
2686
    msr_be = 1;
2687
#endif
2688
#if defined(CONFIG_USER_ONLY)
2689
    msr_fp = 1; /* Allow floating point exceptions */
2690
    msr_pr = 1;
2691
#else
2692
    env->nip = 0xFFFFFFFC;
2693
    ppc_tlb_invalidate_all(env);
2694
#endif
2695
    do_compute_hflags(env);
2696
    env->reserve = -1;
2697
    /* Be sure no exception or interrupt is pending */
2698
    env->pending_interrupts = 0;
2699
    env->exception_index = POWERPC_EXCP_NONE;
2700
    env->error_code = 0;
2701
    /* Flush all TLBs */
2702
    tlb_flush(env, 1);
2703
}
2704

    
2705
CPUPPCState *cpu_ppc_init (void)
2706
{
2707
    CPUPPCState *env;
2708

    
2709
    env = qemu_mallocz(sizeof(CPUPPCState));
2710
    if (!env)
2711
        return NULL;
2712
    cpu_exec_init(env);
2713
    cpu_ppc_reset(env);
2714

    
2715
    return env;
2716
}
2717

    
2718
void cpu_ppc_close (CPUPPCState *env)
2719
{
2720
    /* Should also remove all opcode tables... */
2721
    free(env);
2722
}