Revision db620f46 target-i386/cpu.h

b/target-i386/cpu.h
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#define HF_OSFXSR_SHIFT     16 /* CR4.OSFXSR */
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#define HF_VM_SHIFT         17 /* must be same as eflags */
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#define HF_SMM_SHIFT        19 /* CPU in SMM mode */
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#define HF_GIF_SHIFT        20 /* if set CPU takes interrupts */
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#define HF_HIF_SHIFT        21 /* shadow copy of IF_MASK when in SVM */
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#define HF_NMI_SHIFT        22 /* CPU serving NMI */
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#define HF_SVME_SHIFT       23 /* SVME enabled (copy of EFER.SVME) */
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#define HF_SVMI_SHIFT       24 /* SVM intercepts are active */
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#define HF_SVME_SHIFT       20 /* SVME enabled (copy of EFER.SVME) */
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#define HF_SVMI_SHIFT       21 /* SVM intercepts are active */
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#define HF_CPL_MASK          (3 << HF_CPL_SHIFT)
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#define HF_SOFTMMU_MASK      (1 << HF_SOFTMMU_SHIFT)
......
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#define HF_CS64_MASK         (1 << HF_CS64_SHIFT)
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#define HF_OSFXSR_MASK       (1 << HF_OSFXSR_SHIFT)
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#define HF_SMM_MASK          (1 << HF_SMM_SHIFT)
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#define HF_GIF_MASK          (1 << HF_GIF_SHIFT)
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#define HF_HIF_MASK          (1 << HF_HIF_SHIFT)
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#define HF_NMI_MASK          (1 << HF_NMI_SHIFT)
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#define HF_SVME_MASK         (1 << HF_SVME_SHIFT)
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#define HF_SVMI_MASK         (1 << HF_SVMI_SHIFT)
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/* hflags2 */
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#define HF2_GIF_SHIFT        0 /* if set CPU takes interrupts */
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#define HF2_HIF_SHIFT        1 /* value of IF_MASK when entering SVM */
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#define HF2_NMI_SHIFT        2 /* CPU serving NMI */
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#define HF2_VINTR_SHIFT      3 /* value of V_INTR_MASKING bit */
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#define HF2_GIF_MASK          (1 << HF2_GIF_SHIFT)
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#define HF2_HIF_MASK          (1 << HF2_HIF_SHIFT) 
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#define HF2_NMI_MASK          (1 << HF2_NMI_SHIFT)
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#define HF2_VINTR_MASK        (1 << HF2_VINTR_SHIFT)
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#define CR0_PE_MASK  (1 << 0)
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#define CR0_MP_MASK  (1 << 1)
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#define CR0_EM_MASK  (1 << 2)
......
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    target_ulong cc_dst;
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    uint32_t cc_op;
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    int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
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    uint32_t hflags; /* hidden flags, see HF_xxx constants */
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    uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
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                        are known at translation time. */
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    uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
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    /* segments */
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    SegmentCache segs[6]; /* selector values */
......
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    SegmentCache gdt; /* only base and limit are used */
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    SegmentCache idt; /* only base and limit are used */
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    target_ulong cr[9]; /* NOTE: cr1, cr5-7 are unused */
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    target_ulong cr[5]; /* NOTE: cr1 is unused */
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    uint64_t a20_mask;
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    /* FPU state */
......
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    uint16_t intercept_dr_read;
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    uint16_t intercept_dr_write;
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    uint32_t intercept_exceptions;
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    uint8_t v_tpr;
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#ifdef TARGET_X86_64
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    target_ulong lstar;

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