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1 | fdf9b3e8 | bellard | /*
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2 | fdf9b3e8 | bellard | * SH4 translation
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3 | 5fafdf24 | ths | *
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4 | fdf9b3e8 | bellard | * Copyright (c) 2005 Samuel Tardieu
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5 | fdf9b3e8 | bellard | *
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6 | fdf9b3e8 | bellard | * This library is free software; you can redistribute it and/or
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7 | fdf9b3e8 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | fdf9b3e8 | bellard | * License as published by the Free Software Foundation; either
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9 | fdf9b3e8 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | fdf9b3e8 | bellard | *
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11 | fdf9b3e8 | bellard | * This library is distributed in the hope that it will be useful,
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12 | fdf9b3e8 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | fdf9b3e8 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | fdf9b3e8 | bellard | * Lesser General Public License for more details.
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15 | fdf9b3e8 | bellard | *
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16 | fdf9b3e8 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | fdf9b3e8 | bellard | * License along with this library; if not, write to the Free Software
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18 | fdf9b3e8 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | fdf9b3e8 | bellard | */
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20 | fdf9b3e8 | bellard | #include <stdarg.h> |
21 | fdf9b3e8 | bellard | #include <stdlib.h> |
22 | fdf9b3e8 | bellard | #include <stdio.h> |
23 | fdf9b3e8 | bellard | #include <string.h> |
24 | fdf9b3e8 | bellard | #include <inttypes.h> |
25 | fdf9b3e8 | bellard | #include <assert.h> |
26 | fdf9b3e8 | bellard | |
27 | fdf9b3e8 | bellard | #define DEBUG_DISAS
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28 | fdf9b3e8 | bellard | #define SH4_DEBUG_DISAS
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29 | fdf9b3e8 | bellard | //#define SH4_SINGLE_STEP
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30 | fdf9b3e8 | bellard | |
31 | fdf9b3e8 | bellard | #include "cpu.h" |
32 | fdf9b3e8 | bellard | #include "exec-all.h" |
33 | fdf9b3e8 | bellard | #include "disas.h" |
34 | 57fec1fe | bellard | #include "tcg-op.h" |
35 | ca10f867 | aurel32 | #include "qemu-common.h" |
36 | fdf9b3e8 | bellard | |
37 | a7812ae4 | pbrook | #include "helper.h" |
38 | a7812ae4 | pbrook | #define GEN_HELPER 1 |
39 | a7812ae4 | pbrook | #include "helper.h" |
40 | a7812ae4 | pbrook | |
41 | fdf9b3e8 | bellard | typedef struct DisasContext { |
42 | fdf9b3e8 | bellard | struct TranslationBlock *tb;
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43 | fdf9b3e8 | bellard | target_ulong pc; |
44 | fdf9b3e8 | bellard | uint32_t sr; |
45 | eda9b09b | bellard | uint32_t fpscr; |
46 | fdf9b3e8 | bellard | uint16_t opcode; |
47 | fdf9b3e8 | bellard | uint32_t flags; |
48 | 823029f9 | ths | int bstate;
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49 | fdf9b3e8 | bellard | int memidx;
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50 | fdf9b3e8 | bellard | uint32_t delayed_pc; |
51 | fdf9b3e8 | bellard | int singlestep_enabled;
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52 | fdf9b3e8 | bellard | } DisasContext; |
53 | fdf9b3e8 | bellard | |
54 | fe25591e | aurel32 | #if defined(CONFIG_USER_ONLY)
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55 | fe25591e | aurel32 | #define IS_USER(ctx) 1 |
56 | fe25591e | aurel32 | #else
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57 | fe25591e | aurel32 | #define IS_USER(ctx) (!(ctx->sr & SR_MD))
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58 | fe25591e | aurel32 | #endif
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59 | fe25591e | aurel32 | |
60 | 823029f9 | ths | enum {
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61 | 823029f9 | ths | BS_NONE = 0, /* We go out of the TB without reaching a branch or an |
62 | 823029f9 | ths | * exception condition
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63 | 823029f9 | ths | */
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64 | 823029f9 | ths | BS_STOP = 1, /* We want to stop translation for any reason */ |
65 | 823029f9 | ths | BS_BRANCH = 2, /* We reached a branch condition */ |
66 | 823029f9 | ths | BS_EXCP = 3, /* We reached an exception condition */ |
67 | 823029f9 | ths | }; |
68 | 823029f9 | ths | |
69 | 1e8864f7 | aurel32 | /* global register indexes */
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70 | a7812ae4 | pbrook | static TCGv_ptr cpu_env;
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71 | 1e8864f7 | aurel32 | static TCGv cpu_gregs[24]; |
72 | 3a8a44c4 | aurel32 | static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr;
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73 | 3a8a44c4 | aurel32 | static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
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74 | 1000822b | aurel32 | static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_flags;
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75 | 66ba317c | aurel32 | static TCGv cpu_fregs[32]; |
76 | 1000822b | aurel32 | |
77 | 1000822b | aurel32 | /* internal register indexes */
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78 | 1000822b | aurel32 | static TCGv cpu_flags, cpu_delayed_pc;
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79 | 1e8864f7 | aurel32 | |
80 | 2e70f6ef | pbrook | #include "gen-icount.h" |
81 | 2e70f6ef | pbrook | |
82 | a5f1b965 | blueswir1 | static void sh4_translate_init(void) |
83 | 2e70f6ef | pbrook | { |
84 | 1e8864f7 | aurel32 | int i;
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85 | 2e70f6ef | pbrook | static int done_init = 0; |
86 | 559dd74d | aurel32 | static const char * const gregnames[24] = { |
87 | 1e8864f7 | aurel32 | "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0", |
88 | 1e8864f7 | aurel32 | "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0", |
89 | 1e8864f7 | aurel32 | "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", |
90 | 1e8864f7 | aurel32 | "R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1", |
91 | 1e8864f7 | aurel32 | "R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1" |
92 | 1e8864f7 | aurel32 | }; |
93 | 66ba317c | aurel32 | static const char * const fregnames[32] = { |
94 | 66ba317c | aurel32 | "FPR0_BANK0", "FPR1_BANK0", "FPR2_BANK0", "FPR3_BANK0", |
95 | 66ba317c | aurel32 | "FPR4_BANK0", "FPR5_BANK0", "FPR6_BANK0", "FPR7_BANK0", |
96 | 66ba317c | aurel32 | "FPR8_BANK0", "FPR9_BANK0", "FPR10_BANK0", "FPR11_BANK0", |
97 | 66ba317c | aurel32 | "FPR12_BANK0", "FPR13_BANK0", "FPR14_BANK0", "FPR15_BANK0", |
98 | 66ba317c | aurel32 | "FPR0_BANK1", "FPR1_BANK1", "FPR2_BANK1", "FPR3_BANK1", |
99 | 66ba317c | aurel32 | "FPR4_BANK1", "FPR5_BANK1", "FPR6_BANK1", "FPR7_BANK1", |
100 | 66ba317c | aurel32 | "FPR8_BANK1", "FPR9_BANK1", "FPR10_BANK1", "FPR11_BANK1", |
101 | 66ba317c | aurel32 | "FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1", |
102 | 66ba317c | aurel32 | }; |
103 | 1e8864f7 | aurel32 | |
104 | 2e70f6ef | pbrook | if (done_init)
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105 | 2e70f6ef | pbrook | return;
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106 | 1e8864f7 | aurel32 | |
107 | a7812ae4 | pbrook | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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108 | 1e8864f7 | aurel32 | |
109 | 1e8864f7 | aurel32 | for (i = 0; i < 24; i++) |
110 | a7812ae4 | pbrook | cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0, |
111 | 66ba317c | aurel32 | offsetof(CPUState, gregs[i]), |
112 | 66ba317c | aurel32 | gregnames[i]); |
113 | 988d7eaa | aurel32 | |
114 | a7812ae4 | pbrook | cpu_pc = tcg_global_mem_new_i32(TCG_AREG0, |
115 | a7812ae4 | pbrook | offsetof(CPUState, pc), "PC");
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116 | a7812ae4 | pbrook | cpu_sr = tcg_global_mem_new_i32(TCG_AREG0, |
117 | a7812ae4 | pbrook | offsetof(CPUState, sr), "SR");
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118 | a7812ae4 | pbrook | cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0, |
119 | a7812ae4 | pbrook | offsetof(CPUState, ssr), "SSR");
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120 | a7812ae4 | pbrook | cpu_spc = tcg_global_mem_new_i32(TCG_AREG0, |
121 | a7812ae4 | pbrook | offsetof(CPUState, spc), "SPC");
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122 | a7812ae4 | pbrook | cpu_gbr = tcg_global_mem_new_i32(TCG_AREG0, |
123 | a7812ae4 | pbrook | offsetof(CPUState, gbr), "GBR");
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124 | a7812ae4 | pbrook | cpu_vbr = tcg_global_mem_new_i32(TCG_AREG0, |
125 | a7812ae4 | pbrook | offsetof(CPUState, vbr), "VBR");
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126 | a7812ae4 | pbrook | cpu_sgr = tcg_global_mem_new_i32(TCG_AREG0, |
127 | a7812ae4 | pbrook | offsetof(CPUState, sgr), "SGR");
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128 | a7812ae4 | pbrook | cpu_dbr = tcg_global_mem_new_i32(TCG_AREG0, |
129 | a7812ae4 | pbrook | offsetof(CPUState, dbr), "DBR");
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130 | a7812ae4 | pbrook | cpu_mach = tcg_global_mem_new_i32(TCG_AREG0, |
131 | a7812ae4 | pbrook | offsetof(CPUState, mach), "MACH");
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132 | a7812ae4 | pbrook | cpu_macl = tcg_global_mem_new_i32(TCG_AREG0, |
133 | a7812ae4 | pbrook | offsetof(CPUState, macl), "MACL");
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134 | a7812ae4 | pbrook | cpu_pr = tcg_global_mem_new_i32(TCG_AREG0, |
135 | a7812ae4 | pbrook | offsetof(CPUState, pr), "PR");
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136 | a7812ae4 | pbrook | cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, |
137 | a7812ae4 | pbrook | offsetof(CPUState, fpscr), "FPSCR");
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138 | a7812ae4 | pbrook | cpu_fpul = tcg_global_mem_new_i32(TCG_AREG0, |
139 | a7812ae4 | pbrook | offsetof(CPUState, fpul), "FPUL");
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140 | a7812ae4 | pbrook | |
141 | a7812ae4 | pbrook | cpu_flags = tcg_global_mem_new_i32(TCG_AREG0, |
142 | a7812ae4 | pbrook | offsetof(CPUState, flags), "_flags_");
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143 | a7812ae4 | pbrook | cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0, |
144 | a7812ae4 | pbrook | offsetof(CPUState, delayed_pc), |
145 | a7812ae4 | pbrook | "_delayed_pc_");
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146 | 1000822b | aurel32 | |
147 | 66ba317c | aurel32 | for (i = 0; i < 32; i++) |
148 | 66ba317c | aurel32 | cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0, |
149 | 66ba317c | aurel32 | offsetof(CPUState, fregs[i]), |
150 | 66ba317c | aurel32 | fregnames[i]); |
151 | 66ba317c | aurel32 | |
152 | 988d7eaa | aurel32 | /* register helpers */
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153 | a7812ae4 | pbrook | #define GEN_HELPER 2 |
154 | 988d7eaa | aurel32 | #include "helper.h" |
155 | 988d7eaa | aurel32 | |
156 | 2e70f6ef | pbrook | done_init = 1;
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157 | 2e70f6ef | pbrook | } |
158 | 2e70f6ef | pbrook | |
159 | fdf9b3e8 | bellard | void cpu_dump_state(CPUState * env, FILE * f,
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160 | fdf9b3e8 | bellard | int (*cpu_fprintf) (FILE * f, const char *fmt, ...), |
161 | fdf9b3e8 | bellard | int flags)
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162 | fdf9b3e8 | bellard | { |
163 | fdf9b3e8 | bellard | int i;
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164 | eda9b09b | bellard | cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n",
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165 | eda9b09b | bellard | env->pc, env->sr, env->pr, env->fpscr); |
166 | 274a9e70 | aurel32 | cpu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n",
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167 | 274a9e70 | aurel32 | env->spc, env->ssr, env->gbr, env->vbr); |
168 | 274a9e70 | aurel32 | cpu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n",
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169 | 274a9e70 | aurel32 | env->sgr, env->dbr, env->delayed_pc, env->fpul); |
170 | fdf9b3e8 | bellard | for (i = 0; i < 24; i += 4) { |
171 | fdf9b3e8 | bellard | cpu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n",
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172 | fdf9b3e8 | bellard | i, env->gregs[i], i + 1, env->gregs[i + 1], |
173 | fdf9b3e8 | bellard | i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]); |
174 | fdf9b3e8 | bellard | } |
175 | fdf9b3e8 | bellard | if (env->flags & DELAY_SLOT) {
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176 | fdf9b3e8 | bellard | cpu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n",
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177 | fdf9b3e8 | bellard | env->delayed_pc); |
178 | fdf9b3e8 | bellard | } else if (env->flags & DELAY_SLOT_CONDITIONAL) { |
179 | fdf9b3e8 | bellard | cpu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n",
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180 | fdf9b3e8 | bellard | env->delayed_pc); |
181 | fdf9b3e8 | bellard | } |
182 | fdf9b3e8 | bellard | } |
183 | fdf9b3e8 | bellard | |
184 | fdf9b3e8 | bellard | void cpu_sh4_reset(CPUSH4State * env)
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185 | fdf9b3e8 | bellard | { |
186 | 9c2a9ea1 | pbrook | #if defined(CONFIG_USER_ONLY)
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187 | 4c909d14 | ths | env->sr = SR_FD; /* FD - kernel does lazy fpu context switch */
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188 | 9c2a9ea1 | pbrook | #else
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189 | fdf9b3e8 | bellard | env->sr = 0x700000F0; /* MD, RB, BL, I3-I0 */ |
190 | 9c2a9ea1 | pbrook | #endif
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191 | fdf9b3e8 | bellard | env->vbr = 0;
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192 | fdf9b3e8 | bellard | env->pc = 0xA0000000;
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193 | ea6cf6be | ths | #if defined(CONFIG_USER_ONLY)
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194 | ea6cf6be | ths | env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
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195 | b0b3de89 | bellard | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
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196 | ea6cf6be | ths | #else
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197 | ea6cf6be | ths | env->fpscr = 0x00040001; /* CPU reset value according to SH4 manual */ |
198 | b0b3de89 | bellard | set_float_rounding_mode(float_round_to_zero, &env->fp_status); |
199 | ea6cf6be | ths | #endif
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200 | fdf9b3e8 | bellard | env->mmucr = 0;
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201 | fdf9b3e8 | bellard | } |
202 | fdf9b3e8 | bellard | |
203 | 0fd3ca30 | aurel32 | typedef struct { |
204 | b55266b5 | blueswir1 | const char *name; |
205 | 0fd3ca30 | aurel32 | int id;
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206 | 0fd3ca30 | aurel32 | uint32_t pvr; |
207 | 0fd3ca30 | aurel32 | uint32_t prr; |
208 | 0fd3ca30 | aurel32 | uint32_t cvr; |
209 | 0fd3ca30 | aurel32 | } sh4_def_t; |
210 | 0fd3ca30 | aurel32 | |
211 | 0fd3ca30 | aurel32 | static sh4_def_t sh4_defs[] = {
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212 | 0fd3ca30 | aurel32 | { |
213 | 0fd3ca30 | aurel32 | .name = "SH7750R",
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214 | 0fd3ca30 | aurel32 | .id = SH_CPU_SH7750R, |
215 | 0fd3ca30 | aurel32 | .pvr = 0x00050000,
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216 | 0fd3ca30 | aurel32 | .prr = 0x00000100,
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217 | 0fd3ca30 | aurel32 | .cvr = 0x00110000,
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218 | 0fd3ca30 | aurel32 | }, { |
219 | 0fd3ca30 | aurel32 | .name = "SH7751R",
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220 | 0fd3ca30 | aurel32 | .id = SH_CPU_SH7751R, |
221 | 0fd3ca30 | aurel32 | .pvr = 0x04050005,
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222 | 0fd3ca30 | aurel32 | .prr = 0x00000113,
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223 | 0fd3ca30 | aurel32 | .cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */ |
224 | 0fd3ca30 | aurel32 | }, |
225 | 0fd3ca30 | aurel32 | }; |
226 | 0fd3ca30 | aurel32 | |
227 | b55266b5 | blueswir1 | static const sh4_def_t *cpu_sh4_find_by_name(const char *name) |
228 | 0fd3ca30 | aurel32 | { |
229 | 0fd3ca30 | aurel32 | int i;
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230 | 0fd3ca30 | aurel32 | |
231 | 0fd3ca30 | aurel32 | if (strcasecmp(name, "any") == 0) |
232 | 0fd3ca30 | aurel32 | return &sh4_defs[0]; |
233 | 0fd3ca30 | aurel32 | |
234 | 0fd3ca30 | aurel32 | for (i = 0; i < sizeof(sh4_defs) / sizeof(*sh4_defs); i++) |
235 | 0fd3ca30 | aurel32 | if (strcasecmp(name, sh4_defs[i].name) == 0) |
236 | 0fd3ca30 | aurel32 | return &sh4_defs[i];
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237 | 0fd3ca30 | aurel32 | |
238 | 0fd3ca30 | aurel32 | return NULL; |
239 | 0fd3ca30 | aurel32 | } |
240 | 0fd3ca30 | aurel32 | |
241 | 0fd3ca30 | aurel32 | void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
242 | 0fd3ca30 | aurel32 | { |
243 | 0fd3ca30 | aurel32 | int i;
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244 | 0fd3ca30 | aurel32 | |
245 | 0fd3ca30 | aurel32 | for (i = 0; i < sizeof(sh4_defs) / sizeof(*sh4_defs); i++) |
246 | 0fd3ca30 | aurel32 | (*cpu_fprintf)(f, "%s\n", sh4_defs[i].name);
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247 | 0fd3ca30 | aurel32 | } |
248 | 0fd3ca30 | aurel32 | |
249 | 1ed1a787 | blueswir1 | static void cpu_sh4_register(CPUSH4State *env, const sh4_def_t *def) |
250 | 0fd3ca30 | aurel32 | { |
251 | 0fd3ca30 | aurel32 | env->pvr = def->pvr; |
252 | 0fd3ca30 | aurel32 | env->prr = def->prr; |
253 | 0fd3ca30 | aurel32 | env->cvr = def->cvr; |
254 | 0fd3ca30 | aurel32 | env->id = def->id; |
255 | 0fd3ca30 | aurel32 | } |
256 | 0fd3ca30 | aurel32 | |
257 | aaed909a | bellard | CPUSH4State *cpu_sh4_init(const char *cpu_model) |
258 | fdf9b3e8 | bellard | { |
259 | fdf9b3e8 | bellard | CPUSH4State *env; |
260 | 0fd3ca30 | aurel32 | const sh4_def_t *def;
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261 | fdf9b3e8 | bellard | |
262 | 0fd3ca30 | aurel32 | def = cpu_sh4_find_by_name(cpu_model); |
263 | 0fd3ca30 | aurel32 | if (!def)
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264 | 0fd3ca30 | aurel32 | return NULL; |
265 | fdf9b3e8 | bellard | env = qemu_mallocz(sizeof(CPUSH4State));
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266 | fdf9b3e8 | bellard | if (!env)
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267 | fdf9b3e8 | bellard | return NULL; |
268 | fdf9b3e8 | bellard | cpu_exec_init(env); |
269 | 2e70f6ef | pbrook | sh4_translate_init(); |
270 | 7478757e | aurel32 | env->cpu_model_str = cpu_model; |
271 | fdf9b3e8 | bellard | cpu_sh4_reset(env); |
272 | 0fd3ca30 | aurel32 | cpu_sh4_register(env, def); |
273 | fdf9b3e8 | bellard | tlb_flush(env, 1);
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274 | fdf9b3e8 | bellard | return env;
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275 | fdf9b3e8 | bellard | } |
276 | fdf9b3e8 | bellard | |
277 | fdf9b3e8 | bellard | static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest) |
278 | fdf9b3e8 | bellard | { |
279 | fdf9b3e8 | bellard | TranslationBlock *tb; |
280 | fdf9b3e8 | bellard | tb = ctx->tb; |
281 | fdf9b3e8 | bellard | |
282 | fdf9b3e8 | bellard | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
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283 | fdf9b3e8 | bellard | !ctx->singlestep_enabled) { |
284 | fdf9b3e8 | bellard | /* Use a direct jump if in same page and singlestep not enabled */
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285 | 57fec1fe | bellard | tcg_gen_goto_tb(n); |
286 | 3a8a44c4 | aurel32 | tcg_gen_movi_i32(cpu_pc, dest); |
287 | 57fec1fe | bellard | tcg_gen_exit_tb((long) tb + n);
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288 | fdf9b3e8 | bellard | } else {
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289 | 3a8a44c4 | aurel32 | tcg_gen_movi_i32(cpu_pc, dest); |
290 | 57fec1fe | bellard | if (ctx->singlestep_enabled)
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291 | a7812ae4 | pbrook | gen_helper_debug(); |
292 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
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293 | fdf9b3e8 | bellard | } |
294 | fdf9b3e8 | bellard | } |
295 | fdf9b3e8 | bellard | |
296 | fdf9b3e8 | bellard | static void gen_jump(DisasContext * ctx) |
297 | fdf9b3e8 | bellard | { |
298 | fdf9b3e8 | bellard | if (ctx->delayed_pc == (uint32_t) - 1) { |
299 | fdf9b3e8 | bellard | /* Target is not statically known, it comes necessarily from a
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300 | fdf9b3e8 | bellard | delayed jump as immediate jump are conditinal jumps */
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301 | 1000822b | aurel32 | tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc); |
302 | fdf9b3e8 | bellard | if (ctx->singlestep_enabled)
|
303 | a7812ae4 | pbrook | gen_helper_debug(); |
304 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
305 | fdf9b3e8 | bellard | } else {
|
306 | fdf9b3e8 | bellard | gen_goto_tb(ctx, 0, ctx->delayed_pc);
|
307 | fdf9b3e8 | bellard | } |
308 | fdf9b3e8 | bellard | } |
309 | fdf9b3e8 | bellard | |
310 | 1000822b | aurel32 | static inline void gen_branch_slot(uint32_t delayed_pc, int t) |
311 | 1000822b | aurel32 | { |
312 | c55497ec | aurel32 | TCGv sr; |
313 | 1000822b | aurel32 | int label = gen_new_label();
|
314 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc); |
315 | a7812ae4 | pbrook | sr = tcg_temp_new(); |
316 | c55497ec | aurel32 | tcg_gen_andi_i32(sr, cpu_sr, SR_T); |
317 | c55497ec | aurel32 | tcg_gen_brcondi_i32(TCG_COND_NE, sr, t ? SR_T : 0, label);
|
318 | 1000822b | aurel32 | tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE); |
319 | 1000822b | aurel32 | gen_set_label(label); |
320 | 1000822b | aurel32 | } |
321 | 1000822b | aurel32 | |
322 | fdf9b3e8 | bellard | /* Immediate conditional jump (bt or bf) */
|
323 | fdf9b3e8 | bellard | static void gen_conditional_jump(DisasContext * ctx, |
324 | fdf9b3e8 | bellard | target_ulong ift, target_ulong ifnott) |
325 | fdf9b3e8 | bellard | { |
326 | fdf9b3e8 | bellard | int l1;
|
327 | c55497ec | aurel32 | TCGv sr; |
328 | fdf9b3e8 | bellard | |
329 | fdf9b3e8 | bellard | l1 = gen_new_label(); |
330 | a7812ae4 | pbrook | sr = tcg_temp_new(); |
331 | c55497ec | aurel32 | tcg_gen_andi_i32(sr, cpu_sr, SR_T); |
332 | c55497ec | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, sr, SR_T, l1); |
333 | fdf9b3e8 | bellard | gen_goto_tb(ctx, 0, ifnott);
|
334 | fdf9b3e8 | bellard | gen_set_label(l1); |
335 | fdf9b3e8 | bellard | gen_goto_tb(ctx, 1, ift);
|
336 | fdf9b3e8 | bellard | } |
337 | fdf9b3e8 | bellard | |
338 | fdf9b3e8 | bellard | /* Delayed conditional jump (bt or bf) */
|
339 | fdf9b3e8 | bellard | static void gen_delayed_conditional_jump(DisasContext * ctx) |
340 | fdf9b3e8 | bellard | { |
341 | fdf9b3e8 | bellard | int l1;
|
342 | c55497ec | aurel32 | TCGv ds; |
343 | fdf9b3e8 | bellard | |
344 | fdf9b3e8 | bellard | l1 = gen_new_label(); |
345 | a7812ae4 | pbrook | ds = tcg_temp_new(); |
346 | c55497ec | aurel32 | tcg_gen_andi_i32(ds, cpu_flags, DELAY_SLOT_TRUE); |
347 | c55497ec | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, ds, DELAY_SLOT_TRUE, l1); |
348 | 823029f9 | ths | gen_goto_tb(ctx, 1, ctx->pc + 2); |
349 | fdf9b3e8 | bellard | gen_set_label(l1); |
350 | 1000822b | aurel32 | tcg_gen_andi_i32(cpu_flags, cpu_flags, ~DELAY_SLOT_TRUE); |
351 | 9c2a9ea1 | pbrook | gen_jump(ctx); |
352 | fdf9b3e8 | bellard | } |
353 | fdf9b3e8 | bellard | |
354 | a4625612 | aurel32 | static inline void gen_set_t(void) |
355 | a4625612 | aurel32 | { |
356 | a4625612 | aurel32 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T); |
357 | a4625612 | aurel32 | } |
358 | a4625612 | aurel32 | |
359 | a4625612 | aurel32 | static inline void gen_clr_t(void) |
360 | a4625612 | aurel32 | { |
361 | a4625612 | aurel32 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); |
362 | a4625612 | aurel32 | } |
363 | a4625612 | aurel32 | |
364 | a4625612 | aurel32 | static inline void gen_cmp(int cond, TCGv t0, TCGv t1) |
365 | a4625612 | aurel32 | { |
366 | a4625612 | aurel32 | int label1 = gen_new_label();
|
367 | a4625612 | aurel32 | int label2 = gen_new_label();
|
368 | a4625612 | aurel32 | tcg_gen_brcond_i32(cond, t1, t0, label1); |
369 | a4625612 | aurel32 | gen_clr_t(); |
370 | a4625612 | aurel32 | tcg_gen_br(label2); |
371 | a4625612 | aurel32 | gen_set_label(label1); |
372 | a4625612 | aurel32 | gen_set_t(); |
373 | a4625612 | aurel32 | gen_set_label(label2); |
374 | a4625612 | aurel32 | } |
375 | a4625612 | aurel32 | |
376 | a4625612 | aurel32 | static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm) |
377 | a4625612 | aurel32 | { |
378 | a4625612 | aurel32 | int label1 = gen_new_label();
|
379 | a4625612 | aurel32 | int label2 = gen_new_label();
|
380 | a4625612 | aurel32 | tcg_gen_brcondi_i32(cond, t0, imm, label1); |
381 | a4625612 | aurel32 | gen_clr_t(); |
382 | a4625612 | aurel32 | tcg_gen_br(label2); |
383 | a4625612 | aurel32 | gen_set_label(label1); |
384 | a4625612 | aurel32 | gen_set_t(); |
385 | a4625612 | aurel32 | gen_set_label(label2); |
386 | a4625612 | aurel32 | } |
387 | a4625612 | aurel32 | |
388 | 1000822b | aurel32 | static inline void gen_store_flags(uint32_t flags) |
389 | 1000822b | aurel32 | { |
390 | 1000822b | aurel32 | tcg_gen_andi_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE); |
391 | 1000822b | aurel32 | tcg_gen_ori_i32(cpu_flags, cpu_flags, flags); |
392 | 1000822b | aurel32 | } |
393 | 1000822b | aurel32 | |
394 | 69d6275b | aurel32 | static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1) |
395 | 69d6275b | aurel32 | { |
396 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
397 | 69d6275b | aurel32 | |
398 | 69d6275b | aurel32 | p0 &= 0x1f;
|
399 | 69d6275b | aurel32 | p1 &= 0x1f;
|
400 | 69d6275b | aurel32 | |
401 | 69d6275b | aurel32 | tcg_gen_andi_i32(tmp, t1, (1 << p1));
|
402 | 69d6275b | aurel32 | tcg_gen_andi_i32(t0, t0, ~(1 << p0));
|
403 | 69d6275b | aurel32 | if (p0 < p1)
|
404 | 69d6275b | aurel32 | tcg_gen_shri_i32(tmp, tmp, p1 - p0); |
405 | 69d6275b | aurel32 | else if (p0 > p1) |
406 | 69d6275b | aurel32 | tcg_gen_shli_i32(tmp, tmp, p0 - p1); |
407 | 69d6275b | aurel32 | tcg_gen_or_i32(t0, t0, tmp); |
408 | 69d6275b | aurel32 | |
409 | 69d6275b | aurel32 | tcg_temp_free(tmp); |
410 | 69d6275b | aurel32 | } |
411 | 69d6275b | aurel32 | |
412 | a7812ae4 | pbrook | static inline void gen_load_fpr64(TCGv_i64 t, int reg) |
413 | cc4ba6a9 | aurel32 | { |
414 | 66ba317c | aurel32 | tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]);
|
415 | cc4ba6a9 | aurel32 | } |
416 | cc4ba6a9 | aurel32 | |
417 | a7812ae4 | pbrook | static inline void gen_store_fpr64 (TCGv_i64 t, int reg) |
418 | cc4ba6a9 | aurel32 | { |
419 | a7812ae4 | pbrook | TCGv_i32 tmp = tcg_temp_new_i32(); |
420 | cc4ba6a9 | aurel32 | tcg_gen_trunc_i64_i32(tmp, t); |
421 | 66ba317c | aurel32 | tcg_gen_mov_i32(cpu_fregs[reg + 1], tmp);
|
422 | cc4ba6a9 | aurel32 | tcg_gen_shri_i64(t, t, 32);
|
423 | cc4ba6a9 | aurel32 | tcg_gen_trunc_i64_i32(tmp, t); |
424 | 66ba317c | aurel32 | tcg_gen_mov_i32(cpu_fregs[reg], tmp); |
425 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp); |
426 | cc4ba6a9 | aurel32 | } |
427 | cc4ba6a9 | aurel32 | |
428 | fdf9b3e8 | bellard | #define B3_0 (ctx->opcode & 0xf) |
429 | fdf9b3e8 | bellard | #define B6_4 ((ctx->opcode >> 4) & 0x7) |
430 | fdf9b3e8 | bellard | #define B7_4 ((ctx->opcode >> 4) & 0xf) |
431 | fdf9b3e8 | bellard | #define B7_0 (ctx->opcode & 0xff) |
432 | fdf9b3e8 | bellard | #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff)) |
433 | fdf9b3e8 | bellard | #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \ |
434 | fdf9b3e8 | bellard | (ctx->opcode & 0xfff))
|
435 | fdf9b3e8 | bellard | #define B11_8 ((ctx->opcode >> 8) & 0xf) |
436 | fdf9b3e8 | bellard | #define B15_12 ((ctx->opcode >> 12) & 0xf) |
437 | fdf9b3e8 | bellard | |
438 | fdf9b3e8 | bellard | #define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \ |
439 | 7efbe241 | aurel32 | (cpu_gregs[x + 16]) : (cpu_gregs[x]))
|
440 | fdf9b3e8 | bellard | |
441 | fdf9b3e8 | bellard | #define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \ |
442 | 7efbe241 | aurel32 | ? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
|
443 | fdf9b3e8 | bellard | |
444 | eda9b09b | bellard | #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x)) |
445 | f09111e0 | ths | #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) |
446 | eda9b09b | bellard | #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x)) |
447 | ea6cf6be | ths | #define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */ |
448 | eda9b09b | bellard | |
449 | fdf9b3e8 | bellard | #define CHECK_NOT_DELAY_SLOT \
|
450 | fdf9b3e8 | bellard | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
|
451 | a7812ae4 | pbrook | {gen_helper_raise_slot_illegal_instruction(); ctx->bstate = BS_EXCP; \ |
452 | fdf9b3e8 | bellard | return;}
|
453 | fdf9b3e8 | bellard | |
454 | fe25591e | aurel32 | #define CHECK_PRIVILEGED \
|
455 | fe25591e | aurel32 | if (IS_USER(ctx)) { \
|
456 | a7812ae4 | pbrook | gen_helper_raise_illegal_instruction(); \ |
457 | fe25591e | aurel32 | ctx->bstate = BS_EXCP; \ |
458 | fe25591e | aurel32 | return; \
|
459 | fe25591e | aurel32 | } |
460 | fe25591e | aurel32 | |
461 | b1d8e52e | blueswir1 | static void _decode_opc(DisasContext * ctx) |
462 | fdf9b3e8 | bellard | { |
463 | fdf9b3e8 | bellard | #if 0
|
464 | fdf9b3e8 | bellard | fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);
|
465 | fdf9b3e8 | bellard | #endif
|
466 | fdf9b3e8 | bellard | switch (ctx->opcode) {
|
467 | fdf9b3e8 | bellard | case 0x0019: /* div0u */ |
468 | 3a8a44c4 | aurel32 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T)); |
469 | fdf9b3e8 | bellard | return;
|
470 | fdf9b3e8 | bellard | case 0x000b: /* rts */ |
471 | 1000822b | aurel32 | CHECK_NOT_DELAY_SLOT |
472 | 1000822b | aurel32 | tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr); |
473 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
474 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
475 | fdf9b3e8 | bellard | return;
|
476 | fdf9b3e8 | bellard | case 0x0028: /* clrmac */ |
477 | 3a8a44c4 | aurel32 | tcg_gen_movi_i32(cpu_mach, 0);
|
478 | 3a8a44c4 | aurel32 | tcg_gen_movi_i32(cpu_macl, 0);
|
479 | fdf9b3e8 | bellard | return;
|
480 | fdf9b3e8 | bellard | case 0x0048: /* clrs */ |
481 | 3a8a44c4 | aurel32 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S); |
482 | fdf9b3e8 | bellard | return;
|
483 | fdf9b3e8 | bellard | case 0x0008: /* clrt */ |
484 | a4625612 | aurel32 | gen_clr_t(); |
485 | fdf9b3e8 | bellard | return;
|
486 | fdf9b3e8 | bellard | case 0x0038: /* ldtlb */ |
487 | fe25591e | aurel32 | CHECK_PRIVILEGED |
488 | a7812ae4 | pbrook | gen_helper_ldtlb(); |
489 | fdf9b3e8 | bellard | return;
|
490 | c5e814b2 | ths | case 0x002b: /* rte */ |
491 | fe25591e | aurel32 | CHECK_PRIVILEGED |
492 | 1000822b | aurel32 | CHECK_NOT_DELAY_SLOT |
493 | 1000822b | aurel32 | tcg_gen_mov_i32(cpu_sr, cpu_ssr); |
494 | 1000822b | aurel32 | tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc); |
495 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
496 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
497 | fdf9b3e8 | bellard | return;
|
498 | fdf9b3e8 | bellard | case 0x0058: /* sets */ |
499 | 3a8a44c4 | aurel32 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S); |
500 | fdf9b3e8 | bellard | return;
|
501 | fdf9b3e8 | bellard | case 0x0018: /* sett */ |
502 | a4625612 | aurel32 | gen_set_t(); |
503 | fdf9b3e8 | bellard | return;
|
504 | 24988dc2 | aurel32 | case 0xfbfd: /* frchg */ |
505 | 6f06939b | aurel32 | tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR); |
506 | 823029f9 | ths | ctx->bstate = BS_STOP; |
507 | fdf9b3e8 | bellard | return;
|
508 | 24988dc2 | aurel32 | case 0xf3fd: /* fschg */ |
509 | 6f06939b | aurel32 | tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ); |
510 | 823029f9 | ths | ctx->bstate = BS_STOP; |
511 | fdf9b3e8 | bellard | return;
|
512 | fdf9b3e8 | bellard | case 0x0009: /* nop */ |
513 | fdf9b3e8 | bellard | return;
|
514 | fdf9b3e8 | bellard | case 0x001b: /* sleep */ |
515 | fe25591e | aurel32 | CHECK_PRIVILEGED |
516 | a7812ae4 | pbrook | gen_helper_sleep(tcg_const_i32(ctx->pc + 2));
|
517 | fdf9b3e8 | bellard | return;
|
518 | fdf9b3e8 | bellard | } |
519 | fdf9b3e8 | bellard | |
520 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf000) { |
521 | fdf9b3e8 | bellard | case 0x1000: /* mov.l Rm,@(disp,Rn) */ |
522 | c55497ec | aurel32 | { |
523 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
524 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
|
525 | c55497ec | aurel32 | tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); |
526 | c55497ec | aurel32 | tcg_temp_free(addr); |
527 | c55497ec | aurel32 | } |
528 | fdf9b3e8 | bellard | return;
|
529 | fdf9b3e8 | bellard | case 0x5000: /* mov.l @(disp,Rm),Rn */ |
530 | c55497ec | aurel32 | { |
531 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
532 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4);
|
533 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); |
534 | c55497ec | aurel32 | tcg_temp_free(addr); |
535 | c55497ec | aurel32 | } |
536 | fdf9b3e8 | bellard | return;
|
537 | 24988dc2 | aurel32 | case 0xe000: /* mov #imm,Rn */ |
538 | 7efbe241 | aurel32 | tcg_gen_movi_i32(REG(B11_8), B7_0s); |
539 | fdf9b3e8 | bellard | return;
|
540 | fdf9b3e8 | bellard | case 0x9000: /* mov.w @(disp,PC),Rn */ |
541 | c55497ec | aurel32 | { |
542 | c55497ec | aurel32 | TCGv addr = tcg_const_i32(ctx->pc + 4 + B7_0 * 2); |
543 | c55497ec | aurel32 | tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx); |
544 | c55497ec | aurel32 | tcg_temp_free(addr); |
545 | c55497ec | aurel32 | } |
546 | fdf9b3e8 | bellard | return;
|
547 | fdf9b3e8 | bellard | case 0xd000: /* mov.l @(disp,PC),Rn */ |
548 | c55497ec | aurel32 | { |
549 | c55497ec | aurel32 | TCGv addr = tcg_const_i32((ctx->pc + 4 + B7_0 * 4) & ~3); |
550 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); |
551 | c55497ec | aurel32 | tcg_temp_free(addr); |
552 | c55497ec | aurel32 | } |
553 | fdf9b3e8 | bellard | return;
|
554 | 24988dc2 | aurel32 | case 0x7000: /* add #imm,Rn */ |
555 | 7efbe241 | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), B7_0s); |
556 | fdf9b3e8 | bellard | return;
|
557 | fdf9b3e8 | bellard | case 0xa000: /* bra disp */ |
558 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
559 | 1000822b | aurel32 | ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2; |
560 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc); |
561 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
562 | fdf9b3e8 | bellard | return;
|
563 | fdf9b3e8 | bellard | case 0xb000: /* bsr disp */ |
564 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
565 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
|
566 | 1000822b | aurel32 | ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2; |
567 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc); |
568 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
569 | fdf9b3e8 | bellard | return;
|
570 | fdf9b3e8 | bellard | } |
571 | fdf9b3e8 | bellard | |
572 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf00f) { |
573 | fdf9b3e8 | bellard | case 0x6003: /* mov Rm,Rn */ |
574 | 7efbe241 | aurel32 | tcg_gen_mov_i32(REG(B11_8), REG(B7_4)); |
575 | fdf9b3e8 | bellard | return;
|
576 | fdf9b3e8 | bellard | case 0x2000: /* mov.b Rm,@Rn */ |
577 | 7efbe241 | aurel32 | tcg_gen_qemu_st8(REG(B7_4), REG(B11_8), ctx->memidx); |
578 | fdf9b3e8 | bellard | return;
|
579 | fdf9b3e8 | bellard | case 0x2001: /* mov.w Rm,@Rn */ |
580 | 7efbe241 | aurel32 | tcg_gen_qemu_st16(REG(B7_4), REG(B11_8), ctx->memidx); |
581 | fdf9b3e8 | bellard | return;
|
582 | fdf9b3e8 | bellard | case 0x2002: /* mov.l Rm,@Rn */ |
583 | 7efbe241 | aurel32 | tcg_gen_qemu_st32(REG(B7_4), REG(B11_8), ctx->memidx); |
584 | fdf9b3e8 | bellard | return;
|
585 | fdf9b3e8 | bellard | case 0x6000: /* mov.b @Rm,Rn */ |
586 | 7efbe241 | aurel32 | tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx); |
587 | fdf9b3e8 | bellard | return;
|
588 | fdf9b3e8 | bellard | case 0x6001: /* mov.w @Rm,Rn */ |
589 | 7efbe241 | aurel32 | tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx); |
590 | fdf9b3e8 | bellard | return;
|
591 | fdf9b3e8 | bellard | case 0x6002: /* mov.l @Rm,Rn */ |
592 | 7efbe241 | aurel32 | tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx); |
593 | fdf9b3e8 | bellard | return;
|
594 | fdf9b3e8 | bellard | case 0x2004: /* mov.b Rm,@-Rn */ |
595 | c55497ec | aurel32 | { |
596 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
597 | c55497ec | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 1);
|
598 | c55497ec | aurel32 | tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); /* might cause re-execution */
|
599 | c55497ec | aurel32 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); /* modify register status */ |
600 | c55497ec | aurel32 | tcg_temp_free(addr); |
601 | c55497ec | aurel32 | } |
602 | fdf9b3e8 | bellard | return;
|
603 | fdf9b3e8 | bellard | case 0x2005: /* mov.w Rm,@-Rn */ |
604 | c55497ec | aurel32 | { |
605 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
606 | c55497ec | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 2);
|
607 | c55497ec | aurel32 | tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx); |
608 | c55497ec | aurel32 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 2);
|
609 | c55497ec | aurel32 | tcg_temp_free(addr); |
610 | c55497ec | aurel32 | } |
611 | fdf9b3e8 | bellard | return;
|
612 | fdf9b3e8 | bellard | case 0x2006: /* mov.l Rm,@-Rn */ |
613 | c55497ec | aurel32 | { |
614 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
615 | c55497ec | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
616 | c55497ec | aurel32 | tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); |
617 | c55497ec | aurel32 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
|
618 | c55497ec | aurel32 | } |
619 | fdf9b3e8 | bellard | return;
|
620 | eda9b09b | bellard | case 0x6004: /* mov.b @Rm+,Rn */ |
621 | 7efbe241 | aurel32 | tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx); |
622 | 24988dc2 | aurel32 | if ( B11_8 != B7_4 )
|
623 | 7efbe241 | aurel32 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1);
|
624 | fdf9b3e8 | bellard | return;
|
625 | fdf9b3e8 | bellard | case 0x6005: /* mov.w @Rm+,Rn */ |
626 | 7efbe241 | aurel32 | tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx); |
627 | 24988dc2 | aurel32 | if ( B11_8 != B7_4 )
|
628 | 7efbe241 | aurel32 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
|
629 | fdf9b3e8 | bellard | return;
|
630 | fdf9b3e8 | bellard | case 0x6006: /* mov.l @Rm+,Rn */ |
631 | 7efbe241 | aurel32 | tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx); |
632 | 24988dc2 | aurel32 | if ( B11_8 != B7_4 )
|
633 | 7efbe241 | aurel32 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
|
634 | fdf9b3e8 | bellard | return;
|
635 | fdf9b3e8 | bellard | case 0x0004: /* mov.b Rm,@(R0,Rn) */ |
636 | c55497ec | aurel32 | { |
637 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
638 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(B11_8), REG(0));
|
639 | c55497ec | aurel32 | tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); |
640 | c55497ec | aurel32 | tcg_temp_free(addr); |
641 | c55497ec | aurel32 | } |
642 | fdf9b3e8 | bellard | return;
|
643 | fdf9b3e8 | bellard | case 0x0005: /* mov.w Rm,@(R0,Rn) */ |
644 | c55497ec | aurel32 | { |
645 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
646 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(B11_8), REG(0));
|
647 | c55497ec | aurel32 | tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx); |
648 | c55497ec | aurel32 | tcg_temp_free(addr); |
649 | c55497ec | aurel32 | } |
650 | fdf9b3e8 | bellard | return;
|
651 | fdf9b3e8 | bellard | case 0x0006: /* mov.l Rm,@(R0,Rn) */ |
652 | c55497ec | aurel32 | { |
653 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
654 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(B11_8), REG(0));
|
655 | c55497ec | aurel32 | tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); |
656 | c55497ec | aurel32 | tcg_temp_free(addr); |
657 | c55497ec | aurel32 | } |
658 | fdf9b3e8 | bellard | return;
|
659 | fdf9b3e8 | bellard | case 0x000c: /* mov.b @(R0,Rm),Rn */ |
660 | c55497ec | aurel32 | { |
661 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
662 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(B7_4), REG(0));
|
663 | c55497ec | aurel32 | tcg_gen_qemu_ld8s(REG(B11_8), addr, ctx->memidx); |
664 | c55497ec | aurel32 | tcg_temp_free(addr); |
665 | c55497ec | aurel32 | } |
666 | fdf9b3e8 | bellard | return;
|
667 | fdf9b3e8 | bellard | case 0x000d: /* mov.w @(R0,Rm),Rn */ |
668 | c55497ec | aurel32 | { |
669 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
670 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(B7_4), REG(0));
|
671 | c55497ec | aurel32 | tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx); |
672 | c55497ec | aurel32 | tcg_temp_free(addr); |
673 | c55497ec | aurel32 | } |
674 | fdf9b3e8 | bellard | return;
|
675 | fdf9b3e8 | bellard | case 0x000e: /* mov.l @(R0,Rm),Rn */ |
676 | c55497ec | aurel32 | { |
677 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
678 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(B7_4), REG(0));
|
679 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); |
680 | c55497ec | aurel32 | tcg_temp_free(addr); |
681 | c55497ec | aurel32 | } |
682 | fdf9b3e8 | bellard | return;
|
683 | fdf9b3e8 | bellard | case 0x6008: /* swap.b Rm,Rn */ |
684 | c55497ec | aurel32 | { |
685 | c69e3264 | aurel32 | TCGv highw, high, low; |
686 | a7812ae4 | pbrook | highw = tcg_temp_new(); |
687 | c69e3264 | aurel32 | tcg_gen_andi_i32(highw, REG(B7_4), 0xffff0000);
|
688 | a7812ae4 | pbrook | high = tcg_temp_new(); |
689 | c55497ec | aurel32 | tcg_gen_ext8u_i32(high, REG(B7_4)); |
690 | c55497ec | aurel32 | tcg_gen_shli_i32(high, high, 8);
|
691 | a7812ae4 | pbrook | low = tcg_temp_new(); |
692 | c55497ec | aurel32 | tcg_gen_shri_i32(low, REG(B7_4), 8);
|
693 | c55497ec | aurel32 | tcg_gen_ext8u_i32(low, low); |
694 | c55497ec | aurel32 | tcg_gen_or_i32(REG(B11_8), high, low); |
695 | c69e3264 | aurel32 | tcg_gen_or_i32(REG(B11_8), REG(B11_8), highw); |
696 | c55497ec | aurel32 | tcg_temp_free(low); |
697 | c55497ec | aurel32 | tcg_temp_free(high); |
698 | c55497ec | aurel32 | } |
699 | fdf9b3e8 | bellard | return;
|
700 | fdf9b3e8 | bellard | case 0x6009: /* swap.w Rm,Rn */ |
701 | c55497ec | aurel32 | { |
702 | c55497ec | aurel32 | TCGv high, low; |
703 | a7812ae4 | pbrook | high = tcg_temp_new(); |
704 | c55497ec | aurel32 | tcg_gen_ext16u_i32(high, REG(B7_4)); |
705 | c55497ec | aurel32 | tcg_gen_shli_i32(high, high, 16);
|
706 | a7812ae4 | pbrook | low = tcg_temp_new(); |
707 | c55497ec | aurel32 | tcg_gen_shri_i32(low, REG(B7_4), 16);
|
708 | c55497ec | aurel32 | tcg_gen_ext16u_i32(low, low); |
709 | c55497ec | aurel32 | tcg_gen_or_i32(REG(B11_8), high, low); |
710 | c55497ec | aurel32 | tcg_temp_free(low); |
711 | c55497ec | aurel32 | tcg_temp_free(high); |
712 | c55497ec | aurel32 | } |
713 | fdf9b3e8 | bellard | return;
|
714 | fdf9b3e8 | bellard | case 0x200d: /* xtrct Rm,Rn */ |
715 | c55497ec | aurel32 | { |
716 | c55497ec | aurel32 | TCGv high, low; |
717 | a7812ae4 | pbrook | high = tcg_temp_new(); |
718 | c55497ec | aurel32 | tcg_gen_ext16u_i32(high, REG(B7_4)); |
719 | c55497ec | aurel32 | tcg_gen_shli_i32(high, high, 16);
|
720 | a7812ae4 | pbrook | low = tcg_temp_new(); |
721 | c55497ec | aurel32 | tcg_gen_shri_i32(low, REG(B11_8), 16);
|
722 | c55497ec | aurel32 | tcg_gen_ext16u_i32(low, low); |
723 | c55497ec | aurel32 | tcg_gen_or_i32(REG(B11_8), high, low); |
724 | c55497ec | aurel32 | tcg_temp_free(low); |
725 | c55497ec | aurel32 | tcg_temp_free(high); |
726 | c55497ec | aurel32 | } |
727 | fdf9b3e8 | bellard | return;
|
728 | fdf9b3e8 | bellard | case 0x300c: /* add Rm,Rn */ |
729 | 7efbe241 | aurel32 | tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
730 | fdf9b3e8 | bellard | return;
|
731 | fdf9b3e8 | bellard | case 0x300e: /* addc Rm,Rn */ |
732 | a7812ae4 | pbrook | gen_helper_addc(REG(B11_8), REG(B7_4), REG(B11_8)); |
733 | fdf9b3e8 | bellard | return;
|
734 | fdf9b3e8 | bellard | case 0x300f: /* addv Rm,Rn */ |
735 | a7812ae4 | pbrook | gen_helper_addv(REG(B11_8), REG(B7_4), REG(B11_8)); |
736 | fdf9b3e8 | bellard | return;
|
737 | fdf9b3e8 | bellard | case 0x2009: /* and Rm,Rn */ |
738 | 7efbe241 | aurel32 | tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
739 | fdf9b3e8 | bellard | return;
|
740 | fdf9b3e8 | bellard | case 0x3000: /* cmp/eq Rm,Rn */ |
741 | 7efbe241 | aurel32 | gen_cmp(TCG_COND_EQ, REG(B7_4), REG(B11_8)); |
742 | fdf9b3e8 | bellard | return;
|
743 | fdf9b3e8 | bellard | case 0x3003: /* cmp/ge Rm,Rn */ |
744 | 7efbe241 | aurel32 | gen_cmp(TCG_COND_GE, REG(B7_4), REG(B11_8)); |
745 | fdf9b3e8 | bellard | return;
|
746 | fdf9b3e8 | bellard | case 0x3007: /* cmp/gt Rm,Rn */ |
747 | 7efbe241 | aurel32 | gen_cmp(TCG_COND_GT, REG(B7_4), REG(B11_8)); |
748 | fdf9b3e8 | bellard | return;
|
749 | fdf9b3e8 | bellard | case 0x3006: /* cmp/hi Rm,Rn */ |
750 | 7efbe241 | aurel32 | gen_cmp(TCG_COND_GTU, REG(B7_4), REG(B11_8)); |
751 | fdf9b3e8 | bellard | return;
|
752 | fdf9b3e8 | bellard | case 0x3002: /* cmp/hs Rm,Rn */ |
753 | 7efbe241 | aurel32 | gen_cmp(TCG_COND_GEU, REG(B7_4), REG(B11_8)); |
754 | fdf9b3e8 | bellard | return;
|
755 | fdf9b3e8 | bellard | case 0x200c: /* cmp/str Rm,Rn */ |
756 | 69d6275b | aurel32 | { |
757 | 69d6275b | aurel32 | int label1 = gen_new_label();
|
758 | 69d6275b | aurel32 | int label2 = gen_new_label();
|
759 | c55497ec | aurel32 | TCGv cmp1 = tcg_temp_local_new(TCG_TYPE_I32); |
760 | c55497ec | aurel32 | TCGv cmp2 = tcg_temp_local_new(TCG_TYPE_I32); |
761 | c55497ec | aurel32 | tcg_gen_xor_i32(cmp1, REG(B7_4), REG(B11_8)); |
762 | c55497ec | aurel32 | tcg_gen_andi_i32(cmp2, cmp1, 0xff000000);
|
763 | c55497ec | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
|
764 | c55497ec | aurel32 | tcg_gen_andi_i32(cmp2, cmp1, 0x00ff0000);
|
765 | c55497ec | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
|
766 | c55497ec | aurel32 | tcg_gen_andi_i32(cmp2, cmp1, 0x0000ff00);
|
767 | c55497ec | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
|
768 | c55497ec | aurel32 | tcg_gen_andi_i32(cmp2, cmp1, 0x000000ff);
|
769 | c55497ec | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, cmp2, 0, label1);
|
770 | 69d6275b | aurel32 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); |
771 | 69d6275b | aurel32 | tcg_gen_br(label2); |
772 | 69d6275b | aurel32 | gen_set_label(label1); |
773 | 69d6275b | aurel32 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T); |
774 | 69d6275b | aurel32 | gen_set_label(label2); |
775 | c55497ec | aurel32 | tcg_temp_free(cmp2); |
776 | c55497ec | aurel32 | tcg_temp_free(cmp1); |
777 | 69d6275b | aurel32 | } |
778 | fdf9b3e8 | bellard | return;
|
779 | fdf9b3e8 | bellard | case 0x2007: /* div0s Rm,Rn */ |
780 | c55497ec | aurel32 | { |
781 | c55497ec | aurel32 | gen_copy_bit_i32(cpu_sr, 8, REG(B11_8), 31); /* SR_Q */ |
782 | c55497ec | aurel32 | gen_copy_bit_i32(cpu_sr, 9, REG(B7_4), 31); /* SR_M */ |
783 | a7812ae4 | pbrook | TCGv val = tcg_temp_new(); |
784 | c55497ec | aurel32 | tcg_gen_xor_i32(val, REG(B7_4), REG(B11_8)); |
785 | c55497ec | aurel32 | gen_copy_bit_i32(cpu_sr, 0, val, 31); /* SR_T */ |
786 | c55497ec | aurel32 | tcg_temp_free(val); |
787 | c55497ec | aurel32 | } |
788 | fdf9b3e8 | bellard | return;
|
789 | fdf9b3e8 | bellard | case 0x3004: /* div1 Rm,Rn */ |
790 | a7812ae4 | pbrook | gen_helper_div1(REG(B11_8), REG(B7_4), REG(B11_8)); |
791 | fdf9b3e8 | bellard | return;
|
792 | fdf9b3e8 | bellard | case 0x300d: /* dmuls.l Rm,Rn */ |
793 | 6f06939b | aurel32 | { |
794 | a7812ae4 | pbrook | TCGv_i64 tmp1 = tcg_temp_new_i64(); |
795 | a7812ae4 | pbrook | TCGv_i64 tmp2 = tcg_temp_new_i64(); |
796 | 6f06939b | aurel32 | |
797 | 7efbe241 | aurel32 | tcg_gen_ext_i32_i64(tmp1, REG(B7_4)); |
798 | 7efbe241 | aurel32 | tcg_gen_ext_i32_i64(tmp2, REG(B11_8)); |
799 | 6f06939b | aurel32 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
800 | 6f06939b | aurel32 | tcg_gen_trunc_i64_i32(cpu_macl, tmp1); |
801 | 6f06939b | aurel32 | tcg_gen_shri_i64(tmp1, tmp1, 32);
|
802 | 6f06939b | aurel32 | tcg_gen_trunc_i64_i32(cpu_mach, tmp1); |
803 | 6f06939b | aurel32 | |
804 | a7812ae4 | pbrook | tcg_temp_free_i64(tmp2); |
805 | a7812ae4 | pbrook | tcg_temp_free_i64(tmp1); |
806 | 6f06939b | aurel32 | } |
807 | fdf9b3e8 | bellard | return;
|
808 | fdf9b3e8 | bellard | case 0x3005: /* dmulu.l Rm,Rn */ |
809 | 6f06939b | aurel32 | { |
810 | a7812ae4 | pbrook | TCGv_i64 tmp1 = tcg_temp_new_i64(); |
811 | a7812ae4 | pbrook | TCGv_i64 tmp2 = tcg_temp_new_i64(); |
812 | 6f06939b | aurel32 | |
813 | 7efbe241 | aurel32 | tcg_gen_extu_i32_i64(tmp1, REG(B7_4)); |
814 | 7efbe241 | aurel32 | tcg_gen_extu_i32_i64(tmp2, REG(B11_8)); |
815 | 6f06939b | aurel32 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
816 | 6f06939b | aurel32 | tcg_gen_trunc_i64_i32(cpu_macl, tmp1); |
817 | 6f06939b | aurel32 | tcg_gen_shri_i64(tmp1, tmp1, 32);
|
818 | 6f06939b | aurel32 | tcg_gen_trunc_i64_i32(cpu_mach, tmp1); |
819 | 6f06939b | aurel32 | |
820 | a7812ae4 | pbrook | tcg_temp_free_i64(tmp2); |
821 | a7812ae4 | pbrook | tcg_temp_free_i64(tmp1); |
822 | 6f06939b | aurel32 | } |
823 | fdf9b3e8 | bellard | return;
|
824 | fdf9b3e8 | bellard | case 0x600e: /* exts.b Rm,Rn */ |
825 | 7efbe241 | aurel32 | tcg_gen_ext8s_i32(REG(B11_8), REG(B7_4)); |
826 | fdf9b3e8 | bellard | return;
|
827 | fdf9b3e8 | bellard | case 0x600f: /* exts.w Rm,Rn */ |
828 | 7efbe241 | aurel32 | tcg_gen_ext16s_i32(REG(B11_8), REG(B7_4)); |
829 | fdf9b3e8 | bellard | return;
|
830 | fdf9b3e8 | bellard | case 0x600c: /* extu.b Rm,Rn */ |
831 | 7efbe241 | aurel32 | tcg_gen_ext8u_i32(REG(B11_8), REG(B7_4)); |
832 | fdf9b3e8 | bellard | return;
|
833 | fdf9b3e8 | bellard | case 0x600d: /* extu.w Rm,Rn */ |
834 | 7efbe241 | aurel32 | tcg_gen_ext16u_i32(REG(B11_8), REG(B7_4)); |
835 | fdf9b3e8 | bellard | return;
|
836 | 24988dc2 | aurel32 | case 0x000f: /* mac.l @Rm+,@Rn+ */ |
837 | c55497ec | aurel32 | { |
838 | c55497ec | aurel32 | TCGv arg0, arg1; |
839 | a7812ae4 | pbrook | arg0 = tcg_temp_new(); |
840 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx); |
841 | a7812ae4 | pbrook | arg1 = tcg_temp_new(); |
842 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx); |
843 | a7812ae4 | pbrook | gen_helper_macl(arg0, arg1); |
844 | c55497ec | aurel32 | tcg_temp_free(arg1); |
845 | c55497ec | aurel32 | tcg_temp_free(arg0); |
846 | c55497ec | aurel32 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
|
847 | c55497ec | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
|
848 | c55497ec | aurel32 | } |
849 | fdf9b3e8 | bellard | return;
|
850 | fdf9b3e8 | bellard | case 0x400f: /* mac.w @Rm+,@Rn+ */ |
851 | c55497ec | aurel32 | { |
852 | c55497ec | aurel32 | TCGv arg0, arg1; |
853 | a7812ae4 | pbrook | arg0 = tcg_temp_new(); |
854 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx); |
855 | a7812ae4 | pbrook | arg1 = tcg_temp_new(); |
856 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx); |
857 | a7812ae4 | pbrook | gen_helper_macw(arg0, arg1); |
858 | c55497ec | aurel32 | tcg_temp_free(arg1); |
859 | c55497ec | aurel32 | tcg_temp_free(arg0); |
860 | c55497ec | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2);
|
861 | c55497ec | aurel32 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
|
862 | c55497ec | aurel32 | } |
863 | fdf9b3e8 | bellard | return;
|
864 | fdf9b3e8 | bellard | case 0x0007: /* mul.l Rm,Rn */ |
865 | 7efbe241 | aurel32 | tcg_gen_mul_i32(cpu_macl, REG(B7_4), REG(B11_8)); |
866 | fdf9b3e8 | bellard | return;
|
867 | fdf9b3e8 | bellard | case 0x200f: /* muls.w Rm,Rn */ |
868 | c55497ec | aurel32 | { |
869 | c55497ec | aurel32 | TCGv arg0, arg1; |
870 | a7812ae4 | pbrook | arg0 = tcg_temp_new(); |
871 | c55497ec | aurel32 | tcg_gen_ext16s_i32(arg0, REG(B7_4)); |
872 | a7812ae4 | pbrook | arg1 = tcg_temp_new(); |
873 | c55497ec | aurel32 | tcg_gen_ext16s_i32(arg1, REG(B11_8)); |
874 | c55497ec | aurel32 | tcg_gen_mul_i32(cpu_macl, arg0, arg1); |
875 | c55497ec | aurel32 | tcg_temp_free(arg1); |
876 | c55497ec | aurel32 | tcg_temp_free(arg0); |
877 | c55497ec | aurel32 | } |
878 | fdf9b3e8 | bellard | return;
|
879 | fdf9b3e8 | bellard | case 0x200e: /* mulu.w Rm,Rn */ |
880 | c55497ec | aurel32 | { |
881 | c55497ec | aurel32 | TCGv arg0, arg1; |
882 | a7812ae4 | pbrook | arg0 = tcg_temp_new(); |
883 | c55497ec | aurel32 | tcg_gen_ext16u_i32(arg0, REG(B7_4)); |
884 | a7812ae4 | pbrook | arg1 = tcg_temp_new(); |
885 | c55497ec | aurel32 | tcg_gen_ext16u_i32(arg1, REG(B11_8)); |
886 | c55497ec | aurel32 | tcg_gen_mul_i32(cpu_macl, arg0, arg1); |
887 | c55497ec | aurel32 | tcg_temp_free(arg1); |
888 | c55497ec | aurel32 | tcg_temp_free(arg0); |
889 | c55497ec | aurel32 | } |
890 | fdf9b3e8 | bellard | return;
|
891 | fdf9b3e8 | bellard | case 0x600b: /* neg Rm,Rn */ |
892 | 7efbe241 | aurel32 | tcg_gen_neg_i32(REG(B11_8), REG(B7_4)); |
893 | fdf9b3e8 | bellard | return;
|
894 | fdf9b3e8 | bellard | case 0x600a: /* negc Rm,Rn */ |
895 | a7812ae4 | pbrook | gen_helper_negc(REG(B11_8), REG(B7_4)); |
896 | fdf9b3e8 | bellard | return;
|
897 | fdf9b3e8 | bellard | case 0x6007: /* not Rm,Rn */ |
898 | 7efbe241 | aurel32 | tcg_gen_not_i32(REG(B11_8), REG(B7_4)); |
899 | fdf9b3e8 | bellard | return;
|
900 | fdf9b3e8 | bellard | case 0x200b: /* or Rm,Rn */ |
901 | 7efbe241 | aurel32 | tcg_gen_or_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
902 | fdf9b3e8 | bellard | return;
|
903 | fdf9b3e8 | bellard | case 0x400c: /* shad Rm,Rn */ |
904 | 69d6275b | aurel32 | { |
905 | 69d6275b | aurel32 | int label1 = gen_new_label();
|
906 | 69d6275b | aurel32 | int label2 = gen_new_label();
|
907 | 69d6275b | aurel32 | int label3 = gen_new_label();
|
908 | 69d6275b | aurel32 | int label4 = gen_new_label();
|
909 | c55497ec | aurel32 | TCGv shift = tcg_temp_local_new(TCG_TYPE_I32); |
910 | 7efbe241 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
|
911 | 69d6275b | aurel32 | /* Rm positive, shift to the left */
|
912 | c55497ec | aurel32 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
|
913 | c55497ec | aurel32 | tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift); |
914 | 69d6275b | aurel32 | tcg_gen_br(label4); |
915 | 69d6275b | aurel32 | /* Rm negative, shift to the right */
|
916 | 69d6275b | aurel32 | gen_set_label(label1); |
917 | c55497ec | aurel32 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
|
918 | c55497ec | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
|
919 | c55497ec | aurel32 | tcg_gen_not_i32(shift, REG(B7_4)); |
920 | c55497ec | aurel32 | tcg_gen_andi_i32(shift, shift, 0x1f);
|
921 | c55497ec | aurel32 | tcg_gen_addi_i32(shift, shift, 1);
|
922 | c55497ec | aurel32 | tcg_gen_sar_i32(REG(B11_8), REG(B11_8), shift); |
923 | 69d6275b | aurel32 | tcg_gen_br(label4); |
924 | 69d6275b | aurel32 | /* Rm = -32 */
|
925 | 69d6275b | aurel32 | gen_set_label(label2); |
926 | 7efbe241 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_LT, REG(B11_8), 0, label3);
|
927 | 7efbe241 | aurel32 | tcg_gen_movi_i32(REG(B11_8), 0);
|
928 | 69d6275b | aurel32 | tcg_gen_br(label4); |
929 | 69d6275b | aurel32 | gen_set_label(label3); |
930 | 7efbe241 | aurel32 | tcg_gen_movi_i32(REG(B11_8), 0xffffffff);
|
931 | 69d6275b | aurel32 | gen_set_label(label4); |
932 | c55497ec | aurel32 | tcg_temp_free(shift); |
933 | 69d6275b | aurel32 | } |
934 | fdf9b3e8 | bellard | return;
|
935 | fdf9b3e8 | bellard | case 0x400d: /* shld Rm,Rn */ |
936 | 69d6275b | aurel32 | { |
937 | 69d6275b | aurel32 | int label1 = gen_new_label();
|
938 | 69d6275b | aurel32 | int label2 = gen_new_label();
|
939 | 69d6275b | aurel32 | int label3 = gen_new_label();
|
940 | c55497ec | aurel32 | TCGv shift = tcg_temp_local_new(TCG_TYPE_I32); |
941 | 7efbe241 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
|
942 | 69d6275b | aurel32 | /* Rm positive, shift to the left */
|
943 | c55497ec | aurel32 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
|
944 | c55497ec | aurel32 | tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift); |
945 | 69d6275b | aurel32 | tcg_gen_br(label3); |
946 | 69d6275b | aurel32 | /* Rm negative, shift to the right */
|
947 | 69d6275b | aurel32 | gen_set_label(label1); |
948 | c55497ec | aurel32 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
|
949 | c55497ec | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
|
950 | c55497ec | aurel32 | tcg_gen_not_i32(shift, REG(B7_4)); |
951 | c55497ec | aurel32 | tcg_gen_andi_i32(shift, shift, 0x1f);
|
952 | c55497ec | aurel32 | tcg_gen_addi_i32(shift, shift, 1);
|
953 | c55497ec | aurel32 | tcg_gen_shr_i32(REG(B11_8), REG(B11_8), shift); |
954 | 69d6275b | aurel32 | tcg_gen_br(label3); |
955 | 69d6275b | aurel32 | /* Rm = -32 */
|
956 | 69d6275b | aurel32 | gen_set_label(label2); |
957 | 7efbe241 | aurel32 | tcg_gen_movi_i32(REG(B11_8), 0);
|
958 | 69d6275b | aurel32 | gen_set_label(label3); |
959 | c55497ec | aurel32 | tcg_temp_free(shift); |
960 | 69d6275b | aurel32 | } |
961 | fdf9b3e8 | bellard | return;
|
962 | fdf9b3e8 | bellard | case 0x3008: /* sub Rm,Rn */ |
963 | 7efbe241 | aurel32 | tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
964 | fdf9b3e8 | bellard | return;
|
965 | fdf9b3e8 | bellard | case 0x300a: /* subc Rm,Rn */ |
966 | a7812ae4 | pbrook | gen_helper_subc(REG(B11_8), REG(B7_4), REG(B11_8)); |
967 | fdf9b3e8 | bellard | return;
|
968 | fdf9b3e8 | bellard | case 0x300b: /* subv Rm,Rn */ |
969 | a7812ae4 | pbrook | gen_helper_subv(REG(B11_8), REG(B7_4), REG(B11_8)); |
970 | fdf9b3e8 | bellard | return;
|
971 | fdf9b3e8 | bellard | case 0x2008: /* tst Rm,Rn */ |
972 | c55497ec | aurel32 | { |
973 | a7812ae4 | pbrook | TCGv val = tcg_temp_new(); |
974 | c55497ec | aurel32 | tcg_gen_and_i32(val, REG(B7_4), REG(B11_8)); |
975 | c55497ec | aurel32 | gen_cmp_imm(TCG_COND_EQ, val, 0);
|
976 | c55497ec | aurel32 | tcg_temp_free(val); |
977 | c55497ec | aurel32 | } |
978 | fdf9b3e8 | bellard | return;
|
979 | fdf9b3e8 | bellard | case 0x200a: /* xor Rm,Rn */ |
980 | 7efbe241 | aurel32 | tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
981 | fdf9b3e8 | bellard | return;
|
982 | e67888a7 | ths | case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */ |
983 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
984 | a7812ae4 | pbrook | TCGv_i64 fp = tcg_temp_new_i64(); |
985 | cc4ba6a9 | aurel32 | gen_load_fpr64(fp, XREG(B7_4)); |
986 | cc4ba6a9 | aurel32 | gen_store_fpr64(fp, XREG(B11_8)); |
987 | a7812ae4 | pbrook | tcg_temp_free_i64(fp); |
988 | eda9b09b | bellard | } else {
|
989 | 66ba317c | aurel32 | tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
990 | eda9b09b | bellard | } |
991 | eda9b09b | bellard | return;
|
992 | e67888a7 | ths | case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ |
993 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
994 | 11bb09f1 | aurel32 | TCGv addr_hi = tcg_temp_new(); |
995 | 11bb09f1 | aurel32 | int fr = XREG(B7_4);
|
996 | 11bb09f1 | aurel32 | tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
|
997 | 11bb09f1 | aurel32 | tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx); |
998 | 11bb09f1 | aurel32 | tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
|
999 | 11bb09f1 | aurel32 | tcg_temp_free(addr_hi); |
1000 | eda9b09b | bellard | } else {
|
1001 | 66ba317c | aurel32 | tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx); |
1002 | eda9b09b | bellard | } |
1003 | eda9b09b | bellard | return;
|
1004 | e67888a7 | ths | case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ |
1005 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
1006 | 11bb09f1 | aurel32 | TCGv addr_hi = tcg_temp_new(); |
1007 | 11bb09f1 | aurel32 | int fr = XREG(B11_8);
|
1008 | 11bb09f1 | aurel32 | tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
|
1009 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx); |
1010 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
|
1011 | 11bb09f1 | aurel32 | tcg_temp_free(addr_hi); |
1012 | eda9b09b | bellard | } else {
|
1013 | 66ba317c | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx); |
1014 | eda9b09b | bellard | } |
1015 | eda9b09b | bellard | return;
|
1016 | e67888a7 | ths | case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ |
1017 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
1018 | 11bb09f1 | aurel32 | TCGv addr_hi = tcg_temp_new(); |
1019 | 11bb09f1 | aurel32 | int fr = XREG(B11_8);
|
1020 | 11bb09f1 | aurel32 | tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
|
1021 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx); |
1022 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
|
1023 | 11bb09f1 | aurel32 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8);
|
1024 | 11bb09f1 | aurel32 | tcg_temp_free(addr_hi); |
1025 | eda9b09b | bellard | } else {
|
1026 | 66ba317c | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx); |
1027 | cc4ba6a9 | aurel32 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
|
1028 | eda9b09b | bellard | } |
1029 | eda9b09b | bellard | return;
|
1030 | e67888a7 | ths | case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ |
1031 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
1032 | 11bb09f1 | aurel32 | TCGv addr = tcg_temp_new_i32(); |
1033 | 11bb09f1 | aurel32 | int fr = XREG(B7_4);
|
1034 | 11bb09f1 | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
1035 | 11bb09f1 | aurel32 | tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
|
1036 | cc4ba6a9 | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 8);
|
1037 | 11bb09f1 | aurel32 | tcg_gen_qemu_st32(cpu_fregs[fr ], addr, ctx->memidx); |
1038 | 11bb09f1 | aurel32 | tcg_gen_mov_i32(REG(B11_8), addr); |
1039 | cc4ba6a9 | aurel32 | tcg_temp_free(addr); |
1040 | eda9b09b | bellard | } else {
|
1041 | a7812ae4 | pbrook | TCGv addr; |
1042 | a7812ae4 | pbrook | addr = tcg_temp_new_i32(); |
1043 | cc4ba6a9 | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
1044 | 66ba317c | aurel32 | tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx); |
1045 | cc4ba6a9 | aurel32 | tcg_temp_free(addr); |
1046 | 7efbe241 | aurel32 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
|
1047 | eda9b09b | bellard | } |
1048 | eda9b09b | bellard | return;
|
1049 | e67888a7 | ths | case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ |
1050 | cc4ba6a9 | aurel32 | { |
1051 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new_i32(); |
1052 | cc4ba6a9 | aurel32 | tcg_gen_add_i32(addr, REG(B7_4), REG(0));
|
1053 | cc4ba6a9 | aurel32 | if (ctx->fpscr & FPSCR_SZ) {
|
1054 | 11bb09f1 | aurel32 | int fr = XREG(B11_8);
|
1055 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx); |
1056 | 11bb09f1 | aurel32 | tcg_gen_addi_i32(addr, addr, 4);
|
1057 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
|
1058 | cc4ba6a9 | aurel32 | } else {
|
1059 | 66ba317c | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx); |
1060 | cc4ba6a9 | aurel32 | } |
1061 | cc4ba6a9 | aurel32 | tcg_temp_free(addr); |
1062 | eda9b09b | bellard | } |
1063 | eda9b09b | bellard | return;
|
1064 | e67888a7 | ths | case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */ |
1065 | cc4ba6a9 | aurel32 | { |
1066 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1067 | cc4ba6a9 | aurel32 | tcg_gen_add_i32(addr, REG(B11_8), REG(0));
|
1068 | cc4ba6a9 | aurel32 | if (ctx->fpscr & FPSCR_SZ) {
|
1069 | 11bb09f1 | aurel32 | int fr = XREG(B7_4);
|
1070 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx); |
1071 | 11bb09f1 | aurel32 | tcg_gen_addi_i32(addr, addr, 4);
|
1072 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
|
1073 | cc4ba6a9 | aurel32 | } else {
|
1074 | 66ba317c | aurel32 | tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx); |
1075 | cc4ba6a9 | aurel32 | } |
1076 | cc4ba6a9 | aurel32 | tcg_temp_free(addr); |
1077 | eda9b09b | bellard | } |
1078 | eda9b09b | bellard | return;
|
1079 | e67888a7 | ths | case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
1080 | e67888a7 | ths | case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
1081 | e67888a7 | ths | case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
1082 | e67888a7 | ths | case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
1083 | e67888a7 | ths | case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
1084 | e67888a7 | ths | case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
1085 | cc4ba6a9 | aurel32 | { |
1086 | cc4ba6a9 | aurel32 | if (ctx->fpscr & FPSCR_PR) {
|
1087 | a7812ae4 | pbrook | TCGv_i64 fp0, fp1; |
1088 | a7812ae4 | pbrook | |
1089 | cc4ba6a9 | aurel32 | if (ctx->opcode & 0x0110) |
1090 | cc4ba6a9 | aurel32 | break; /* illegal instruction */ |
1091 | a7812ae4 | pbrook | fp0 = tcg_temp_new_i64(); |
1092 | a7812ae4 | pbrook | fp1 = tcg_temp_new_i64(); |
1093 | cc4ba6a9 | aurel32 | gen_load_fpr64(fp0, DREG(B11_8)); |
1094 | cc4ba6a9 | aurel32 | gen_load_fpr64(fp1, DREG(B7_4)); |
1095 | a7812ae4 | pbrook | switch (ctx->opcode & 0xf00f) { |
1096 | a7812ae4 | pbrook | case 0xf000: /* fadd Rm,Rn */ |
1097 | a7812ae4 | pbrook | gen_helper_fadd_DT(fp0, fp0, fp1); |
1098 | a7812ae4 | pbrook | break;
|
1099 | a7812ae4 | pbrook | case 0xf001: /* fsub Rm,Rn */ |
1100 | a7812ae4 | pbrook | gen_helper_fsub_DT(fp0, fp0, fp1); |
1101 | a7812ae4 | pbrook | break;
|
1102 | a7812ae4 | pbrook | case 0xf002: /* fmul Rm,Rn */ |
1103 | a7812ae4 | pbrook | gen_helper_fmul_DT(fp0, fp0, fp1); |
1104 | a7812ae4 | pbrook | break;
|
1105 | a7812ae4 | pbrook | case 0xf003: /* fdiv Rm,Rn */ |
1106 | a7812ae4 | pbrook | gen_helper_fdiv_DT(fp0, fp0, fp1); |
1107 | a7812ae4 | pbrook | break;
|
1108 | a7812ae4 | pbrook | case 0xf004: /* fcmp/eq Rm,Rn */ |
1109 | a7812ae4 | pbrook | gen_helper_fcmp_eq_DT(fp0, fp1); |
1110 | a7812ae4 | pbrook | return;
|
1111 | a7812ae4 | pbrook | case 0xf005: /* fcmp/gt Rm,Rn */ |
1112 | a7812ae4 | pbrook | gen_helper_fcmp_gt_DT(fp0, fp1); |
1113 | a7812ae4 | pbrook | return;
|
1114 | a7812ae4 | pbrook | } |
1115 | a7812ae4 | pbrook | gen_store_fpr64(fp0, DREG(B11_8)); |
1116 | a7812ae4 | pbrook | tcg_temp_free_i64(fp0); |
1117 | a7812ae4 | pbrook | tcg_temp_free_i64(fp1); |
1118 | a7812ae4 | pbrook | } else {
|
1119 | a7812ae4 | pbrook | switch (ctx->opcode & 0xf00f) { |
1120 | a7812ae4 | pbrook | case 0xf000: /* fadd Rm,Rn */ |
1121 | 66ba317c | aurel32 | gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
1122 | a7812ae4 | pbrook | break;
|
1123 | a7812ae4 | pbrook | case 0xf001: /* fsub Rm,Rn */ |
1124 | 66ba317c | aurel32 | gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
1125 | a7812ae4 | pbrook | break;
|
1126 | a7812ae4 | pbrook | case 0xf002: /* fmul Rm,Rn */ |
1127 | 66ba317c | aurel32 | gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
1128 | a7812ae4 | pbrook | break;
|
1129 | a7812ae4 | pbrook | case 0xf003: /* fdiv Rm,Rn */ |
1130 | 66ba317c | aurel32 | gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
1131 | a7812ae4 | pbrook | break;
|
1132 | a7812ae4 | pbrook | case 0xf004: /* fcmp/eq Rm,Rn */ |
1133 | 66ba317c | aurel32 | gen_helper_fcmp_eq_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
1134 | a7812ae4 | pbrook | return;
|
1135 | a7812ae4 | pbrook | case 0xf005: /* fcmp/gt Rm,Rn */ |
1136 | 66ba317c | aurel32 | gen_helper_fcmp_gt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
1137 | a7812ae4 | pbrook | return;
|
1138 | a7812ae4 | pbrook | } |
1139 | cc4ba6a9 | aurel32 | } |
1140 | ea6cf6be | ths | } |
1141 | ea6cf6be | ths | return;
|
1142 | fdf9b3e8 | bellard | } |
1143 | fdf9b3e8 | bellard | |
1144 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xff00) { |
1145 | fdf9b3e8 | bellard | case 0xc900: /* and #imm,R0 */ |
1146 | 7efbe241 | aurel32 | tcg_gen_andi_i32(REG(0), REG(0), B7_0); |
1147 | fdf9b3e8 | bellard | return;
|
1148 | 24988dc2 | aurel32 | case 0xcd00: /* and.b #imm,@(R0,GBR) */ |
1149 | c55497ec | aurel32 | { |
1150 | c55497ec | aurel32 | TCGv addr, val; |
1151 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
1152 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(0), cpu_gbr);
|
1153 | a7812ae4 | pbrook | val = tcg_temp_new(); |
1154 | c55497ec | aurel32 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
1155 | c55497ec | aurel32 | tcg_gen_andi_i32(val, val, B7_0); |
1156 | c55497ec | aurel32 | tcg_gen_qemu_st8(val, addr, ctx->memidx); |
1157 | c55497ec | aurel32 | tcg_temp_free(val); |
1158 | c55497ec | aurel32 | tcg_temp_free(addr); |
1159 | c55497ec | aurel32 | } |
1160 | fdf9b3e8 | bellard | return;
|
1161 | fdf9b3e8 | bellard | case 0x8b00: /* bf label */ |
1162 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
1163 | fdf9b3e8 | bellard | gen_conditional_jump(ctx, ctx->pc + 2,
|
1164 | fdf9b3e8 | bellard | ctx->pc + 4 + B7_0s * 2); |
1165 | 823029f9 | ths | ctx->bstate = BS_BRANCH; |
1166 | fdf9b3e8 | bellard | return;
|
1167 | fdf9b3e8 | bellard | case 0x8f00: /* bf/s label */ |
1168 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
1169 | 1000822b | aurel32 | gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 0); |
1170 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT_CONDITIONAL; |
1171 | fdf9b3e8 | bellard | return;
|
1172 | fdf9b3e8 | bellard | case 0x8900: /* bt label */ |
1173 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
1174 | fdf9b3e8 | bellard | gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2, |
1175 | fdf9b3e8 | bellard | ctx->pc + 2);
|
1176 | 823029f9 | ths | ctx->bstate = BS_BRANCH; |
1177 | fdf9b3e8 | bellard | return;
|
1178 | fdf9b3e8 | bellard | case 0x8d00: /* bt/s label */ |
1179 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
1180 | 1000822b | aurel32 | gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 1); |
1181 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT_CONDITIONAL; |
1182 | fdf9b3e8 | bellard | return;
|
1183 | fdf9b3e8 | bellard | case 0x8800: /* cmp/eq #imm,R0 */ |
1184 | 7efbe241 | aurel32 | gen_cmp_imm(TCG_COND_EQ, REG(0), B7_0s);
|
1185 | fdf9b3e8 | bellard | return;
|
1186 | fdf9b3e8 | bellard | case 0xc400: /* mov.b @(disp,GBR),R0 */ |
1187 | c55497ec | aurel32 | { |
1188 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1189 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0); |
1190 | c55497ec | aurel32 | tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
|
1191 | c55497ec | aurel32 | tcg_temp_free(addr); |
1192 | c55497ec | aurel32 | } |
1193 | fdf9b3e8 | bellard | return;
|
1194 | fdf9b3e8 | bellard | case 0xc500: /* mov.w @(disp,GBR),R0 */ |
1195 | c55497ec | aurel32 | { |
1196 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1197 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
|
1198 | c55497ec | aurel32 | tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
|
1199 | c55497ec | aurel32 | tcg_temp_free(addr); |
1200 | c55497ec | aurel32 | } |
1201 | fdf9b3e8 | bellard | return;
|
1202 | fdf9b3e8 | bellard | case 0xc600: /* mov.l @(disp,GBR),R0 */ |
1203 | c55497ec | aurel32 | { |
1204 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1205 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
|
1206 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(REG(0), addr, ctx->memidx);
|
1207 | c55497ec | aurel32 | tcg_temp_free(addr); |
1208 | c55497ec | aurel32 | } |
1209 | fdf9b3e8 | bellard | return;
|
1210 | fdf9b3e8 | bellard | case 0xc000: /* mov.b R0,@(disp,GBR) */ |
1211 | c55497ec | aurel32 | { |
1212 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1213 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0); |
1214 | c55497ec | aurel32 | tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
|
1215 | c55497ec | aurel32 | tcg_temp_free(addr); |
1216 | c55497ec | aurel32 | } |
1217 | fdf9b3e8 | bellard | return;
|
1218 | fdf9b3e8 | bellard | case 0xc100: /* mov.w R0,@(disp,GBR) */ |
1219 | c55497ec | aurel32 | { |
1220 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1221 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
|
1222 | c55497ec | aurel32 | tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
|
1223 | c55497ec | aurel32 | tcg_temp_free(addr); |
1224 | c55497ec | aurel32 | } |
1225 | fdf9b3e8 | bellard | return;
|
1226 | fdf9b3e8 | bellard | case 0xc200: /* mov.l R0,@(disp,GBR) */ |
1227 | c55497ec | aurel32 | { |
1228 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1229 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
|
1230 | c55497ec | aurel32 | tcg_gen_qemu_st32(REG(0), addr, ctx->memidx);
|
1231 | c55497ec | aurel32 | tcg_temp_free(addr); |
1232 | c55497ec | aurel32 | } |
1233 | fdf9b3e8 | bellard | return;
|
1234 | fdf9b3e8 | bellard | case 0x8000: /* mov.b R0,@(disp,Rn) */ |
1235 | c55497ec | aurel32 | { |
1236 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1237 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0); |
1238 | c55497ec | aurel32 | tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
|
1239 | c55497ec | aurel32 | tcg_temp_free(addr); |
1240 | c55497ec | aurel32 | } |
1241 | fdf9b3e8 | bellard | return;
|
1242 | fdf9b3e8 | bellard | case 0x8100: /* mov.w R0,@(disp,Rn) */ |
1243 | c55497ec | aurel32 | { |
1244 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1245 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
|
1246 | c55497ec | aurel32 | tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
|
1247 | c55497ec | aurel32 | tcg_temp_free(addr); |
1248 | c55497ec | aurel32 | } |
1249 | fdf9b3e8 | bellard | return;
|
1250 | fdf9b3e8 | bellard | case 0x8400: /* mov.b @(disp,Rn),R0 */ |
1251 | c55497ec | aurel32 | { |
1252 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1253 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0); |
1254 | c55497ec | aurel32 | tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
|
1255 | c55497ec | aurel32 | tcg_temp_free(addr); |
1256 | c55497ec | aurel32 | } |
1257 | fdf9b3e8 | bellard | return;
|
1258 | fdf9b3e8 | bellard | case 0x8500: /* mov.w @(disp,Rn),R0 */ |
1259 | c55497ec | aurel32 | { |
1260 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1261 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
|
1262 | c55497ec | aurel32 | tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
|
1263 | c55497ec | aurel32 | tcg_temp_free(addr); |
1264 | c55497ec | aurel32 | } |
1265 | fdf9b3e8 | bellard | return;
|
1266 | fdf9b3e8 | bellard | case 0xc700: /* mova @(disp,PC),R0 */ |
1267 | 7efbe241 | aurel32 | tcg_gen_movi_i32(REG(0), ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3); |
1268 | fdf9b3e8 | bellard | return;
|
1269 | fdf9b3e8 | bellard | case 0xcb00: /* or #imm,R0 */ |
1270 | 7efbe241 | aurel32 | tcg_gen_ori_i32(REG(0), REG(0), B7_0); |
1271 | fdf9b3e8 | bellard | return;
|
1272 | 24988dc2 | aurel32 | case 0xcf00: /* or.b #imm,@(R0,GBR) */ |
1273 | c55497ec | aurel32 | { |
1274 | c55497ec | aurel32 | TCGv addr, val; |
1275 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
1276 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(0), cpu_gbr);
|
1277 | a7812ae4 | pbrook | val = tcg_temp_new(); |
1278 | c55497ec | aurel32 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
1279 | c55497ec | aurel32 | tcg_gen_ori_i32(val, val, B7_0); |
1280 | c55497ec | aurel32 | tcg_gen_qemu_st8(val, addr, ctx->memidx); |
1281 | c55497ec | aurel32 | tcg_temp_free(val); |
1282 | c55497ec | aurel32 | tcg_temp_free(addr); |
1283 | c55497ec | aurel32 | } |
1284 | fdf9b3e8 | bellard | return;
|
1285 | fdf9b3e8 | bellard | case 0xc300: /* trapa #imm */ |
1286 | c55497ec | aurel32 | { |
1287 | c55497ec | aurel32 | TCGv imm; |
1288 | c55497ec | aurel32 | CHECK_NOT_DELAY_SLOT |
1289 | c55497ec | aurel32 | tcg_gen_movi_i32(cpu_pc, ctx->pc); |
1290 | c55497ec | aurel32 | imm = tcg_const_i32(B7_0); |
1291 | a7812ae4 | pbrook | gen_helper_trapa(imm); |
1292 | c55497ec | aurel32 | tcg_temp_free(imm); |
1293 | c55497ec | aurel32 | ctx->bstate = BS_BRANCH; |
1294 | c55497ec | aurel32 | } |
1295 | fdf9b3e8 | bellard | return;
|
1296 | fdf9b3e8 | bellard | case 0xc800: /* tst #imm,R0 */ |
1297 | c55497ec | aurel32 | { |
1298 | a7812ae4 | pbrook | TCGv val = tcg_temp_new(); |
1299 | c55497ec | aurel32 | tcg_gen_andi_i32(val, REG(0), B7_0);
|
1300 | c55497ec | aurel32 | gen_cmp_imm(TCG_COND_EQ, val, 0);
|
1301 | c55497ec | aurel32 | tcg_temp_free(val); |
1302 | c55497ec | aurel32 | } |
1303 | fdf9b3e8 | bellard | return;
|
1304 | 24988dc2 | aurel32 | case 0xcc00: /* tst.b #imm,@(R0,GBR) */ |
1305 | c55497ec | aurel32 | { |
1306 | a7812ae4 | pbrook | TCGv val = tcg_temp_new(); |
1307 | c55497ec | aurel32 | tcg_gen_add_i32(val, REG(0), cpu_gbr);
|
1308 | c55497ec | aurel32 | tcg_gen_qemu_ld8u(val, val, ctx->memidx); |
1309 | c55497ec | aurel32 | tcg_gen_andi_i32(val, val, B7_0); |
1310 | c55497ec | aurel32 | gen_cmp_imm(TCG_COND_EQ, val, 0);
|
1311 | c55497ec | aurel32 | tcg_temp_free(val); |
1312 | c55497ec | aurel32 | } |
1313 | fdf9b3e8 | bellard | return;
|
1314 | fdf9b3e8 | bellard | case 0xca00: /* xor #imm,R0 */ |
1315 | 7efbe241 | aurel32 | tcg_gen_xori_i32(REG(0), REG(0), B7_0); |
1316 | fdf9b3e8 | bellard | return;
|
1317 | 24988dc2 | aurel32 | case 0xce00: /* xor.b #imm,@(R0,GBR) */ |
1318 | c55497ec | aurel32 | { |
1319 | c55497ec | aurel32 | TCGv addr, val; |
1320 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
1321 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(0), cpu_gbr);
|
1322 | a7812ae4 | pbrook | val = tcg_temp_new(); |
1323 | c55497ec | aurel32 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
1324 | c55497ec | aurel32 | tcg_gen_xori_i32(val, val, B7_0); |
1325 | c55497ec | aurel32 | tcg_gen_qemu_st8(val, addr, ctx->memidx); |
1326 | c55497ec | aurel32 | tcg_temp_free(val); |
1327 | c55497ec | aurel32 | tcg_temp_free(addr); |
1328 | c55497ec | aurel32 | } |
1329 | fdf9b3e8 | bellard | return;
|
1330 | fdf9b3e8 | bellard | } |
1331 | fdf9b3e8 | bellard | |
1332 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf08f) { |
1333 | fdf9b3e8 | bellard | case 0x408e: /* ldc Rm,Rn_BANK */ |
1334 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1335 | 7efbe241 | aurel32 | tcg_gen_mov_i32(ALTREG(B6_4), REG(B11_8)); |
1336 | fdf9b3e8 | bellard | return;
|
1337 | fdf9b3e8 | bellard | case 0x4087: /* ldc.l @Rm+,Rn_BANK */ |
1338 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1339 | 7efbe241 | aurel32 | tcg_gen_qemu_ld32s(ALTREG(B6_4), REG(B11_8), ctx->memidx); |
1340 | 7efbe241 | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
|
1341 | fdf9b3e8 | bellard | return;
|
1342 | fdf9b3e8 | bellard | case 0x0082: /* stc Rm_BANK,Rn */ |
1343 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1344 | 7efbe241 | aurel32 | tcg_gen_mov_i32(REG(B11_8), ALTREG(B6_4)); |
1345 | fdf9b3e8 | bellard | return;
|
1346 | fdf9b3e8 | bellard | case 0x4083: /* stc.l Rm_BANK,@-Rn */ |
1347 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1348 | c55497ec | aurel32 | { |
1349 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1350 | c55497ec | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
1351 | c55497ec | aurel32 | tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx); |
1352 | c55497ec | aurel32 | tcg_temp_free(addr); |
1353 | c55497ec | aurel32 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
|
1354 | c55497ec | aurel32 | } |
1355 | fdf9b3e8 | bellard | return;
|
1356 | fdf9b3e8 | bellard | } |
1357 | fdf9b3e8 | bellard | |
1358 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf0ff) { |
1359 | fdf9b3e8 | bellard | case 0x0023: /* braf Rn */ |
1360 | 7efbe241 | aurel32 | CHECK_NOT_DELAY_SLOT |
1361 | 7efbe241 | aurel32 | tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->pc + 4);
|
1362 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
1363 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
1364 | fdf9b3e8 | bellard | return;
|
1365 | fdf9b3e8 | bellard | case 0x0003: /* bsrf Rn */ |
1366 | 7efbe241 | aurel32 | CHECK_NOT_DELAY_SLOT |
1367 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
|
1368 | 7efbe241 | aurel32 | tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr); |
1369 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
1370 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
1371 | fdf9b3e8 | bellard | return;
|
1372 | fdf9b3e8 | bellard | case 0x4015: /* cmp/pl Rn */ |
1373 | 7efbe241 | aurel32 | gen_cmp_imm(TCG_COND_GT, REG(B11_8), 0);
|
1374 | fdf9b3e8 | bellard | return;
|
1375 | fdf9b3e8 | bellard | case 0x4011: /* cmp/pz Rn */ |
1376 | 7efbe241 | aurel32 | gen_cmp_imm(TCG_COND_GE, REG(B11_8), 0);
|
1377 | fdf9b3e8 | bellard | return;
|
1378 | fdf9b3e8 | bellard | case 0x4010: /* dt Rn */ |
1379 | 7efbe241 | aurel32 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1);
|
1380 | 7efbe241 | aurel32 | gen_cmp_imm(TCG_COND_EQ, REG(B11_8), 0);
|
1381 | fdf9b3e8 | bellard | return;
|
1382 | fdf9b3e8 | bellard | case 0x402b: /* jmp @Rn */ |
1383 | 7efbe241 | aurel32 | CHECK_NOT_DELAY_SLOT |
1384 | 7efbe241 | aurel32 | tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); |
1385 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
1386 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
1387 | fdf9b3e8 | bellard | return;
|
1388 | fdf9b3e8 | bellard | case 0x400b: /* jsr @Rn */ |
1389 | 7efbe241 | aurel32 | CHECK_NOT_DELAY_SLOT |
1390 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
|
1391 | 7efbe241 | aurel32 | tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); |
1392 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
1393 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
1394 | fdf9b3e8 | bellard | return;
|
1395 | fe25591e | aurel32 | case 0x400e: /* ldc Rm,SR */ |
1396 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1397 | 7efbe241 | aurel32 | tcg_gen_andi_i32(cpu_sr, REG(B11_8), 0x700083f3);
|
1398 | 390af821 | aurel32 | ctx->bstate = BS_STOP; |
1399 | 390af821 | aurel32 | return;
|
1400 | fe25591e | aurel32 | case 0x4007: /* ldc.l @Rm+,SR */ |
1401 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1402 | c55497ec | aurel32 | { |
1403 | a7812ae4 | pbrook | TCGv val = tcg_temp_new(); |
1404 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(val, REG(B11_8), ctx->memidx); |
1405 | c55497ec | aurel32 | tcg_gen_andi_i32(cpu_sr, val, 0x700083f3);
|
1406 | c55497ec | aurel32 | tcg_temp_free(val); |
1407 | c55497ec | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
|
1408 | c55497ec | aurel32 | ctx->bstate = BS_STOP; |
1409 | c55497ec | aurel32 | } |
1410 | 390af821 | aurel32 | return;
|
1411 | fe25591e | aurel32 | case 0x0002: /* stc SR,Rn */ |
1412 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1413 | 7efbe241 | aurel32 | tcg_gen_mov_i32(REG(B11_8), cpu_sr); |
1414 | 390af821 | aurel32 | return;
|
1415 | fe25591e | aurel32 | case 0x4003: /* stc SR,@-Rn */ |
1416 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1417 | c55497ec | aurel32 | { |
1418 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1419 | c55497ec | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
1420 | c55497ec | aurel32 | tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx); |
1421 | c55497ec | aurel32 | tcg_temp_free(addr); |
1422 | c55497ec | aurel32 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
|
1423 | c55497ec | aurel32 | } |
1424 | 390af821 | aurel32 | return;
|
1425 | fe25591e | aurel32 | #define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \
|
1426 | fdf9b3e8 | bellard | case ldnum: \
|
1427 | fe25591e | aurel32 | prechk \ |
1428 | 7efbe241 | aurel32 | tcg_gen_mov_i32 (cpu_##reg, REG(B11_8)); \ |
1429 | fdf9b3e8 | bellard | return; \
|
1430 | fdf9b3e8 | bellard | case ldpnum: \
|
1431 | fe25591e | aurel32 | prechk \ |
1432 | 7efbe241 | aurel32 | tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx); \ |
1433 | 7efbe241 | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); \
|
1434 | fdf9b3e8 | bellard | return; \
|
1435 | fdf9b3e8 | bellard | case stnum: \
|
1436 | fe25591e | aurel32 | prechk \ |
1437 | 7efbe241 | aurel32 | tcg_gen_mov_i32 (REG(B11_8), cpu_##reg); \ |
1438 | fdf9b3e8 | bellard | return; \
|
1439 | fdf9b3e8 | bellard | case stpnum: \
|
1440 | fe25591e | aurel32 | prechk \ |
1441 | c55497ec | aurel32 | { \ |
1442 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); \ |
1443 | c55497ec | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 4); \
|
1444 | c55497ec | aurel32 | tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx); \ |
1445 | c55497ec | aurel32 | tcg_temp_free(addr); \ |
1446 | c55497ec | aurel32 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); \
|
1447 | 86e0abc7 | aurel32 | } \ |
1448 | fdf9b3e8 | bellard | return;
|
1449 | fe25591e | aurel32 | LDST(gbr, 0x401e, 0x4017, 0x0012, 0x4013, {}) |
1450 | fe25591e | aurel32 | LDST(vbr, 0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED) |
1451 | fe25591e | aurel32 | LDST(ssr, 0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED) |
1452 | fe25591e | aurel32 | LDST(spc, 0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED) |
1453 | fe25591e | aurel32 | LDST(dbr, 0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED) |
1454 | fe25591e | aurel32 | LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {}) |
1455 | fe25591e | aurel32 | LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {}) |
1456 | fe25591e | aurel32 | LDST(pr, 0x402a, 0x4026, 0x002a, 0x4022, {}) |
1457 | fe25591e | aurel32 | LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {}) |
1458 | 390af821 | aurel32 | case 0x406a: /* lds Rm,FPSCR */ |
1459 | a7812ae4 | pbrook | gen_helper_ld_fpscr(REG(B11_8)); |
1460 | 390af821 | aurel32 | ctx->bstate = BS_STOP; |
1461 | 390af821 | aurel32 | return;
|
1462 | 390af821 | aurel32 | case 0x4066: /* lds.l @Rm+,FPSCR */ |
1463 | c55497ec | aurel32 | { |
1464 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1465 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx); |
1466 | c55497ec | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
|
1467 | a7812ae4 | pbrook | gen_helper_ld_fpscr(addr); |
1468 | c55497ec | aurel32 | tcg_temp_free(addr); |
1469 | c55497ec | aurel32 | ctx->bstate = BS_STOP; |
1470 | c55497ec | aurel32 | } |
1471 | 390af821 | aurel32 | return;
|
1472 | 390af821 | aurel32 | case 0x006a: /* sts FPSCR,Rn */ |
1473 | c55497ec | aurel32 | tcg_gen_andi_i32(REG(B11_8), cpu_fpscr, 0x003fffff);
|
1474 | 390af821 | aurel32 | return;
|
1475 | 390af821 | aurel32 | case 0x4062: /* sts FPSCR,@-Rn */ |
1476 | c55497ec | aurel32 | { |
1477 | c55497ec | aurel32 | TCGv addr, val; |
1478 | a7812ae4 | pbrook | val = tcg_temp_new(); |
1479 | c55497ec | aurel32 | tcg_gen_andi_i32(val, cpu_fpscr, 0x003fffff);
|
1480 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
1481 | c55497ec | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
1482 | c55497ec | aurel32 | tcg_gen_qemu_st32(val, addr, ctx->memidx); |
1483 | c55497ec | aurel32 | tcg_temp_free(addr); |
1484 | c55497ec | aurel32 | tcg_temp_free(val); |
1485 | c55497ec | aurel32 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
|
1486 | c55497ec | aurel32 | } |
1487 | 390af821 | aurel32 | return;
|
1488 | fdf9b3e8 | bellard | case 0x00c3: /* movca.l R0,@Rm */ |
1489 | 7efbe241 | aurel32 | tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
|
1490 | fdf9b3e8 | bellard | return;
|
1491 | 7526aa2d | aurel32 | case 0x40a9: |
1492 | 7526aa2d | aurel32 | /* MOVUA.L @Rm,R0 (Rm) -> R0
|
1493 | 7526aa2d | aurel32 | Load non-boundary-aligned data */
|
1494 | 7526aa2d | aurel32 | tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);
|
1495 | 7526aa2d | aurel32 | return;
|
1496 | 7526aa2d | aurel32 | case 0x40e9: |
1497 | 7526aa2d | aurel32 | /* MOVUA.L @Rm+,R0 (Rm) -> R0, Rm + 4 -> Rm
|
1498 | 7526aa2d | aurel32 | Load non-boundary-aligned data */
|
1499 | 7526aa2d | aurel32 | tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);
|
1500 | 7526aa2d | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
|
1501 | 7526aa2d | aurel32 | return;
|
1502 | fdf9b3e8 | bellard | case 0x0029: /* movt Rn */ |
1503 | 7efbe241 | aurel32 | tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T); |
1504 | fdf9b3e8 | bellard | return;
|
1505 | fdf9b3e8 | bellard | case 0x0093: /* ocbi @Rn */ |
1506 | c55497ec | aurel32 | { |
1507 | a7812ae4 | pbrook | TCGv dummy = tcg_temp_new(); |
1508 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); |
1509 | c55497ec | aurel32 | tcg_temp_free(dummy); |
1510 | c55497ec | aurel32 | } |
1511 | fdf9b3e8 | bellard | return;
|
1512 | 24988dc2 | aurel32 | case 0x00a3: /* ocbp @Rn */ |
1513 | c55497ec | aurel32 | { |
1514 | a7812ae4 | pbrook | TCGv dummy = tcg_temp_new(); |
1515 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); |
1516 | c55497ec | aurel32 | tcg_temp_free(dummy); |
1517 | c55497ec | aurel32 | } |
1518 | fdf9b3e8 | bellard | return;
|
1519 | fdf9b3e8 | bellard | case 0x00b3: /* ocbwb @Rn */ |
1520 | c55497ec | aurel32 | { |
1521 | a7812ae4 | pbrook | TCGv dummy = tcg_temp_new(); |
1522 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); |
1523 | c55497ec | aurel32 | tcg_temp_free(dummy); |
1524 | c55497ec | aurel32 | } |
1525 | fdf9b3e8 | bellard | return;
|
1526 | fdf9b3e8 | bellard | case 0x0083: /* pref @Rn */ |
1527 | fdf9b3e8 | bellard | return;
|
1528 | fdf9b3e8 | bellard | case 0x4024: /* rotcl Rn */ |
1529 | c55497ec | aurel32 | { |
1530 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
1531 | c55497ec | aurel32 | tcg_gen_mov_i32(tmp, cpu_sr); |
1532 | c55497ec | aurel32 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); |
1533 | c55497ec | aurel32 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
|
1534 | c55497ec | aurel32 | gen_copy_bit_i32(REG(B11_8), 0, tmp, 0); |
1535 | c55497ec | aurel32 | tcg_temp_free(tmp); |
1536 | c55497ec | aurel32 | } |
1537 | fdf9b3e8 | bellard | return;
|
1538 | fdf9b3e8 | bellard | case 0x4025: /* rotcr Rn */ |
1539 | c55497ec | aurel32 | { |
1540 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
1541 | c55497ec | aurel32 | tcg_gen_mov_i32(tmp, cpu_sr); |
1542 | c55497ec | aurel32 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1543 | c55497ec | aurel32 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
|
1544 | c55497ec | aurel32 | gen_copy_bit_i32(REG(B11_8), 31, tmp, 0); |
1545 | c55497ec | aurel32 | tcg_temp_free(tmp); |
1546 | c55497ec | aurel32 | } |
1547 | fdf9b3e8 | bellard | return;
|
1548 | fdf9b3e8 | bellard | case 0x4004: /* rotl Rn */ |
1549 | 7efbe241 | aurel32 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); |
1550 | 7efbe241 | aurel32 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
|
1551 | 7efbe241 | aurel32 | gen_copy_bit_i32(REG(B11_8), 0, cpu_sr, 0); |
1552 | fdf9b3e8 | bellard | return;
|
1553 | fdf9b3e8 | bellard | case 0x4005: /* rotr Rn */ |
1554 | 7efbe241 | aurel32 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1555 | 7efbe241 | aurel32 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
|
1556 | 7efbe241 | aurel32 | gen_copy_bit_i32(REG(B11_8), 31, cpu_sr, 0); |
1557 | fdf9b3e8 | bellard | return;
|
1558 | fdf9b3e8 | bellard | case 0x4000: /* shll Rn */ |
1559 | fdf9b3e8 | bellard | case 0x4020: /* shal Rn */ |
1560 | 7efbe241 | aurel32 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); |
1561 | 7efbe241 | aurel32 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
|
1562 | fdf9b3e8 | bellard | return;
|
1563 | fdf9b3e8 | bellard | case 0x4021: /* shar Rn */ |
1564 | 7efbe241 | aurel32 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1565 | 7efbe241 | aurel32 | tcg_gen_sari_i32(REG(B11_8), REG(B11_8), 1);
|
1566 | fdf9b3e8 | bellard | return;
|
1567 | fdf9b3e8 | bellard | case 0x4001: /* shlr Rn */ |
1568 | 7efbe241 | aurel32 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1569 | 7efbe241 | aurel32 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
|
1570 | fdf9b3e8 | bellard | return;
|
1571 | fdf9b3e8 | bellard | case 0x4008: /* shll2 Rn */ |
1572 | 7efbe241 | aurel32 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 2);
|
1573 | fdf9b3e8 | bellard | return;
|
1574 | fdf9b3e8 | bellard | case 0x4018: /* shll8 Rn */ |
1575 | 7efbe241 | aurel32 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 8);
|
1576 | fdf9b3e8 | bellard | return;
|
1577 | fdf9b3e8 | bellard | case 0x4028: /* shll16 Rn */ |
1578 | 7efbe241 | aurel32 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 16);
|
1579 | fdf9b3e8 | bellard | return;
|
1580 | fdf9b3e8 | bellard | case 0x4009: /* shlr2 Rn */ |
1581 | 7efbe241 | aurel32 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 2);
|
1582 | fdf9b3e8 | bellard | return;
|
1583 | fdf9b3e8 | bellard | case 0x4019: /* shlr8 Rn */ |
1584 | 7efbe241 | aurel32 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 8);
|
1585 | fdf9b3e8 | bellard | return;
|
1586 | fdf9b3e8 | bellard | case 0x4029: /* shlr16 Rn */ |
1587 | 7efbe241 | aurel32 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16);
|
1588 | fdf9b3e8 | bellard | return;
|
1589 | fdf9b3e8 | bellard | case 0x401b: /* tas.b @Rn */ |
1590 | c55497ec | aurel32 | { |
1591 | c55497ec | aurel32 | TCGv addr, val; |
1592 | c55497ec | aurel32 | addr = tcg_temp_local_new(TCG_TYPE_I32); |
1593 | c55497ec | aurel32 | tcg_gen_mov_i32(addr, REG(B11_8)); |
1594 | c55497ec | aurel32 | val = tcg_temp_local_new(TCG_TYPE_I32); |
1595 | c55497ec | aurel32 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
1596 | c55497ec | aurel32 | gen_cmp_imm(TCG_COND_EQ, val, 0);
|
1597 | c55497ec | aurel32 | tcg_gen_ori_i32(val, val, 0x80);
|
1598 | c55497ec | aurel32 | tcg_gen_qemu_st8(val, addr, ctx->memidx); |
1599 | c55497ec | aurel32 | tcg_temp_free(val); |
1600 | c55497ec | aurel32 | tcg_temp_free(addr); |
1601 | c55497ec | aurel32 | } |
1602 | fdf9b3e8 | bellard | return;
|
1603 | e67888a7 | ths | case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ |
1604 | cc4ba6a9 | aurel32 | { |
1605 | 66ba317c | aurel32 | tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fpul); |
1606 | cc4ba6a9 | aurel32 | } |
1607 | eda9b09b | bellard | return;
|
1608 | e67888a7 | ths | case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */ |
1609 | cc4ba6a9 | aurel32 | { |
1610 | 66ba317c | aurel32 | tcg_gen_mov_i32(cpu_fpul, cpu_fregs[FREG(B11_8)]); |
1611 | cc4ba6a9 | aurel32 | } |
1612 | eda9b09b | bellard | return;
|
1613 | e67888a7 | ths | case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */ |
1614 | ea6cf6be | ths | if (ctx->fpscr & FPSCR_PR) {
|
1615 | a7812ae4 | pbrook | TCGv_i64 fp; |
1616 | ea6cf6be | ths | if (ctx->opcode & 0x0100) |
1617 | ea6cf6be | ths | break; /* illegal instruction */ |
1618 | a7812ae4 | pbrook | fp = tcg_temp_new_i64(); |
1619 | a7812ae4 | pbrook | gen_helper_float_DT(fp, cpu_fpul); |
1620 | cc4ba6a9 | aurel32 | gen_store_fpr64(fp, DREG(B11_8)); |
1621 | a7812ae4 | pbrook | tcg_temp_free_i64(fp); |
1622 | ea6cf6be | ths | } |
1623 | ea6cf6be | ths | else {
|
1624 | 66ba317c | aurel32 | gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_fpul); |
1625 | ea6cf6be | ths | } |
1626 | ea6cf6be | ths | return;
|
1627 | e67888a7 | ths | case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
1628 | ea6cf6be | ths | if (ctx->fpscr & FPSCR_PR) {
|
1629 | a7812ae4 | pbrook | TCGv_i64 fp; |
1630 | ea6cf6be | ths | if (ctx->opcode & 0x0100) |
1631 | ea6cf6be | ths | break; /* illegal instruction */ |
1632 | a7812ae4 | pbrook | fp = tcg_temp_new_i64(); |
1633 | cc4ba6a9 | aurel32 | gen_load_fpr64(fp, DREG(B11_8)); |
1634 | a7812ae4 | pbrook | gen_helper_ftrc_DT(cpu_fpul, fp); |
1635 | a7812ae4 | pbrook | tcg_temp_free_i64(fp); |
1636 | ea6cf6be | ths | } |
1637 | ea6cf6be | ths | else {
|
1638 | 66ba317c | aurel32 | gen_helper_ftrc_FT(cpu_fpul, cpu_fregs[FREG(B11_8)]); |
1639 | ea6cf6be | ths | } |
1640 | ea6cf6be | ths | return;
|
1641 | 24988dc2 | aurel32 | case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ |
1642 | 7fdf924f | aurel32 | { |
1643 | 66ba317c | aurel32 | gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); |
1644 | 7fdf924f | aurel32 | } |
1645 | 24988dc2 | aurel32 | return;
|
1646 | 24988dc2 | aurel32 | case 0xf05d: /* fabs FRn/DRn */ |
1647 | 24988dc2 | aurel32 | if (ctx->fpscr & FPSCR_PR) {
|
1648 | 24988dc2 | aurel32 | if (ctx->opcode & 0x0100) |
1649 | 24988dc2 | aurel32 | break; /* illegal instruction */ |
1650 | a7812ae4 | pbrook | TCGv_i64 fp = tcg_temp_new_i64(); |
1651 | cc4ba6a9 | aurel32 | gen_load_fpr64(fp, DREG(B11_8)); |
1652 | a7812ae4 | pbrook | gen_helper_fabs_DT(fp, fp); |
1653 | cc4ba6a9 | aurel32 | gen_store_fpr64(fp, DREG(B11_8)); |
1654 | a7812ae4 | pbrook | tcg_temp_free_i64(fp); |
1655 | 24988dc2 | aurel32 | } else {
|
1656 | 66ba317c | aurel32 | gen_helper_fabs_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); |
1657 | 24988dc2 | aurel32 | } |
1658 | 24988dc2 | aurel32 | return;
|
1659 | 24988dc2 | aurel32 | case 0xf06d: /* fsqrt FRn */ |
1660 | 24988dc2 | aurel32 | if (ctx->fpscr & FPSCR_PR) {
|
1661 | 24988dc2 | aurel32 | if (ctx->opcode & 0x0100) |
1662 | 24988dc2 | aurel32 | break; /* illegal instruction */ |
1663 | a7812ae4 | pbrook | TCGv_i64 fp = tcg_temp_new_i64(); |
1664 | cc4ba6a9 | aurel32 | gen_load_fpr64(fp, DREG(B11_8)); |
1665 | a7812ae4 | pbrook | gen_helper_fsqrt_DT(fp, fp); |
1666 | cc4ba6a9 | aurel32 | gen_store_fpr64(fp, DREG(B11_8)); |
1667 | a7812ae4 | pbrook | tcg_temp_free_i64(fp); |
1668 | 24988dc2 | aurel32 | } else {
|
1669 | 66ba317c | aurel32 | gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); |
1670 | 24988dc2 | aurel32 | } |
1671 | 24988dc2 | aurel32 | return;
|
1672 | 24988dc2 | aurel32 | case 0xf07d: /* fsrra FRn */ |
1673 | 24988dc2 | aurel32 | break;
|
1674 | e67888a7 | ths | case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ |
1675 | ea6cf6be | ths | if (!(ctx->fpscr & FPSCR_PR)) {
|
1676 | 66ba317c | aurel32 | tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0);
|
1677 | ea6cf6be | ths | } |
1678 | 12d96138 | aurel32 | return;
|
1679 | e67888a7 | ths | case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ |
1680 | ea6cf6be | ths | if (!(ctx->fpscr & FPSCR_PR)) {
|
1681 | 66ba317c | aurel32 | tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000);
|
1682 | ea6cf6be | ths | } |
1683 | 12d96138 | aurel32 | return;
|
1684 | 24988dc2 | aurel32 | case 0xf0ad: /* fcnvsd FPUL,DRn */ |
1685 | cc4ba6a9 | aurel32 | { |
1686 | a7812ae4 | pbrook | TCGv_i64 fp = tcg_temp_new_i64(); |
1687 | a7812ae4 | pbrook | gen_helper_fcnvsd_FT_DT(fp, cpu_fpul); |
1688 | cc4ba6a9 | aurel32 | gen_store_fpr64(fp, DREG(B11_8)); |
1689 | a7812ae4 | pbrook | tcg_temp_free_i64(fp); |
1690 | cc4ba6a9 | aurel32 | } |
1691 | 24988dc2 | aurel32 | return;
|
1692 | 24988dc2 | aurel32 | case 0xf0bd: /* fcnvds DRn,FPUL */ |
1693 | cc4ba6a9 | aurel32 | { |
1694 | a7812ae4 | pbrook | TCGv_i64 fp = tcg_temp_new_i64(); |
1695 | cc4ba6a9 | aurel32 | gen_load_fpr64(fp, DREG(B11_8)); |
1696 | a7812ae4 | pbrook | gen_helper_fcnvds_DT_FT(cpu_fpul, fp); |
1697 | a7812ae4 | pbrook | tcg_temp_free_i64(fp); |
1698 | cc4ba6a9 | aurel32 | } |
1699 | 24988dc2 | aurel32 | return;
|
1700 | fdf9b3e8 | bellard | } |
1701 | fdf9b3e8 | bellard | |
1702 | fdf9b3e8 | bellard | fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
|
1703 | fdf9b3e8 | bellard | ctx->opcode, ctx->pc); |
1704 | a7812ae4 | pbrook | gen_helper_raise_illegal_instruction(); |
1705 | 823029f9 | ths | ctx->bstate = BS_EXCP; |
1706 | 823029f9 | ths | } |
1707 | 823029f9 | ths | |
1708 | b1d8e52e | blueswir1 | static void decode_opc(DisasContext * ctx) |
1709 | 823029f9 | ths | { |
1710 | 823029f9 | ths | uint32_t old_flags = ctx->flags; |
1711 | 823029f9 | ths | |
1712 | 823029f9 | ths | _decode_opc(ctx); |
1713 | 823029f9 | ths | |
1714 | 823029f9 | ths | if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
|
1715 | 823029f9 | ths | if (ctx->flags & DELAY_SLOT_CLEARME) {
|
1716 | 1000822b | aurel32 | gen_store_flags(0);
|
1717 | 274a9e70 | aurel32 | } else {
|
1718 | 274a9e70 | aurel32 | /* go out of the delay slot */
|
1719 | 274a9e70 | aurel32 | uint32_t new_flags = ctx->flags; |
1720 | 274a9e70 | aurel32 | new_flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); |
1721 | 1000822b | aurel32 | gen_store_flags(new_flags); |
1722 | 823029f9 | ths | } |
1723 | 823029f9 | ths | ctx->flags = 0;
|
1724 | 823029f9 | ths | ctx->bstate = BS_BRANCH; |
1725 | 823029f9 | ths | if (old_flags & DELAY_SLOT_CONDITIONAL) {
|
1726 | 823029f9 | ths | gen_delayed_conditional_jump(ctx); |
1727 | 823029f9 | ths | } else if (old_flags & DELAY_SLOT) { |
1728 | 823029f9 | ths | gen_jump(ctx); |
1729 | 823029f9 | ths | } |
1730 | 823029f9 | ths | |
1731 | 823029f9 | ths | } |
1732 | 274a9e70 | aurel32 | |
1733 | 274a9e70 | aurel32 | /* go into a delay slot */
|
1734 | 274a9e70 | aurel32 | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL))
|
1735 | 1000822b | aurel32 | gen_store_flags(ctx->flags); |
1736 | fdf9b3e8 | bellard | } |
1737 | fdf9b3e8 | bellard | |
1738 | 2cfc5f17 | ths | static inline void |
1739 | 820e00f2 | ths | gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb, |
1740 | 820e00f2 | ths | int search_pc)
|
1741 | fdf9b3e8 | bellard | { |
1742 | fdf9b3e8 | bellard | DisasContext ctx; |
1743 | fdf9b3e8 | bellard | target_ulong pc_start; |
1744 | fdf9b3e8 | bellard | static uint16_t *gen_opc_end;
|
1745 | a1d1bb31 | aliguori | CPUBreakpoint *bp; |
1746 | 355fb23d | pbrook | int i, ii;
|
1747 | 2e70f6ef | pbrook | int num_insns;
|
1748 | 2e70f6ef | pbrook | int max_insns;
|
1749 | fdf9b3e8 | bellard | |
1750 | fdf9b3e8 | bellard | pc_start = tb->pc; |
1751 | fdf9b3e8 | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
1752 | fdf9b3e8 | bellard | ctx.pc = pc_start; |
1753 | 823029f9 | ths | ctx.flags = (uint32_t)tb->flags; |
1754 | 823029f9 | ths | ctx.bstate = BS_NONE; |
1755 | fdf9b3e8 | bellard | ctx.sr = env->sr; |
1756 | eda9b09b | bellard | ctx.fpscr = env->fpscr; |
1757 | fdf9b3e8 | bellard | ctx.memidx = (env->sr & SR_MD) ? 1 : 0; |
1758 | 9854bc46 | pbrook | /* We don't know if the delayed pc came from a dynamic or static branch,
|
1759 | 9854bc46 | pbrook | so assume it is a dynamic branch. */
|
1760 | 823029f9 | ths | ctx.delayed_pc = -1; /* use delayed pc from env pointer */ |
1761 | fdf9b3e8 | bellard | ctx.tb = tb; |
1762 | fdf9b3e8 | bellard | ctx.singlestep_enabled = env->singlestep_enabled; |
1763 | fdf9b3e8 | bellard | |
1764 | fdf9b3e8 | bellard | #ifdef DEBUG_DISAS
|
1765 | fdf9b3e8 | bellard | if (loglevel & CPU_LOG_TB_CPU) {
|
1766 | fdf9b3e8 | bellard | fprintf(logfile, |
1767 | fdf9b3e8 | bellard | "------------------------------------------------\n");
|
1768 | fdf9b3e8 | bellard | cpu_dump_state(env, logfile, fprintf, 0);
|
1769 | fdf9b3e8 | bellard | } |
1770 | fdf9b3e8 | bellard | #endif
|
1771 | fdf9b3e8 | bellard | |
1772 | 355fb23d | pbrook | ii = -1;
|
1773 | 2e70f6ef | pbrook | num_insns = 0;
|
1774 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
1775 | 2e70f6ef | pbrook | if (max_insns == 0) |
1776 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
1777 | 2e70f6ef | pbrook | gen_icount_start(); |
1778 | 823029f9 | ths | while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
|
1779 | c0ce998e | aliguori | if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
|
1780 | c0ce998e | aliguori | TAILQ_FOREACH(bp, &env->breakpoints, entry) { |
1781 | a1d1bb31 | aliguori | if (ctx.pc == bp->pc) {
|
1782 | fdf9b3e8 | bellard | /* We have hit a breakpoint - make sure PC is up-to-date */
|
1783 | 3a8a44c4 | aurel32 | tcg_gen_movi_i32(cpu_pc, ctx.pc); |
1784 | a7812ae4 | pbrook | gen_helper_debug(); |
1785 | 823029f9 | ths | ctx.bstate = BS_EXCP; |
1786 | fdf9b3e8 | bellard | break;
|
1787 | fdf9b3e8 | bellard | } |
1788 | fdf9b3e8 | bellard | } |
1789 | fdf9b3e8 | bellard | } |
1790 | 355fb23d | pbrook | if (search_pc) {
|
1791 | 355fb23d | pbrook | i = gen_opc_ptr - gen_opc_buf; |
1792 | 355fb23d | pbrook | if (ii < i) {
|
1793 | 355fb23d | pbrook | ii++; |
1794 | 355fb23d | pbrook | while (ii < i)
|
1795 | 355fb23d | pbrook | gen_opc_instr_start[ii++] = 0;
|
1796 | 355fb23d | pbrook | } |
1797 | 355fb23d | pbrook | gen_opc_pc[ii] = ctx.pc; |
1798 | 823029f9 | ths | gen_opc_hflags[ii] = ctx.flags; |
1799 | 355fb23d | pbrook | gen_opc_instr_start[ii] = 1;
|
1800 | 2e70f6ef | pbrook | gen_opc_icount[ii] = num_insns; |
1801 | 355fb23d | pbrook | } |
1802 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
1803 | 2e70f6ef | pbrook | gen_io_start(); |
1804 | fdf9b3e8 | bellard | #if 0
|
1805 | fdf9b3e8 | bellard | fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc);
|
1806 | fdf9b3e8 | bellard | fflush(stderr);
|
1807 | fdf9b3e8 | bellard | #endif
|
1808 | fdf9b3e8 | bellard | ctx.opcode = lduw_code(ctx.pc); |
1809 | fdf9b3e8 | bellard | decode_opc(&ctx); |
1810 | 2e70f6ef | pbrook | num_insns++; |
1811 | fdf9b3e8 | bellard | ctx.pc += 2;
|
1812 | fdf9b3e8 | bellard | if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) |
1813 | fdf9b3e8 | bellard | break;
|
1814 | fdf9b3e8 | bellard | if (env->singlestep_enabled)
|
1815 | fdf9b3e8 | bellard | break;
|
1816 | 2e70f6ef | pbrook | if (num_insns >= max_insns)
|
1817 | 2e70f6ef | pbrook | break;
|
1818 | fdf9b3e8 | bellard | #ifdef SH4_SINGLE_STEP
|
1819 | fdf9b3e8 | bellard | break;
|
1820 | fdf9b3e8 | bellard | #endif
|
1821 | fdf9b3e8 | bellard | } |
1822 | 2e70f6ef | pbrook | if (tb->cflags & CF_LAST_IO)
|
1823 | 2e70f6ef | pbrook | gen_io_end(); |
1824 | fdf9b3e8 | bellard | if (env->singlestep_enabled) {
|
1825 | bdbf22e6 | aurel32 | tcg_gen_movi_i32(cpu_pc, ctx.pc); |
1826 | a7812ae4 | pbrook | gen_helper_debug(); |
1827 | 823029f9 | ths | } else {
|
1828 | 823029f9 | ths | switch (ctx.bstate) {
|
1829 | 823029f9 | ths | case BS_STOP:
|
1830 | 823029f9 | ths | /* gen_op_interrupt_restart(); */
|
1831 | 823029f9 | ths | /* fall through */
|
1832 | 823029f9 | ths | case BS_NONE:
|
1833 | 823029f9 | ths | if (ctx.flags) {
|
1834 | 1000822b | aurel32 | gen_store_flags(ctx.flags | DELAY_SLOT_CLEARME); |
1835 | 823029f9 | ths | } |
1836 | 823029f9 | ths | gen_goto_tb(&ctx, 0, ctx.pc);
|
1837 | 823029f9 | ths | break;
|
1838 | 823029f9 | ths | case BS_EXCP:
|
1839 | 823029f9 | ths | /* gen_op_interrupt_restart(); */
|
1840 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
1841 | 823029f9 | ths | break;
|
1842 | 823029f9 | ths | case BS_BRANCH:
|
1843 | 823029f9 | ths | default:
|
1844 | 823029f9 | ths | break;
|
1845 | 823029f9 | ths | } |
1846 | fdf9b3e8 | bellard | } |
1847 | 823029f9 | ths | |
1848 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
1849 | fdf9b3e8 | bellard | *gen_opc_ptr = INDEX_op_end; |
1850 | 355fb23d | pbrook | if (search_pc) {
|
1851 | 355fb23d | pbrook | i = gen_opc_ptr - gen_opc_buf; |
1852 | 355fb23d | pbrook | ii++; |
1853 | 355fb23d | pbrook | while (ii <= i)
|
1854 | 355fb23d | pbrook | gen_opc_instr_start[ii++] = 0;
|
1855 | 355fb23d | pbrook | } else {
|
1856 | 355fb23d | pbrook | tb->size = ctx.pc - pc_start; |
1857 | 2e70f6ef | pbrook | tb->icount = num_insns; |
1858 | 355fb23d | pbrook | } |
1859 | fdf9b3e8 | bellard | |
1860 | fdf9b3e8 | bellard | #ifdef DEBUG_DISAS
|
1861 | fdf9b3e8 | bellard | #ifdef SH4_DEBUG_DISAS
|
1862 | fdf9b3e8 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM)
|
1863 | fdf9b3e8 | bellard | fprintf(logfile, "\n");
|
1864 | fdf9b3e8 | bellard | #endif
|
1865 | fdf9b3e8 | bellard | if (loglevel & CPU_LOG_TB_IN_ASM) {
|
1866 | fdf9b3e8 | bellard | fprintf(logfile, "IN:\n"); /* , lookup_symbol(pc_start)); */ |
1867 | fdf9b3e8 | bellard | target_disas(logfile, pc_start, ctx.pc - pc_start, 0);
|
1868 | fdf9b3e8 | bellard | fprintf(logfile, "\n");
|
1869 | fdf9b3e8 | bellard | } |
1870 | fdf9b3e8 | bellard | #endif
|
1871 | fdf9b3e8 | bellard | } |
1872 | fdf9b3e8 | bellard | |
1873 | 2cfc5f17 | ths | void gen_intermediate_code(CPUState * env, struct TranslationBlock *tb) |
1874 | fdf9b3e8 | bellard | { |
1875 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 0);
|
1876 | fdf9b3e8 | bellard | } |
1877 | fdf9b3e8 | bellard | |
1878 | 2cfc5f17 | ths | void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb) |
1879 | fdf9b3e8 | bellard | { |
1880 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 1);
|
1881 | fdf9b3e8 | bellard | } |
1882 | d2856f1a | aurel32 | |
1883 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
1884 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc) |
1885 | d2856f1a | aurel32 | { |
1886 | d2856f1a | aurel32 | env->pc = gen_opc_pc[pc_pos]; |
1887 | d2856f1a | aurel32 | env->flags = gen_opc_hflags[pc_pos]; |
1888 | d2856f1a | aurel32 | } |