Revision dbda808a
| b/hw/openpic.c | ||
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/* |
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* OpenPIC emulation |
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* |
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* Copyright (c) 2004 Jocelyn Mayer |
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a copy |
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* of this software and associated documentation files (the "Software"), to deal |
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* in the Software without restriction, including without limitation the rights |
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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* copies of the Software, and to permit persons to whom the Software is |
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* furnished to do so, subject to the following conditions: |
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* |
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* The above copyright notice and this permission notice shall be included in |
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* all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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* THE SOFTWARE. |
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*/ |
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/* |
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* |
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* Based on OpenPic implementations: |
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* - Intel GW80314 I/O compagnion chip developper's manual |
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* - Motorola MPC8245 & MPC8540 user manuals. |
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* - Motorola MCP750 (aka Raven) programmer manual. |
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* - Motorola Harrier programmer manuel |
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* |
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* Serial interrupts, as implemented in Raven chipset are not supported yet. |
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* |
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*/ |
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#include "vl.h" |
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#define DEBUG_OPENPIC |
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#ifdef DEBUG_OPENPIC |
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#define DPRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
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#else |
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#define DPRINTF(fmt, args...) do { } while (0)
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#endif |
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#define ERROR(fmr, args...) do { printf("ERROR: " fmr , ##args); } while (0)
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#define USE_MPCxxx /* Intel model is broken, for now */ |
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#if defined (USE_INTEL_GW80314) |
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/* Intel GW80314 I/O Companion chip */ |
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#define MAX_CPU 4 |
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#define MAX_IRQ 32 |
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#define MAX_DBL 4 |
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#define MAX_MBX 4 |
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#define MAX_TMR 4 |
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#define VECTOR_BITS 8 |
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#define MAX_IPI 0 |
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#define VID (0x00000000) |
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|
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#define OPENPIC_LITTLE_ENDIAN 1 |
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#define OPENPIC_BIG_ENDIAN 0 |
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#elif defined(USE_MPCxxx) |
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#define MAX_CPU 2 |
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#define MAX_IRQ 64 |
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#define EXT_IRQ 16 |
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#define MAX_DBL 0 |
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#define MAX_MBX 0 |
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#define MAX_TMR 4 |
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#define VECTOR_BITS 8 |
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#define MAX_IPI 4 |
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#define VID 0x03 /* MPIC version ID */ |
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#define VENI 0x00000000 /* Vendor ID */ |
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enum {
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IRQ_IPVP = 0, |
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IRQ_IDE, |
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}; |
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#define OPENPIC_LITTLE_ENDIAN 1 |
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#define OPENPIC_BIG_ENDIAN 0 |
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#else |
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#error "Please select which OpenPic implementation is to be emulated" |
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#endif |
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#if (OPENPIC_BIG_ENDIAN && !TARGET_WORDS_BIGENDIAN) || \ |
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(OPENPIC_LITTLE_ENDIAN && TARGET_WORDS_BIGENDIAN) |
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#define OPENPIC_SWAP |
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#endif |
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|
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/* Interrupt definitions */ |
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#define IRQ_FE (EXT_IRQ) /* Internal functional IRQ */ |
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#define IRQ_ERR (EXT_IRQ + 1) /* Error IRQ */ |
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#define IRQ_TIM0 (EXT_IRQ + 2) /* First timer IRQ */ |
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#if MAX_IPI > 0 |
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#define IRQ_IPI0 (IRQ_TIM0 + MAX_TMR) /* First IPI IRQ */ |
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#define IRQ_DBL0 (IRQ_IPI0 + (MAX_CPU * MAX_IPI)) /* First doorbell IRQ */ |
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#else |
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#define IRQ_DBL0 (IRQ_TIM0 + MAX_TMR) /* First doorbell IRQ */ |
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#define IRQ_MBX0 (IRQ_DBL0 + MAX_DBL) /* First mailbox IRQ */ |
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#endif |
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|
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#define BF_WIDTH(_bits_) \ |
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(((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8)) |
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static inline void set_bit (uint32_t *field, int bit) |
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{
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field[bit >> 5] |= 1 << (bit & 0x1F); |
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} |
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static inline void reset_bit (uint32_t *field, int bit) |
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{
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field[bit >> 5] &= ~(1 << (bit & 0x1F)); |
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} |
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static inline int test_bit (uint32_t *field, int bit) |
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{
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return (field[bit >> 5] & 1 << (bit & 0x1F)) != 0; |
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} |
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enum {
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IRQ_EXTERNAL = 0x01, |
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IRQ_INTERNAL = 0x02, |
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IRQ_TIMER = 0x04, |
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IRQ_SPECIAL = 0x08, |
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} IRQ_src_type; |
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typedef struct IRQ_queue_t {
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uint32_t queue[BF_WIDTH(MAX_IRQ)]; |
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int next; |
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int priority; |
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} IRQ_queue_t; |
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typedef struct IRQ_src_t {
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uint32_t ipvp; /* IRQ vector/priority register */ |
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uint32_t ide; /* IRQ destination register */ |
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int type; |
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int last_cpu; |
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int waited_acks; |
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} IRQ_src_t; |
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enum IPVP_bits {
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IPVP_MASK = 31, |
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IPVP_ACTIVITY = 30, |
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IPVP_MODE = 29, |
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IPVP_POLARITY = 23, |
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IPVP_SENSE = 22, |
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}; |
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#define IPVP_PRIORITY_MASK (0x1F << 16) |
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#define IPVP_PRIORITY(_ipvpr_) (((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16) |
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#define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1) |
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#define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK) |
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typedef struct IRQ_dst_t {
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uint32_t pctp; /* CPU current task priority */ |
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uint32_t pcsr; /* CPU sensitivity register */ |
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IRQ_queue_t raised; |
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IRQ_queue_t servicing; |
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CPUState *env; /* Needed if we did SMP */ |
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} IRQ_dst_t; |
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|
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typedef struct openpic_t {
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PCIDevice pci_dev; |
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/* Global registers */ |
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uint32_t frep; /* Feature reporting register */ |
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uint32_t glbc; /* Global configuration register */ |
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uint32_t micr; /* MPIC interrupt configuration register */ |
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uint32_t veni; /* Vendor identification register */ |
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uint32_t spve; /* Spurious vector register */ |
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uint32_t tifr; /* Timer frequency reporting register */ |
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/* Source registers */ |
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IRQ_src_t src[MAX_IRQ]; |
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/* Local registers per output pin */ |
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IRQ_dst_t dst[MAX_CPU]; |
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int nb_cpus; |
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/* Timer registers */ |
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struct {
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uint32_t ticc; /* Global timer current count register */ |
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uint32_t tibc; /* Global timer base count register */ |
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} timers[MAX_TMR]; |
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#if MAX_DBL > 0 |
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/* Doorbell registers */ |
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uint32_t dar; /* Doorbell activate register */ |
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struct {
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uint32_t dmr; /* Doorbell messaging register */ |
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} doorbells[MAX_DBL]; |
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#endif |
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#if MAX_MBX > 0 |
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/* Mailbox registers */ |
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struct {
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uint32_t mbr; /* Mailbox register */ |
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} mailboxes[MAX_MAILBOXES]; |
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#endif |
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} openpic_t; |
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static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ) |
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{
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set_bit(q->queue, n_IRQ); |
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} |
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static inline void IRQ_resetbit (IRQ_queue_t *q, int n_IRQ) |
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{
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reset_bit(q->queue, n_IRQ); |
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} |
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static inline int IRQ_testbit (IRQ_queue_t *q, int n_IRQ) |
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{
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return test_bit(q->queue, n_IRQ); |
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} |
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static void IRQ_check (openpic_t *opp, IRQ_queue_t *q) |
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{
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int next, i; |
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int priority; |
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next = -1; |
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priority = -1; |
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for (i = 0; i < MAX_IRQ; i++) {
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if (IRQ_testbit(q, i)) {
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if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) {
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next = i; |
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priority = IPVP_PRIORITY(opp->src[i].ipvp); |
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} |
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} |
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} |
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q->next = next; |
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q->priority = priority; |
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} |
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static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q) |
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{
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if (q->next == -1) {
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if (q->queue == 0) {
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/* No more IRQ */ |
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return -1; |
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} |
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IRQ_check(opp, q); |
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} |
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return q->next; |
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} |
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static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ) |
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{
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IRQ_dst_t *dst; |
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IRQ_src_t *src; |
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int priority; |
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dst = &opp->dst[n_CPU]; |
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src = &opp->src[n_IRQ]; |
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priority = IPVP_PRIORITY(src->ipvp); |
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if (priority <= dst->pctp) {
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/* Too low priority */ |
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return; |
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} |
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if (IRQ_testbit(&dst->raised, n_IRQ)) {
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/* Interrupt miss */ |
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return; |
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} |
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set_bit(&src->ipvp, IPVP_ACTIVITY); |
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IRQ_setbit(&dst->raised, n_IRQ); |
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if (priority > dst->raised.priority) {
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IRQ_get_next(opp, &dst->raised); |
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DPRINTF("Raise CPU IRQ\n");
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cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); |
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} |
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} |
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|
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void openpic_set_IRQ (openpic_t *opp, int n_IRQ, int level) |
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{
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IRQ_src_t *src; |
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int i; |
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src = &opp->src[n_IRQ]; |
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if (!test_bit(&src->ipvp, IPVP_MASK)) {
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/* Interrupt source is disabled */ |
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return; |
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} |
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if (IPVP_PRIORITY(src->ipvp) == 0) {
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/* Priority set to zero */ |
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return; |
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} |
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if (src->ide == 0x00000000) {
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/* No target */ |
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return; |
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} |
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if (level == 0) {
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if (test_bit(&src->ipvp, IPVP_ACTIVITY) && |
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test_bit(&src->ipvp, IPVP_SENSE)) {
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/* Inactivate a active level-sensitive IRQ */ |
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reset_bit(&src->ipvp, IPVP_ACTIVITY); |
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} |
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} else {
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if (test_bit(&src->ipvp, IPVP_ACTIVITY)) {
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/* Interrupt already pending */ |
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return; |
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} |
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if (!test_bit(&src->ipvp, IPVP_MODE) || |
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src->ide == (1 << src->last_cpu)) {
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/* Directed delivery mode */ |
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for (i = 0; i < opp->nb_cpus; i++) {
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if (test_bit(&src->ide, i)) |
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IRQ_local_pipe(opp, i, n_IRQ); |
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} |
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} else {
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/* Distributed delivery mode */ |
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for (i = src->last_cpu; i < src->last_cpu; i++) {
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if (i == MAX_IRQ) |
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i = 0; |
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if (test_bit(&src->ide, i)) {
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IRQ_local_pipe(opp, i, n_IRQ); |
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src->last_cpu = i; |
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break; |
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} |
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} |
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} |
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} |
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} |
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|
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static void openpic_reset (openpic_t *opp) |
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{
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int i; |
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opp->glbc = 0x80000000; |
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/* Initialise controler registers */ |
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opp->frep = ((EXT_IRQ - 1) << 16) | ((MAX_CPU - 1) << 8) | VID; |
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opp->veni = VENI; |
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opp->spve = 0x000000FF; |
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opp->tifr = 0x003F7A00; |
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/* ? */ |
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opp->micr = 0x00000000; |
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/* Initialise IRQ sources */ |
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for (i = 0; i < MAX_IRQ; i++) {
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opp->src[i].ipvp = 0xA0000000; |
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opp->src[i].ide = 0x00000000; |
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} |
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/* Initialise IRQ destinations */ |
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for (i = 0; i < opp->nb_cpus; i++) {
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opp->dst[i].pctp = 0x0000000F; |
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opp->dst[i].pcsr = 0x00000000; |
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memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t)); |
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memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t)); |
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} |
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/* Initialise timers */ |
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for (i = 0; i < MAX_TMR; i++) {
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opp->timers[i].ticc = 0x00000000; |
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opp->timers[i].tibc = 0x80000000; |
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} |
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/* Initialise doorbells */ |
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#if MAX_DBL > 0 |
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opp->dar = 0x00000000; |
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for (i = 0; i < MAX_DBL; i++) {
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| 356 |
opp->doorbells[i].dmr = 0x00000000; |
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} |
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| 358 |
#endif |
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| 359 |
/* Initialise mailboxes */ |
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| 360 |
#if MAX_MBX > 0 |
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| 361 |
for (i = 0; i < MAX_MBX; i++) { /* ? */
|
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| 362 |
opp->mailboxes[i].mbr = 0x00000000; |
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| 363 |
} |
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| 364 |
#endif |
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| 365 |
/* Go out of RESET state */ |
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| 366 |
opp->glbc = 0x00000000; |
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| 367 |
} |
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| 368 |
|
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| 369 |
static inline uint32_t read_IRQreg (openpic_t *opp, int n_IRQ, uint32_t reg) |
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| 370 |
{
|
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| 371 |
uint32_t retval; |
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| 372 |
|
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| 373 |
switch (reg) {
|
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| 374 |
case IRQ_IPVP: |
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| 375 |
retval = opp->src[n_IRQ].ipvp; |
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| 376 |
break; |
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| 377 |
case IRQ_IDE: |
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| 378 |
retval = opp->src[n_IRQ].ide; |
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| 379 |
break; |
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| 380 |
} |
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| 381 |
|
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| 382 |
return retval; |
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| 383 |
} |
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| 384 |
|
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| 385 |
static inline void write_IRQreg (openpic_t *opp, int n_IRQ, |
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| 386 |
uint32_t reg, uint32_t val) |
|
| 387 |
{
|
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| 388 |
uint32_t tmp; |
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| 389 |
|
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| 390 |
switch (reg) {
|
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| 391 |
case IRQ_IPVP: |
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| 392 |
tmp = opp->src[n_IRQ].ipvp & 0x40000000; |
|
| 393 |
if (tmp == 0) {
|
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| 394 |
tmp |= val & 0x80000000; |
|
| 395 |
if ((opp->src[n_IRQ].type & IRQ_EXTERNAL) != 0) |
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| 396 |
tmp |= val & 0x40C00000; |
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| 397 |
else if ((opp->src[n_IRQ].type & IRQ_TIMER) != 0) |
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| 398 |
tmp |= val & 0x00F00000; |
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| 399 |
} else {
|
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| 400 |
tmp |= val & 0x80000000; |
|
| 401 |
} |
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| 402 |
opp->src[n_IRQ].ipvp = tmp | (val & 0x000F00FF); |
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| 403 |
DPRINTF("Set IPVP %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ipvp);
|
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| 404 |
break; |
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| 405 |
case IRQ_IDE: |
|
| 406 |
tmp = val & 0xC0000000; |
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| 407 |
tmp |= val & ((1 << MAX_CPU) - 1); |
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| 408 |
opp->src[n_IRQ].ide = tmp; |
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DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
|
|
| 410 |
break; |
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| 411 |
} |
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| 412 |
} |
|
| 413 |
|
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| 414 |
#if 0 // Code provision for Intel model |
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| 415 |
#if MAX_DBL > 0 |
|
| 416 |
static uint32_t read_doorbell_register (openpic_t *opp, |
|
| 417 |
int n_dbl, uint32_t offset) |
|
| 418 |
{
|
|
| 419 |
uint32_t retval; |
|
| 420 |
|
|
| 421 |
switch (offset) {
|
|
| 422 |
case DBL_IPVP_OFFSET: |
|
| 423 |
retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP); |
|
| 424 |
break; |
|
| 425 |
case DBL_IDE_OFFSET: |
|
| 426 |
retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE); |
|
| 427 |
break; |
|
| 428 |
case DBL_DMR_OFFSET: |
|
| 429 |
retval = opp->doorbells[n_dbl].dmr; |
|
| 430 |
break; |
|
| 431 |
} |
|
| 432 |
|
|
| 433 |
return retval; |
|
| 434 |
} |
|
| 435 |
|
|
| 436 |
static void write_doorbell_register (penpic_t *opp, int n_dbl, |
|
| 437 |
uint32_t offset, uint32_t value) |
|
| 438 |
{
|
|
| 439 |
switch (offset) {
|
|
| 440 |
case DBL_IVPR_OFFSET: |
|
| 441 |
write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP, value); |
|
| 442 |
break; |
|
| 443 |
case DBL_IDE_OFFSET: |
|
| 444 |
write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE, value); |
|
| 445 |
break; |
|
| 446 |
case DBL_DMR_OFFSET: |
|
| 447 |
opp->doorbells[n_dbl].dmr = value; |
|
| 448 |
break; |
|
| 449 |
} |
|
| 450 |
} |
|
| 451 |
#endif |
|
| 452 |
|
|
| 453 |
#if MAX_MBX > 0 |
|
| 454 |
static uint32_t read_mailbox_register (openpic_t *opp, |
|
| 455 |
int n_mbx, uint32_t offset) |
|
| 456 |
{
|
|
| 457 |
uint32_t retval; |
|
| 458 |
|
|
| 459 |
switch (offset) {
|
|
| 460 |
case MBX_MBR_OFFSET: |
|
| 461 |
retval = opp->mailboxes[n_mbx].mbr; |
|
| 462 |
break; |
|
| 463 |
case MBX_IVPR_OFFSET: |
|
| 464 |
retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP); |
|
| 465 |
break; |
|
| 466 |
case MBX_DMR_OFFSET: |
|
| 467 |
retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE); |
|
| 468 |
break; |
|
| 469 |
} |
|
| 470 |
|
|
| 471 |
return retval; |
|
| 472 |
} |
|
| 473 |
|
|
| 474 |
static void write_mailbox_register (openpic_t *opp, int n_mbx, |
|
| 475 |
uint32_t address, uint32_t value) |
|
| 476 |
{
|
|
| 477 |
switch (offset) {
|
|
| 478 |
case MBX_MBR_OFFSET: |
|
| 479 |
opp->mailboxes[n_mbx].mbr = value; |
|
| 480 |
break; |
|
| 481 |
case MBX_IVPR_OFFSET: |
|
| 482 |
write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP, value); |
|
| 483 |
break; |
|
| 484 |
case MBX_DMR_OFFSET: |
|
| 485 |
write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE, value); |
|
| 486 |
break; |
|
| 487 |
} |
|
| 488 |
} |
|
| 489 |
#endif |
|
| 490 |
#endif /* 0 : Code provision for Intel model */ |
|
| 491 |
|
|
| 492 |
static void openpic_gbl_write (void *opaque, uint32_t addr, uint32_t val) |
|
| 493 |
{
|
|
| 494 |
openpic_t *opp = opaque; |
|
| 495 |
|
|
| 496 |
DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
|
|
| 497 |
if (addr & 0xF) |
|
| 498 |
return; |
|
| 499 |
#if defined OPENPIC_SWAP |
|
| 500 |
val = bswap32(val); |
|
| 501 |
#endif |
|
| 502 |
addr &= 0xFF; |
|
| 503 |
switch (addr) {
|
|
| 504 |
case 0x00: /* FREP */ |
|
| 505 |
break; |
|
| 506 |
case 0x20: /* GLBC */ |
|
| 507 |
if (val & 0x80000000) |
|
| 508 |
openpic_reset(opp); |
|
| 509 |
opp->glbc = val & ~0x80000000; |
|
| 510 |
break; |
|
| 511 |
case 0x80: /* VENI */ |
|
| 512 |
break; |
|
| 513 |
case 0x90: /* PINT */ |
|
| 514 |
/* XXX: Should be able to reset any CPU */ |
|
| 515 |
if (val & 1) {
|
|
| 516 |
DPRINTF("Reset CPU IRQ\n");
|
|
| 517 |
// cpu_interrupt(cpu_single_env, CPU_INTERRUPT_RESET); |
|
| 518 |
} |
|
| 519 |
break; |
|
| 520 |
#if MAX_IPI > 0 |
|
| 521 |
case 0xA0: /* IPI_IPVP */ |
|
| 522 |
case 0xB0: |
|
| 523 |
case 0xC0: |
|
| 524 |
case 0xD0: |
|
| 525 |
{
|
|
| 526 |
int idx; |
|
| 527 |
idx = (addr - 0xA0) >> 4; |
|
| 528 |
write_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IPVP, val); |
|
| 529 |
} |
|
| 530 |
break; |
|
| 531 |
#endif |
|
| 532 |
case 0xE0: /* SPVE */ |
|
| 533 |
opp->spve = val & 0x000000FF; |
|
| 534 |
break; |
|
| 535 |
case 0xF0: /* TIFR */ |
|
| 536 |
opp->tifr = val; |
|
| 537 |
break; |
|
| 538 |
default: |
|
| 539 |
break; |
|
| 540 |
} |
|
| 541 |
} |
|
| 542 |
|
|
| 543 |
static uint32_t openpic_gbl_read (void *opaque, uint32_t addr) |
|
| 544 |
{
|
|
| 545 |
openpic_t *opp = opaque; |
|
| 546 |
uint32_t retval; |
|
| 547 |
|
|
| 548 |
DPRINTF("%s: addr %08x\n", __func__, addr);
|
|
| 549 |
retval = 0xFFFFFFFF; |
|
| 550 |
if (addr & 0xF) |
|
| 551 |
return retval; |
|
| 552 |
addr &= 0xFF; |
|
| 553 |
switch (addr) {
|
|
| 554 |
case 0x00: /* FREP */ |
|
| 555 |
retval = opp->frep; |
|
| 556 |
break; |
|
| 557 |
case 0x20: /* GLBC */ |
|
| 558 |
retval = opp->glbc; |
|
| 559 |
break; |
|
| 560 |
case 0x80: /* VENI */ |
|
| 561 |
retval = opp->veni; |
|
| 562 |
break; |
|
| 563 |
case 0x90: /* PINT */ |
|
| 564 |
retval = 0x00000000; |
|
| 565 |
break; |
|
| 566 |
#if MAX_IPI > 0 |
|
| 567 |
case 0xA0: /* IPI_IPVP */ |
|
| 568 |
case 0xB0: |
|
| 569 |
case 0xC0: |
|
| 570 |
case 0xD0: |
|
| 571 |
{
|
|
| 572 |
int idx; |
|
| 573 |
idx = (addr - 0xA0) >> 4; |
|
| 574 |
retval = read_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IPVP); |
|
| 575 |
} |
|
| 576 |
break; |
|
| 577 |
#endif |
|
| 578 |
case 0xE0: /* SPVE */ |
|
| 579 |
retval = opp->spve; |
|
| 580 |
break; |
|
| 581 |
case 0xF0: /* TIFR */ |
|
| 582 |
retval = opp->tifr; |
|
| 583 |
break; |
|
| 584 |
default: |
|
| 585 |
break; |
|
| 586 |
} |
|
| 587 |
DPRINTF("%s: => %08x\n", __func__, retval);
|
|
| 588 |
#if defined OPENPIC_SWAP |
|
| 589 |
retval = bswap32(retval); |
|
| 590 |
#endif |
|
| 591 |
|
|
| 592 |
return retval; |
|
| 593 |
} |
|
| 594 |
|
|
| 595 |
static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val) |
|
| 596 |
{
|
|
| 597 |
openpic_t *opp = opaque; |
|
| 598 |
int idx; |
|
| 599 |
|
|
| 600 |
DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
|
|
| 601 |
if (addr & 0xF) |
|
| 602 |
return; |
|
| 603 |
#if defined OPENPIC_SWAP |
|
| 604 |
val = bswap32(val); |
|
| 605 |
#endif |
|
| 606 |
addr -= 0x1100; |
|
| 607 |
addr &= 0xFFFF; |
|
| 608 |
idx = (addr & 0xFFF0) >> 6; |
|
| 609 |
addr = addr & 0x30; |
|
| 610 |
switch (addr) {
|
|
| 611 |
case 0x00: /* TICC */ |
|
| 612 |
break; |
|
| 613 |
case 0x10: /* TIBC */ |
|
| 614 |
if ((opp->timers[idx].ticc & 0x80000000) != 0 && |
|
| 615 |
(val & 0x800000000) == 0 && |
|
| 616 |
(opp->timers[idx].tibc & 0x80000000) != 0) |
|
| 617 |
opp->timers[idx].ticc &= ~0x80000000; |
|
| 618 |
opp->timers[idx].tibc = val; |
|
| 619 |
break; |
|
| 620 |
case 0x20: /* TIVP */ |
|
| 621 |
write_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IPVP, val); |
|
| 622 |
break; |
|
| 623 |
case 0x30: /* TIDE */ |
|
| 624 |
write_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IDE, val); |
|
| 625 |
break; |
|
| 626 |
} |
|
| 627 |
} |
|
| 628 |
|
|
| 629 |
static uint32_t openpic_timer_read (void *opaque, uint32_t addr) |
|
| 630 |
{
|
|
| 631 |
openpic_t *opp = opaque; |
|
| 632 |
uint32_t retval; |
|
| 633 |
int idx; |
|
| 634 |
|
|
| 635 |
DPRINTF("%s: addr %08x\n", __func__, addr);
|
|
| 636 |
retval = 0xFFFFFFFF; |
|
| 637 |
if (addr & 0xF) |
|
| 638 |
return retval; |
|
| 639 |
addr -= 0x1100; |
|
| 640 |
addr &= 0xFFFF; |
|
| 641 |
idx = (addr & 0xFFF0) >> 6; |
|
| 642 |
addr = addr & 0x30; |
|
| 643 |
switch (addr) {
|
|
| 644 |
case 0x00: /* TICC */ |
|
| 645 |
retval = opp->timers[idx].ticc; |
|
| 646 |
break; |
|
| 647 |
case 0x10: /* TIBC */ |
|
| 648 |
retval = opp->timers[idx].tibc; |
|
| 649 |
break; |
|
| 650 |
case 0x20: /* TIPV */ |
|
| 651 |
retval = read_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IPVP); |
|
| 652 |
break; |
|
| 653 |
case 0x30: /* TIDE */ |
|
| 654 |
retval = read_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IDE); |
|
| 655 |
break; |
|
| 656 |
} |
|
| 657 |
DPRINTF("%s: => %08x\n", __func__, retval);
|
|
| 658 |
#if defined OPENPIC_SWAP |
|
| 659 |
retval = bswap32(retval); |
|
| 660 |
#endif |
|
| 661 |
|
|
| 662 |
return retval; |
|
| 663 |
} |
|
| 664 |
|
|
| 665 |
static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val) |
|
| 666 |
{
|
|
| 667 |
openpic_t *opp = opaque; |
|
| 668 |
int idx; |
|
| 669 |
|
|
| 670 |
DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
|
|
| 671 |
if (addr & 0xF) |
|
| 672 |
return; |
|
| 673 |
#if defined OPENPIC_SWAP |
|
| 674 |
val = tswap32(val); |
|
| 675 |
#endif |
|
| 676 |
addr = addr & 0xFFF0; |
|
| 677 |
idx = addr >> 5; |
|
| 678 |
if (addr & 0x10) {
|
|
| 679 |
/* EXDE / IFEDE / IEEDE */ |
|
| 680 |
write_IRQreg(opp, idx, IRQ_IDE, val); |
|
| 681 |
} else {
|
|
| 682 |
/* EXVP / IFEVP / IEEVP */ |
|
| 683 |
write_IRQreg(opp, idx, IRQ_IPVP, val); |
|
| 684 |
} |
|
| 685 |
} |
|
| 686 |
|
|
| 687 |
static uint32_t openpic_src_read (void *opaque, uint32_t addr) |
|
| 688 |
{
|
|
| 689 |
openpic_t *opp = opaque; |
|
| 690 |
uint32_t retval; |
|
| 691 |
int idx; |
|
| 692 |
|
|
| 693 |
DPRINTF("%s: addr %08x\n", __func__, addr);
|
|
| 694 |
retval = 0xFFFFFFFF; |
|
| 695 |
if (addr & 0xF) |
|
| 696 |
return retval; |
|
| 697 |
addr = addr & 0xFFF0; |
|
| 698 |
idx = addr >> 5; |
|
| 699 |
if (addr & 0x10) {
|
|
| 700 |
/* EXDE / IFEDE / IEEDE */ |
|
| 701 |
retval = read_IRQreg(opp, idx, IRQ_IDE); |
|
| 702 |
} else {
|
|
| 703 |
/* EXVP / IFEVP / IEEVP */ |
|
| 704 |
retval = read_IRQreg(opp, idx, IRQ_IPVP); |
|
| 705 |
} |
|
| 706 |
DPRINTF("%s: => %08x\n", __func__, retval);
|
|
| 707 |
#if defined OPENPIC_SWAP |
|
| 708 |
retval = tswap32(retval); |
|
| 709 |
#endif |
|
| 710 |
|
|
| 711 |
return retval; |
|
| 712 |
} |
|
| 713 |
|
|
| 714 |
static void openpic_cpu_write (void *opaque, uint32_t addr, uint32_t val) |
|
| 715 |
{
|
|
| 716 |
openpic_t *opp = opaque; |
|
| 717 |
IRQ_src_t *src; |
|
| 718 |
IRQ_dst_t *dst; |
|
| 719 |
int idx, n_IRQ; |
|
| 720 |
|
|
| 721 |
DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
|
|
| 722 |
if (addr & 0xF) |
|
| 723 |
return; |
|
| 724 |
#if defined OPENPIC_SWAP |
|
| 725 |
val = bswap32(val); |
|
| 726 |
#endif |
|
| 727 |
addr &= 0x1FFF0; |
|
| 728 |
idx = addr / 0x1000; |
|
| 729 |
dst = &opp->dst[idx]; |
|
| 730 |
addr &= 0xFF0; |
|
| 731 |
switch (addr) {
|
|
| 732 |
#if MAX_IPI > 0 |
|
| 733 |
case 0x40: /* PIPD */ |
|
| 734 |
case 0x50: |
|
| 735 |
case 0x60: |
|
| 736 |
case 0x70: |
|
| 737 |
idx = (addr - 0x40) >> 4; |
|
| 738 |
write_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IDE, val); |
|
| 739 |
openpic_set_IRQ(opp, IRQ_IPI0 + idx, 1); |
|
| 740 |
openpic_set_IRQ(opp, IRQ_IPI0 + idx, 0); |
|
| 741 |
break; |
|
| 742 |
#endif |
|
| 743 |
case 0x80: /* PCTP */ |
|
| 744 |
dst->pctp = val & 0x0000000F; |
|
| 745 |
break; |
|
| 746 |
case 0x90: /* WHOAMI */ |
|
| 747 |
/* Read-only register */ |
|
| 748 |
break; |
|
| 749 |
case 0xA0: /* PIAC */ |
|
| 750 |
/* Read-only register */ |
|
| 751 |
break; |
|
| 752 |
case 0xB0: /* PEOI */ |
|
| 753 |
DPRINTF("PEOI\n");
|
|
| 754 |
n_IRQ = IRQ_get_next(opp, &dst->servicing); |
|
| 755 |
IRQ_resetbit(&dst->servicing, n_IRQ); |
|
| 756 |
dst->servicing.next = -1; |
|
| 757 |
src = &opp->src[n_IRQ]; |
|
| 758 |
/* Set up next servicing IRQ */ |
|
| 759 |
IRQ_get_next(opp, &dst->servicing); |
|
| 760 |
/* Check queued interrupts. */ |
|
| 761 |
n_IRQ = IRQ_get_next(opp, &dst->raised); |
|
| 762 |
if (n_IRQ != -1) {
|
|
| 763 |
src = &opp->src[n_IRQ]; |
|
| 764 |
if (IPVP_PRIORITY(src->ipvp) > dst->servicing.priority) {
|
|
| 765 |
DPRINTF("Raise CPU IRQ\n");
|
|
| 766 |
cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); |
|
| 767 |
} |
|
| 768 |
} |
|
| 769 |
break; |
|
| 770 |
default: |
|
| 771 |
break; |
|
| 772 |
} |
|
| 773 |
} |
|
| 774 |
|
|
| 775 |
static uint32_t openpic_cpu_read (void *opaque, uint32_t addr) |
|
| 776 |
{
|
|
| 777 |
openpic_t *opp = opaque; |
|
| 778 |
IRQ_src_t *src; |
|
| 779 |
IRQ_dst_t *dst; |
|
| 780 |
uint32_t retval; |
|
| 781 |
int idx, n_IRQ; |
|
| 782 |
|
|
| 783 |
DPRINTF("%s: addr %08x\n", __func__, addr);
|
|
| 784 |
retval = 0xFFFFFFFF; |
|
| 785 |
if (addr & 0xF) |
|
| 786 |
return retval; |
|
| 787 |
addr &= 0x1FFF0; |
|
| 788 |
idx = addr / 0x1000; |
|
| 789 |
dst = &opp->dst[idx]; |
|
| 790 |
addr &= 0xFF0; |
|
| 791 |
switch (addr) {
|
|
| 792 |
case 0x80: /* PCTP */ |
|
| 793 |
retval = dst->pctp; |
|
| 794 |
break; |
|
| 795 |
case 0x90: /* WHOAMI */ |
|
| 796 |
retval = idx; |
|
| 797 |
break; |
|
| 798 |
case 0xA0: /* PIAC */ |
|
| 799 |
n_IRQ = IRQ_get_next(opp, &dst->raised); |
|
| 800 |
DPRINTF("PIAC: irq=%d\n", n_IRQ);
|
|
| 801 |
if (n_IRQ == -1) {
|
|
| 802 |
/* No more interrupt pending */ |
|
| 803 |
retval = opp->spve; |
|
| 804 |
} else {
|
|
| 805 |
src = &opp->src[n_IRQ]; |
|
| 806 |
if (!test_bit(&src->ipvp, IPVP_ACTIVITY) || |
|
| 807 |
!(IPVP_PRIORITY(src->ipvp) > dst->pctp)) {
|
|
| 808 |
/* - Spurious level-sensitive IRQ |
|
| 809 |
* - Priorities has been changed |
|
| 810 |
* and the pending IRQ isn't allowed anymore |
|
| 811 |
*/ |
|
| 812 |
reset_bit(&src->ipvp, IPVP_ACTIVITY); |
|
| 813 |
retval = IPVP_VECTOR(opp->spve); |
|
| 814 |
} else {
|
|
| 815 |
/* IRQ enter servicing state */ |
|
| 816 |
IRQ_setbit(&dst->servicing, n_IRQ); |
|
| 817 |
retval = IPVP_VECTOR(src->ipvp); |
|
| 818 |
} |
|
| 819 |
IRQ_resetbit(&dst->raised, n_IRQ); |
|
| 820 |
dst->raised.next = -1; |
|
| 821 |
if (!test_bit(&src->ipvp, IPVP_SENSE)) |
|
| 822 |
reset_bit(&src->ipvp, IPVP_ACTIVITY); |
|
| 823 |
} |
|
| 824 |
break; |
|
| 825 |
case 0xB0: /* PEOI */ |
|
| 826 |
retval = 0; |
|
| 827 |
break; |
|
| 828 |
#if MAX_IPI > 0 |
|
| 829 |
case 0x40: /* IDE */ |
|
| 830 |
case 0x50: |
|
| 831 |
idx = (addr - 0x40) >> 4; |
|
| 832 |
retval = read_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IDE); |
|
| 833 |
break; |
|
| 834 |
#endif |
|
| 835 |
default: |
|
| 836 |
break; |
|
| 837 |
} |
|
| 838 |
DPRINTF("%s: => %08x\n", __func__, retval);
|
|
| 839 |
#if defined OPENPIC_SWAP |
|
| 840 |
retval= bswap32(retval); |
|
| 841 |
#endif |
|
| 842 |
|
|
| 843 |
return retval; |
|
| 844 |
} |
|
| 845 |
|
|
| 846 |
static void openpic_buggy_write (void *opaque, |
|
| 847 |
target_phys_addr_t addr, uint32_t val) |
|
| 848 |
{
|
|
| 849 |
printf("Invalid OPENPIC write access !\n");
|
|
| 850 |
} |
|
| 851 |
|
|
| 852 |
static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr) |
|
| 853 |
{
|
|
| 854 |
printf("Invalid OPENPIC read access !\n");
|
|
| 855 |
|
|
| 856 |
return -1; |
|
| 857 |
} |
|
| 858 |
|
|
| 859 |
static void openpic_writel (void *opaque, |
|
| 860 |
target_phys_addr_t addr, uint32_t val) |
|
| 861 |
{
|
|
| 862 |
openpic_t *opp = opaque; |
|
| 863 |
|
|
| 864 |
addr &= 0x3FFFF; |
|
| 865 |
DPRINTF("%s: offset %08lx val: %08x\n", __func__, addr, val);
|
|
| 866 |
if (addr < 0x1100) {
|
|
| 867 |
/* Global registers */ |
|
| 868 |
openpic_gbl_write(opp, addr, val); |
|
| 869 |
} else if (addr < 0x10000) {
|
|
| 870 |
/* Timers registers */ |
|
| 871 |
openpic_timer_write(opp, addr, val); |
|
| 872 |
} else if (addr < 0x20000) {
|
|
| 873 |
/* Source registers */ |
|
| 874 |
openpic_src_write(opp, addr, val); |
|
| 875 |
} else {
|
|
| 876 |
/* CPU registers */ |
|
| 877 |
openpic_cpu_write(opp, addr, val); |
|
| 878 |
} |
|
| 879 |
} |
|
| 880 |
|
|
| 881 |
static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr) |
|
| 882 |
{
|
|
| 883 |
openpic_t *opp = opaque; |
|
| 884 |
uint32_t retval; |
|
| 885 |
|
|
| 886 |
addr &= 0x3FFFF; |
|
| 887 |
DPRINTF("%s: offset %08lx\n", __func__, addr);
|
|
| 888 |
if (addr < 0x1100) {
|
|
| 889 |
/* Global registers */ |
|
| 890 |
retval = openpic_gbl_read(opp, addr); |
|
| 891 |
} else if (addr < 0x10000) {
|
|
| 892 |
/* Timers registers */ |
|
| 893 |
retval = openpic_timer_read(opp, addr); |
|
| 894 |
} else if (addr < 0x20000) {
|
|
| 895 |
/* Source registers */ |
|
| 896 |
retval = openpic_src_read(opp, addr); |
|
| 897 |
} else {
|
|
| 898 |
/* CPU registers */ |
|
| 899 |
retval = openpic_cpu_read(opp, addr); |
|
| 900 |
} |
|
| 901 |
|
|
| 902 |
return retval; |
|
| 903 |
} |
|
| 904 |
|
|
| 905 |
static CPUWriteMemoryFunc *openpic_write[] = {
|
|
| 906 |
&openpic_buggy_write, |
|
| 907 |
&openpic_buggy_write, |
|
| 908 |
&openpic_writel, |
|
| 909 |
}; |
|
| 910 |
|
|
| 911 |
static CPUReadMemoryFunc *openpic_read[] = {
|
|
| 912 |
&openpic_buggy_read, |
|
| 913 |
&openpic_buggy_read, |
|
| 914 |
&openpic_readl, |
|
| 915 |
}; |
|
| 916 |
|
|
| 917 |
static void openpic_map(PCIDevice *pci_dev, int region_num, |
|
| 918 |
uint32_t addr, uint32_t size, int type) |
|
| 919 |
{
|
|
| 920 |
openpic_t *opp; |
|
| 921 |
int opp_io_memory; |
|
| 922 |
|
|
| 923 |
DPRINTF("Map OpenPIC\n");
|
|
| 924 |
opp = (openpic_t *)pci_dev; |
|
| 925 |
/* Global registers */ |
|
| 926 |
DPRINTF("Register OPENPIC gbl %08x => %08x\n",
|
|
| 927 |
addr + 0x1000, addr + 0x1000 + 0x100); |
|
| 928 |
/* Timer registers */ |
|
| 929 |
DPRINTF("Register OPENPIC timer %08x => %08x\n",
|
|
| 930 |
addr + 0x1100, addr + 0x1100 + 0x40 * MAX_TMR); |
|
| 931 |
/* Interrupt source registers */ |
|
| 932 |
DPRINTF("Register OPENPIC src %08x => %08x\n",
|
|
| 933 |
addr + 0x10000, addr + 0x10000 + 0x20 * (EXT_IRQ + 2)); |
|
| 934 |
/* Per CPU registers */ |
|
| 935 |
DPRINTF("Register OPENPIC dst %08x => %08x\n",
|
|
| 936 |
addr + 0x20000, addr + 0x20000 + 0x1000 * MAX_CPU); |
|
| 937 |
opp_io_memory = cpu_register_io_memory(0, openpic_read, |
|
| 938 |
openpic_write, opp); |
|
| 939 |
cpu_register_physical_memory(addr, 0x40000, opp_io_memory); |
|
| 940 |
#if 0 // Don't implement ISU for now |
|
| 941 |
opp_io_memory = cpu_register_io_memory(0, openpic_src_read, |
|
| 942 |
openpic_src_write); |
|
| 943 |
cpu_register_physical_memory(isu_base, 0x20 * (EXT_IRQ + 2), |
|
| 944 |
opp_io_memory); |
|
| 945 |
#endif |
|
| 946 |
} |
|
| 947 |
|
|
| 948 |
openpic_t *openpic_init (uint32_t isu_base, uint32_t idu_base, int nb_cpus) |
|
| 949 |
{
|
|
| 950 |
openpic_t *opp; |
|
| 951 |
uint8_t *pci_conf; |
|
| 952 |
int i, m; |
|
| 953 |
|
|
| 954 |
/* XXX: for now, only one CPU is supported */ |
|
| 955 |
if (nb_cpus != 1) |
|
| 956 |
return NULL; |
|
| 957 |
opp = (openpic_t *)pci_register_device("OpenPIC", sizeof(openpic_t),
|
|
| 958 |
0, -1, NULL, NULL); |
|
| 959 |
if (opp == NULL) |
|
| 960 |
return NULL; |
|
| 961 |
pci_conf = opp->pci_dev.config; |
|
| 962 |
pci_conf[0x00] = 0x14; // IBM MPIC2 |
|
| 963 |
pci_conf[0x01] = 0x10; |
|
| 964 |
pci_conf[0x02] = 0xFF; |
|
| 965 |
pci_conf[0x03] = 0xFF; |
|
| 966 |
pci_conf[0x0a] = 0x80; // PIC |
|
| 967 |
pci_conf[0x0b] = 0x08; |
|
| 968 |
pci_conf[0x0e] = 0x00; // header_type |
|
| 969 |
pci_conf[0x3d] = 0x00; // no interrupt pin |
|
| 970 |
|
|
| 971 |
/* Register I/O spaces */ |
|
| 972 |
pci_register_io_region((PCIDevice *)opp, 0, 0x40000, |
|
| 973 |
PCI_ADDRESS_SPACE_MEM, &openpic_map); |
|
| 974 |
|
|
| 975 |
isu_base &= 0xFFFC0000; |
|
| 976 |
opp->nb_cpus = nb_cpus; |
|
| 977 |
/* Set IRQ types */ |
|
| 978 |
for (i = 0; i < EXT_IRQ; i++) {
|
|
| 979 |
opp->src[i].type = IRQ_EXTERNAL; |
|
| 980 |
} |
|
| 981 |
for (; i < IRQ_TIM0; i++) {
|
|
| 982 |
opp->src[i].type = IRQ_SPECIAL; |
|
| 983 |
} |
|
| 984 |
#if MAX_IPI > 0 |
|
| 985 |
m = IRQ_IPI0; |
|
| 986 |
#else |
|
| 987 |
m = IRQ_DBL0; |
|
| 988 |
#endif |
|
| 989 |
for (; i < m; i++) {
|
|
| 990 |
opp->src[i].type = IRQ_TIMER; |
|
| 991 |
} |
|
| 992 |
for (; i < MAX_IRQ; i++) {
|
|
| 993 |
opp->src[i].type = IRQ_INTERNAL; |
|
| 994 |
} |
|
| 995 |
openpic_reset(opp); |
|
| 996 |
|
|
| 997 |
return opp; |
|
| 998 |
} |
|
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