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1
/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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25
#ifndef NDEBUG
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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    "%g0",
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    "%g1",
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    "%g2",
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    "%g3",
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    "%g4",
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    "%g5",
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    "%g6",
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    "%g7",
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    "%o0",
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    "%o1",
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    "%o2",
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    "%o3",
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    "%o4",
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    "%o5",
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    "%o6",
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    "%o7",
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    "%l0",
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    "%l1",
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    "%l2",
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    "%l3",
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    "%l4",
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    "%l5",
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    "%l6",
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    "%l7",
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    "%i0",
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    "%i1",
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    "%i2",
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    "%i3",
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    "%i4",
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    "%i5",
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    "%i6",
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    "%i7",
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};
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#endif
61

    
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static const int tcg_target_reg_alloc_order[] = {
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    TCG_REG_L0,
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    TCG_REG_L1,
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    TCG_REG_L2,
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    TCG_REG_L3,
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    TCG_REG_L4,
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    TCG_REG_L5,
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    TCG_REG_L6,
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    TCG_REG_L7,
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    TCG_REG_I0,
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    TCG_REG_I1,
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    TCG_REG_I2,
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    TCG_REG_I3,
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    TCG_REG_I4,
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};
77

    
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static const int tcg_target_call_iarg_regs[6] = {
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    TCG_REG_O0,
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    TCG_REG_O1,
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    TCG_REG_O2,
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    TCG_REG_O3,
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    TCG_REG_O4,
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    TCG_REG_O5,
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};
86

    
87
static const int tcg_target_call_oarg_regs[2] = {
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    TCG_REG_O0,
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    TCG_REG_O1,
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};
91

    
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static inline int check_fit_tl(tcg_target_long val, unsigned int bits)
93
{
94
    return (val << ((sizeof(tcg_target_long) * 8 - bits))
95
            >> (sizeof(tcg_target_long) * 8 - bits)) == val;
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}
97

    
98
static inline int check_fit_i32(uint32_t val, unsigned int bits)
99
{
100
    return ((val << (32 - bits)) >> (32 - bits)) == val;
101
}
102

    
103
static void patch_reloc(uint8_t *code_ptr, int type,
104
                        tcg_target_long value, tcg_target_long addend)
105
{
106
    value += addend;
107
    switch (type) {
108
    case R_SPARC_32:
109
        if (value != (uint32_t)value)
110
            tcg_abort();
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        *(uint32_t *)code_ptr = value;
112
        break;
113
    case R_SPARC_WDISP22:
114
        value -= (long)code_ptr;
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        value >>= 2;
116
        if (!check_fit_tl(value, 22))
117
            tcg_abort();
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        *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x3fffff) | value;
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        break;
120
    case R_SPARC_WDISP19:
121
        value -= (long)code_ptr;
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        value >>= 2;
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        if (!check_fit_tl(value, 19))
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            tcg_abort();
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        *(uint32_t *)code_ptr = ((*(uint32_t *)code_ptr) & ~0x7ffff) | value;
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        break;
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    default:
128
        tcg_abort();
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    }
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}
131

    
132
/* maximum number of register used for input function arguments */
133
static inline int tcg_target_get_call_iarg_regs_count(int flags)
134
{
135
    return 6;
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}
137

    
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/* parse target specific constraints */
139
static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
140
{
141
    const char *ct_str;
142

    
143
    ct_str = *pct_str;
144
    switch (ct_str[0]) {
145
    case 'r':
146
        ct->ct |= TCG_CT_REG;
147
        tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
148
        break;
149
    case 'L': /* qemu_ld/st constraint */
150
        ct->ct |= TCG_CT_REG;
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        tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
152
        // Helper args
153
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
154
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
155
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
156
        break;
157
    case 'I':
158
        ct->ct |= TCG_CT_CONST_S11;
159
        break;
160
    case 'J':
161
        ct->ct |= TCG_CT_CONST_S13;
162
        break;
163
    default:
164
        return -1;
165
    }
166
    ct_str++;
167
    *pct_str = ct_str;
168
    return 0;
169
}
170

    
171
/* test if a constant matches the constraint */
172
static inline int tcg_target_const_match(tcg_target_long val,
173
                                         const TCGArgConstraint *arg_ct)
174
{
175
    int ct;
176

    
177
    ct = arg_ct->ct;
178
    if (ct & TCG_CT_CONST)
179
        return 1;
180
    else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11))
181
        return 1;
182
    else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13))
183
        return 1;
184
    else
185
        return 0;
186
}
187

    
188
#define INSN_OP(x)  ((x) << 30)
189
#define INSN_OP2(x) ((x) << 22)
190
#define INSN_OP3(x) ((x) << 19)
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#define INSN_OPF(x) ((x) << 5)
192
#define INSN_RD(x)  ((x) << 25)
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#define INSN_RS1(x) ((x) << 14)
194
#define INSN_RS2(x) (x)
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#define INSN_ASI(x) ((x) << 5)
196

    
197
#define INSN_IMM11(x) ((1 << 13) | ((x) & 0x7ff))
198
#define INSN_IMM13(x) ((1 << 13) | ((x) & 0x1fff))
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#define INSN_OFF19(x) (((x) >> 2) & 0x07ffff)
200
#define INSN_OFF22(x) (((x) >> 2) & 0x3fffff)
201

    
202
#define INSN_COND(x, a) (((x) << 25) | ((a) << 29))
203
#define COND_N     0x0
204
#define COND_E     0x1
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#define COND_LE    0x2
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#define COND_L     0x3
207
#define COND_LEU   0x4
208
#define COND_CS    0x5
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#define COND_NEG   0x6
210
#define COND_VS    0x7
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#define COND_A     0x8
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#define COND_NE    0x9
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#define COND_G     0xa
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#define COND_GE    0xb
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#define COND_GU    0xc
216
#define COND_CC    0xd
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#define COND_POS   0xe
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#define COND_VC    0xf
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#define BA         (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2))
220

    
221
#define MOVCC_ICC  (1 << 18)
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#define MOVCC_XCC  (1 << 18 | 1 << 12)
223

    
224
#define ARITH_ADD  (INSN_OP(2) | INSN_OP3(0x00))
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#define ARITH_ADDCC (INSN_OP(2) | INSN_OP3(0x10))
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#define ARITH_AND  (INSN_OP(2) | INSN_OP3(0x01))
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#define ARITH_OR   (INSN_OP(2) | INSN_OP3(0x02))
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#define ARITH_ORCC (INSN_OP(2) | INSN_OP3(0x12))
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#define ARITH_XOR  (INSN_OP(2) | INSN_OP3(0x03))
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#define ARITH_SUB  (INSN_OP(2) | INSN_OP3(0x04))
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#define ARITH_SUBCC (INSN_OP(2) | INSN_OP3(0x14))
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#define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x10))
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#define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
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#define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
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#define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
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#define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
237
#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
238
#define ARITH_UDIVX (INSN_OP(2) | INSN_OP3(0x0d))
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#define ARITH_SDIVX (INSN_OP(2) | INSN_OP3(0x2d))
240
#define ARITH_MOVCC (INSN_OP(2) | INSN_OP3(0x2c))
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242
#define SHIFT_SLL  (INSN_OP(2) | INSN_OP3(0x25))
243
#define SHIFT_SRL  (INSN_OP(2) | INSN_OP3(0x26))
244
#define SHIFT_SRA  (INSN_OP(2) | INSN_OP3(0x27))
245

    
246
#define SHIFT_SLLX (INSN_OP(2) | INSN_OP3(0x25) | (1 << 12))
247
#define SHIFT_SRLX (INSN_OP(2) | INSN_OP3(0x26) | (1 << 12))
248
#define SHIFT_SRAX (INSN_OP(2) | INSN_OP3(0x27) | (1 << 12))
249

    
250
#define RDY        (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(0))
251
#define WRY        (INSN_OP(2) | INSN_OP3(0x30) | INSN_RD(0))
252
#define JMPL       (INSN_OP(2) | INSN_OP3(0x38))
253
#define SAVE       (INSN_OP(2) | INSN_OP3(0x3c))
254
#define RESTORE    (INSN_OP(2) | INSN_OP3(0x3d))
255
#define SETHI      (INSN_OP(0) | INSN_OP2(0x4))
256
#define CALL       INSN_OP(1)
257
#define LDUB       (INSN_OP(3) | INSN_OP3(0x01))
258
#define LDSB       (INSN_OP(3) | INSN_OP3(0x09))
259
#define LDUH       (INSN_OP(3) | INSN_OP3(0x02))
260
#define LDSH       (INSN_OP(3) | INSN_OP3(0x0a))
261
#define LDUW       (INSN_OP(3) | INSN_OP3(0x00))
262
#define LDSW       (INSN_OP(3) | INSN_OP3(0x08))
263
#define LDX        (INSN_OP(3) | INSN_OP3(0x0b))
264
#define STB        (INSN_OP(3) | INSN_OP3(0x05))
265
#define STH        (INSN_OP(3) | INSN_OP3(0x06))
266
#define STW        (INSN_OP(3) | INSN_OP3(0x04))
267
#define STX        (INSN_OP(3) | INSN_OP3(0x0e))
268
#define LDUBA      (INSN_OP(3) | INSN_OP3(0x11))
269
#define LDSBA      (INSN_OP(3) | INSN_OP3(0x19))
270
#define LDUHA      (INSN_OP(3) | INSN_OP3(0x12))
271
#define LDSHA      (INSN_OP(3) | INSN_OP3(0x1a))
272
#define LDUWA      (INSN_OP(3) | INSN_OP3(0x10))
273
#define LDSWA      (INSN_OP(3) | INSN_OP3(0x18))
274
#define LDXA       (INSN_OP(3) | INSN_OP3(0x1b))
275
#define STBA       (INSN_OP(3) | INSN_OP3(0x15))
276
#define STHA       (INSN_OP(3) | INSN_OP3(0x16))
277
#define STWA       (INSN_OP(3) | INSN_OP3(0x14))
278
#define STXA       (INSN_OP(3) | INSN_OP3(0x1e))
279

    
280
#ifndef ASI_PRIMARY_LITTLE
281
#define ASI_PRIMARY_LITTLE 0x88
282
#endif
283

    
284
static inline void tcg_out_arith(TCGContext *s, int rd, int rs1, int rs2,
285
                                 int op)
286
{
287
    tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
288
              INSN_RS2(rs2));
289
}
290

    
291
static inline void tcg_out_arithi(TCGContext *s, int rd, int rs1,
292
                                  uint32_t offset, int op)
293
{
294
    tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
295
              INSN_IMM13(offset));
296
}
297

    
298
static void tcg_out_arithc(TCGContext *s, int rd, int rs1,
299
                           int val2, int val2const, int op)
300
{
301
    tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1)
302
              | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2)));
303
}
304

    
305
static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
306
{
307
    tcg_out_arith(s, ret, arg, TCG_REG_G0, ARITH_OR);
308
}
309

    
310
static inline void tcg_out_sethi(TCGContext *s, int ret, uint32_t arg)
311
{
312
    tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
313
}
314

    
315
static inline void tcg_out_movi_imm13(TCGContext *s, int ret, uint32_t arg)
316
{
317
    tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR);
318
}
319

    
320
static inline void tcg_out_movi_imm32(TCGContext *s, int ret, uint32_t arg)
321
{
322
    if (check_fit_tl(arg, 13))
323
        tcg_out_movi_imm13(s, ret, arg);
324
    else {
325
        tcg_out_sethi(s, ret, arg);
326
        if (arg & 0x3ff)
327
            tcg_out_arithi(s, ret, ret, arg & 0x3ff, ARITH_OR);
328
    }
329
}
330

    
331
static inline void tcg_out_movi(TCGContext *s, TCGType type,
332
                                int ret, tcg_target_long arg)
333
{
334
    /* All 32-bit constants, as well as 64-bit constants with
335
       no high bits set go through movi_imm32.  */
336
    if (TCG_TARGET_REG_BITS == 32
337
        || type == TCG_TYPE_I32
338
        || (arg & ~(tcg_target_long)0xffffffff) == 0) {
339
        tcg_out_movi_imm32(s, ret, arg);
340
    } else if (check_fit_tl(arg, 13)) {
341
        /* A 13-bit constant sign-extended to 64-bits.  */
342
        tcg_out_movi_imm13(s, ret, arg);
343
    } else if (check_fit_tl(arg, 32)) {
344
        /* A 32-bit constant sign-extended to 64-bits.  */
345
        tcg_out_sethi(s, ret, ~arg);
346
        tcg_out_arithi(s, ret, ret, (arg & 0x3ff) | -0x400, ARITH_XOR);
347
    } else {
348
        tcg_out_movi_imm32(s, TCG_REG_I4, arg >> (TCG_TARGET_REG_BITS / 2));
349
        tcg_out_arithi(s, TCG_REG_I4, TCG_REG_I4, 32, SHIFT_SLLX);
350
        tcg_out_movi_imm32(s, ret, arg);
351
        tcg_out_arith(s, ret, ret, TCG_REG_I4, ARITH_OR);
352
    }
353
}
354

    
355
static inline void tcg_out_ld_raw(TCGContext *s, int ret,
356
                                  tcg_target_long arg)
357
{
358
    tcg_out_sethi(s, ret, arg);
359
    tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
360
              INSN_IMM13(arg & 0x3ff));
361
}
362

    
363
static inline void tcg_out_ld_ptr(TCGContext *s, int ret,
364
                                  tcg_target_long arg)
365
{
366
    if (!check_fit_tl(arg, 10))
367
        tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ffULL);
368
    if (TCG_TARGET_REG_BITS == 64) {
369
        tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |
370
                  INSN_IMM13(arg & 0x3ff));
371
    } else {
372
        tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
373
                  INSN_IMM13(arg & 0x3ff));
374
    }
375
}
376

    
377
static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset, int op)
378
{
379
    if (check_fit_tl(offset, 13))
380
        tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
381
                  INSN_IMM13(offset));
382
    else {
383
        tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
384
        tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
385
                  INSN_RS2(addr));
386
    }
387
}
388

    
389
static inline void tcg_out_ldst_asi(TCGContext *s, int ret, int addr,
390
                                    int offset, int op, int asi)
391
{
392
    tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, offset);
393
    tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
394
              INSN_ASI(asi) | INSN_RS2(addr));
395
}
396

    
397
static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
398
                              int arg1, tcg_target_long arg2)
399
{
400
    if (type == TCG_TYPE_I32)
401
        tcg_out_ldst(s, ret, arg1, arg2, LDUW);
402
    else
403
        tcg_out_ldst(s, ret, arg1, arg2, LDX);
404
}
405

    
406
static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
407
                              int arg1, tcg_target_long arg2)
408
{
409
    if (type == TCG_TYPE_I32)
410
        tcg_out_ldst(s, arg, arg1, arg2, STW);
411
    else
412
        tcg_out_ldst(s, arg, arg1, arg2, STX);
413
}
414

    
415
static inline void tcg_out_sety(TCGContext *s, int rs)
416
{
417
    tcg_out32(s, WRY | INSN_RS1(TCG_REG_G0) | INSN_RS2(rs));
418
}
419

    
420
static inline void tcg_out_rdy(TCGContext *s, int rd)
421
{
422
    tcg_out32(s, RDY | INSN_RD(rd));
423
}
424

    
425
static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
426
{
427
    if (val != 0) {
428
        if (check_fit_tl(val, 13))
429
            tcg_out_arithi(s, reg, reg, val, ARITH_ADD);
430
        else {
431
            tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I5, val);
432
            tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_ADD);
433
        }
434
    }
435
}
436

    
437
static inline void tcg_out_andi(TCGContext *s, int reg, tcg_target_long val)
438
{
439
    if (val != 0) {
440
        if (check_fit_tl(val, 13))
441
            tcg_out_arithi(s, reg, reg, val, ARITH_AND);
442
        else {
443
            tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, val);
444
            tcg_out_arith(s, reg, reg, TCG_REG_I5, ARITH_AND);
445
        }
446
    }
447
}
448

    
449
static void tcg_out_div32(TCGContext *s, int rd, int rs1,
450
                          int val2, int val2const, int uns)
451
{
452
    /* Load Y with the sign/zero extension of RS1 to 64-bits.  */
453
    if (uns) {
454
        tcg_out_sety(s, TCG_REG_G0);
455
    } else {
456
        tcg_out_arithi(s, TCG_REG_I5, rs1, 31, SHIFT_SRA);
457
        tcg_out_sety(s, TCG_REG_I5);
458
    }
459

    
460
    tcg_out_arithc(s, rd, rs1, val2, val2const,
461
                   uns ? ARITH_UDIV : ARITH_SDIV);
462
}
463

    
464
static inline void tcg_out_nop(TCGContext *s)
465
{
466
    tcg_out_sethi(s, TCG_REG_G0, 0);
467
}
468

    
469
static void tcg_out_branch_i32(TCGContext *s, int opc, int label_index)
470
{
471
    int32_t val;
472
    TCGLabel *l = &s->labels[label_index];
473

    
474
    if (l->has_value) {
475
        val = l->u.value - (tcg_target_long)s->code_ptr;
476
        tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2)
477
                      | INSN_OFF22(l->u.value - (unsigned long)s->code_ptr)));
478
    } else {
479
        tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP22, label_index, 0);
480
        tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x2) | 0));
481
    }
482
}
483

    
484
#if TCG_TARGET_REG_BITS == 64
485
static void tcg_out_branch_i64(TCGContext *s, int opc, int label_index)
486
{
487
    int32_t val;
488
    TCGLabel *l = &s->labels[label_index];
489

    
490
    if (l->has_value) {
491
        val = l->u.value - (tcg_target_long)s->code_ptr;
492
        tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
493
                      (0x5 << 19) |
494
                      INSN_OFF19(l->u.value - (unsigned long)s->code_ptr)));
495
    } else {
496
        tcg_out_reloc(s, s->code_ptr, R_SPARC_WDISP19, label_index, 0);
497
        tcg_out32(s, (INSN_OP(0) | INSN_COND(opc, 0) | INSN_OP2(0x1) |
498
                      (0x5 << 19) | 0));
499
    }
500
}
501
#endif
502

    
503
static const uint8_t tcg_cond_to_bcond[10] = {
504
    [TCG_COND_EQ] = COND_E,
505
    [TCG_COND_NE] = COND_NE,
506
    [TCG_COND_LT] = COND_L,
507
    [TCG_COND_GE] = COND_GE,
508
    [TCG_COND_LE] = COND_LE,
509
    [TCG_COND_GT] = COND_G,
510
    [TCG_COND_LTU] = COND_CS,
511
    [TCG_COND_GEU] = COND_CC,
512
    [TCG_COND_LEU] = COND_LEU,
513
    [TCG_COND_GTU] = COND_GU,
514
};
515

    
516
static void tcg_out_cmp(TCGContext *s, TCGArg c1, TCGArg c2, int c2const)
517
{
518
    tcg_out_arithc(s, TCG_REG_G0, c1, c2, c2const, ARITH_SUBCC);
519
}
520

    
521
static void tcg_out_brcond_i32(TCGContext *s, int cond,
522
                               TCGArg arg1, TCGArg arg2, int const_arg2,
523
                               int label_index)
524
{
525
    tcg_out_cmp(s, arg1, arg2, const_arg2);
526
    tcg_out_branch_i32(s, tcg_cond_to_bcond[cond], label_index);
527
    tcg_out_nop(s);
528
}
529

    
530
#if TCG_TARGET_REG_BITS == 64
531
static void tcg_out_brcond_i64(TCGContext *s, int cond,
532
                               TCGArg arg1, TCGArg arg2, int const_arg2,
533
                               int label_index)
534
{
535
    tcg_out_cmp(s, arg1, arg2, const_arg2);
536
    tcg_out_branch_i64(s, tcg_cond_to_bcond[cond], label_index);
537
    tcg_out_nop(s);
538
}
539
#else
540
static void tcg_out_brcond2_i32(TCGContext *s, int cond,
541
                                TCGArg al, TCGArg ah,
542
                                TCGArg bl, int blconst,
543
                                TCGArg bh, int bhconst, int label_dest)
544
{
545
    int cc, label_next = gen_new_label();
546

    
547
    tcg_out_cmp(s, ah, bh, bhconst);
548

    
549
    /* Note that we fill one of the delay slots with the second compare.  */
550
    switch (cond) {
551
    case TCG_COND_EQ:
552
        cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
553
        tcg_out_branch_i32(s, cc, label_next);
554
        tcg_out_cmp(s, al, bl, blconst);
555
        cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_EQ], 0);
556
        tcg_out_branch_i32(s, cc, label_dest);
557
        break;
558

    
559
    case TCG_COND_NE:
560
        cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
561
        tcg_out_branch_i32(s, cc, label_dest);
562
        tcg_out_cmp(s, al, bl, blconst);
563
        tcg_out_branch_i32(s, cc, label_dest);
564
        break;
565

    
566
    default:
567
        /* ??? One could fairly easily special-case 64-bit unsigned
568
           compares against 32-bit zero-extended constants.  For instance,
569
           we know that (unsigned)AH < 0 is false and need not emit it.
570
           Similarly, (unsigned)AH > 0 being true implies AH != 0, so the
571
           second branch will never be taken.  */
572
        cc = INSN_COND(tcg_cond_to_bcond[cond], 0);
573
        tcg_out_branch_i32(s, cc, label_dest);
574
        tcg_out_nop(s);
575
        cc = INSN_COND(tcg_cond_to_bcond[TCG_COND_NE], 0);
576
        tcg_out_branch_i32(s, cc, label_next);
577
        tcg_out_cmp(s, al, bl, blconst);
578
        cc = INSN_COND(tcg_cond_to_bcond[tcg_unsigned_cond(cond)], 0);
579
        tcg_out_branch_i32(s, cc, label_dest);
580
        break;
581
    }
582
    tcg_out_nop(s);
583

    
584
    tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr);
585
}
586
#endif
587

    
588
static void tcg_out_setcond_i32(TCGContext *s, int cond, TCGArg ret,
589
                                TCGArg c1, TCGArg c2, int c2const)
590
{
591
    TCGArg t;
592

    
593
    /* For 32-bit comparisons, we can play games with ADDX/SUBX.  */
594
    switch (cond) {
595
    case TCG_COND_EQ:
596
    case TCG_COND_NE:
597
        if (c2 != 0) {
598
            tcg_out_arithc(s, ret, c1, c2, c2const, ARITH_XOR);
599
        }
600
        c1 = TCG_REG_G0, c2 = ret, c2const = 0;
601
        cond = (cond == TCG_COND_EQ ? TCG_COND_LEU : TCG_COND_LTU);
602
        break;
603

    
604
    case TCG_COND_GTU:
605
    case TCG_COND_GEU:
606
        if (c2const && c2 != 0) {
607
            tcg_out_movi_imm13(s, TCG_REG_I5, c2);
608
            c2 = TCG_REG_I5;
609
        }
610
        t = c1, c1 = c2, c2 = t, c2const = 0;
611
        cond = tcg_swap_cond(cond);
612
        break;
613

    
614
    case TCG_COND_LTU:
615
    case TCG_COND_LEU:
616
        break;
617

    
618
    default:
619
        tcg_out_cmp(s, c1, c2, c2const);
620
#if defined(__sparc_v9__) || defined(__sparc_v8plus__)
621
        tcg_out_movi_imm13(s, ret, 0);
622
        tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
623
                   | INSN_RS1(tcg_cond_to_bcond[cond])
624
                   | MOVCC_ICC | INSN_IMM11(1));
625
#else
626
        t = gen_new_label();
627
        tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), t);
628
        tcg_out_movi_imm13(s, ret, 1);
629
        tcg_out_movi_imm13(s, ret, 0);
630
        tcg_out_label(s, t, (tcg_target_long)s->code_ptr);
631
#endif
632
        return;
633
    }
634

    
635
    tcg_out_cmp(s, c1, c2, c2const);
636
    if (cond == TCG_COND_LTU) {
637
        tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDX);
638
    } else {
639
        tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBX);
640
    }
641
}
642

    
643
#if TCG_TARGET_REG_BITS == 64
644
static void tcg_out_setcond_i64(TCGContext *s, int cond, TCGArg ret,
645
                                TCGArg c1, TCGArg c2, int c2const)
646
{
647
    tcg_out_cmp(s, c1, c2, c2const);
648
    tcg_out_movi_imm13(s, ret, 0);
649
    tcg_out32 (s, ARITH_MOVCC | INSN_RD(ret)
650
               | INSN_RS1(tcg_cond_to_bcond[cond])
651
               | MOVCC_XCC | INSN_IMM11(1));
652
}
653
#else
654
static void tcg_out_setcond2_i32(TCGContext *s, int cond, TCGArg ret,
655
                                 TCGArg al, TCGArg ah,
656
                                 TCGArg bl, int blconst,
657
                                 TCGArg bh, int bhconst)
658
{
659
    int lab;
660

    
661
    switch (cond) {
662
    case TCG_COND_EQ:
663
        tcg_out_setcond_i32(s, TCG_COND_EQ, TCG_REG_I5, al, bl, blconst);
664
        tcg_out_setcond_i32(s, TCG_COND_EQ, ret, ah, bh, bhconst);
665
        tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_AND);
666
        break;
667

    
668
    case TCG_COND_NE:
669
        tcg_out_setcond_i32(s, TCG_COND_NE, TCG_REG_I5, al, al, blconst);
670
        tcg_out_setcond_i32(s, TCG_COND_NE, ret, ah, bh, bhconst);
671
        tcg_out_arith(s, ret, ret, TCG_REG_I5, ARITH_OR);
672
        break;
673

    
674
    default:
675
        lab = gen_new_label();
676

    
677
        tcg_out_cmp(s, ah, bh, bhconst);
678
        tcg_out_branch_i32(s, INSN_COND(tcg_cond_to_bcond[cond], 1), lab);
679
        tcg_out_movi_imm13(s, ret, 1);
680
        tcg_out_branch_i32(s, INSN_COND(COND_NE, 1), lab);
681
        tcg_out_movi_imm13(s, ret, 0);
682

    
683
        tcg_out_setcond_i32(s, tcg_unsigned_cond(cond), ret, al, bl, blconst);
684

    
685
        tcg_out_label(s, lab, (tcg_target_long)s->code_ptr);
686
        break;
687
    }
688
}
689
#endif
690

    
691
/* Generate global QEMU prologue and epilogue code */
692
void tcg_target_qemu_prologue(TCGContext *s)
693
{
694
    tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
695
              INSN_IMM13(-TCG_TARGET_STACK_MINFRAME));
696
    tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I0) |
697
              INSN_RS2(TCG_REG_G0));
698
    tcg_out_nop(s);
699
}
700

    
701
#if defined(CONFIG_SOFTMMU)
702

    
703
#include "../../softmmu_defs.h"
704

    
705
static const void * const qemu_ld_helpers[4] = {
706
    __ldb_mmu,
707
    __ldw_mmu,
708
    __ldl_mmu,
709
    __ldq_mmu,
710
};
711

    
712
static const void * const qemu_st_helpers[4] = {
713
    __stb_mmu,
714
    __stw_mmu,
715
    __stl_mmu,
716
    __stq_mmu,
717
};
718
#endif
719

    
720
#if TARGET_LONG_BITS == 32
721
#define TARGET_LD_OP LDUW
722
#else
723
#define TARGET_LD_OP LDX
724
#endif
725

    
726
#if TARGET_PHYS_ADDR_BITS == 32
727
#define TARGET_ADDEND_LD_OP LDUW
728
#else
729
#define TARGET_ADDEND_LD_OP LDX
730
#endif
731

    
732
#ifdef __arch64__
733
#define HOST_LD_OP LDX
734
#define HOST_ST_OP STX
735
#define HOST_SLL_OP SHIFT_SLLX
736
#define HOST_SRA_OP SHIFT_SRAX
737
#else
738
#define HOST_LD_OP LDUW
739
#define HOST_ST_OP STW
740
#define HOST_SLL_OP SHIFT_SLL
741
#define HOST_SRA_OP SHIFT_SRA
742
#endif
743

    
744
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
745
                            int opc)
746
{
747
    int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
748
#if defined(CONFIG_SOFTMMU)
749
    uint32_t *label1_ptr, *label2_ptr;
750
#endif
751

    
752
    data_reg = *args++;
753
    addr_reg = *args++;
754
    mem_index = *args;
755
    s_bits = opc & 3;
756

    
757
    arg0 = TCG_REG_O0;
758
    arg1 = TCG_REG_O1;
759
    arg2 = TCG_REG_O2;
760

    
761
#if defined(CONFIG_SOFTMMU)
762
    /* srl addr_reg, x, arg1 */
763
    tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
764
                   SHIFT_SRL);
765
    /* and addr_reg, x, arg0 */
766
    tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
767
                   ARITH_AND);
768

    
769
    /* and arg1, x, arg1 */
770
    tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
771

    
772
    /* add arg1, x, arg1 */
773
    tcg_out_addi(s, arg1, offsetof(CPUState,
774
                                   tlb_table[mem_index][0].addr_read));
775

    
776
    /* add env, arg1, arg1 */
777
    tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
778

    
779
    /* ld [arg1], arg2 */
780
    tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
781
              INSN_RS2(TCG_REG_G0));
782

    
783
    /* subcc arg0, arg2, %g0 */
784
    tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC);
785

    
786
    /* will become:
787
       be label1
788
        or
789
       be,pt %xcc label1 */
790
    label1_ptr = (uint32_t *)s->code_ptr;
791
    tcg_out32(s, 0);
792

    
793
    /* mov (delay slot) */
794
    tcg_out_mov(s, arg0, addr_reg);
795

    
796
    /* mov */
797
    tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index);
798

    
799
    /* XXX: move that code at the end of the TB */
800
    /* qemu_ld_helper[s_bits](arg0, arg1) */
801
    tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_ld_helpers[s_bits]
802
                           - (tcg_target_ulong)s->code_ptr) >> 2)
803
                         & 0x3fffffff));
804
    /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
805
       global registers */
806
    // delay slot
807
    tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
808
                 TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
809
                 sizeof(long), HOST_ST_OP);
810
    tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
811
                 TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
812
                 sizeof(long), HOST_LD_OP);
813

    
814
    /* data_reg = sign_extend(arg0) */
815
    switch(opc) {
816
    case 0 | 4:
817
        /* sll arg0, 24/56, data_reg */
818
        tcg_out_arithi(s, data_reg, arg0, (int)sizeof(tcg_target_long) * 8 - 8,
819
                       HOST_SLL_OP);
820
        /* sra data_reg, 24/56, data_reg */
821
        tcg_out_arithi(s, data_reg, data_reg,
822
                       (int)sizeof(tcg_target_long) * 8 - 8, HOST_SRA_OP);
823
        break;
824
    case 1 | 4:
825
        /* sll arg0, 16/48, data_reg */
826
        tcg_out_arithi(s, data_reg, arg0,
827
                       (int)sizeof(tcg_target_long) * 8 - 16, HOST_SLL_OP);
828
        /* sra data_reg, 16/48, data_reg */
829
        tcg_out_arithi(s, data_reg, data_reg,
830
                       (int)sizeof(tcg_target_long) * 8 - 16, HOST_SRA_OP);
831
        break;
832
    case 2 | 4:
833
        /* sll arg0, 32, data_reg */
834
        tcg_out_arithi(s, data_reg, arg0, 32, HOST_SLL_OP);
835
        /* sra data_reg, 32, data_reg */
836
        tcg_out_arithi(s, data_reg, data_reg, 32, HOST_SRA_OP);
837
        break;
838
    case 0:
839
    case 1:
840
    case 2:
841
    case 3:
842
    default:
843
        /* mov */
844
        tcg_out_mov(s, data_reg, arg0);
845
        break;
846
    }
847

    
848
    /* will become:
849
       ba label2 */
850
    label2_ptr = (uint32_t *)s->code_ptr;
851
    tcg_out32(s, 0);
852

    
853
    /* nop (delay slot */
854
    tcg_out_nop(s);
855

    
856
    /* label1: */
857
#if TARGET_LONG_BITS == 32
858
    /* be label1 */
859
    *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
860
                   INSN_OFF22((unsigned long)s->code_ptr -
861
                              (unsigned long)label1_ptr));
862
#else
863
    /* be,pt %xcc label1 */
864
    *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) |
865
                   (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr -
866
                              (unsigned long)label1_ptr));
867
#endif
868

    
869
    /* ld [arg1 + x], arg1 */
870
    tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) -
871
                 offsetof(CPUTLBEntry, addr_read), TARGET_ADDEND_LD_OP);
872

    
873
#if TARGET_LONG_BITS == 32
874
    /* and addr_reg, x, arg0 */
875
    tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
876
    tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND);
877
    /* add arg0, arg1, arg0 */
878
    tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD);
879
#else
880
    /* add addr_reg, arg1, arg0 */
881
    tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD);
882
#endif
883

    
884
#else
885
    arg0 = addr_reg;
886
#endif
887

    
888
    switch(opc) {
889
    case 0:
890
        /* ldub [arg0], data_reg */
891
        tcg_out_ldst(s, data_reg, arg0, 0, LDUB);
892
        break;
893
    case 0 | 4:
894
        /* ldsb [arg0], data_reg */
895
        tcg_out_ldst(s, data_reg, arg0, 0, LDSB);
896
        break;
897
    case 1:
898
#ifdef TARGET_WORDS_BIGENDIAN
899
        /* lduh [arg0], data_reg */
900
        tcg_out_ldst(s, data_reg, arg0, 0, LDUH);
901
#else
902
        /* lduha [arg0] ASI_PRIMARY_LITTLE, data_reg */
903
        tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUHA, ASI_PRIMARY_LITTLE);
904
#endif
905
        break;
906
    case 1 | 4:
907
#ifdef TARGET_WORDS_BIGENDIAN
908
        /* ldsh [arg0], data_reg */
909
        tcg_out_ldst(s, data_reg, arg0, 0, LDSH);
910
#else
911
        /* ldsha [arg0] ASI_PRIMARY_LITTLE, data_reg */
912
        tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSHA, ASI_PRIMARY_LITTLE);
913
#endif
914
        break;
915
    case 2:
916
#ifdef TARGET_WORDS_BIGENDIAN
917
        /* lduw [arg0], data_reg */
918
        tcg_out_ldst(s, data_reg, arg0, 0, LDUW);
919
#else
920
        /* lduwa [arg0] ASI_PRIMARY_LITTLE, data_reg */
921
        tcg_out_ldst_asi(s, data_reg, arg0, 0, LDUWA, ASI_PRIMARY_LITTLE);
922
#endif
923
        break;
924
    case 2 | 4:
925
#ifdef TARGET_WORDS_BIGENDIAN
926
        /* ldsw [arg0], data_reg */
927
        tcg_out_ldst(s, data_reg, arg0, 0, LDSW);
928
#else
929
        /* ldswa [arg0] ASI_PRIMARY_LITTLE, data_reg */
930
        tcg_out_ldst_asi(s, data_reg, arg0, 0, LDSWA, ASI_PRIMARY_LITTLE);
931
#endif
932
        break;
933
    case 3:
934
#ifdef TARGET_WORDS_BIGENDIAN
935
        /* ldx [arg0], data_reg */
936
        tcg_out_ldst(s, data_reg, arg0, 0, LDX);
937
#else
938
        /* ldxa [arg0] ASI_PRIMARY_LITTLE, data_reg */
939
        tcg_out_ldst_asi(s, data_reg, arg0, 0, LDXA, ASI_PRIMARY_LITTLE);
940
#endif
941
        break;
942
    default:
943
        tcg_abort();
944
    }
945

    
946
#if defined(CONFIG_SOFTMMU)
947
    /* label2: */
948
    *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
949
                   INSN_OFF22((unsigned long)s->code_ptr -
950
                              (unsigned long)label2_ptr));
951
#endif
952
}
953

    
954
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
955
                            int opc)
956
{
957
    int addr_reg, data_reg, arg0, arg1, arg2, mem_index, s_bits;
958
#if defined(CONFIG_SOFTMMU)
959
    uint32_t *label1_ptr, *label2_ptr;
960
#endif
961

    
962
    data_reg = *args++;
963
    addr_reg = *args++;
964
    mem_index = *args;
965

    
966
    s_bits = opc;
967

    
968
    arg0 = TCG_REG_O0;
969
    arg1 = TCG_REG_O1;
970
    arg2 = TCG_REG_O2;
971

    
972
#if defined(CONFIG_SOFTMMU)
973
    /* srl addr_reg, x, arg1 */
974
    tcg_out_arithi(s, arg1, addr_reg, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS,
975
                   SHIFT_SRL);
976

    
977
    /* and addr_reg, x, arg0 */
978
    tcg_out_arithi(s, arg0, addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
979
                   ARITH_AND);
980

    
981
    /* and arg1, x, arg1 */
982
    tcg_out_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
983

    
984
    /* add arg1, x, arg1 */
985
    tcg_out_addi(s, arg1, offsetof(CPUState,
986
                                   tlb_table[mem_index][0].addr_write));
987

    
988
    /* add env, arg1, arg1 */
989
    tcg_out_arith(s, arg1, TCG_AREG0, arg1, ARITH_ADD);
990

    
991
    /* ld [arg1], arg2 */
992
    tcg_out32(s, TARGET_LD_OP | INSN_RD(arg2) | INSN_RS1(arg1) |
993
              INSN_RS2(TCG_REG_G0));
994

    
995
    /* subcc arg0, arg2, %g0 */
996
    tcg_out_arith(s, TCG_REG_G0, arg0, arg2, ARITH_SUBCC);
997

    
998
    /* will become:
999
       be label1
1000
        or
1001
       be,pt %xcc label1 */
1002
    label1_ptr = (uint32_t *)s->code_ptr;
1003
    tcg_out32(s, 0);
1004

    
1005
    /* mov (delay slot) */
1006
    tcg_out_mov(s, arg0, addr_reg);
1007

    
1008
    /* mov */
1009
    tcg_out_mov(s, arg1, data_reg);
1010

    
1011
    /* mov */
1012
    tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index);
1013

    
1014
    /* XXX: move that code at the end of the TB */
1015
    /* qemu_st_helper[s_bits](arg0, arg1, arg2) */
1016
    tcg_out32(s, CALL | ((((tcg_target_ulong)qemu_st_helpers[s_bits]
1017
                           - (tcg_target_ulong)s->code_ptr) >> 2)
1018
                         & 0x3fffffff));
1019
    /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
1020
       global registers */
1021
    // delay slot
1022
    tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1023
                 TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1024
                 sizeof(long), HOST_ST_OP);
1025
    tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1026
                 TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1027
                 sizeof(long), HOST_LD_OP);
1028

    
1029
    /* will become:
1030
       ba label2 */
1031
    label2_ptr = (uint32_t *)s->code_ptr;
1032
    tcg_out32(s, 0);
1033

    
1034
    /* nop (delay slot) */
1035
    tcg_out_nop(s);
1036

    
1037
#if TARGET_LONG_BITS == 32
1038
    /* be label1 */
1039
    *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x2) |
1040
                   INSN_OFF22((unsigned long)s->code_ptr -
1041
                              (unsigned long)label1_ptr));
1042
#else
1043
    /* be,pt %xcc label1 */
1044
    *label1_ptr = (INSN_OP(0) | INSN_COND(COND_E, 0) | INSN_OP2(0x1) |
1045
                   (0x5 << 19) | INSN_OFF19((unsigned long)s->code_ptr -
1046
                              (unsigned long)label1_ptr));
1047
#endif
1048

    
1049
    /* ld [arg1 + x], arg1 */
1050
    tcg_out_ldst(s, arg1, arg1, offsetof(CPUTLBEntry, addend) -
1051
                 offsetof(CPUTLBEntry, addr_write), TARGET_ADDEND_LD_OP);
1052

    
1053
#if TARGET_LONG_BITS == 32
1054
    /* and addr_reg, x, arg0 */
1055
    tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_I5, 0xffffffff);
1056
    tcg_out_arith(s, arg0, addr_reg, TCG_REG_I5, ARITH_AND);
1057
    /* add arg0, arg1, arg0 */
1058
    tcg_out_arith(s, arg0, arg0, arg1, ARITH_ADD);
1059
#else
1060
    /* add addr_reg, arg1, arg0 */
1061
    tcg_out_arith(s, arg0, addr_reg, arg1, ARITH_ADD);
1062
#endif
1063

    
1064
#else
1065
    arg0 = addr_reg;
1066
#endif
1067

    
1068
    switch(opc) {
1069
    case 0:
1070
        /* stb data_reg, [arg0] */
1071
        tcg_out_ldst(s, data_reg, arg0, 0, STB);
1072
        break;
1073
    case 1:
1074
#ifdef TARGET_WORDS_BIGENDIAN
1075
        /* sth data_reg, [arg0] */
1076
        tcg_out_ldst(s, data_reg, arg0, 0, STH);
1077
#else
1078
        /* stha data_reg, [arg0] ASI_PRIMARY_LITTLE */
1079
        tcg_out_ldst_asi(s, data_reg, arg0, 0, STHA, ASI_PRIMARY_LITTLE);
1080
#endif
1081
        break;
1082
    case 2:
1083
#ifdef TARGET_WORDS_BIGENDIAN
1084
        /* stw data_reg, [arg0] */
1085
        tcg_out_ldst(s, data_reg, arg0, 0, STW);
1086
#else
1087
        /* stwa data_reg, [arg0] ASI_PRIMARY_LITTLE */
1088
        tcg_out_ldst_asi(s, data_reg, arg0, 0, STWA, ASI_PRIMARY_LITTLE);
1089
#endif
1090
        break;
1091
    case 3:
1092
#ifdef TARGET_WORDS_BIGENDIAN
1093
        /* stx data_reg, [arg0] */
1094
        tcg_out_ldst(s, data_reg, arg0, 0, STX);
1095
#else
1096
        /* stxa data_reg, [arg0] ASI_PRIMARY_LITTLE */
1097
        tcg_out_ldst_asi(s, data_reg, arg0, 0, STXA, ASI_PRIMARY_LITTLE);
1098
#endif
1099
        break;
1100
    default:
1101
        tcg_abort();
1102
    }
1103

    
1104
#if defined(CONFIG_SOFTMMU)
1105
    /* label2: */
1106
    *label2_ptr = (INSN_OP(0) | INSN_COND(COND_A, 0) | INSN_OP2(0x2) |
1107
                   INSN_OFF22((unsigned long)s->code_ptr -
1108
                              (unsigned long)label2_ptr));
1109
#endif
1110
}
1111

    
1112
static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
1113
                              const int *const_args)
1114
{
1115
    int c;
1116

    
1117
    switch (opc) {
1118
    case INDEX_op_exit_tb:
1119
        tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, args[0]);
1120
        tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I7) |
1121
                  INSN_IMM13(8));
1122
        tcg_out32(s, RESTORE | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_G0) |
1123
                      INSN_RS2(TCG_REG_G0));
1124
        break;
1125
    case INDEX_op_goto_tb:
1126
        if (s->tb_jmp_offset) {
1127
            /* direct jump method */
1128
            tcg_out_sethi(s, TCG_REG_I5, args[0] & 0xffffe000);
1129
            tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
1130
                      INSN_IMM13((args[0] & 0x1fff)));
1131
            s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1132
        } else {
1133
            /* indirect jump method */
1134
            tcg_out_ld_ptr(s, TCG_REG_I5, (tcg_target_long)(s->tb_next + args[0]));
1135
            tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I5) |
1136
                      INSN_RS2(TCG_REG_G0));
1137
        }
1138
        tcg_out_nop(s);
1139
        s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1140
        break;
1141
    case INDEX_op_call:
1142
        if (const_args[0])
1143
            tcg_out32(s, CALL | ((((tcg_target_ulong)args[0]
1144
                                   - (tcg_target_ulong)s->code_ptr) >> 2)
1145
                                 & 0x3fffffff));
1146
        else {
1147
            tcg_out_ld_ptr(s, TCG_REG_I5,
1148
                           (tcg_target_long)(s->tb_next + args[0]));
1149
            tcg_out32(s, JMPL | INSN_RD(TCG_REG_O7) | INSN_RS1(TCG_REG_I5) |
1150
                      INSN_RS2(TCG_REG_G0));
1151
        }
1152
        /* Store AREG0 in stack to avoid ugly glibc bugs that mangle
1153
           global registers */
1154
        // delay slot
1155
        tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1156
                     TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1157
                     sizeof(long), HOST_ST_OP);
1158
        tcg_out_ldst(s, TCG_AREG0, TCG_REG_CALL_STACK,
1159
                     TCG_TARGET_CALL_STACK_OFFSET - TCG_STATIC_CALL_ARGS_SIZE -
1160
                     sizeof(long), HOST_LD_OP);
1161
        break;
1162
    case INDEX_op_jmp:
1163
    case INDEX_op_br:
1164
        tcg_out_branch_i32(s, COND_A, args[0]);
1165
        tcg_out_nop(s);
1166
        break;
1167
    case INDEX_op_movi_i32:
1168
        tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
1169
        break;
1170

    
1171
#if TCG_TARGET_REG_BITS == 64
1172
#define OP_32_64(x)                             \
1173
        glue(glue(case INDEX_op_, x), _i32):    \
1174
        glue(glue(case INDEX_op_, x), _i64)
1175
#else
1176
#define OP_32_64(x)                             \
1177
        glue(glue(case INDEX_op_, x), _i32)
1178
#endif
1179
    OP_32_64(ld8u):
1180
        tcg_out_ldst(s, args[0], args[1], args[2], LDUB);
1181
        break;
1182
    OP_32_64(ld8s):
1183
        tcg_out_ldst(s, args[0], args[1], args[2], LDSB);
1184
        break;
1185
    OP_32_64(ld16u):
1186
        tcg_out_ldst(s, args[0], args[1], args[2], LDUH);
1187
        break;
1188
    OP_32_64(ld16s):
1189
        tcg_out_ldst(s, args[0], args[1], args[2], LDSH);
1190
        break;
1191
    case INDEX_op_ld_i32:
1192
#if TCG_TARGET_REG_BITS == 64
1193
    case INDEX_op_ld32u_i64:
1194
#endif
1195
        tcg_out_ldst(s, args[0], args[1], args[2], LDUW);
1196
        break;
1197
    OP_32_64(st8):
1198
        tcg_out_ldst(s, args[0], args[1], args[2], STB);
1199
        break;
1200
    OP_32_64(st16):
1201
        tcg_out_ldst(s, args[0], args[1], args[2], STH);
1202
        break;
1203
    case INDEX_op_st_i32:
1204
#if TCG_TARGET_REG_BITS == 64
1205
    case INDEX_op_st32_i64:
1206
#endif
1207
        tcg_out_ldst(s, args[0], args[1], args[2], STW);
1208
        break;
1209
    OP_32_64(add):
1210
        c = ARITH_ADD;
1211
        goto gen_arith;
1212
    OP_32_64(sub):
1213
        c = ARITH_SUB;
1214
        goto gen_arith;
1215
    OP_32_64(and):
1216
        c = ARITH_AND;
1217
        goto gen_arith;
1218
    OP_32_64(or):
1219
        c = ARITH_OR;
1220
        goto gen_arith;
1221
    OP_32_64(xor):
1222
        c = ARITH_XOR;
1223
        goto gen_arith;
1224
    case INDEX_op_shl_i32:
1225
        c = SHIFT_SLL;
1226
        goto gen_arith;
1227
    case INDEX_op_shr_i32:
1228
        c = SHIFT_SRL;
1229
        goto gen_arith;
1230
    case INDEX_op_sar_i32:
1231
        c = SHIFT_SRA;
1232
        goto gen_arith;
1233
    case INDEX_op_mul_i32:
1234
        c = ARITH_UMUL;
1235
        goto gen_arith;
1236

    
1237
    case INDEX_op_div_i32:
1238
        tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 0);
1239
        break;
1240
    case INDEX_op_divu_i32:
1241
        tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 1);
1242
        break;
1243

    
1244
    case INDEX_op_rem_i32:
1245
    case INDEX_op_remu_i32:
1246
        tcg_out_div32(s, TCG_REG_I5, args[1], args[2], const_args[2],
1247
                      opc == INDEX_op_remu_i32);
1248
        tcg_out_arithc(s, TCG_REG_I5, TCG_REG_I5, args[2], const_args[2],
1249
                       ARITH_UMUL);
1250
        tcg_out_arith(s, args[0], args[1], TCG_REG_I5, ARITH_SUB);
1251
        break;
1252

    
1253
    case INDEX_op_brcond_i32:
1254
        tcg_out_brcond_i32(s, args[2], args[0], args[1], const_args[1],
1255
                           args[3]);
1256
        break;
1257
    case INDEX_op_setcond_i32:
1258
        tcg_out_setcond_i32(s, args[3], args[0], args[1],
1259
                            args[2], const_args[2]);
1260
        break;
1261

    
1262
#if TCG_TARGET_REG_BITS == 32
1263
    case INDEX_op_brcond2_i32:
1264
        tcg_out_brcond2_i32(s, args[4], args[0], args[1],
1265
                            args[2], const_args[2],
1266
                            args[3], const_args[3], args[5]);
1267
        break;
1268
    case INDEX_op_setcond2_i32:
1269
        tcg_out_setcond2_i32(s, args[5], args[0], args[1], args[2],
1270
                             args[3], const_args[3],
1271
                             args[4], const_args[4]);
1272
        break;
1273
    case INDEX_op_add2_i32:
1274
        tcg_out_arithc(s, args[0], args[2], args[4], const_args[4],
1275
                       ARITH_ADDCC);
1276
        tcg_out_arithc(s, args[1], args[3], args[5], const_args[5],
1277
                       ARITH_ADDX);
1278
        break;
1279
    case INDEX_op_sub2_i32:
1280
        tcg_out_arithc(s, args[0], args[2], args[4], const_args[4],
1281
                       ARITH_SUBCC);
1282
        tcg_out_arithc(s, args[1], args[3], args[5], const_args[5],
1283
                       ARITH_SUBX);
1284
        break;
1285
    case INDEX_op_mulu2_i32:
1286
        tcg_out_arithc(s, args[0], args[2], args[3], const_args[3],
1287
                       ARITH_UMUL);
1288
        tcg_out_rdy(s, args[1]);
1289
        break;
1290
#endif
1291

    
1292
    case INDEX_op_qemu_ld8u:
1293
        tcg_out_qemu_ld(s, args, 0);
1294
        break;
1295
    case INDEX_op_qemu_ld8s:
1296
        tcg_out_qemu_ld(s, args, 0 | 4);
1297
        break;
1298
    case INDEX_op_qemu_ld16u:
1299
        tcg_out_qemu_ld(s, args, 1);
1300
        break;
1301
    case INDEX_op_qemu_ld16s:
1302
        tcg_out_qemu_ld(s, args, 1 | 4);
1303
        break;
1304
    case INDEX_op_qemu_ld32u:
1305
        tcg_out_qemu_ld(s, args, 2);
1306
        break;
1307
    case INDEX_op_qemu_ld32s:
1308
        tcg_out_qemu_ld(s, args, 2 | 4);
1309
        break;
1310
    case INDEX_op_qemu_st8:
1311
        tcg_out_qemu_st(s, args, 0);
1312
        break;
1313
    case INDEX_op_qemu_st16:
1314
        tcg_out_qemu_st(s, args, 1);
1315
        break;
1316
    case INDEX_op_qemu_st32:
1317
        tcg_out_qemu_st(s, args, 2);
1318
        break;
1319

    
1320
#if TCG_TARGET_REG_BITS == 64
1321
    case INDEX_op_movi_i64:
1322
        tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1323
        break;
1324
    case INDEX_op_ld32s_i64:
1325
        tcg_out_ldst(s, args[0], args[1], args[2], LDSW);
1326
        break;
1327
    case INDEX_op_ld_i64:
1328
        tcg_out_ldst(s, args[0], args[1], args[2], LDX);
1329
        break;
1330
    case INDEX_op_st_i64:
1331
        tcg_out_ldst(s, args[0], args[1], args[2], STX);
1332
        break;
1333
    case INDEX_op_shl_i64:
1334
        c = SHIFT_SLLX;
1335
        goto gen_arith;
1336
    case INDEX_op_shr_i64:
1337
        c = SHIFT_SRLX;
1338
        goto gen_arith;
1339
    case INDEX_op_sar_i64:
1340
        c = SHIFT_SRAX;
1341
        goto gen_arith;
1342
    case INDEX_op_mul_i64:
1343
        c = ARITH_MULX;
1344
        goto gen_arith;
1345
    case INDEX_op_div_i64:
1346
        c = ARITH_SDIVX;
1347
        goto gen_arith;
1348
    case INDEX_op_divu_i64:
1349
        c = ARITH_UDIVX;
1350
        goto gen_arith;
1351
    case INDEX_op_rem_i64:
1352
    case INDEX_op_remu_i64:
1353
        tcg_out_arithc(s, TCG_REG_I5, args[1], args[2], const_args[2],
1354
                       opc == INDEX_op_rem_i64 ? ARITH_SDIVX : ARITH_UDIVX);
1355
        tcg_out_arithc(s, TCG_REG_I5, TCG_REG_I5, args[2], const_args[2],
1356
                       ARITH_MULX);
1357
        tcg_out_arith(s, args[0], args[1], TCG_REG_I5, ARITH_SUB);
1358
        break;
1359
    case INDEX_op_ext32s_i64:
1360
        if (const_args[1]) {
1361
            tcg_out_movi(s, TCG_TYPE_I64, args[0], (int32_t)args[1]);
1362
        } else {
1363
            tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRA);
1364
        }
1365
        break;
1366
    case INDEX_op_ext32u_i64:
1367
        if (const_args[1]) {
1368
            tcg_out_movi_imm32(s, args[0], args[1]);
1369
        } else {
1370
            tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRL);
1371
        }
1372
        break;
1373

    
1374
    case INDEX_op_brcond_i64:
1375
        tcg_out_brcond_i64(s, args[2], args[0], args[1], const_args[1],
1376
                           args[3]);
1377
        break;
1378
    case INDEX_op_setcond_i64:
1379
        tcg_out_setcond_i64(s, args[3], args[0], args[1],
1380
                            args[2], const_args[2]);
1381
        break;
1382

    
1383
    case INDEX_op_qemu_ld64:
1384
        tcg_out_qemu_ld(s, args, 3);
1385
        break;
1386
    case INDEX_op_qemu_st64:
1387
        tcg_out_qemu_st(s, args, 3);
1388
        break;
1389

    
1390
#endif
1391
    gen_arith:
1392
        tcg_out_arithc(s, args[0], args[1], args[2], const_args[2], c);
1393
        break;
1394

    
1395
    default:
1396
        fprintf(stderr, "unknown opcode 0x%x\n", opc);
1397
        tcg_abort();
1398
    }
1399
}
1400

    
1401
static const TCGTargetOpDef sparc_op_defs[] = {
1402
    { INDEX_op_exit_tb, { } },
1403
    { INDEX_op_goto_tb, { } },
1404
    { INDEX_op_call, { "ri" } },
1405
    { INDEX_op_jmp, { "ri" } },
1406
    { INDEX_op_br, { } },
1407

    
1408
    { INDEX_op_mov_i32, { "r", "r" } },
1409
    { INDEX_op_movi_i32, { "r" } },
1410
    { INDEX_op_ld8u_i32, { "r", "r" } },
1411
    { INDEX_op_ld8s_i32, { "r", "r" } },
1412
    { INDEX_op_ld16u_i32, { "r", "r" } },
1413
    { INDEX_op_ld16s_i32, { "r", "r" } },
1414
    { INDEX_op_ld_i32, { "r", "r" } },
1415
    { INDEX_op_st8_i32, { "r", "r" } },
1416
    { INDEX_op_st16_i32, { "r", "r" } },
1417
    { INDEX_op_st_i32, { "r", "r" } },
1418

    
1419
    { INDEX_op_add_i32, { "r", "r", "rJ" } },
1420
    { INDEX_op_mul_i32, { "r", "r", "rJ" } },
1421
    { INDEX_op_div_i32, { "r", "r", "rJ" } },
1422
    { INDEX_op_divu_i32, { "r", "r", "rJ" } },
1423
    { INDEX_op_rem_i32, { "r", "r", "rJ" } },
1424
    { INDEX_op_remu_i32, { "r", "r", "rJ" } },
1425
    { INDEX_op_sub_i32, { "r", "r", "rJ" } },
1426
    { INDEX_op_and_i32, { "r", "r", "rJ" } },
1427
    { INDEX_op_or_i32, { "r", "r", "rJ" } },
1428
    { INDEX_op_xor_i32, { "r", "r", "rJ" } },
1429

    
1430
    { INDEX_op_shl_i32, { "r", "r", "rJ" } },
1431
    { INDEX_op_shr_i32, { "r", "r", "rJ" } },
1432
    { INDEX_op_sar_i32, { "r", "r", "rJ" } },
1433

    
1434
    { INDEX_op_brcond_i32, { "r", "rJ" } },
1435
    { INDEX_op_setcond_i32, { "r", "r", "rJ" } },
1436

    
1437
#if TCG_TARGET_REG_BITS == 32
1438
    { INDEX_op_brcond2_i32, { "r", "r", "rJ", "rJ" } },
1439
    { INDEX_op_setcond2_i32, { "r", "r", "r", "rJ", "rJ" } },
1440
    { INDEX_op_add2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
1441
    { INDEX_op_sub2_i32, { "r", "r", "r", "r", "rJ", "rJ" } },
1442
    { INDEX_op_mulu2_i32, { "r", "r", "r", "rJ" } },
1443
#endif
1444

    
1445
    { INDEX_op_qemu_ld8u, { "r", "L" } },
1446
    { INDEX_op_qemu_ld8s, { "r", "L" } },
1447
    { INDEX_op_qemu_ld16u, { "r", "L" } },
1448
    { INDEX_op_qemu_ld16s, { "r", "L" } },
1449
    { INDEX_op_qemu_ld32u, { "r", "L" } },
1450
    { INDEX_op_qemu_ld32s, { "r", "L" } },
1451

    
1452
    { INDEX_op_qemu_st8, { "L", "L" } },
1453
    { INDEX_op_qemu_st16, { "L", "L" } },
1454
    { INDEX_op_qemu_st32, { "L", "L" } },
1455

    
1456
#if TCG_TARGET_REG_BITS == 64
1457
    { INDEX_op_mov_i64, { "r", "r" } },
1458
    { INDEX_op_movi_i64, { "r" } },
1459
    { INDEX_op_ld8u_i64, { "r", "r" } },
1460
    { INDEX_op_ld8s_i64, { "r", "r" } },
1461
    { INDEX_op_ld16u_i64, { "r", "r" } },
1462
    { INDEX_op_ld16s_i64, { "r", "r" } },
1463
    { INDEX_op_ld32u_i64, { "r", "r" } },
1464
    { INDEX_op_ld32s_i64, { "r", "r" } },
1465
    { INDEX_op_ld_i64, { "r", "r" } },
1466
    { INDEX_op_st8_i64, { "r", "r" } },
1467
    { INDEX_op_st16_i64, { "r", "r" } },
1468
    { INDEX_op_st32_i64, { "r", "r" } },
1469
    { INDEX_op_st_i64, { "r", "r" } },
1470
    { INDEX_op_qemu_ld64, { "L", "L" } },
1471
    { INDEX_op_qemu_st64, { "L", "L" } },
1472

    
1473
    { INDEX_op_add_i64, { "r", "r", "rJ" } },
1474
    { INDEX_op_mul_i64, { "r", "r", "rJ" } },
1475
    { INDEX_op_div_i64, { "r", "r", "rJ" } },
1476
    { INDEX_op_divu_i64, { "r", "r", "rJ" } },
1477
    { INDEX_op_rem_i64, { "r", "r", "rJ" } },
1478
    { INDEX_op_remu_i64, { "r", "r", "rJ" } },
1479
    { INDEX_op_sub_i64, { "r", "r", "rJ" } },
1480
    { INDEX_op_and_i64, { "r", "r", "rJ" } },
1481
    { INDEX_op_or_i64, { "r", "r", "rJ" } },
1482
    { INDEX_op_xor_i64, { "r", "r", "rJ" } },
1483

    
1484
    { INDEX_op_shl_i64, { "r", "r", "rJ" } },
1485
    { INDEX_op_shr_i64, { "r", "r", "rJ" } },
1486
    { INDEX_op_sar_i64, { "r", "r", "rJ" } },
1487
    { INDEX_op_ext32s_i64, { "r", "ri" } },
1488
    { INDEX_op_ext32u_i64, { "r", "ri" } },
1489

    
1490
    { INDEX_op_brcond_i64, { "r", "rJ" } },
1491
    { INDEX_op_setcond_i64, { "r", "r", "rJ" } },
1492
#endif
1493
    { -1 },
1494
};
1495

    
1496
void tcg_target_init(TCGContext *s)
1497
{
1498
    tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1499
#if TCG_TARGET_REG_BITS == 64
1500
    tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1501
#endif
1502
    tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1503
                     (1 << TCG_REG_G1) |
1504
                     (1 << TCG_REG_G2) |
1505
                     (1 << TCG_REG_G3) |
1506
                     (1 << TCG_REG_G4) |
1507
                     (1 << TCG_REG_G5) |
1508
                     (1 << TCG_REG_G6) |
1509
                     (1 << TCG_REG_G7) |
1510
                     (1 << TCG_REG_O0) |
1511
                     (1 << TCG_REG_O1) |
1512
                     (1 << TCG_REG_O2) |
1513
                     (1 << TCG_REG_O3) |
1514
                     (1 << TCG_REG_O4) |
1515
                     (1 << TCG_REG_O5) |
1516
                     (1 << TCG_REG_O7));
1517

    
1518
    tcg_regset_clear(s->reserved_regs);
1519
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_G0);
1520
#if TCG_TARGET_REG_BITS == 64
1521
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_I4); // for internal use
1522
#endif
1523
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_I5); // for internal use
1524
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_I6);
1525
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_I7);
1526
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_O6);
1527
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_O7);
1528
    tcg_add_target_add_op_defs(sparc_op_defs);
1529
}