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1
/*
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 * Copyright (C) 2010 Red Hat, Inc.
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 *
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 * written by Gerd Hoffmann <kraxel@redhat.com>
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 or
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 * (at your option) version 3 of the License.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include "hw.h"
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#include "pci.h"
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#include "qemu-timer.h"
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#include "audiodev.h"
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#include "intel-hda.h"
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#include "intel-hda-defs.h"
26

    
27
/* --------------------------------------------------------------------- */
28
/* hda bus                                                               */
29

    
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static struct BusInfo hda_codec_bus_info = {
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    .name      = "HDA",
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    .size      = sizeof(HDACodecBus),
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    .props     = (Property[]) {
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        DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
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        DEFINE_PROP_END_OF_LIST()
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    }
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};
38

    
39
void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus,
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                        hda_codec_response_func response,
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                        hda_codec_xfer_func xfer)
42
{
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    qbus_create_inplace(&bus->qbus, &hda_codec_bus_info, dev, NULL);
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    bus->response = response;
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    bus->xfer = xfer;
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}
47

    
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static int hda_codec_dev_init(DeviceState *qdev, DeviceInfo *base)
49
{
50
    HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus);
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    HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
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    HDACodecDeviceInfo *info = DO_UPCAST(HDACodecDeviceInfo, qdev, base);
53

    
54
    dev->info = info;
55
    if (dev->cad == -1) {
56
        dev->cad = bus->next_cad;
57
    }
58
    if (dev->cad > 15)
59
        return -1;
60
    bus->next_cad = dev->cad + 1;
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    return info->init(dev);
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}
63

    
64
static int hda_codec_dev_exit(DeviceState *qdev)
65
{
66
    HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
67

    
68
    if (dev->info->exit) {
69
        dev->info->exit(dev);
70
    }
71
    return 0;
72
}
73

    
74
void hda_codec_register(HDACodecDeviceInfo *info)
75
{
76
    info->qdev.init = hda_codec_dev_init;
77
    info->qdev.exit = hda_codec_dev_exit;
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    info->qdev.bus_info = &hda_codec_bus_info;
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    qdev_register(&info->qdev);
80
}
81

    
82
HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
83
{
84
    DeviceState *qdev;
85
    HDACodecDevice *cdev;
86

    
87
    QLIST_FOREACH(qdev, &bus->qbus.children, sibling) {
88
        cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
89
        if (cdev->cad == cad) {
90
            return cdev;
91
        }
92
    }
93
    return NULL;
94
}
95

    
96
void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response)
97
{
98
    HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
99
    bus->response(dev, solicited, response);
100
}
101

    
102
bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
103
                    uint8_t *buf, uint32_t len)
104
{
105
    HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
106
    return bus->xfer(dev, stnr, output, buf, len);
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}
108

    
109
/* --------------------------------------------------------------------- */
110
/* intel hda emulation                                                   */
111

    
112
typedef struct IntelHDAStream IntelHDAStream;
113
typedef struct IntelHDAState IntelHDAState;
114
typedef struct IntelHDAReg IntelHDAReg;
115

    
116
typedef struct bpl {
117
    uint64_t addr;
118
    uint32_t len;
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    uint32_t flags;
120
} bpl;
121

    
122
struct IntelHDAStream {
123
    /* registers */
124
    uint32_t ctl;
125
    uint32_t lpib;
126
    uint32_t cbl;
127
    uint32_t lvi;
128
    uint32_t fmt;
129
    uint32_t bdlp_lbase;
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    uint32_t bdlp_ubase;
131

    
132
    /* state */
133
    bpl      *bpl;
134
    uint32_t bentries;
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    uint32_t bsize, be, bp;
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};
137

    
138
struct IntelHDAState {
139
    PCIDevice pci;
140
    const char *name;
141
    HDACodecBus codecs;
142

    
143
    /* registers */
144
    uint32_t g_ctl;
145
    uint32_t wake_en;
146
    uint32_t state_sts;
147
    uint32_t int_ctl;
148
    uint32_t int_sts;
149
    uint32_t wall_clk;
150

    
151
    uint32_t corb_lbase;
152
    uint32_t corb_ubase;
153
    uint32_t corb_rp;
154
    uint32_t corb_wp;
155
    uint32_t corb_ctl;
156
    uint32_t corb_sts;
157
    uint32_t corb_size;
158

    
159
    uint32_t rirb_lbase;
160
    uint32_t rirb_ubase;
161
    uint32_t rirb_wp;
162
    uint32_t rirb_cnt;
163
    uint32_t rirb_ctl;
164
    uint32_t rirb_sts;
165
    uint32_t rirb_size;
166

    
167
    uint32_t dp_lbase;
168
    uint32_t dp_ubase;
169

    
170
    uint32_t icw;
171
    uint32_t irr;
172
    uint32_t ics;
173

    
174
    /* streams */
175
    IntelHDAStream st[8];
176

    
177
    /* state */
178
    int mmio_addr;
179
    uint32_t rirb_count;
180
    int64_t wall_base_ns;
181

    
182
    /* debug logging */
183
    const IntelHDAReg *last_reg;
184
    uint32_t last_val;
185
    uint32_t last_write;
186
    uint32_t last_sec;
187
    uint32_t repeat_count;
188

    
189
    /* properties */
190
    uint32_t debug;
191
};
192

    
193
struct IntelHDAReg {
194
    const char *name;      /* register name */
195
    uint32_t   size;       /* size in bytes */
196
    uint32_t   reset;      /* reset value */
197
    uint32_t   wmask;      /* write mask */
198
    uint32_t   wclear;     /* write 1 to clear bits */
199
    uint32_t   offset;     /* location in IntelHDAState */
200
    uint32_t   shift;      /* byte access entries for dwords */
201
    uint32_t   stream;
202
    void       (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
203
    void       (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
204
};
205

    
206
static void intel_hda_reset(DeviceState *dev);
207

    
208
/* --------------------------------------------------------------------- */
209

    
210
static target_phys_addr_t intel_hda_addr(uint32_t lbase, uint32_t ubase)
211
{
212
    target_phys_addr_t addr;
213

    
214
#if TARGET_PHYS_ADDR_BITS == 32
215
    addr = lbase;
216
#else
217
    addr = ubase;
218
    addr <<= 32;
219
    addr |= lbase;
220
#endif
221
    return addr;
222
}
223

    
224
static void stl_phys_le(target_phys_addr_t addr, uint32_t value)
225
{
226
    uint32_t value_le = cpu_to_le32(value);
227
    cpu_physical_memory_write(addr, (uint8_t*)(&value_le), sizeof(value_le));
228
}
229

    
230
static uint32_t ldl_phys_le(target_phys_addr_t addr)
231
{
232
    uint32_t value_le;
233
    cpu_physical_memory_read(addr, (uint8_t*)(&value_le), sizeof(value_le));
234
    return le32_to_cpu(value_le);
235
}
236

    
237
static void intel_hda_update_int_sts(IntelHDAState *d)
238
{
239
    uint32_t sts = 0;
240
    uint32_t i;
241

    
242
    /* update controller status */
243
    if (d->rirb_sts & ICH6_RBSTS_IRQ) {
244
        sts |= (1 << 30);
245
    }
246
    if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
247
        sts |= (1 << 30);
248
    }
249
    if (d->state_sts) {
250
        sts |= (1 << 30);
251
    }
252

    
253
    /* update stream status */
254
    for (i = 0; i < 8; i++) {
255
        /* buffer completion interrupt */
256
        if (d->st[i].ctl & (1 << 26)) {
257
            sts |= (1 << i);
258
        }
259
    }
260

    
261
    /* update global status */
262
    if (sts & d->int_ctl) {
263
        sts |= (1 << 31);
264
    }
265

    
266
    d->int_sts = sts;
267
}
268

    
269
static void intel_hda_update_irq(IntelHDAState *d)
270
{
271
    int level;
272

    
273
    intel_hda_update_int_sts(d);
274
    if (d->int_sts & (1 << 31) && d->int_ctl & (1 << 31)) {
275
        level = 1;
276
    } else {
277
        level = 0;
278
    }
279
    dprint(d, 2, "%s: level %d\n", __FUNCTION__, level);
280
    qemu_set_irq(d->pci.irq[0], level);
281
}
282

    
283
static int intel_hda_send_command(IntelHDAState *d, uint32_t verb)
284
{
285
    uint32_t cad, nid, data;
286
    HDACodecDevice *codec;
287

    
288
    cad = (verb >> 28) & 0x0f;
289
    if (verb & (1 << 27)) {
290
        /* indirect node addressing, not specified in HDA 1.0 */
291
        dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__);
292
        return -1;
293
    }
294
    nid = (verb >> 20) & 0x7f;
295
    data = verb & 0xfffff;
296

    
297
    codec = hda_codec_find(&d->codecs, cad);
298
    if (codec == NULL) {
299
        dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__);
300
        return -1;
301
    }
302
    codec->info->command(codec, nid, data);
303
    return 0;
304
}
305

    
306
static void intel_hda_corb_run(IntelHDAState *d)
307
{
308
    target_phys_addr_t addr;
309
    uint32_t rp, verb;
310

    
311
    if (d->ics & ICH6_IRS_BUSY) {
312
        dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw);
313
        intel_hda_send_command(d, d->icw);
314
        return;
315
    }
316

    
317
    for (;;) {
318
        if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
319
            dprint(d, 2, "%s: !run\n", __FUNCTION__);
320
            return;
321
        }
322
        if ((d->corb_rp & 0xff) == d->corb_wp) {
323
            dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__);
324
            return;
325
        }
326
        if (d->rirb_count == d->rirb_cnt) {
327
            dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__);
328
            return;
329
        }
330

    
331
        rp = (d->corb_rp + 1) & 0xff;
332
        addr = intel_hda_addr(d->corb_lbase, d->corb_ubase);
333
        verb = ldl_phys_le(addr + 4*rp);
334
        d->corb_rp = rp;
335

    
336
        dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb);
337
        intel_hda_send_command(d, verb);
338
    }
339
}
340

    
341
static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response)
342
{
343
    HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
344
    IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
345
    target_phys_addr_t addr;
346
    uint32_t wp, ex;
347

    
348
    if (d->ics & ICH6_IRS_BUSY) {
349
        dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
350
               __FUNCTION__, response, dev->cad);
351
        d->irr = response;
352
        d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
353
        d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
354
        return;
355
    }
356

    
357
    if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
358
        dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__);
359
        return;
360
    }
361

    
362
    ex = (solicited ? 0 : (1 << 4)) | dev->cad;
363
    wp = (d->rirb_wp + 1) & 0xff;
364
    addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
365
    stl_phys_le(addr + 8*wp, response);
366
    stl_phys_le(addr + 8*wp + 4, ex);
367
    d->rirb_wp = wp;
368

    
369
    dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
370
           __FUNCTION__, wp, response, ex);
371

    
372
    d->rirb_count++;
373
    if (d->rirb_count == d->rirb_cnt) {
374
        dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count);
375
        if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
376
            d->rirb_sts |= ICH6_RBSTS_IRQ;
377
            intel_hda_update_irq(d);
378
        }
379
    } else if ((d->corb_rp & 0xff) == d->corb_wp) {
380
        dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__,
381
               d->rirb_count, d->rirb_cnt);
382
        if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
383
            d->rirb_sts |= ICH6_RBSTS_IRQ;
384
            intel_hda_update_irq(d);
385
        }
386
    }
387
}
388

    
389
static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
390
                           uint8_t *buf, uint32_t len)
391
{
392
    HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
393
    IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
394
    IntelHDAStream *st = NULL;
395
    target_phys_addr_t addr;
396
    uint32_t s, copy, left;
397
    bool irq = false;
398

    
399
    for (s = 0; s < ARRAY_SIZE(d->st); s++) {
400
        if (stnr == ((d->st[s].ctl >> 20) & 0x0f)) {
401
            st = d->st + s;
402
            break;
403
        }
404
    }
405
    if (st == NULL) {
406
        return false;
407
    }
408
    if (st->bpl == NULL) {
409
        return false;
410
    }
411
    if (st->ctl & (1 << 26)) {
412
        /*
413
         * Wait with the next DMA xfer until the guest
414
         * has acked the buffer completion interrupt
415
         */
416
        return false;
417
    }
418

    
419
    left = len;
420
    while (left > 0) {
421
        copy = left;
422
        if (copy > st->bsize - st->lpib)
423
            copy = st->bsize - st->lpib;
424
        if (copy > st->bpl[st->be].len - st->bp)
425
            copy = st->bpl[st->be].len - st->bp;
426

    
427
        dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n",
428
               st->be, st->bp, st->bpl[st->be].len, copy);
429

    
430
        cpu_physical_memory_rw(st->bpl[st->be].addr + st->bp,
431
                               buf, copy, !output);
432
        st->lpib += copy;
433
        st->bp += copy;
434
        buf += copy;
435
        left -= copy;
436

    
437
        if (st->bpl[st->be].len == st->bp) {
438
            /* bpl entry filled */
439
            if (st->bpl[st->be].flags & 0x01) {
440
                irq = true;
441
            }
442
            st->bp = 0;
443
            st->be++;
444
            if (st->be == st->bentries) {
445
                /* bpl wrap around */
446
                st->be = 0;
447
                st->lpib = 0;
448
            }
449
        }
450
    }
451
    if (d->dp_lbase & 0x01) {
452
        addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
453
        stl_phys_le(addr + 8*s, st->lpib);
454
    }
455
    dprint(d, 3, "dma: --\n");
456

    
457
    if (irq) {
458
        st->ctl |= (1 << 26); /* buffer completion interrupt */
459
        intel_hda_update_irq(d);
460
    }
461
    return true;
462
}
463

    
464
static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
465
{
466
    target_phys_addr_t addr;
467
    uint8_t buf[16];
468
    uint32_t i;
469

    
470
    addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase);
471
    st->bentries = st->lvi +1;
472
    qemu_free(st->bpl);
473
    st->bpl = qemu_malloc(sizeof(bpl) * st->bentries);
474
    for (i = 0; i < st->bentries; i++, addr += 16) {
475
        cpu_physical_memory_read(addr, buf, 16);
476
        st->bpl[i].addr  = le64_to_cpu(*(uint64_t *)buf);
477
        st->bpl[i].len   = le32_to_cpu(*(uint32_t *)(buf + 8));
478
        st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
479
        dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n",
480
               i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags);
481
    }
482

    
483
    st->bsize = st->cbl;
484
    st->lpib  = 0;
485
    st->be    = 0;
486
    st->bp    = 0;
487
}
488

    
489
static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running)
490
{
491
    DeviceState *qdev;
492
    HDACodecDevice *cdev;
493

    
494
    QLIST_FOREACH(qdev, &d->codecs.qbus.children, sibling) {
495
        cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
496
        if (cdev->info->stream) {
497
            cdev->info->stream(cdev, stream, running);
498
        }
499
    }
500
}
501

    
502
/* --------------------------------------------------------------------- */
503

    
504
static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
505
{
506
    if ((d->g_ctl & ICH6_GCTL_RESET) == 0) {
507
        intel_hda_reset(&d->pci.qdev);
508
    }
509
}
510

    
511
static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
512
{
513
    intel_hda_update_irq(d);
514
}
515

    
516
static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
517
{
518
    intel_hda_update_irq(d);
519
}
520

    
521
static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg)
522
{
523
    int64_t ns;
524

    
525
    ns = qemu_get_clock_ns(vm_clock) - d->wall_base_ns;
526
    d->wall_clk = (uint32_t)(ns * 24 / 1000);  /* 24 MHz */
527
}
528

    
529
static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
530
{
531
    intel_hda_corb_run(d);
532
}
533

    
534
static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
535
{
536
    intel_hda_corb_run(d);
537
}
538

    
539
static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
540
{
541
    if (d->rirb_wp & ICH6_RIRBWP_RST) {
542
        d->rirb_wp = 0;
543
    }
544
}
545

    
546
static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
547
{
548
    intel_hda_update_irq(d);
549

    
550
    if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
551
        /* cleared ICH6_RBSTS_IRQ */
552
        d->rirb_count = 0;
553
        intel_hda_corb_run(d);
554
    }
555
}
556

    
557
static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
558
{
559
    if (d->ics & ICH6_IRS_BUSY) {
560
        intel_hda_corb_run(d);
561
    }
562
}
563

    
564
static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
565
{
566
    IntelHDAStream *st = d->st + reg->stream;
567

    
568
    if (st->ctl & 0x01) {
569
        /* reset */
570
        dprint(d, 1, "st #%d: reset\n", reg->stream);
571
        st->ctl = 0;
572
    }
573
    if ((st->ctl & 0x02) != (old & 0x02)) {
574
        uint32_t stnr = (st->ctl >> 20) & 0x0f;
575
        /* run bit flipped */
576
        if (st->ctl & 0x02) {
577
            /* start */
578
            dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",
579
                   reg->stream, stnr, st->cbl);
580
            intel_hda_parse_bdl(d, st);
581
            intel_hda_notify_codecs(d, stnr, true);
582
        } else {
583
            /* stop */
584
            dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);
585
            intel_hda_notify_codecs(d, stnr, false);
586
        }
587
    }
588
    intel_hda_update_irq(d);
589
}
590

    
591
/* --------------------------------------------------------------------- */
592

    
593
#define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
594

    
595
static const struct IntelHDAReg regtab[] = {
596
    /* global */
597
    [ ICH6_REG_GCAP ] = {
598
        .name     = "GCAP",
599
        .size     = 2,
600
        .reset    = 0x4401,
601
    },
602
    [ ICH6_REG_VMIN ] = {
603
        .name     = "VMIN",
604
        .size     = 1,
605
    },
606
    [ ICH6_REG_VMAJ ] = {
607
        .name     = "VMAJ",
608
        .size     = 1,
609
        .reset    = 1,
610
    },
611
    [ ICH6_REG_OUTPAY ] = {
612
        .name     = "OUTPAY",
613
        .size     = 2,
614
        .reset    = 0x3c,
615
    },
616
    [ ICH6_REG_INPAY ] = {
617
        .name     = "INPAY",
618
        .size     = 2,
619
        .reset    = 0x1d,
620
    },
621
    [ ICH6_REG_GCTL ] = {
622
        .name     = "GCTL",
623
        .size     = 4,
624
        .wmask    = 0x0103,
625
        .offset   = offsetof(IntelHDAState, g_ctl),
626
        .whandler = intel_hda_set_g_ctl,
627
    },
628
    [ ICH6_REG_WAKEEN ] = {
629
        .name     = "WAKEEN",
630
        .size     = 2,
631
        .offset   = offsetof(IntelHDAState, wake_en),
632
    },
633
    [ ICH6_REG_STATESTS ] = {
634
        .name     = "STATESTS",
635
        .size     = 2,
636
        .wmask    = 0x3fff,
637
        .wclear   = 0x3fff,
638
        .offset   = offsetof(IntelHDAState, state_sts),
639
        .whandler = intel_hda_set_state_sts,
640
    },
641

    
642
    /* interrupts */
643
    [ ICH6_REG_INTCTL ] = {
644
        .name     = "INTCTL",
645
        .size     = 4,
646
        .wmask    = 0xc00000ff,
647
        .offset   = offsetof(IntelHDAState, int_ctl),
648
        .whandler = intel_hda_set_int_ctl,
649
    },
650
    [ ICH6_REG_INTSTS ] = {
651
        .name     = "INTSTS",
652
        .size     = 4,
653
        .wmask    = 0xc00000ff,
654
        .wclear   = 0xc00000ff,
655
        .offset   = offsetof(IntelHDAState, int_sts),
656
    },
657

    
658
    /* misc */
659
    [ ICH6_REG_WALLCLK ] = {
660
        .name     = "WALLCLK",
661
        .size     = 4,
662
        .offset   = offsetof(IntelHDAState, wall_clk),
663
        .rhandler = intel_hda_get_wall_clk,
664
    },
665
    [ ICH6_REG_WALLCLK + 0x2000 ] = {
666
        .name     = "WALLCLK(alias)",
667
        .size     = 4,
668
        .offset   = offsetof(IntelHDAState, wall_clk),
669
        .rhandler = intel_hda_get_wall_clk,
670
    },
671

    
672
    /* dma engine */
673
    [ ICH6_REG_CORBLBASE ] = {
674
        .name     = "CORBLBASE",
675
        .size     = 4,
676
        .wmask    = 0xffffff80,
677
        .offset   = offsetof(IntelHDAState, corb_lbase),
678
    },
679
    [ ICH6_REG_CORBUBASE ] = {
680
        .name     = "CORBUBASE",
681
        .size     = 4,
682
        .wmask    = 0xffffffff,
683
        .offset   = offsetof(IntelHDAState, corb_ubase),
684
    },
685
    [ ICH6_REG_CORBWP ] = {
686
        .name     = "CORBWP",
687
        .size     = 2,
688
        .wmask    = 0xff,
689
        .offset   = offsetof(IntelHDAState, corb_wp),
690
        .whandler = intel_hda_set_corb_wp,
691
    },
692
    [ ICH6_REG_CORBRP ] = {
693
        .name     = "CORBRP",
694
        .size     = 2,
695
        .wmask    = 0x80ff,
696
        .offset   = offsetof(IntelHDAState, corb_rp),
697
    },
698
    [ ICH6_REG_CORBCTL ] = {
699
        .name     = "CORBCTL",
700
        .size     = 1,
701
        .wmask    = 0x03,
702
        .offset   = offsetof(IntelHDAState, corb_ctl),
703
        .whandler = intel_hda_set_corb_ctl,
704
    },
705
    [ ICH6_REG_CORBSTS ] = {
706
        .name     = "CORBSTS",
707
        .size     = 1,
708
        .wmask    = 0x01,
709
        .wclear   = 0x01,
710
        .offset   = offsetof(IntelHDAState, corb_sts),
711
    },
712
    [ ICH6_REG_CORBSIZE ] = {
713
        .name     = "CORBSIZE",
714
        .size     = 1,
715
        .reset    = 0x42,
716
        .offset   = offsetof(IntelHDAState, corb_size),
717
    },
718
    [ ICH6_REG_RIRBLBASE ] = {
719
        .name     = "RIRBLBASE",
720
        .size     = 4,
721
        .wmask    = 0xffffff80,
722
        .offset   = offsetof(IntelHDAState, rirb_lbase),
723
    },
724
    [ ICH6_REG_RIRBUBASE ] = {
725
        .name     = "RIRBUBASE",
726
        .size     = 4,
727
        .wmask    = 0xffffffff,
728
        .offset   = offsetof(IntelHDAState, rirb_ubase),
729
    },
730
    [ ICH6_REG_RIRBWP ] = {
731
        .name     = "RIRBWP",
732
        .size     = 2,
733
        .wmask    = 0x8000,
734
        .offset   = offsetof(IntelHDAState, rirb_wp),
735
        .whandler = intel_hda_set_rirb_wp,
736
    },
737
    [ ICH6_REG_RINTCNT ] = {
738
        .name     = "RINTCNT",
739
        .size     = 2,
740
        .wmask    = 0xff,
741
        .offset   = offsetof(IntelHDAState, rirb_cnt),
742
    },
743
    [ ICH6_REG_RIRBCTL ] = {
744
        .name     = "RIRBCTL",
745
        .size     = 1,
746
        .wmask    = 0x07,
747
        .offset   = offsetof(IntelHDAState, rirb_ctl),
748
    },
749
    [ ICH6_REG_RIRBSTS ] = {
750
        .name     = "RIRBSTS",
751
        .size     = 1,
752
        .wmask    = 0x05,
753
        .wclear   = 0x05,
754
        .offset   = offsetof(IntelHDAState, rirb_sts),
755
        .whandler = intel_hda_set_rirb_sts,
756
    },
757
    [ ICH6_REG_RIRBSIZE ] = {
758
        .name     = "RIRBSIZE",
759
        .size     = 1,
760
        .reset    = 0x42,
761
        .offset   = offsetof(IntelHDAState, rirb_size),
762
    },
763

    
764
    [ ICH6_REG_DPLBASE ] = {
765
        .name     = "DPLBASE",
766
        .size     = 4,
767
        .wmask    = 0xffffff81,
768
        .offset   = offsetof(IntelHDAState, dp_lbase),
769
    },
770
    [ ICH6_REG_DPUBASE ] = {
771
        .name     = "DPUBASE",
772
        .size     = 4,
773
        .wmask    = 0xffffffff,
774
        .offset   = offsetof(IntelHDAState, dp_ubase),
775
    },
776

    
777
    [ ICH6_REG_IC ] = {
778
        .name     = "ICW",
779
        .size     = 4,
780
        .wmask    = 0xffffffff,
781
        .offset   = offsetof(IntelHDAState, icw),
782
    },
783
    [ ICH6_REG_IR ] = {
784
        .name     = "IRR",
785
        .size     = 4,
786
        .offset   = offsetof(IntelHDAState, irr),
787
    },
788
    [ ICH6_REG_IRS ] = {
789
        .name     = "ICS",
790
        .size     = 2,
791
        .wmask    = 0x0003,
792
        .wclear   = 0x0002,
793
        .offset   = offsetof(IntelHDAState, ics),
794
        .whandler = intel_hda_set_ics,
795
    },
796

    
797
#define HDA_STREAM(_t, _i)                                            \
798
    [ ST_REG(_i, ICH6_REG_SD_CTL) ] = {                               \
799
        .stream   = _i,                                               \
800
        .name     = _t stringify(_i) " CTL",                          \
801
        .size     = 4,                                                \
802
        .wmask    = 0x1cff001f,                                       \
803
        .offset   = offsetof(IntelHDAState, st[_i].ctl),              \
804
        .whandler = intel_hda_set_st_ctl,                             \
805
    },                                                                \
806
    [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = {                            \
807
        .stream   = _i,                                               \
808
        .name     = _t stringify(_i) " CTL(stnr)",                    \
809
        .size     = 1,                                                \
810
        .shift    = 16,                                               \
811
        .wmask    = 0x00ff0000,                                       \
812
        .offset   = offsetof(IntelHDAState, st[_i].ctl),              \
813
        .whandler = intel_hda_set_st_ctl,                             \
814
    },                                                                \
815
    [ ST_REG(_i, ICH6_REG_SD_STS)] = {                                \
816
        .stream   = _i,                                               \
817
        .name     = _t stringify(_i) " CTL(sts)",                     \
818
        .size     = 1,                                                \
819
        .shift    = 24,                                               \
820
        .wmask    = 0x1c000000,                                       \
821
        .wclear   = 0x1c000000,                                       \
822
        .offset   = offsetof(IntelHDAState, st[_i].ctl),              \
823
        .whandler = intel_hda_set_st_ctl,                             \
824
    },                                                                \
825
    [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = {                              \
826
        .stream   = _i,                                               \
827
        .name     = _t stringify(_i) " LPIB",                         \
828
        .size     = 4,                                                \
829
        .offset   = offsetof(IntelHDAState, st[_i].lpib),             \
830
    },                                                                \
831
    [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = {                     \
832
        .stream   = _i,                                               \
833
        .name     = _t stringify(_i) " LPIB(alias)",                  \
834
        .size     = 4,                                                \
835
        .offset   = offsetof(IntelHDAState, st[_i].lpib),             \
836
    },                                                                \
837
    [ ST_REG(_i, ICH6_REG_SD_CBL) ] = {                               \
838
        .stream   = _i,                                               \
839
        .name     = _t stringify(_i) " CBL",                          \
840
        .size     = 4,                                                \
841
        .wmask    = 0xffffffff,                                       \
842
        .offset   = offsetof(IntelHDAState, st[_i].cbl),              \
843
    },                                                                \
844
    [ ST_REG(_i, ICH6_REG_SD_LVI) ] = {                               \
845
        .stream   = _i,                                               \
846
        .name     = _t stringify(_i) " LVI",                          \
847
        .size     = 2,                                                \
848
        .wmask    = 0x00ff,                                           \
849
        .offset   = offsetof(IntelHDAState, st[_i].lvi),              \
850
    },                                                                \
851
    [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = {                          \
852
        .stream   = _i,                                               \
853
        .name     = _t stringify(_i) " FIFOS",                        \
854
        .size     = 2,                                                \
855
        .reset    = HDA_BUFFER_SIZE,                                  \
856
    },                                                                \
857
    [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = {                            \
858
        .stream   = _i,                                               \
859
        .name     = _t stringify(_i) " FMT",                          \
860
        .size     = 2,                                                \
861
        .wmask    = 0x7f7f,                                           \
862
        .offset   = offsetof(IntelHDAState, st[_i].fmt),              \
863
    },                                                                \
864
    [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = {                             \
865
        .stream   = _i,                                               \
866
        .name     = _t stringify(_i) " BDLPL",                        \
867
        .size     = 4,                                                \
868
        .wmask    = 0xffffff80,                                       \
869
        .offset   = offsetof(IntelHDAState, st[_i].bdlp_lbase),       \
870
    },                                                                \
871
    [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = {                             \
872
        .stream   = _i,                                               \
873
        .name     = _t stringify(_i) " BDLPU",                        \
874
        .size     = 4,                                                \
875
        .wmask    = 0xffffffff,                                       \
876
        .offset   = offsetof(IntelHDAState, st[_i].bdlp_ubase),       \
877
    },                                                                \
878

    
879
    HDA_STREAM("IN", 0)
880
    HDA_STREAM("IN", 1)
881
    HDA_STREAM("IN", 2)
882
    HDA_STREAM("IN", 3)
883

    
884
    HDA_STREAM("OUT", 4)
885
    HDA_STREAM("OUT", 5)
886
    HDA_STREAM("OUT", 6)
887
    HDA_STREAM("OUT", 7)
888

    
889
};
890

    
891
static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, target_phys_addr_t addr)
892
{
893
    const IntelHDAReg *reg;
894

    
895
    if (addr >= sizeof(regtab)/sizeof(regtab[0])) {
896
        goto noreg;
897
    }
898
    reg = regtab+addr;
899
    if (reg->name == NULL) {
900
        goto noreg;
901
    }
902
    return reg;
903

    
904
noreg:
905
    dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr);
906
    return NULL;
907
}
908

    
909
static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg)
910
{
911
    uint8_t *addr = (void*)d;
912

    
913
    addr += reg->offset;
914
    return (uint32_t*)addr;
915
}
916

    
917
static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val,
918
                                uint32_t wmask)
919
{
920
    uint32_t *addr;
921
    uint32_t old;
922

    
923
    if (!reg) {
924
        return;
925
    }
926

    
927
    if (d->debug) {
928
        time_t now = time(NULL);
929
        if (d->last_write && d->last_reg == reg && d->last_val == val) {
930
            d->repeat_count++;
931
            if (d->last_sec != now) {
932
                dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
933
                d->last_sec = now;
934
                d->repeat_count = 0;
935
            }
936
        } else {
937
            if (d->repeat_count) {
938
                dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
939
            }
940
            dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask);
941
            d->last_write = 1;
942
            d->last_reg   = reg;
943
            d->last_val   = val;
944
            d->last_sec   = now;
945
            d->repeat_count = 0;
946
        }
947
    }
948
    assert(reg->offset != 0);
949

    
950
    addr = intel_hda_reg_addr(d, reg);
951
    old = *addr;
952

    
953
    if (reg->shift) {
954
        val <<= reg->shift;
955
        wmask <<= reg->shift;
956
    }
957
    wmask &= reg->wmask;
958
    *addr &= ~wmask;
959
    *addr |= wmask & val;
960
    *addr &= ~(val & reg->wclear);
961

    
962
    if (reg->whandler) {
963
        reg->whandler(d, reg, old);
964
    }
965
}
966

    
967
static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg,
968
                                   uint32_t rmask)
969
{
970
    uint32_t *addr, ret;
971

    
972
    if (!reg) {
973
        return 0;
974
    }
975

    
976
    if (reg->rhandler) {
977
        reg->rhandler(d, reg);
978
    }
979

    
980
    if (reg->offset == 0) {
981
        /* constant read-only register */
982
        ret = reg->reset;
983
    } else {
984
        addr = intel_hda_reg_addr(d, reg);
985
        ret = *addr;
986
        if (reg->shift) {
987
            ret >>= reg->shift;
988
        }
989
        ret &= rmask;
990
    }
991
    if (d->debug) {
992
        time_t now = time(NULL);
993
        if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
994
            d->repeat_count++;
995
            if (d->last_sec != now) {
996
                dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
997
                d->last_sec = now;
998
                d->repeat_count = 0;
999
            }
1000
        } else {
1001
            if (d->repeat_count) {
1002
                dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1003
            }
1004
            dprint(d, 2, "read  %-16s: 0x%x (%x)\n", reg->name, ret, rmask);
1005
            d->last_write = 0;
1006
            d->last_reg   = reg;
1007
            d->last_val   = ret;
1008
            d->last_sec   = now;
1009
            d->repeat_count = 0;
1010
        }
1011
    }
1012
    return ret;
1013
}
1014

    
1015
static void intel_hda_regs_reset(IntelHDAState *d)
1016
{
1017
    uint32_t *addr;
1018
    int i;
1019

    
1020
    for (i = 0; i < sizeof(regtab)/sizeof(regtab[0]); i++) {
1021
        if (regtab[i].name == NULL) {
1022
            continue;
1023
        }
1024
        if (regtab[i].offset == 0) {
1025
            continue;
1026
        }
1027
        addr = intel_hda_reg_addr(d, regtab + i);
1028
        *addr = regtab[i].reset;
1029
    }
1030
}
1031

    
1032
/* --------------------------------------------------------------------- */
1033

    
1034
static void intel_hda_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1035
{
1036
    IntelHDAState *d = opaque;
1037
    const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1038

    
1039
    intel_hda_reg_write(d, reg, val, 0xff);
1040
}
1041

    
1042
static void intel_hda_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1043
{
1044
    IntelHDAState *d = opaque;
1045
    const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1046

    
1047
    intel_hda_reg_write(d, reg, val, 0xffff);
1048
}
1049

    
1050
static void intel_hda_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1051
{
1052
    IntelHDAState *d = opaque;
1053
    const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1054

    
1055
    intel_hda_reg_write(d, reg, val, 0xffffffff);
1056
}
1057

    
1058
static uint32_t intel_hda_mmio_readb(void *opaque, target_phys_addr_t addr)
1059
{
1060
    IntelHDAState *d = opaque;
1061
    const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1062

    
1063
    return intel_hda_reg_read(d, reg, 0xff);
1064
}
1065

    
1066
static uint32_t intel_hda_mmio_readw(void *opaque, target_phys_addr_t addr)
1067
{
1068
    IntelHDAState *d = opaque;
1069
    const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1070

    
1071
    return intel_hda_reg_read(d, reg, 0xffff);
1072
}
1073

    
1074
static uint32_t intel_hda_mmio_readl(void *opaque, target_phys_addr_t addr)
1075
{
1076
    IntelHDAState *d = opaque;
1077
    const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1078

    
1079
    return intel_hda_reg_read(d, reg, 0xffffffff);
1080
}
1081

    
1082
static CPUReadMemoryFunc * const intel_hda_mmio_read[3] = {
1083
    intel_hda_mmio_readb,
1084
    intel_hda_mmio_readw,
1085
    intel_hda_mmio_readl,
1086
};
1087

    
1088
static CPUWriteMemoryFunc * const intel_hda_mmio_write[3] = {
1089
    intel_hda_mmio_writeb,
1090
    intel_hda_mmio_writew,
1091
    intel_hda_mmio_writel,
1092
};
1093

    
1094
static void intel_hda_map(PCIDevice *pci, int region_num,
1095
                          pcibus_t addr, pcibus_t size, int type)
1096
{
1097
    IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1098

    
1099
    cpu_register_physical_memory(addr, 0x4000, d->mmio_addr);
1100
}
1101

    
1102
/* --------------------------------------------------------------------- */
1103

    
1104
static void intel_hda_reset(DeviceState *dev)
1105
{
1106
    IntelHDAState *d = DO_UPCAST(IntelHDAState, pci.qdev, dev);
1107
    DeviceState *qdev;
1108
    HDACodecDevice *cdev;
1109

    
1110
    intel_hda_regs_reset(d);
1111
    d->wall_base_ns = qemu_get_clock(vm_clock);
1112

    
1113
    /* reset codecs */
1114
    QLIST_FOREACH(qdev, &d->codecs.qbus.children, sibling) {
1115
        cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
1116
        if (qdev->info->reset) {
1117
            qdev->info->reset(qdev);
1118
        }
1119
        d->state_sts |= (1 << cdev->cad);
1120
    }
1121
    intel_hda_update_irq(d);
1122
}
1123

    
1124
static int intel_hda_init(PCIDevice *pci)
1125
{
1126
    IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1127
    uint8_t *conf = d->pci.config;
1128

    
1129
    d->name = d->pci.qdev.info->name;
1130

    
1131
    pci_config_set_vendor_id(conf, PCI_VENDOR_ID_INTEL);
1132
    pci_config_set_device_id(conf, 0x2668);
1133
    pci_config_set_revision(conf, 1);
1134
    pci_config_set_class(conf, PCI_CLASS_MULTIMEDIA_HD_AUDIO);
1135
    pci_config_set_interrupt_pin(conf, 1);
1136

    
1137
    /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1138
    conf[0x40] = 0x01;
1139

    
1140
    d->mmio_addr = cpu_register_io_memory(intel_hda_mmio_read,
1141
                                          intel_hda_mmio_write, d);
1142
    pci_register_bar(&d->pci, 0, 0x4000, PCI_BASE_ADDRESS_SPACE_MEMORY,
1143
                     intel_hda_map);
1144

    
1145
    hda_codec_bus_init(&d->pci.qdev, &d->codecs,
1146
                       intel_hda_response, intel_hda_xfer);
1147

    
1148
    return 0;
1149
}
1150

    
1151
static int intel_hda_exit(PCIDevice *pci)
1152
{
1153
    IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1154

    
1155
    cpu_unregister_io_memory(d->mmio_addr);
1156
    return 0;
1157
}
1158

    
1159
static int intel_hda_post_load(void *opaque, int version)
1160
{
1161
    IntelHDAState* d = opaque;
1162
    int i;
1163

    
1164
    dprint(d, 1, "%s\n", __FUNCTION__);
1165
    for (i = 0; i < ARRAY_SIZE(d->st); i++) {
1166
        if (d->st[i].ctl & 0x02) {
1167
            intel_hda_parse_bdl(d, &d->st[i]);
1168
        }
1169
    }
1170
    intel_hda_update_irq(d);
1171
    return 0;
1172
}
1173

    
1174
static const VMStateDescription vmstate_intel_hda_stream = {
1175
    .name = "intel-hda-stream",
1176
    .version_id = 1,
1177
    .fields = (VMStateField []) {
1178
        VMSTATE_UINT32(ctl, IntelHDAStream),
1179
        VMSTATE_UINT32(lpib, IntelHDAStream),
1180
        VMSTATE_UINT32(cbl, IntelHDAStream),
1181
        VMSTATE_UINT32(lvi, IntelHDAStream),
1182
        VMSTATE_UINT32(fmt, IntelHDAStream),
1183
        VMSTATE_UINT32(bdlp_lbase, IntelHDAStream),
1184
        VMSTATE_UINT32(bdlp_ubase, IntelHDAStream),
1185
        VMSTATE_END_OF_LIST()
1186
    }
1187
};
1188

    
1189
static const VMStateDescription vmstate_intel_hda = {
1190
    .name = "intel-hda",
1191
    .version_id = 1,
1192
    .post_load = intel_hda_post_load,
1193
    .fields = (VMStateField []) {
1194
        VMSTATE_PCI_DEVICE(pci, IntelHDAState),
1195

    
1196
        /* registers */
1197
        VMSTATE_UINT32(g_ctl, IntelHDAState),
1198
        VMSTATE_UINT32(wake_en, IntelHDAState),
1199
        VMSTATE_UINT32(state_sts, IntelHDAState),
1200
        VMSTATE_UINT32(int_ctl, IntelHDAState),
1201
        VMSTATE_UINT32(int_sts, IntelHDAState),
1202
        VMSTATE_UINT32(wall_clk, IntelHDAState),
1203
        VMSTATE_UINT32(corb_lbase, IntelHDAState),
1204
        VMSTATE_UINT32(corb_ubase, IntelHDAState),
1205
        VMSTATE_UINT32(corb_rp, IntelHDAState),
1206
        VMSTATE_UINT32(corb_wp, IntelHDAState),
1207
        VMSTATE_UINT32(corb_ctl, IntelHDAState),
1208
        VMSTATE_UINT32(corb_sts, IntelHDAState),
1209
        VMSTATE_UINT32(corb_size, IntelHDAState),
1210
        VMSTATE_UINT32(rirb_lbase, IntelHDAState),
1211
        VMSTATE_UINT32(rirb_ubase, IntelHDAState),
1212
        VMSTATE_UINT32(rirb_wp, IntelHDAState),
1213
        VMSTATE_UINT32(rirb_cnt, IntelHDAState),
1214
        VMSTATE_UINT32(rirb_ctl, IntelHDAState),
1215
        VMSTATE_UINT32(rirb_sts, IntelHDAState),
1216
        VMSTATE_UINT32(rirb_size, IntelHDAState),
1217
        VMSTATE_UINT32(dp_lbase, IntelHDAState),
1218
        VMSTATE_UINT32(dp_ubase, IntelHDAState),
1219
        VMSTATE_UINT32(icw, IntelHDAState),
1220
        VMSTATE_UINT32(irr, IntelHDAState),
1221
        VMSTATE_UINT32(ics, IntelHDAState),
1222
        VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0,
1223
                             vmstate_intel_hda_stream,
1224
                             IntelHDAStream),
1225

    
1226
        /* additional state info */
1227
        VMSTATE_UINT32(rirb_count, IntelHDAState),
1228
        VMSTATE_INT64(wall_base_ns, IntelHDAState),
1229

    
1230
        VMSTATE_END_OF_LIST()
1231
    }
1232
};
1233

    
1234
static PCIDeviceInfo intel_hda_info = {
1235
    .qdev.name    = "intel-hda",
1236
    .qdev.desc    = "Intel HD Audio Controller",
1237
    .qdev.size    = sizeof(IntelHDAState),
1238
    .qdev.vmsd    = &vmstate_intel_hda,
1239
    .qdev.reset   = intel_hda_reset,
1240
    .init         = intel_hda_init,
1241
    .exit         = intel_hda_exit,
1242
    .qdev.props   = (Property[]) {
1243
        DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0),
1244
        DEFINE_PROP_END_OF_LIST(),
1245
    }
1246
};
1247

    
1248
static void intel_hda_register(void)
1249
{
1250
    pci_qdev_register(&intel_hda_info);
1251
}
1252
device_init(intel_hda_register);
1253

    
1254
/*
1255
 * create intel hda controller with codec attached to it,
1256
 * so '-soundhw hda' works.
1257
 */
1258
int intel_hda_and_codec_init(PCIBus *bus)
1259
{
1260
    PCIDevice *controller;
1261
    BusState *hdabus;
1262
    DeviceState *codec;
1263

    
1264
    controller = pci_create_simple(bus, -1, "intel-hda");
1265
    hdabus = QLIST_FIRST(&controller->qdev.child_bus);
1266
    codec = qdev_create(hdabus, "hda-duplex");
1267
    qdev_init_nofail(codec);
1268
    return 0;
1269
}
1270