Revision dc99a3f2 target-sparc/translate.c
| b/target-sparc/translate.c | ||
|---|---|---|
| 46 | 46 |
according to jump_pc[T2] */ |
| 47 | 47 |
|
| 48 | 48 |
/* global register indexes */ |
| 49 |
static TCGv cpu_env, cpu_T[3], cpu_regwptr; |
|
| 49 |
static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_dst, cpu_psr; |
|
| 50 |
#ifdef TARGET_SPARC64 |
|
| 51 |
static TCGv cpu_xcc; |
|
| 52 |
#endif |
|
| 50 | 53 |
/* local register indexes (only used inside old micro ops) */ |
| 51 | 54 |
static TCGv cpu_tmp0; |
| 52 | 55 |
|
| ... | ... | |
| 356 | 359 |
tcg_gen_andi_tl(reg, reg, 0x1); |
| 357 | 360 |
} |
| 358 | 361 |
|
| 362 |
static inline void gen_op_exception(int exception) |
|
| 363 |
{
|
|
| 364 |
TCGv r_except; |
|
| 365 |
|
|
| 366 |
r_except = tcg_temp_new(TCG_TYPE_I32); |
|
| 367 |
tcg_gen_movi_i32(r_except, exception); |
|
| 368 |
tcg_gen_helper_0_1(raise_exception, r_except); |
|
| 369 |
} |
|
| 370 |
|
|
| 371 |
static inline void gen_cc_clear(void) |
|
| 372 |
{
|
|
| 373 |
tcg_gen_movi_i32(cpu_psr, 0); |
|
| 374 |
#ifdef TARGET_SPARC64 |
|
| 375 |
tcg_gen_movi_i32(cpu_xcc, 0); |
|
| 376 |
#endif |
|
| 377 |
} |
|
| 378 |
|
|
| 379 |
/* old op: |
|
| 380 |
if (!T0) |
|
| 381 |
env->psr |= PSR_ZERO; |
|
| 382 |
if ((int32_t) T0 < 0) |
|
| 383 |
env->psr |= PSR_NEG; |
|
| 384 |
*/ |
|
| 385 |
static inline void gen_cc_NZ(TCGv dst) |
|
| 386 |
{
|
|
| 387 |
int l1, l2; |
|
| 388 |
TCGv r_zero; |
|
| 389 |
|
|
| 390 |
l1 = gen_new_label(); |
|
| 391 |
l2 = gen_new_label(); |
|
| 392 |
r_zero = tcg_temp_new(TCG_TYPE_TL); |
|
| 393 |
tcg_gen_movi_tl(r_zero, 0); |
|
| 394 |
tcg_gen_brcond_i32(TCG_COND_NE, dst, r_zero, l1); |
|
| 395 |
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO); |
|
| 396 |
gen_set_label(l1); |
|
| 397 |
tcg_gen_brcond_i32(TCG_COND_GE, dst, r_zero, l2); |
|
| 398 |
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG); |
|
| 399 |
gen_set_label(l2); |
|
| 400 |
#ifdef TARGET_SPARC64 |
|
| 401 |
{
|
|
| 402 |
int l3, l4; |
|
| 403 |
|
|
| 404 |
l3 = gen_new_label(); |
|
| 405 |
l4 = gen_new_label(); |
|
| 406 |
tcg_gen_brcond_tl(TCG_COND_NE, dst, r_zero, l3); |
|
| 407 |
tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO); |
|
| 408 |
gen_set_label(l3); |
|
| 409 |
tcg_gen_brcond_tl(TCG_COND_GE, dst, r_zero, l4); |
|
| 410 |
tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG); |
|
| 411 |
gen_set_label(l4); |
|
| 412 |
} |
|
| 413 |
#endif |
|
| 414 |
} |
|
| 415 |
|
|
| 416 |
/* old op: |
|
| 417 |
if (T0 < src1) |
|
| 418 |
env->psr |= PSR_CARRY; |
|
| 419 |
*/ |
|
| 420 |
static inline void gen_cc_C_add(TCGv dst, TCGv src1) |
|
| 421 |
{
|
|
| 422 |
int l1; |
|
| 423 |
|
|
| 424 |
l1 = gen_new_label(); |
|
| 425 |
tcg_gen_brcond_i32(TCG_COND_GEU, dst, src1, l1); |
|
| 426 |
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
|
| 427 |
gen_set_label(l1); |
|
| 428 |
#ifdef TARGET_SPARC64 |
|
| 429 |
{
|
|
| 430 |
int l2; |
|
| 431 |
|
|
| 432 |
l2 = gen_new_label(); |
|
| 433 |
tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l2); |
|
| 434 |
tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); |
|
| 435 |
gen_set_label(l2); |
|
| 436 |
} |
|
| 437 |
#endif |
|
| 438 |
} |
|
| 439 |
|
|
| 440 |
/* old op: |
|
| 441 |
if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31)) |
|
| 442 |
env->psr |= PSR_OVF; |
|
| 443 |
*/ |
|
| 444 |
static inline void gen_cc_V_add(TCGv dst, TCGv src1, TCGv src2) |
|
| 445 |
{
|
|
| 446 |
TCGv r_temp, r_temp2, r_temp3, r_zero; |
|
| 447 |
int l1; |
|
| 448 |
|
|
| 449 |
l1 = gen_new_label(); |
|
| 450 |
|
|
| 451 |
r_temp = tcg_temp_new(TCG_TYPE_TL); |
|
| 452 |
r_temp2 = tcg_temp_new(TCG_TYPE_TL); |
|
| 453 |
r_temp3 = tcg_temp_new(TCG_TYPE_TL); |
|
| 454 |
r_zero = tcg_temp_new(TCG_TYPE_TL); |
|
| 455 |
tcg_gen_movi_tl(r_zero, 0); |
|
| 456 |
tcg_gen_xor_tl(r_temp, src1, src2); |
|
| 457 |
tcg_gen_xori_tl(r_temp, r_temp, -1); |
|
| 458 |
tcg_gen_xor_tl(r_temp2, src1, dst); |
|
| 459 |
tcg_gen_and_tl(r_temp, r_temp, r_temp2); |
|
| 460 |
tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31)); |
|
| 461 |
tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1); |
|
| 462 |
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
|
| 463 |
gen_set_label(l1); |
|
| 464 |
#ifdef TARGET_SPARC64 |
|
| 465 |
{
|
|
| 466 |
int l2; |
|
| 467 |
|
|
| 468 |
l2 = gen_new_label(); |
|
| 469 |
tcg_gen_movi_tl(r_zero, 0); |
|
| 470 |
tcg_gen_xor_tl(r_temp, src1, src2); |
|
| 471 |
tcg_gen_xori_tl(r_temp, r_temp, -1); |
|
| 472 |
tcg_gen_xor_tl(r_temp2, src1, dst); |
|
| 473 |
tcg_gen_and_tl(r_temp, r_temp, r_temp2); |
|
| 474 |
tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63)); |
|
| 475 |
tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2); |
|
| 476 |
tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF); |
|
| 477 |
gen_set_label(l2); |
|
| 478 |
} |
|
| 479 |
#endif |
|
| 480 |
} |
|
| 481 |
|
|
| 482 |
static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) |
|
| 483 |
{
|
|
| 484 |
TCGv r_temp, r_temp2, r_temp3, r_zero; |
|
| 485 |
int l1; |
|
| 486 |
|
|
| 487 |
l1 = gen_new_label(); |
|
| 488 |
|
|
| 489 |
r_temp = tcg_temp_new(TCG_TYPE_TL); |
|
| 490 |
r_temp2 = tcg_temp_new(TCG_TYPE_TL); |
|
| 491 |
r_temp3 = tcg_temp_new(TCG_TYPE_TL); |
|
| 492 |
r_zero = tcg_temp_new(TCG_TYPE_TL); |
|
| 493 |
tcg_gen_movi_tl(r_zero, 0); |
|
| 494 |
tcg_gen_xor_tl(r_temp, src1, src2); |
|
| 495 |
tcg_gen_xori_tl(r_temp, r_temp, -1); |
|
| 496 |
tcg_gen_xor_tl(r_temp2, src1, dst); |
|
| 497 |
tcg_gen_and_tl(r_temp, r_temp, r_temp2); |
|
| 498 |
tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31)); |
|
| 499 |
tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1); |
|
| 500 |
gen_op_exception(TT_TOVF); |
|
| 501 |
gen_set_label(l1); |
|
| 502 |
#ifdef TARGET_SPARC64 |
|
| 503 |
{
|
|
| 504 |
int l2; |
|
| 505 |
|
|
| 506 |
l2 = gen_new_label(); |
|
| 507 |
tcg_gen_movi_tl(r_zero, 0); |
|
| 508 |
tcg_gen_xor_tl(r_temp, src1, src2); |
|
| 509 |
tcg_gen_xori_tl(r_temp, r_temp, -1); |
|
| 510 |
tcg_gen_xor_tl(r_temp2, src1, dst); |
|
| 511 |
tcg_gen_and_tl(r_temp, r_temp, r_temp2); |
|
| 512 |
tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63)); |
|
| 513 |
tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2); |
|
| 514 |
gen_op_exception(TT_TOVF); |
|
| 515 |
gen_set_label(l2); |
|
| 516 |
} |
|
| 517 |
#endif |
|
| 518 |
} |
|
| 519 |
|
|
| 520 |
static inline void gen_cc_V_tag(TCGv src1, TCGv src2) |
|
| 521 |
{
|
|
| 522 |
int l1; |
|
| 523 |
TCGv r_zero, r_temp; |
|
| 524 |
|
|
| 525 |
l1 = gen_new_label(); |
|
| 526 |
r_zero = tcg_temp_new(TCG_TYPE_TL); |
|
| 527 |
r_temp = tcg_temp_new(TCG_TYPE_TL); |
|
| 528 |
tcg_gen_movi_tl(r_zero, 0); |
|
| 529 |
tcg_gen_or_tl(r_temp, src1, src2); |
|
| 530 |
tcg_gen_andi_tl(r_temp, r_temp, 0x3); |
|
| 531 |
tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, r_zero, l1); |
|
| 532 |
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
|
| 533 |
gen_set_label(l1); |
|
| 534 |
} |
|
| 535 |
|
|
| 536 |
static inline void gen_tag_tv(TCGv src1, TCGv src2) |
|
| 537 |
{
|
|
| 538 |
int l1; |
|
| 539 |
TCGv r_zero, r_temp; |
|
| 540 |
|
|
| 541 |
l1 = gen_new_label(); |
|
| 542 |
r_zero = tcg_temp_new(TCG_TYPE_TL); |
|
| 543 |
r_temp = tcg_temp_new(TCG_TYPE_TL); |
|
| 544 |
tcg_gen_movi_tl(r_zero, 0); |
|
| 545 |
tcg_gen_or_tl(r_temp, src1, src2); |
|
| 546 |
tcg_gen_andi_tl(r_temp, r_temp, 0x3); |
|
| 547 |
tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, r_zero, l1); |
|
| 548 |
gen_op_exception(TT_TOVF); |
|
| 549 |
gen_set_label(l1); |
|
| 550 |
} |
|
| 551 |
|
|
| 552 |
static inline void gen_op_add_T1_T0_cc(void) |
|
| 553 |
{
|
|
| 554 |
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
|
| 555 |
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
|
| 556 |
gen_cc_clear(); |
|
| 557 |
gen_cc_NZ(cpu_T[0]); |
|
| 558 |
gen_cc_C_add(cpu_T[0], cpu_cc_src); |
|
| 559 |
gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]); |
|
| 560 |
} |
|
| 561 |
|
|
| 562 |
static inline void gen_op_addx_T1_T0_cc(void) |
|
| 563 |
{
|
|
| 564 |
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
|
| 565 |
gen_mov_reg_C(cpu_tmp0, cpu_psr); |
|
| 566 |
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
|
| 567 |
gen_cc_clear(); |
|
| 568 |
gen_cc_C_add(cpu_T[0], cpu_cc_src); |
|
| 569 |
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
|
| 570 |
gen_cc_C_add(cpu_T[0], cpu_cc_src); |
|
| 571 |
gen_cc_NZ(cpu_T[0]); |
|
| 572 |
gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]); |
|
| 573 |
} |
|
| 574 |
|
|
| 575 |
static inline void gen_op_tadd_T1_T0_cc(void) |
|
| 576 |
{
|
|
| 577 |
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
|
| 578 |
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
|
| 579 |
gen_cc_clear(); |
|
| 580 |
gen_cc_NZ(cpu_T[0]); |
|
| 581 |
gen_cc_C_add(cpu_T[0], cpu_cc_src); |
|
| 582 |
gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]); |
|
| 583 |
gen_cc_V_tag(cpu_cc_src, cpu_T[1]); |
|
| 584 |
} |
|
| 585 |
|
|
| 586 |
static inline void gen_op_tadd_T1_T0_ccTV(void) |
|
| 587 |
{
|
|
| 588 |
gen_tag_tv(cpu_T[0], cpu_T[1]); |
|
| 589 |
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
|
| 590 |
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
|
| 591 |
gen_add_tv(cpu_T[0], cpu_cc_src, cpu_T[1]); |
|
| 592 |
gen_cc_clear(); |
|
| 593 |
gen_cc_NZ(cpu_T[0]); |
|
| 594 |
gen_cc_C_add(cpu_T[0], cpu_cc_src); |
|
| 595 |
} |
|
| 596 |
|
|
| 597 |
/* old op: |
|
| 598 |
if (src1 < T1) |
|
| 599 |
env->psr |= PSR_CARRY; |
|
| 600 |
*/ |
|
| 601 |
static inline void gen_cc_C_sub(TCGv src1, TCGv src2) |
|
| 602 |
{
|
|
| 603 |
int l1; |
|
| 604 |
|
|
| 605 |
l1 = gen_new_label(); |
|
| 606 |
tcg_gen_brcond_i32(TCG_COND_GEU, src1, src2, l1); |
|
| 607 |
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
|
| 608 |
gen_set_label(l1); |
|
| 609 |
#ifdef TARGET_SPARC64 |
|
| 610 |
{
|
|
| 611 |
int l2; |
|
| 612 |
|
|
| 613 |
l2 = gen_new_label(); |
|
| 614 |
tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l2); |
|
| 615 |
tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); |
|
| 616 |
gen_set_label(l2); |
|
| 617 |
} |
|
| 618 |
#endif |
|
| 619 |
} |
|
| 620 |
|
|
| 621 |
/* old op: |
|
| 622 |
if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31)) |
|
| 623 |
env->psr |= PSR_OVF; |
|
| 624 |
*/ |
|
| 625 |
static inline void gen_cc_V_sub(TCGv dst, TCGv src1, TCGv src2) |
|
| 626 |
{
|
|
| 627 |
TCGv r_temp, r_temp2, r_temp3, r_zero; |
|
| 628 |
int l1; |
|
| 629 |
|
|
| 630 |
l1 = gen_new_label(); |
|
| 631 |
|
|
| 632 |
r_temp = tcg_temp_new(TCG_TYPE_TL); |
|
| 633 |
r_temp2 = tcg_temp_new(TCG_TYPE_TL); |
|
| 634 |
r_temp3 = tcg_temp_new(TCG_TYPE_TL); |
|
| 635 |
r_zero = tcg_temp_new(TCG_TYPE_TL); |
|
| 636 |
tcg_gen_movi_tl(r_zero, 0); |
|
| 637 |
tcg_gen_xor_tl(r_temp, src1, src2); |
|
| 638 |
tcg_gen_xor_tl(r_temp2, src1, dst); |
|
| 639 |
tcg_gen_and_tl(r_temp, r_temp, r_temp2); |
|
| 640 |
tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31)); |
|
| 641 |
tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1); |
|
| 642 |
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
|
| 643 |
gen_set_label(l1); |
|
| 644 |
#ifdef TARGET_SPARC64 |
|
| 645 |
{
|
|
| 646 |
int l2; |
|
| 647 |
|
|
| 648 |
l2 = gen_new_label(); |
|
| 649 |
tcg_gen_movi_tl(r_zero, 0); |
|
| 650 |
tcg_gen_xor_tl(r_temp, src1, src2); |
|
| 651 |
tcg_gen_xor_tl(r_temp2, src1, dst); |
|
| 652 |
tcg_gen_and_tl(r_temp, r_temp, r_temp2); |
|
| 653 |
tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63)); |
|
| 654 |
tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2); |
|
| 655 |
tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF); |
|
| 656 |
gen_set_label(l2); |
|
| 657 |
} |
|
| 658 |
#endif |
|
| 659 |
} |
|
| 660 |
|
|
| 661 |
static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) |
|
| 662 |
{
|
|
| 663 |
TCGv r_temp, r_temp2, r_temp3, r_zero; |
|
| 664 |
int l1; |
|
| 665 |
|
|
| 666 |
l1 = gen_new_label(); |
|
| 667 |
|
|
| 668 |
r_temp = tcg_temp_new(TCG_TYPE_TL); |
|
| 669 |
r_temp2 = tcg_temp_new(TCG_TYPE_TL); |
|
| 670 |
r_temp3 = tcg_temp_new(TCG_TYPE_TL); |
|
| 671 |
r_zero = tcg_temp_new(TCG_TYPE_TL); |
|
| 672 |
tcg_gen_movi_tl(r_zero, 0); |
|
| 673 |
tcg_gen_xor_tl(r_temp, src1, src2); |
|
| 674 |
tcg_gen_xor_tl(r_temp2, src1, dst); |
|
| 675 |
tcg_gen_and_tl(r_temp, r_temp, r_temp2); |
|
| 676 |
tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31)); |
|
| 677 |
tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1); |
|
| 678 |
gen_op_exception(TT_TOVF); |
|
| 679 |
gen_set_label(l1); |
|
| 680 |
#ifdef TARGET_SPARC64 |
|
| 681 |
{
|
|
| 682 |
int l2; |
|
| 683 |
|
|
| 684 |
l2 = gen_new_label(); |
|
| 685 |
tcg_gen_movi_tl(r_zero, 0); |
|
| 686 |
tcg_gen_xor_tl(r_temp, src1, src2); |
|
| 687 |
tcg_gen_xor_tl(r_temp2, src1, dst); |
|
| 688 |
tcg_gen_and_tl(r_temp, r_temp, r_temp2); |
|
| 689 |
tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63)); |
|
| 690 |
tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2); |
|
| 691 |
gen_op_exception(TT_TOVF); |
|
| 692 |
gen_set_label(l2); |
|
| 693 |
} |
|
| 694 |
#endif |
|
| 695 |
} |
|
| 696 |
|
|
| 697 |
static inline void gen_op_sub_T1_T0_cc(void) |
|
| 698 |
{
|
|
| 699 |
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
|
| 700 |
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
|
| 701 |
gen_cc_clear(); |
|
| 702 |
gen_cc_NZ(cpu_T[0]); |
|
| 703 |
gen_cc_C_sub(cpu_cc_src, cpu_T[1]); |
|
| 704 |
gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]); |
|
| 705 |
} |
|
| 706 |
|
|
| 707 |
static inline void gen_op_subx_T1_T0_cc(void) |
|
| 708 |
{
|
|
| 709 |
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
|
| 710 |
gen_mov_reg_C(cpu_tmp0, cpu_psr); |
|
| 711 |
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
|
| 712 |
gen_cc_clear(); |
|
| 713 |
gen_cc_C_sub(cpu_T[0], cpu_cc_src); |
|
| 714 |
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
|
| 715 |
gen_cc_C_sub(cpu_T[0], cpu_cc_src); |
|
| 716 |
gen_cc_NZ(cpu_T[0]); |
|
| 717 |
gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]); |
|
| 718 |
} |
|
| 719 |
|
|
| 720 |
static inline void gen_op_tsub_T1_T0_cc(void) |
|
| 721 |
{
|
|
| 722 |
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
|
| 723 |
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
|
| 724 |
gen_cc_clear(); |
|
| 725 |
gen_cc_NZ(cpu_T[0]); |
|
| 726 |
gen_cc_C_sub(cpu_cc_src, cpu_T[1]); |
|
| 727 |
gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]); |
|
| 728 |
gen_cc_V_tag(cpu_cc_src, cpu_T[1]); |
|
| 729 |
} |
|
| 730 |
|
|
| 731 |
static inline void gen_op_tsub_T1_T0_ccTV(void) |
|
| 732 |
{
|
|
| 733 |
gen_tag_tv(cpu_T[0], cpu_T[1]); |
|
| 734 |
tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
|
| 735 |
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
|
| 736 |
gen_sub_tv(cpu_T[0], cpu_cc_src, cpu_T[1]); |
|
| 737 |
gen_cc_clear(); |
|
| 738 |
gen_cc_NZ(cpu_T[0]); |
|
| 739 |
gen_cc_C_sub(cpu_cc_src, cpu_T[1]); |
|
| 740 |
} |
|
| 741 |
|
|
| 742 |
static inline void gen_op_div_cc(void) |
|
| 743 |
{
|
|
| 744 |
int l1; |
|
| 745 |
TCGv r_zero; |
|
| 746 |
|
|
| 747 |
gen_cc_clear(); |
|
| 748 |
gen_cc_NZ(cpu_T[0]); |
|
| 749 |
l1 = gen_new_label(); |
|
| 750 |
r_zero = tcg_temp_new(TCG_TYPE_TL); |
|
| 751 |
tcg_gen_movi_tl(r_zero, 0); |
|
| 752 |
tcg_gen_brcond_i32(TCG_COND_EQ, cpu_T[1], r_zero, l1); |
|
| 753 |
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
|
| 754 |
gen_set_label(l1); |
|
| 755 |
} |
|
| 756 |
|
|
| 757 |
static inline void gen_op_logic_T0_cc(void) |
|
| 758 |
{
|
|
| 759 |
gen_cc_clear(); |
|
| 760 |
gen_cc_NZ(cpu_T[0]); |
|
| 761 |
} |
|
| 762 |
|
|
| 359 | 763 |
// 1 |
| 360 | 764 |
static inline void gen_op_eval_ba(TCGv dst) |
| 361 | 765 |
{
|
| ... | ... | |
| 789 | 1193 |
{
|
| 790 | 1194 |
TCGv r_src; |
| 791 | 1195 |
|
| 792 |
r_src = tcg_temp_new(TCG_TYPE_TL); |
|
| 793 | 1196 |
#ifdef TARGET_SPARC64 |
| 794 | 1197 |
if (cc) |
| 795 |
tcg_gen_ld_i32(r_src, cpu_env, offsetof(CPUSPARCState, xcc));
|
|
| 1198 |
r_src = cpu_xcc;
|
|
| 796 | 1199 |
else |
| 797 |
tcg_gen_ld_i32(r_src, cpu_env, offsetof(CPUSPARCState, psr));
|
|
| 1200 |
r_src = cpu_psr;
|
|
| 798 | 1201 |
#else |
| 799 |
tcg_gen_ld_i32(r_src, cpu_env, offsetof(CPUSPARCState, psr));
|
|
| 1202 |
r_src = cpu_psr;
|
|
| 800 | 1203 |
#endif |
| 801 | 1204 |
switch (cond) {
|
| 802 | 1205 |
case 0x0: |
| ... | ... | |
| 1170 | 1573 |
|
| 1171 | 1574 |
#endif |
| 1172 | 1575 |
|
| 1173 |
static inline void gen_op_exception(int exception) |
|
| 1174 |
{
|
|
| 1175 |
TCGv r_except; |
|
| 1176 |
|
|
| 1177 |
r_except = tcg_temp_new(TCG_TYPE_I32); |
|
| 1178 |
tcg_gen_movi_i32(r_except, exception); |
|
| 1179 |
tcg_gen_helper_0_1(raise_exception, r_except); |
|
| 1180 |
} |
|
| 1181 |
|
|
| 1182 | 1576 |
static inline void gen_op_fpexception_im(int fsr_flags) |
| 1183 | 1577 |
{
|
| 1184 | 1578 |
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr)); |
| ... | ... | |
| 2632 | 3026 |
if (xop & 0x10) |
| 2633 | 3027 |
gen_op_addx_T1_T0_cc(); |
| 2634 | 3028 |
else {
|
| 2635 |
tcg_gen_ld_i32(cpu_tmp0, cpu_env, |
|
| 2636 |
offsetof(CPUSPARCState, psr)); |
|
| 2637 |
gen_mov_reg_C(cpu_tmp0, cpu_tmp0); |
|
| 3029 |
gen_mov_reg_C(cpu_tmp0, cpu_psr); |
|
| 2638 | 3030 |
tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0); |
| 2639 | 3031 |
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
| 2640 | 3032 |
} |
| ... | ... | |
| 2658 | 3050 |
if (xop & 0x10) |
| 2659 | 3051 |
gen_op_subx_T1_T0_cc(); |
| 2660 | 3052 |
else {
|
| 2661 |
tcg_gen_ld_i32(cpu_tmp0, cpu_env, |
|
| 2662 |
offsetof(CPUSPARCState, psr)); |
|
| 2663 |
gen_mov_reg_C(cpu_tmp0, cpu_tmp0); |
|
| 3053 |
gen_mov_reg_C(cpu_tmp0, cpu_psr); |
|
| 2664 | 3054 |
tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0); |
| 2665 | 3055 |
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
| 2666 | 3056 |
} |
| ... | ... | |
| 4345 | 4735 |
TCG_AREG0, offsetof(CPUState, t1), "T1"); |
| 4346 | 4736 |
cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL, |
| 4347 | 4737 |
TCG_AREG0, offsetof(CPUState, t2), "T2"); |
| 4738 |
cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32, |
|
| 4739 |
TCG_AREG0, offsetof(CPUState, xcc), |
|
| 4740 |
"xcc"); |
|
| 4348 | 4741 |
#else |
| 4349 | 4742 |
cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0"); |
| 4350 | 4743 |
cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1"); |
| 4351 | 4744 |
cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2"); |
| 4352 | 4745 |
#endif |
| 4746 |
cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL, |
|
| 4747 |
TCG_AREG0, offsetof(CPUState, cc_src), |
|
| 4748 |
"cc_src"); |
|
| 4749 |
cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL, |
|
| 4750 |
TCG_AREG0, offsetof(CPUState, cc_dst), |
|
| 4751 |
"cc_dst"); |
|
| 4752 |
cpu_psr = tcg_global_mem_new(TCG_TYPE_I32, |
|
| 4753 |
TCG_AREG0, offsetof(CPUState, psr), |
|
| 4754 |
"psr"); |
|
| 4353 | 4755 |
} |
| 4354 | 4756 |
|
| 4355 | 4757 |
cpu_reset(env); |
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