Revision dcac9679 hw/mips_jazz.c
| b/hw/mips_jazz.c | ||
|---|---|---|
| 129 | 129 |
enum jazz_model_e jazz_model) |
| 130 | 130 |
{
|
| 131 | 131 |
char buf[1024]; |
| 132 |
unsigned long bios_offset; |
|
| 133 | 132 |
int bios_size, n; |
| 134 | 133 |
CPUState *env; |
| 135 | 134 |
qemu_irq *rc4030, *i8259; |
| ... | ... | |
| 141 | 140 |
PITState *pit; |
| 142 | 141 |
BlockDriverState *fds[MAX_FD]; |
| 143 | 142 |
qemu_irq esp_reset; |
| 143 |
ram_addr_t ram_offset; |
|
| 144 |
ram_addr_t bios_offset; |
|
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ram_addr_t vga_ram_offset; |
|
| 144 | 146 |
|
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/* init CPUs */ |
| 146 | 148 |
if (cpu_model == NULL) {
|
| ... | ... | |
| 159 | 161 |
qemu_register_reset(main_cpu_reset, env); |
| 160 | 162 |
|
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/* allocate RAM */ |
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cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); |
|
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ram_offset = qemu_ram_alloc(ram_size); |
|
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cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); |
|
| 166 |
|
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vga_ram_offset = qemu_ram_alloc(vga_ram_size); |
|
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bios_offset = qemu_ram_alloc(MAGNUM_BIOS_SIZE); |
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cpu_register_physical_memory(0x1fc00000LL, |
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MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM); |
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cpu_register_physical_memory(0xfff00000LL, |
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MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM); |
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| 163 | 173 |
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/* load the BIOS image. */ |
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bios_offset = ram_size + vga_ram_size; |
|
| 166 | 175 |
if (bios_name == NULL) |
| 167 | 176 |
bios_name = BIOS_FILENAME; |
| 168 | 177 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
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bios_size = load_image(buf, phys_ram_base + bios_offset);
|
|
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bios_size = load_image_targphys(buf, 0xfff00000LL, MAGNUM_BIOS_SIZE);
|
|
| 170 | 179 |
if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
|
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fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n", |
| 172 | 181 |
buf); |
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exit(1); |
| 174 | 183 |
} |
| 175 | 184 |
|
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cpu_register_physical_memory(0x1fc00000LL, |
|
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MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM); |
|
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cpu_register_physical_memory(0xfff00000LL, |
|
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MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM); |
|
| 180 |
|
|
| 181 | 185 |
/* Init CPU internal devices */ |
| 182 | 186 |
cpu_mips_irq_init_cpu(env); |
| 183 | 187 |
cpu_mips_clock_init(env); |
| ... | ... | |
| 201 | 205 |
/* Video card */ |
| 202 | 206 |
switch (jazz_model) {
|
| 203 | 207 |
case JAZZ_MAGNUM: |
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g364fb_mm_init(phys_ram_base + ram_size, ram_size, vga_ram_size,
|
|
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g364fb_mm_init(phys_ram_base + vga_ram_offset, ram_size, vga_ram_size,
|
|
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0x40000000, 0x60000000, 0, rc4030[3]); |
| 206 | 210 |
break; |
| 207 | 211 |
case JAZZ_PICA61: |
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isa_vga_mm_init(phys_ram_base + ram_size, ram_size, vga_ram_size,
|
|
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isa_vga_mm_init(phys_ram_base + vga_ram_offset, ram_size, vga_ram_size,
|
|
| 209 | 213 |
0x40000000, 0x60000000, 0); |
| 210 | 214 |
break; |
| 211 | 215 |
default: |
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