root / hw / char / grlib_apbuart.c @ dccfcd0e
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/*
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* QEMU GRLIB APB UART Emulator
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*
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* Copyright (c) 2010-2011 AdaCore
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/sysbus.h" |
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#include "sysemu/char.h" |
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#include "trace.h" |
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#define UART_REG_SIZE 20 /* Size of memory mapped registers */ |
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/* UART status register fields */
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#define UART_DATA_READY (1 << 0) |
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#define UART_TRANSMIT_SHIFT_EMPTY (1 << 1) |
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#define UART_TRANSMIT_FIFO_EMPTY (1 << 2) |
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#define UART_BREAK_RECEIVED (1 << 3) |
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#define UART_OVERRUN (1 << 4) |
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#define UART_PARITY_ERROR (1 << 5) |
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#define UART_FRAMING_ERROR (1 << 6) |
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#define UART_TRANSMIT_FIFO_HALF (1 << 7) |
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#define UART_RECEIVE_FIFO_HALF (1 << 8) |
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#define UART_TRANSMIT_FIFO_FULL (1 << 9) |
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#define UART_RECEIVE_FIFO_FULL (1 << 10) |
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/* UART control register fields */
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#define UART_RECEIVE_ENABLE (1 << 0) |
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#define UART_TRANSMIT_ENABLE (1 << 1) |
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#define UART_RECEIVE_INTERRUPT (1 << 2) |
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#define UART_TRANSMIT_INTERRUPT (1 << 3) |
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#define UART_PARITY_SELECT (1 << 4) |
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#define UART_PARITY_ENABLE (1 << 5) |
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#define UART_FLOW_CONTROL (1 << 6) |
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#define UART_LOOPBACK (1 << 7) |
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#define UART_EXTERNAL_CLOCK (1 << 8) |
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#define UART_RECEIVE_FIFO_INTERRUPT (1 << 9) |
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#define UART_TRANSMIT_FIFO_INTERRUPT (1 << 10) |
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#define UART_FIFO_DEBUG_MODE (1 << 11) |
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#define UART_OUTPUT_ENABLE (1 << 12) |
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#define UART_FIFO_AVAILABLE (1 << 31) |
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/* Memory mapped register offsets */
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#define DATA_OFFSET 0x00 |
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#define STATUS_OFFSET 0x04 |
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#define CONTROL_OFFSET 0x08 |
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#define SCALER_OFFSET 0x0C /* not supported */ |
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#define FIFO_DEBUG_OFFSET 0x10 /* not supported */ |
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#define FIFO_LENGTH 1024 |
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typedef struct UART { |
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SysBusDevice busdev; |
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MemoryRegion iomem; |
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qemu_irq irq; |
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CharDriverState *chr; |
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/* registers */
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uint32_t status; |
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uint32_t control; |
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/* FIFO */
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char buffer[FIFO_LENGTH];
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int len;
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int current;
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} UART; |
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static int uart_data_to_read(UART *uart) |
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{ |
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return uart->current < uart->len;
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} |
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static char uart_pop(UART *uart) |
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{ |
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char ret;
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if (uart->len == 0) { |
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uart->status &= ~UART_DATA_READY; |
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return 0; |
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} |
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ret = uart->buffer[uart->current++]; |
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if (uart->current >= uart->len) {
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/* Flush */
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uart->len = 0;
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uart->current = 0;
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} |
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if (!uart_data_to_read(uart)) {
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uart->status &= ~UART_DATA_READY; |
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} |
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return ret;
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} |
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static void uart_add_to_fifo(UART *uart, |
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const uint8_t *buffer,
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int length)
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{ |
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if (uart->len + length > FIFO_LENGTH) {
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abort(); |
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} |
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memcpy(uart->buffer + uart->len, buffer, length); |
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uart->len += length; |
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} |
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static int grlib_apbuart_can_receive(void *opaque) |
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{ |
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UART *uart = opaque; |
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return FIFO_LENGTH - uart->len;
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} |
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static void grlib_apbuart_receive(void *opaque, const uint8_t *buf, int size) |
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{ |
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UART *uart = opaque; |
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if (uart->control & UART_RECEIVE_ENABLE) {
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uart_add_to_fifo(uart, buf, size); |
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uart->status |= UART_DATA_READY; |
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if (uart->control & UART_RECEIVE_INTERRUPT) {
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qemu_irq_pulse(uart->irq); |
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} |
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} |
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} |
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static void grlib_apbuart_event(void *opaque, int event) |
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{ |
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trace_grlib_apbuart_event(event); |
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} |
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static uint64_t grlib_apbuart_read(void *opaque, hwaddr addr, |
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unsigned size)
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{ |
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UART *uart = opaque; |
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addr &= 0xff;
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/* Unit registers */
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switch (addr) {
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case DATA_OFFSET:
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case DATA_OFFSET + 3: /* when only one byte read */ |
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return uart_pop(uart);
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case STATUS_OFFSET:
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/* Read Only */
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return uart->status;
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case CONTROL_OFFSET:
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return uart->control;
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case SCALER_OFFSET:
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/* Not supported */
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return 0; |
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default:
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trace_grlib_apbuart_readl_unknown(addr); |
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return 0; |
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} |
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} |
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static void grlib_apbuart_write(void *opaque, hwaddr addr, |
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uint64_t value, unsigned size)
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{ |
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UART *uart = opaque; |
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unsigned char c = 0; |
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addr &= 0xff;
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/* Unit registers */
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switch (addr) {
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case DATA_OFFSET:
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case DATA_OFFSET + 3: /* When only one byte write */ |
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/* Transmit when character device available and transmitter enabled */
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if ((uart->chr) && (uart->control & UART_TRANSMIT_ENABLE)) {
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c = value & 0xFF;
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qemu_chr_fe_write(uart->chr, &c, 1);
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/* Generate interrupt */
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if (uart->control & UART_TRANSMIT_INTERRUPT) {
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qemu_irq_pulse(uart->irq); |
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} |
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} |
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return;
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case STATUS_OFFSET:
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/* Read Only */
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return;
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case CONTROL_OFFSET:
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uart->control = value; |
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return;
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case SCALER_OFFSET:
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/* Not supported */
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return;
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default:
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break;
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} |
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trace_grlib_apbuart_writel_unknown(addr, value); |
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} |
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static const MemoryRegionOps grlib_apbuart_ops = { |
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.write = grlib_apbuart_write, |
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.read = grlib_apbuart_read, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
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}; |
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static int grlib_apbuart_init(SysBusDevice *dev) |
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{ |
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UART *uart = FROM_SYSBUS(typeof(*uart), dev); |
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qemu_chr_add_handlers(uart->chr, |
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grlib_apbuart_can_receive, |
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grlib_apbuart_receive, |
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grlib_apbuart_event, |
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uart); |
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sysbus_init_irq(dev, &uart->irq); |
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memory_region_init_io(&uart->iomem, &grlib_apbuart_ops, uart, |
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"uart", UART_REG_SIZE);
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sysbus_init_mmio(dev, &uart->iomem); |
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return 0; |
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} |
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static void grlib_apbuart_reset(DeviceState *d) |
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{ |
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UART *uart = container_of(d, UART, busdev.qdev); |
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/* Transmitter FIFO and shift registers are always empty in QEMU */
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uart->status = UART_TRANSMIT_FIFO_EMPTY | UART_TRANSMIT_SHIFT_EMPTY; |
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/* Everything is off */
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uart->control = 0;
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/* Flush receive FIFO */
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uart->len = 0;
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uart->current = 0;
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} |
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static Property grlib_apbuart_properties[] = {
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DEFINE_PROP_CHR("chrdev", UART, chr),
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DEFINE_PROP_END_OF_LIST(), |
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}; |
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static void grlib_apbuart_class_init(ObjectClass *klass, void *data) |
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{ |
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DeviceClass *dc = DEVICE_CLASS(klass); |
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
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k->init = grlib_apbuart_init; |
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dc->reset = grlib_apbuart_reset; |
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dc->props = grlib_apbuart_properties; |
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} |
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static const TypeInfo grlib_apbuart_info = { |
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.name = "grlib,apbuart",
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.parent = TYPE_SYS_BUS_DEVICE, |
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.instance_size = sizeof(UART),
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.class_init = grlib_apbuart_class_init, |
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}; |
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static void grlib_apbuart_register_types(void) |
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{ |
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type_register_static(&grlib_apbuart_info); |
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} |
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type_init(grlib_apbuart_register_types) |