Revision dcfd14b3

b/cpu-exec.c
704 704
    return ret;
705 705
}
706 706

  
707
/* must only be called from the generated code as an exception can be
708
   generated */
709
void tb_invalidate_page_range(target_ulong start, target_ulong end)
710
{
711
    /* XXX: cannot enable it yet because it yields to MMU exception
712
       where NIP != read address on PowerPC */
713
#if 0
714
    target_ulong phys_addr;
715
    phys_addr = get_phys_addr_code(env, start);
716
    tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
717
#endif
718
}
719

  
720 707
#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
721 708

  
722 709
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
b/exec-all.h
95 95
int page_unprotect(target_ulong address, unsigned long pc, void *puc);
96 96
void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
97 97
                                   int is_cpu_write_access);
98
void tb_invalidate_page_range(target_ulong start, target_ulong end);
99 98
void tlb_flush_page(CPUState *env, target_ulong addr);
100 99
void tlb_flush(CPUState *env, int flush_global);
101 100
#if !defined(CONFIG_USER_ONLY)
b/linux-user/main.c
455 455

  
456 456
#ifdef TARGET_ARM
457 457

  
458
static void arm_cache_flush(abi_ulong start, abi_ulong last)
459
{
460
    abi_ulong addr, last1;
461

  
462
    if (last < start)
463
        return;
464
    addr = start;
465
    for(;;) {
466
        last1 = ((addr + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK) - 1;
467
        if (last1 > last)
468
            last1 = last;
469
        tb_invalidate_page_range(addr, last1 + 1);
470
        if (last1 == last)
471
            break;
472
        addr = last1 + 1;
473
    }
474
}
475

  
476 458
/* Handle a jump to the kernel code page.  */
477 459
static int
478 460
do_kernel_trap(CPUARMState *env)
......
717 699
                }
718 700

  
719 701
                if (n == ARM_NR_cacheflush) {
720
                    arm_cache_flush(env->regs[0], env->regs[1]);
702
                    /* nop */
721 703
                } else if (n == ARM_NR_semihosting
722 704
                           || n == ARM_NR_thumb_semihosting) {
723 705
                    env->regs[0] = do_arm_semihosting (env);
......
733 715
                    if ( n > ARM_NR_BASE) {
734 716
                        switch (n) {
735 717
                        case ARM_NR_cacheflush:
736
                            arm_cache_flush(env->regs[0], env->regs[1]);
718
                            /* nop */
737 719
                            break;
738 720
                        case ARM_NR_set_tls:
739 721
                            cpu_set_tls(env, env->regs[0]);
b/target-ppc/op_helper.c
362 362
     * do the load "by hand".
363 363
     */
364 364
    ldl(addr);
365
    tb_invalidate_page_range(addr, addr + env->icache_line_size);
366 365
}
367 366

  
368 367
// XXX: to be tested
b/target-sparc/helper.h
35 35
DEF_HELPER_0(debug, void)
36 36
DEF_HELPER_0(save, void)
37 37
DEF_HELPER_0(restore, void)
38
DEF_HELPER_1(flush, void, tl)
39 38
DEF_HELPER_2(udiv, tl, tl, tl)
40 39
DEF_HELPER_2(udiv_cc, tl, tl, tl)
41 40
DEF_HELPER_2(sdiv, tl, tl, tl)
b/target-sparc/op_helper.c
4092 4092
}
4093 4093
#endif
4094 4094

  
4095
void helper_flush(target_ulong addr)
4096
{
4097
    addr &= ~7;
4098
    tb_invalidate_page_range(addr, addr + 8);
4099
}
4100

  
4101 4095
#ifdef TARGET_SPARC64
4102 4096
#ifdef DEBUG_PCALL
4103 4097
static const char * const excp_names[0x80] = {
b/target-sparc/translate.c
4226 4226
                case 0x3b: /* flush */
4227 4227
                    if (!((dc)->def->features & CPU_FEATURE_FLUSH))
4228 4228
                        goto unimp_flush;
4229
                    gen_helper_flush(cpu_dst);
4229
                    /* nop */
4230 4230
                    break;
4231 4231
                case 0x3c:      /* save */
4232 4232
                    save_state(dc, cpu_cond);

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