root / hw / mc146818rtc.c @ dd17765b
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/*
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* QEMU MC146818 RTC emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "qemu-timer.h" |
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#include "sysemu.h" |
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#include "pc.h" |
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#include "isa.h" |
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#include "hpet_emul.h" |
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//#define DEBUG_CMOS
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#define RTC_REINJECT_ON_ACK_COUNT 20 |
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#define RTC_SECONDS 0 |
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#define RTC_SECONDS_ALARM 1 |
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#define RTC_MINUTES 2 |
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#define RTC_MINUTES_ALARM 3 |
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#define RTC_HOURS 4 |
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#define RTC_HOURS_ALARM 5 |
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#define RTC_ALARM_DONT_CARE 0xC0 |
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|
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#define RTC_DAY_OF_WEEK 6 |
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#define RTC_DAY_OF_MONTH 7 |
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#define RTC_MONTH 8 |
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#define RTC_YEAR 9 |
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|
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#define RTC_REG_A 10 |
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#define RTC_REG_B 11 |
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#define RTC_REG_C 12 |
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#define RTC_REG_D 13 |
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|
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#define REG_A_UIP 0x80 |
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|
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#define REG_B_SET 0x80 |
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#define REG_B_PIE 0x40 |
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#define REG_B_AIE 0x20 |
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#define REG_B_UIE 0x10 |
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#define REG_B_SQWE 0x08 |
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#define REG_B_DM 0x04 |
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|
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#define REG_C_UF 0x10 |
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#define REG_C_IRQF 0x80 |
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#define REG_C_PF 0x40 |
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#define REG_C_AF 0x20 |
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|
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struct RTCState {
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ISADevice dev; |
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uint8_t cmos_data[128];
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uint8_t cmos_index; |
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struct tm current_tm;
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int32_t base_year; |
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qemu_irq irq; |
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qemu_irq sqw_irq; |
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int it_shift;
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/* periodic timer */
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QEMUTimer *periodic_timer; |
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int64_t next_periodic_time; |
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/* second update */
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int64_t next_second_time; |
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uint16_t irq_reinject_on_ack_count; |
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uint32_t irq_coalesced; |
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uint32_t period; |
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QEMUTimer *coalesced_timer; |
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QEMUTimer *second_timer; |
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QEMUTimer *second_timer2; |
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}; |
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|
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static void rtc_irq_raise(qemu_irq irq) |
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{
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/* When HPET is operating in legacy mode, RTC interrupts are disabled
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* We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
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* mode is established while interrupt is raised. We want it to
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* be lowered in any case
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*/
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#if defined TARGET_I386
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if (!hpet_in_legacy_mode())
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#endif
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qemu_irq_raise(irq); |
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} |
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|
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static void rtc_set_time(RTCState *s); |
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static void rtc_copy_date(RTCState *s); |
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|
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#ifdef TARGET_I386
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static void rtc_coalesced_timer_update(RTCState *s) |
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{
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if (s->irq_coalesced == 0) { |
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qemu_del_timer(s->coalesced_timer); |
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} else {
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/* divide each RTC interval to 2 - 8 smaller intervals */
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int c = MIN(s->irq_coalesced, 7) + 1; |
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int64_t next_clock = qemu_get_clock(rtc_clock) + |
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muldiv64(s->period / c, get_ticks_per_sec(), 32768);
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qemu_mod_timer(s->coalesced_timer, next_clock); |
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} |
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} |
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static void rtc_coalesced_timer(void *opaque) |
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{
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RTCState *s = opaque; |
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|
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if (s->irq_coalesced != 0) { |
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apic_reset_irq_delivered(); |
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s->cmos_data[RTC_REG_C] |= 0xc0;
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rtc_irq_raise(s->irq); |
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if (apic_get_irq_delivered()) {
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s->irq_coalesced--; |
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} |
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} |
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|
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rtc_coalesced_timer_update(s); |
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} |
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#endif
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|
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static void rtc_timer_update(RTCState *s, int64_t current_time) |
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{
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int period_code, period;
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int64_t cur_clock, next_irq_clock; |
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int enable_pie;
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period_code = s->cmos_data[RTC_REG_A] & 0x0f;
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#if defined TARGET_I386
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/* disable periodic timer if hpet is in legacy mode, since interrupts are
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* disabled anyway.
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*/
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enable_pie = !hpet_in_legacy_mode(); |
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#else
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enable_pie = 1;
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#endif
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if (period_code != 0 |
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&& (((s->cmos_data[RTC_REG_B] & REG_B_PIE) && enable_pie) |
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|| ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
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if (period_code <= 2) |
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period_code += 7;
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/* period in 32 Khz cycles */
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period = 1 << (period_code - 1); |
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#ifdef TARGET_I386
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if(period != s->period)
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s->irq_coalesced = (s->irq_coalesced * s->period) / period; |
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s->period = period; |
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#endif
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/* compute 32 khz clock */
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cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
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next_irq_clock = (cur_clock & ~(period - 1)) + period;
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s->next_periodic_time = |
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muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1; |
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qemu_mod_timer(s->periodic_timer, s->next_periodic_time); |
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} else {
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#ifdef TARGET_I386
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s->irq_coalesced = 0;
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#endif
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qemu_del_timer(s->periodic_timer); |
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} |
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} |
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static void rtc_periodic_timer(void *opaque) |
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{
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RTCState *s = opaque; |
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rtc_timer_update(s, s->next_periodic_time); |
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if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
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s->cmos_data[RTC_REG_C] |= 0xc0;
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#ifdef TARGET_I386
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if(rtc_td_hack) {
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if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
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s->irq_reinject_on_ack_count = 0;
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apic_reset_irq_delivered(); |
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rtc_irq_raise(s->irq); |
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if (!apic_get_irq_delivered()) {
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s->irq_coalesced++; |
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rtc_coalesced_timer_update(s); |
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} |
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} else
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#endif
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rtc_irq_raise(s->irq); |
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} |
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if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
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/* Not square wave at all but we don't want 2048Hz interrupts!
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Must be seen as a pulse. */
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qemu_irq_raise(s->sqw_irq); |
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} |
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} |
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|
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static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) |
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{
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RTCState *s = opaque; |
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|
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if ((addr & 1) == 0) { |
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s->cmos_index = data & 0x7f;
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} else {
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#ifdef DEBUG_CMOS
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printf("cmos: write index=0x%02x val=0x%02x\n",
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s->cmos_index, data); |
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#endif
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switch(s->cmos_index) {
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case RTC_SECONDS_ALARM:
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case RTC_MINUTES_ALARM:
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case RTC_HOURS_ALARM:
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/* XXX: not supported */
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s->cmos_data[s->cmos_index] = data; |
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break;
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case RTC_SECONDS:
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case RTC_MINUTES:
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case RTC_HOURS:
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case RTC_DAY_OF_WEEK:
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case RTC_DAY_OF_MONTH:
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case RTC_MONTH:
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case RTC_YEAR:
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s->cmos_data[s->cmos_index] = data; |
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/* if in set mode, do not update the time */
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if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
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rtc_set_time(s); |
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} |
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break;
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case RTC_REG_A:
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/* UIP bit is read only */
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s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | |
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(s->cmos_data[RTC_REG_A] & REG_A_UIP); |
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rtc_timer_update(s, qemu_get_clock(rtc_clock)); |
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break;
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case RTC_REG_B:
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if (data & REG_B_SET) {
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/* set mode: reset UIP mode */
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s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
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data &= ~REG_B_UIE; |
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} else {
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/* if disabling set mode, update the time */
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if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
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rtc_set_time(s); |
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} |
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} |
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s->cmos_data[RTC_REG_B] = data; |
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rtc_timer_update(s, qemu_get_clock(rtc_clock)); |
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break;
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case RTC_REG_C:
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case RTC_REG_D:
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/* cannot write to them */
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break;
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default:
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s->cmos_data[s->cmos_index] = data; |
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break;
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} |
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} |
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} |
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|
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static inline int rtc_to_bcd(RTCState *s, int a) |
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{
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if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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return a;
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} else {
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return ((a / 10) << 4) | (a % 10); |
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} |
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} |
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static inline int rtc_from_bcd(RTCState *s, int a) |
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{
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if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
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return a;
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} else {
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return ((a >> 4) * 10) + (a & 0x0f); |
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} |
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} |
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|
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static void rtc_set_time(RTCState *s) |
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{
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struct tm *tm = &s->current_tm;
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|
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tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); |
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tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); |
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tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
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if (!(s->cmos_data[RTC_REG_B] & 0x02) && |
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(s->cmos_data[RTC_HOURS] & 0x80)) {
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tm->tm_hour += 12;
|
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} |
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tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
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tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); |
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tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
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tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
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} |
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|
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static void rtc_copy_date(RTCState *s) |
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{
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const struct tm *tm = &s->current_tm; |
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int year;
|
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|
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s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec); |
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s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min); |
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if (s->cmos_data[RTC_REG_B] & 0x02) { |
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/* 24 hour format */
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s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour); |
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} else {
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/* 12 hour format */
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s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour % 12);
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if (tm->tm_hour >= 12) |
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s->cmos_data[RTC_HOURS] |= 0x80;
|
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} |
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s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
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s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday); |
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s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
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year = (tm->tm_year - s->base_year) % 100;
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if (year < 0) |
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year += 100;
|
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s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year); |
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} |
| 326 |
|
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/* month is between 0 and 11. */
|
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static int get_days_in_month(int month, int year) |
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{
|
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static const int days_tab[12] = { |
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31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 |
| 332 |
}; |
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int d;
|
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if ((unsigned )month >= 12) |
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return 31; |
| 336 |
d = days_tab[month]; |
| 337 |
if (month == 1) { |
| 338 |
if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) |
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d++; |
| 340 |
} |
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return d;
|
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} |
| 343 |
|
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/* update 'tm' to the next second */
|
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static void rtc_next_second(struct tm *tm) |
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{
|
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int days_in_month;
|
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|
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tm->tm_sec++; |
| 350 |
if ((unsigned)tm->tm_sec >= 60) { |
| 351 |
tm->tm_sec = 0;
|
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tm->tm_min++; |
| 353 |
if ((unsigned)tm->tm_min >= 60) { |
| 354 |
tm->tm_min = 0;
|
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tm->tm_hour++; |
| 356 |
if ((unsigned)tm->tm_hour >= 24) { |
| 357 |
tm->tm_hour = 0;
|
| 358 |
/* next day */
|
| 359 |
tm->tm_wday++; |
| 360 |
if ((unsigned)tm->tm_wday >= 7) |
| 361 |
tm->tm_wday = 0;
|
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days_in_month = get_days_in_month(tm->tm_mon, |
| 363 |
tm->tm_year + 1900);
|
| 364 |
tm->tm_mday++; |
| 365 |
if (tm->tm_mday < 1) { |
| 366 |
tm->tm_mday = 1;
|
| 367 |
} else if (tm->tm_mday > days_in_month) { |
| 368 |
tm->tm_mday = 1;
|
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tm->tm_mon++; |
| 370 |
if (tm->tm_mon >= 12) { |
| 371 |
tm->tm_mon = 0;
|
| 372 |
tm->tm_year++; |
| 373 |
} |
| 374 |
} |
| 375 |
} |
| 376 |
} |
| 377 |
} |
| 378 |
} |
| 379 |
|
| 380 |
|
| 381 |
static void rtc_update_second(void *opaque) |
| 382 |
{
|
| 383 |
RTCState *s = opaque; |
| 384 |
int64_t delay; |
| 385 |
|
| 386 |
/* if the oscillator is not in normal operation, we do not update */
|
| 387 |
if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) { |
| 388 |
s->next_second_time += get_ticks_per_sec(); |
| 389 |
qemu_mod_timer(s->second_timer, s->next_second_time); |
| 390 |
} else {
|
| 391 |
rtc_next_second(&s->current_tm); |
| 392 |
|
| 393 |
if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
| 394 |
/* update in progress bit */
|
| 395 |
s->cmos_data[RTC_REG_A] |= REG_A_UIP; |
| 396 |
} |
| 397 |
/* should be 244 us = 8 / 32768 seconds, but currently the
|
| 398 |
timers do not have the necessary resolution. */
|
| 399 |
delay = (get_ticks_per_sec() * 1) / 100; |
| 400 |
if (delay < 1) |
| 401 |
delay = 1;
|
| 402 |
qemu_mod_timer(s->second_timer2, |
| 403 |
s->next_second_time + delay); |
| 404 |
} |
| 405 |
} |
| 406 |
|
| 407 |
static void rtc_update_second2(void *opaque) |
| 408 |
{
|
| 409 |
RTCState *s = opaque; |
| 410 |
|
| 411 |
if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
|
| 412 |
rtc_copy_date(s); |
| 413 |
} |
| 414 |
|
| 415 |
/* check alarm */
|
| 416 |
if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
|
| 417 |
if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 || |
| 418 |
s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) && |
| 419 |
((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 || |
| 420 |
s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) && |
| 421 |
((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 || |
| 422 |
s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {
|
| 423 |
|
| 424 |
s->cmos_data[RTC_REG_C] |= 0xa0;
|
| 425 |
rtc_irq_raise(s->irq); |
| 426 |
} |
| 427 |
} |
| 428 |
|
| 429 |
/* update ended interrupt */
|
| 430 |
s->cmos_data[RTC_REG_C] |= REG_C_UF; |
| 431 |
if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
|
| 432 |
s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
| 433 |
rtc_irq_raise(s->irq); |
| 434 |
} |
| 435 |
|
| 436 |
/* clear update in progress bit */
|
| 437 |
s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; |
| 438 |
|
| 439 |
s->next_second_time += get_ticks_per_sec(); |
| 440 |
qemu_mod_timer(s->second_timer, s->next_second_time); |
| 441 |
} |
| 442 |
|
| 443 |
static uint32_t cmos_ioport_read(void *opaque, uint32_t addr) |
| 444 |
{
|
| 445 |
RTCState *s = opaque; |
| 446 |
int ret;
|
| 447 |
if ((addr & 1) == 0) { |
| 448 |
return 0xff; |
| 449 |
} else {
|
| 450 |
switch(s->cmos_index) {
|
| 451 |
case RTC_SECONDS:
|
| 452 |
case RTC_MINUTES:
|
| 453 |
case RTC_HOURS:
|
| 454 |
case RTC_DAY_OF_WEEK:
|
| 455 |
case RTC_DAY_OF_MONTH:
|
| 456 |
case RTC_MONTH:
|
| 457 |
case RTC_YEAR:
|
| 458 |
ret = s->cmos_data[s->cmos_index]; |
| 459 |
break;
|
| 460 |
case RTC_REG_A:
|
| 461 |
ret = s->cmos_data[s->cmos_index]; |
| 462 |
break;
|
| 463 |
case RTC_REG_C:
|
| 464 |
ret = s->cmos_data[s->cmos_index]; |
| 465 |
qemu_irq_lower(s->irq); |
| 466 |
#ifdef TARGET_I386
|
| 467 |
if(s->irq_coalesced &&
|
| 468 |
s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
|
| 469 |
s->irq_reinject_on_ack_count++; |
| 470 |
apic_reset_irq_delivered(); |
| 471 |
qemu_irq_raise(s->irq); |
| 472 |
if (apic_get_irq_delivered())
|
| 473 |
s->irq_coalesced--; |
| 474 |
break;
|
| 475 |
} |
| 476 |
#endif
|
| 477 |
|
| 478 |
s->cmos_data[RTC_REG_C] = 0x00;
|
| 479 |
break;
|
| 480 |
default:
|
| 481 |
ret = s->cmos_data[s->cmos_index]; |
| 482 |
break;
|
| 483 |
} |
| 484 |
#ifdef DEBUG_CMOS
|
| 485 |
printf("cmos: read index=0x%02x val=0x%02x\n",
|
| 486 |
s->cmos_index, ret); |
| 487 |
#endif
|
| 488 |
return ret;
|
| 489 |
} |
| 490 |
} |
| 491 |
|
| 492 |
void rtc_set_memory(RTCState *s, int addr, int val) |
| 493 |
{
|
| 494 |
if (addr >= 0 && addr <= 127) |
| 495 |
s->cmos_data[addr] = val; |
| 496 |
} |
| 497 |
|
| 498 |
void rtc_set_date(RTCState *s, const struct tm *tm) |
| 499 |
{
|
| 500 |
s->current_tm = *tm; |
| 501 |
rtc_copy_date(s); |
| 502 |
} |
| 503 |
|
| 504 |
/* PC cmos mappings */
|
| 505 |
#define REG_IBM_CENTURY_BYTE 0x32 |
| 506 |
#define REG_IBM_PS2_CENTURY_BYTE 0x37 |
| 507 |
|
| 508 |
static void rtc_set_date_from_host(RTCState *s) |
| 509 |
{
|
| 510 |
struct tm tm;
|
| 511 |
int val;
|
| 512 |
|
| 513 |
/* set the CMOS date */
|
| 514 |
qemu_get_timedate(&tm, 0);
|
| 515 |
rtc_set_date(s, &tm); |
| 516 |
|
| 517 |
val = rtc_to_bcd(s, (tm.tm_year / 100) + 19); |
| 518 |
rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val); |
| 519 |
rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val); |
| 520 |
} |
| 521 |
|
| 522 |
static int rtc_post_load(void *opaque, int version_id) |
| 523 |
{
|
| 524 |
#ifdef TARGET_I386
|
| 525 |
RTCState *s = opaque; |
| 526 |
|
| 527 |
if (version_id >= 2) { |
| 528 |
if (rtc_td_hack) {
|
| 529 |
rtc_coalesced_timer_update(s); |
| 530 |
} |
| 531 |
} |
| 532 |
#endif
|
| 533 |
return 0; |
| 534 |
} |
| 535 |
|
| 536 |
static const VMStateDescription vmstate_rtc = { |
| 537 |
.name = "mc146818rtc",
|
| 538 |
.version_id = 2,
|
| 539 |
.minimum_version_id = 1,
|
| 540 |
.minimum_version_id_old = 1,
|
| 541 |
.post_load = rtc_post_load, |
| 542 |
.fields = (VMStateField []) {
|
| 543 |
VMSTATE_BUFFER(cmos_data, RTCState), |
| 544 |
VMSTATE_UINT8(cmos_index, RTCState), |
| 545 |
VMSTATE_INT32(current_tm.tm_sec, RTCState), |
| 546 |
VMSTATE_INT32(current_tm.tm_min, RTCState), |
| 547 |
VMSTATE_INT32(current_tm.tm_hour, RTCState), |
| 548 |
VMSTATE_INT32(current_tm.tm_wday, RTCState), |
| 549 |
VMSTATE_INT32(current_tm.tm_mday, RTCState), |
| 550 |
VMSTATE_INT32(current_tm.tm_mon, RTCState), |
| 551 |
VMSTATE_INT32(current_tm.tm_year, RTCState), |
| 552 |
VMSTATE_TIMER(periodic_timer, RTCState), |
| 553 |
VMSTATE_INT64(next_periodic_time, RTCState), |
| 554 |
VMSTATE_INT64(next_second_time, RTCState), |
| 555 |
VMSTATE_TIMER(second_timer, RTCState), |
| 556 |
VMSTATE_TIMER(second_timer2, RTCState), |
| 557 |
VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
|
| 558 |
VMSTATE_UINT32_V(period, RTCState, 2),
|
| 559 |
VMSTATE_END_OF_LIST() |
| 560 |
} |
| 561 |
}; |
| 562 |
|
| 563 |
static void rtc_reset(void *opaque) |
| 564 |
{
|
| 565 |
RTCState *s = opaque; |
| 566 |
|
| 567 |
s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE); |
| 568 |
s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF); |
| 569 |
|
| 570 |
qemu_irq_lower(s->irq); |
| 571 |
|
| 572 |
#ifdef TARGET_I386
|
| 573 |
if (rtc_td_hack)
|
| 574 |
s->irq_coalesced = 0;
|
| 575 |
#endif
|
| 576 |
} |
| 577 |
|
| 578 |
static int rtc_initfn(ISADevice *dev) |
| 579 |
{
|
| 580 |
RTCState *s = DO_UPCAST(RTCState, dev, dev); |
| 581 |
int base = 0x70; |
| 582 |
int isairq = 8; |
| 583 |
|
| 584 |
isa_init_irq(dev, &s->irq, isairq); |
| 585 |
|
| 586 |
s->cmos_data[RTC_REG_A] = 0x26;
|
| 587 |
s->cmos_data[RTC_REG_B] = 0x02;
|
| 588 |
s->cmos_data[RTC_REG_C] = 0x00;
|
| 589 |
s->cmos_data[RTC_REG_D] = 0x80;
|
| 590 |
|
| 591 |
rtc_set_date_from_host(s); |
| 592 |
|
| 593 |
s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s); |
| 594 |
#ifdef TARGET_I386
|
| 595 |
if (rtc_td_hack)
|
| 596 |
s->coalesced_timer = |
| 597 |
qemu_new_timer(rtc_clock, rtc_coalesced_timer, s); |
| 598 |
#endif
|
| 599 |
s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s); |
| 600 |
s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s); |
| 601 |
|
| 602 |
s->next_second_time = |
| 603 |
qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100; |
| 604 |
qemu_mod_timer(s->second_timer2, s->next_second_time); |
| 605 |
|
| 606 |
register_ioport_write(base, 2, 1, cmos_ioport_write, s); |
| 607 |
register_ioport_read(base, 2, 1, cmos_ioport_read, s); |
| 608 |
|
| 609 |
vmstate_register(base, &vmstate_rtc, s); |
| 610 |
qemu_register_reset(rtc_reset, s); |
| 611 |
return 0; |
| 612 |
} |
| 613 |
|
| 614 |
RTCState *rtc_init(int base_year)
|
| 615 |
{
|
| 616 |
ISADevice *dev; |
| 617 |
|
| 618 |
dev = isa_create("mc146818rtc");
|
| 619 |
qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
|
| 620 |
qdev_init_nofail(&dev->qdev); |
| 621 |
return DO_UPCAST(RTCState, dev, dev);
|
| 622 |
} |
| 623 |
|
| 624 |
static ISADeviceInfo mc146818rtc_info = {
|
| 625 |
.qdev.name = "mc146818rtc",
|
| 626 |
.qdev.size = sizeof(RTCState),
|
| 627 |
.qdev.no_user = 1,
|
| 628 |
.init = rtc_initfn, |
| 629 |
.qdev.props = (Property[]) {
|
| 630 |
DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980), |
| 631 |
DEFINE_PROP_END_OF_LIST(), |
| 632 |
} |
| 633 |
}; |
| 634 |
|
| 635 |
static void mc146818rtc_register(void) |
| 636 |
{
|
| 637 |
isa_qdev_register(&mc146818rtc_info); |
| 638 |
} |
| 639 |
device_init(mc146818rtc_register) |