Revision dd5d6fe9

b/gen-icount.h
1
/* Helpewrs for instruction counting code genration.  */
2

  
3
static TCGArg *icount_arg;
4
static int icount_label;
5

  
6
static inline void gen_icount_start(void)
7
{
8
    TCGv count;
9

  
10
    if (!use_icount)
11
        return;
12

  
13
    icount_label = gen_new_label();
14
    /* FIXME: This generates lousy code.  We can't use tcg_new_temp because
15
       count needs to live over the conditional branch.  To workaround this
16
       we allow the target to supply a convenient register temporary.  */
17
#ifndef ICOUNT_TEMP
18
    count = tcg_temp_local_new(TCG_TYPE_I32);
19
#else
20
    count = ICOUNT_TEMP;
21
#endif
22
    tcg_gen_ld_i32(count, cpu_env, offsetof(CPUState, icount_decr.u32));
23
    /* This is a horrid hack to allow fixing up the value later.  */
24
    icount_arg = gen_opparam_ptr + 1;
25
    tcg_gen_subi_i32(count, count, 0xdeadbeef);
26

  
27
    tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, icount_label);
28
    tcg_gen_st16_i32(count, cpu_env, offsetof(CPUState, icount_decr.u16.low));
29
#ifndef ICOUNT_TEMP
30
    tcg_temp_free(count);
31
#endif
32
}
33

  
34
static void gen_icount_end(TranslationBlock *tb, int num_insns)
35
{
36
    if (use_icount) {
37
        *icount_arg = num_insns;
38
        gen_set_label(icount_label);
39
        tcg_gen_exit_tb((long)tb + 2);
40
    }
41
}
42

  
43
static void inline gen_io_start(void)
44
{
45
    TCGv tmp = tcg_const_i32(1);
46
    tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, can_do_io));
47
    tcg_temp_free(tmp);
48
}
49

  
50
static inline void gen_io_end(void)
51
{
52
    TCGv tmp = tcg_const_i32(0);
53
    tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, can_do_io));
54
    tcg_temp_free(tmp);
55
}
56

  
b/qemu-doc.texi
974 974

  
975 975
Note that while this option can give deterministic behavior, it does not
976 976
provide cycle accurate emulation.  Modern CPUs contain superscalar out of
977
order cores with complex cache heirachies.  The number of instructions
977
order cores with complex cache hierarchies.  The number of instructions
978 978
executed often has little or no correlation with actual performance.
979 979
@end table
980 980

  
b/target-mips/translate.c
7862 7862
    ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;
7863 7863
#endif
7864 7864
    num_insns = 0;
7865
    num_insns = 0;
7866 7865
    max_insns = tb->cflags & CF_COUNT_MASK;
7867 7866
    if (max_insns == 0)
7868 7867
        max_insns = CF_COUNT_MASK;
b/vl.c
7446 7446
           "                To see what timers are available use -clock ?\n"
7447 7447
           "-startdate      select initial date of the clock\n"
7448 7448
           "-icount [N|auto]\n"
7449
           "                Enable virtual instruction counter with 2^N clock ticks per instructon\n"
7449
           "                Enable virtual instruction counter with 2^N clock ticks per instruction\n"
7450 7450
           "\n"
7451 7451
           "During emulation, the following keys are useful:\n"
7452 7452
           "ctrl-alt-f      toggle full screen\n"

Also available in: Unified diff