w32: Fix compilation and replace non-portable usage of ulong
ulong is undefined for w32 (and maybe other) compilations.Replace it by uintptr_t (which also fixes compilation for w64and is a better choice for pointer to integer conversions).
Cc: Aurelien Jarno <aurelien@aurel32.net>...
Fix a bug in mtsr/mtsrin emulation on ppc64
Early ppc64 CPUs include a hack to partially simulate the ppc32 segmentregisters, by translating writes to them into writes to the SLB. This isnot used by any current Linux kernel, but it is used by the openbios used...
Merge branch 'ppc-next' of git://repo.or.cz/qemu/agraf
PPC: Add GS MSR definition
The BookE specification defines MSR bit 28 as Guest State. Add itto the list of MSR macros.
Signed-off-by: Alexander Graf <agraf@suse.de>
PPC: Add another 64 bits to instruction feature mask
To enable quick runtime detection of instruction groups to the currentlyselected CPU emulation, we have a feature mask of what exactly the respectiveinstruction supports.
This feature mask is 64 bits long and we just successfully exceeded those 64...
PPC: Implement e500 (FSL) MMU
Most of the code to support e500 style MMUs is already in place, butwe're missing on some of the special TLB0-TLB1 handling code and slightlydifferent TLB modification.
This patch adds support for the FSL style MMU.
kvm: ppc: detect old headers
When compiling Qemu with older kernel headers, the PVR settingmechanism isn't available yet. Unfortunately, back then I didn't adda capability we could check against, so all we can do is add a configuretest to see if we support PVR setting. For BookE, we don't care yet....
kvm: ppc: fixes for KVM_SET_SREGS on init
Classic/server ppc has had SREGS for a while now (though I think notalways?), but it's still missing for booke. Check the capability beforecalling KVM_SET_SREGS.
Without this, booke kvm fails to boot as of commit...
monitor: add PPC BookE SPRs
Read them via KVM_GET_SREGS in kvm_arch_get_registers(),and display them in "info registers".
Also get CR and PID from the existing KVM_GET_REGS.
Signed-off-by: Scott Wood <scottwood@freescale.com>Signed-off-by: Alexander Graf <agraf@suse.de>
Fix typos in comments (instanciation -> instantiation)
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
Fix typo in comment (embeded -> embedded)
Remove unused function parameter from cpu_restore_state
The previous patch removed the need for parameter puc.Is is now unused, so remove it.
Cc: Aurelien Jarno <aurelien@aurel32.net>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Remove unused function parameters from gen_pc_load and rename the function
Function gen_pc_load was introduced in commitd2856f1ad4c259e5766847c49acbb4e390731bd4.The only reason for parameter searched_pc wasa debug statement in target-i386/translate.c....
target-ppc: fix SPE comparison functions
efstst*() functions are fast SPE funtions which do not take into accountspecial values (infinites, NaN, etc.), while efscmp*() functions areIEEE754 compliant.
Given that float32_*() functions are IEEE754 compliant, the efscmp*()...
softfloat: rename float*_eq() into float*_eq_quiet()
float*_eq functions have a different semantics than other comparisonfunctions. Fix that by first renaming float*_quiet() into float*_eq_quiet().
Note that it is purely mechanical, and the behaviour should be unchanged....
target-ppc: remove #ifdef FLOAT128
Now that PPC defaults to softfloat which always provides float128support, there is no need to keep two version of the code, depending iffloat128 support is available or not. Suggested by Peter Maydell.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
Fix conversions from pointer to tcg_target_long
tcg_gen_exit_tb takes a parameter of type tcg_target_long,so the type casts of pointer to long should be replaced bytype casts of pointer to tcg_target_long (suggested by Blue Swirl).
These changes are needed for build environments where...
ppce500_mpc8544ds: Fix compile with --enable-debug and --disable-kvm
When configured with --enable-debug, we compile without optimization.This means that the function mpc8544_copy_soc_cell() in ppce500_mpc8544ds.cis not optimized out, even though it is never called without kvm. That in...
Use existing helper function to implement popcntd instruction
The recent patches adding partial support for POWER7 cpu emulation includedimplementing the popcntd instruction. The support for this was open coded,but host-utils.h already included a function implementing an equivalent...
Implement PAPR VPA functions for pSeries shared processor partitions
Shared-processor partitions are those where a CPU is time-sliced betweenpartitions, rather than being permanently dedicated to a singlepartition. qemu emulated partitions, since they are just scheduled with...
Implement PAPR CRQ hypercalls
This patch implements the infrastructure and hypercalls necessary for thePAPR specified CRQ (Command Request Queue) mechanism. This generalrequest queueing system is used by many of the PAPR virtual IO devices,including the virtual scsi adapter....
Clean up slb_lookup() function
The slb_lookup() function, used in the ppc translation path returns anumber of slb entry fields in reference parameters. However, only oneof the two callers of slb_lookup() actually wants this information.
This patch, therefore, makes slb_lookup() return a simple pointer to the...
Parse SDR1 on mtspr instead of at translate time
On ppc machines with hash table MMUs, the special purpose register SDR1contains both the base address of the encoded size (hashed) page tables.
At present, we interpret the SDR1 value within the address translation...
Use "hash" more consistently in ppc mmu code
Currently, get_segment() has a variable called hash. However it doesn't(quite) get the hash value for the ppc hashed page table. Instead itgets the hash shifted - effectively the offset of the hash bucket within...
Better factor the ppc hash translation path
Currently the path handling hash page table translation in get_segment()has a mix of common and 32 or 64 bit specific code. However thedivision is not done terribly well which results in a lot of messy codeflipping between common and divided paths....
Support 1T segments on ppc
Traditionally, the "segments" used for the two-stage translation used onpowerpc MMUs were 256MB in size. This was the only option on all hashpage table based 32-bit powerpc cpus, and on the earlier 64-bit hash pagetable based cpus. However, newer 64-bit cpus also permit 1TB segments...
Add POWER7 support for ppc
This adds emulation support for the recent POWER7 cpu to qemu. It's farfrom perfect - it's missing a number of POWER7 features so far, includingany support for VSX or decimal floating point instructions. However, it'sclose enough to boot a kernel with the POWER7 PVR....
Virtual hash page table handling on pSeries machine
On pSeries logical partitions, excepting the old POWER4-style full systempartitions, the guest does not have direct access to the hardware pagetable. Instead, the pagetable exists in hypervisor memory, and the guest...
Clean up PowerPC SLB handling code
Currently the SLB information when emulating a PowerPC 970 isstoreed in a structure with the unhelpfully named fields 'tmp'and 'tmp64'. While the layout in these fields does match thedescription of the SLB in the architecture document, it is not...
Add a hook to allow hypercalls to be emulated on PowerPC
PowerPC and POWER chips since the POWER4 and 970 have a specialhypervisor mode, and a corresponding form of the system callinstruction which traps to the hypervisor.
qemu currently has stub implementations of hypervisor mode. That...
Implement PowerPC slbmfee and slbmfev instructions
For a 64-bit PowerPC target, qemu correctly implements translationthrough the segment lookaside buffer. Likewise it supports theslbmte instruction which is used to load entries into the SLB.
However, it does not emulate the slbmfee and slbmfev instructions...
Implement missing parts of the logic for the POWER PURR
The PURR (Processor Utilization Resource Register) is a register foundon recent POWER CPUs. The guts of implementing it at least enough toget by are already present in qemu, however some of the helper...
Correct ppc popcntb logic, implement popcntw and popcntd
qemu already includes support for the popcntb instruction introducedin POWER5 (although it doesn't actually allow you to choose POWER5).
However, the logic is slightly incorrect: it will generate results...
target-ppc: ext32u instead of andi with constant
Cc: Alexander Graf <agraf@suse.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Alexander Graf <agraf@suse.de>
target-ppc: add support for 6 SPE instructions
Add support for 6 SPE instructions: evmra, evmwsmi{a{a}}, evmwumi{a{a}}
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Merge remote branch 'qemu-kvm/uq/master' into staging
change all other clock references to use nanosecond resolution accessors
This was done with:
sed -i 's/qemu_get_clock\>/qemu_get_clock_ns/' \ $(git grep -l 'qemu_get_clock\>' ) sed -i 's/qemu_new_timer\>/qemu_new_timer_ns/' \ $(git grep -l 'qemu_new_timer\>' )...
kvm: Align kvm_arch_handle_exit to kvm_cpu_exec changes
Make the return code of kvm_arch_handle_exit directly usable forkvm_cpu_exec. This is straightforward for x86 and ppc, just s390would require more work. Avoid this for now by pushing the return code...
kvm: Rename kvm_arch_process_irqchip_events to async_events
We will broaden the scope of this function on x86 beyond irqchip events.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
kvm: ppc: Fix breakage of kvm_arch_pre_run/process_irqchip_events
Commit 7a39fe5882 failed to convert the right arch function.
inline cpu_halted into sole caller
All implementations are now the same, and there is only one caller,so inline the function there.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Handle icount for powerpc tbl/tbu/decr load and store.
Handle option '-icount X' on powerpc targets.
Signed-off-by: Tristan Gingold <gingold@adacore.com>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@petalogix.com>
kvm: Drop return values from kvm_arch_pre/post_run
We do not check them, and the only arch with non-empty implementationsalways returns 0 (this is also true for qemu-kvm).
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>CC: Alexander Graf <agraf@suse.de>...
kvm: Provide sigbus services arch-independently
Provide arch-independent kvm_on_sigbus* stubs to remove the #ifdef'eryfrom cpus.c. This patch also fixes --disable-kvm build by providing themissing kvm_on_sigbus_vcpu kvm-stub.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>...
aliguori: fix build with !defined(KVM_CAP_ASYNC_PF)
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
kvm: Consolidate must-have capability checks
Instead of splattering the code with #ifdefs and runtime checks forcapabilities we cannot work without anyway, provide central testinfrastructure for verifying their availability both at build andruntime.
kvm: Drop smp_cpus argument from init functions
No longer used.
kvm: Stop on all fatal exit reasons
Ensure that we stop the guest whenever we face a fatal or unknown exitreason. If we stop, we also have to enforce a cpu loop exit.
ppc: Correct BookE tlb reads
Call the tlb read helper (and not the write helper) for tlbreads.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
target-ppc: fix wrong NaN tests
Some tests in FPU emulation code were wrongly using float64_is_nan()before commit 185698715dfb18c82ad2a5dbc169908602d43e81, and wronglyusing float64_is_quiet_nan() after. Fix them by using float64_is_any_nan()instead.
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>...
target-ppc: fix sNaN propagation
The current FPU code returns 0.0 if one of the operand is asignaling NaN and the VXSNAN exception is disabled.
fload_invalid_op_excp() doesn't return a qNaN in case of a VXSNANexception as the operand should be propagated instead of a new...
target-ppc: use float32_is_any_nan()
Use the new function float32_is_any_nan() instead offloat32_is_quiet_nan() || float32_is_signaling_nan().
Acked-by: Alexander Graf <agraf@suse.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-ppc: fix default qNaN
On PPC the default qNaN doesn't have the sign bit set.
target-ppc: remove PRECISE_EMULATION define
The PRECISE_EMULATION is "hardcoded" to one in target-ppc/exec.h and notsomething easily tunable. Remove it and non-precise emulation code asit doesn't make a noticeable difference in speed. People wanting speed...
softfloat: Rename float*_is_nan() functions to float*_is_quiet_nan()
The softfloat functions float*_is_nan() were badly misnamed,because they return true only for quiet NaNs, not for all NaNs.Rename them to float*_is_quiet_nan() to more accurately reflect...
Fix translation of unary PPC/SPE instructions (efdneg etc.).
Signed-off-by: Mike Pall <mike-lp10@luajit.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
ppc: kvm: fix signedness warning
I get a warning on a signed comparison with an unsigned variable, solet's make the variable signed and be happy.
Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>...
ppc: avoid write only variables
Compiling with GCC 4.6.0 20100925 produced warnings:/src/qemu/target-ppc/op_helper.c: In function 'helper_icbi':/src/qemu/target-ppc/op_helper.c:351:14: error: variable 'tmp' set but not used [-Werror=unused-but-set-variable]...
ppc: remove video.x
Only Mac-on-Linux stuff used video.x, OpenBIOS does not need it.
Remove video.x MoL hacks.
Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
ppc: Minor 40x MMU fixes
Signed-off-by: John Clark <clarkjc@runbox.com>Signed-off-by: Alexander Graf <agraf@suse.de>Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
powerpc: Add a virtex5 ml507 refdesign board
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>Signed-off-by: Alexander Graf <agraf@suse.de>
powerpc: Add a ppc-440x5 Xilinx model
Add a powerpc 440x5 with the model ID on the Xilinx virtex5.Connect the 440x5 to the 40x interrupt logic.
powerpc: Improve emulation of the BookE MMU
Improve the emulation of the BookE MMU to be able to boot linuxon virtex5 boards.
PPC: Suppress gcc warnings with -Wtype-limits
The hack added by c5b76b381081680633e2e0a91216507430409fb2 was notenough to avoid warnings with gcc flag -Wtype-limits. Add a new macroto fix both problems.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
PPC: Redesign interrupt trigger path
According to the Book3S spec, the interrupt context starts with an MSRvalue that is rather simple. If we leave out the HV case, it's almostalways 0.
To reflect this, let's redesign the way that MSR value gets calculated....
PPC: Enable hint bits for lwarx/ldarx
The lwarx and ldarx instructions have a bit to give some hint to theCPU which is safe to ignore. We currently refuse to accept any instructionwith that bit set, as it used to be declared MBZ.
Let's remove the reserved bit and make the instruction work as expected....
powerpc: Avoid TLB related log spamming
Invalid TLB entries are normal and should not spam the log.
KVM: PPC: Add level based interrupt logic
KVM on PowerPC used to have completely broken interrupt logic. Usually,interrupts work by having a PIC that pulls a line up/down, so the CPU knowsthat an interrupt is active. This line stays active until some action is...
PPC: Add PV hypercall transport through fw_cfg
On KVM for PPC we need to tell the guest which instructions to use whendoing a hypercall. The clean way to do this is to go through an ioctlfrom userspace and passing it on to the guest using the device tree....
target-ppc: fix power mode checking on 7400/7410
Only the PowerPC 7440/7450 family don't support DOZE mode. PowerPC7400 and 7410 support it.
target-ppc: add vexptefp instruction
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
remove exec-all.h inclusion from cpu.h
move cpu_pc_from_tb to target-*/exec.h
tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.
Some hosts (amd64, ia64) have an ABI that ignores the high bitsof the 64-bit register when passing 32-bit arguments. Othersrequire the value to be properly sign-extended for the type.I.e. "int32_t" must be sign-extended and "uint32_t" must be...
target-ppc: remove useless line
This line was a bit clear.The next lines set or reset this bit (LE) depending of another bit (ILE).So the first line is useless.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-ppc: fix RFI by clearing some bits of MSR
Since commit 2ada0ed, "Return From Interrupt" is broken for PPC processorsbecause some interrupt specifics bits of SRR1 are copied to MSR.
SRR1 is a save of MSR during interrupt.During RFI, MSR must be restored from SRR1....
Fix %lld or %llx printf format use
PPC/KVM: make iothread work
When running with --enable-io-thread the timer we have doesn't help,because it doesn't wake up the CPU thread. So instead we need toactually kick it.
While at it I refined the logic a bit to not dumbly trigger a timerevery 500ms, but rather do it more often after an interrupt got injected....
Do not stop VM if emulation failed in userspace.
Continue vcpu execution in case emulation failure happened while vcpuwas in userspace. In this case #UD will be injected into the guestallowing guest OS to kill offending process and continue.
Signed-off-by: Gleb Natapov <gleb@redhat.com>...
kvm: enable smp > 1
Process INIT/SIPI requests and enable -smp > 1.
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>Signed-off-by: Avi Kivity <avi@redhat.com>
target-ppc: Remove duplicate cpu log.
Logging for -d cpu is done in generic code.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
ppc: remove dead assignments, spotted by clang analyzer
Value stored is never read.
PPC: avoid function pointer type mismatch, spotted by clang
Fixes clang errors: CC ppc-softmmu/translate.o/src/qemu/target-ppc/translate.c:3748:13: error: comparison of distinct pointer types ('void (*)(void *, int, int)' and 'void *') if (likely(read_cb != SPR_NOACCESS)) {...
target-ppc: generic PowerPC TBL
Time base SPRs TBL/TBU should be accessible in user/priv modes for readingas specified in POWER ISA documentation. Therefore SPRs permissions werechanged in gen_tbl function.
Signed-off-by: Dmitry Ilyevsky <ilyevsky@gmail.com>...
Large page TLB flush
QEMU uses a fixed page size for the CPU TLB. If the guest uses largepages then we effectively split these into multiple smaller pages, andpopulate the corresponding TLB entries on demand.
When the guest invalidates the TLB by virtual address we must invalidate...
Target specific usermode cleanup
Disable various target specific code that is only relevant to system emulation.
Signed-off-by: Paul Brook <paul@codesourcery.com>
Remove cpu_get_phys_page_debug from userspace emulation
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.
Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Removes a set of ifdefs from exec.c.
Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets otherthan Alpha. This will be used for page_find_alloc, which issupposed to be using virtual addresses in the first place....
target-ppc: fix evsrwu and evsrws (second try)
target-ppc: fix evsrwu and evsrws
target-ppc: fix evslw instruction
KVM: Rework VCPU state writeback API
This grand cleanup drops all reset and vmsave/load relatedsynchronization points in favor of four(!) generic hooks:
- cpu_synchronize_all_states in qemu_savevm_state_complete (initial sync from kernel before vmsave)...
Revert "target-ppc: stop translation after a trap instruction"
This reverts commit 6454e7be1b2504533f7ffb190d54ebe2993cb434.
target-ppc: don't print invalid opcode messages on the console
Invalid opcode messages can be perfectly normal, for example if thiscode is never executed. Don't print an error message on the console,but keep the message in the log for debugging purposes....
target-ppc: stop translation after a trap instruction
target-ppc: fix SPE evsplat* instructions
The shifts in the gen_evsplat* functions were expecting rA to be masked,not extracted, and so used the wrong shift amounts to sign-extend or padwith zeroes.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>...
target-ppc: fix SPE evcmp* instructions
The CRF_{CH,CL,CH_OR_CL,CH_AND_CL} constants were all off by one bitposition. Because of this, the SPE evcmp* family of instructions wouldstore values in the result condition register that were also off by onebit position....
PPC: Add timer when running KVM
For some odd reason we sometimes hang inside KVM forever. I'd guess it'sa race condition where we actually have a level triggered interrupt, butthe infrastructure can't expose that yet, so the guest ACKs it, goes tosleep and never gets notified that there's still an interrupt pending....