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1
/*
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 *  PowerPC CPU initialization for qemu.
3
 *
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 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
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 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
20

    
21
/* A lot of PowerPC definition have been included here.
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 * Most of them are not usable for now but have been kept
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 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
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 */
25

    
26
#include "dis-asm.h"
27

    
28
//#define PPC_DUMP_CPU
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//#define PPC_DEBUG_SPR
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//#define PPC_DEBUG_IRQ
31

    
32
struct ppc_def_t {
33
    const unsigned char *name;
34
    uint32_t pvr;
35
    uint32_t pvr_mask;
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    uint64_t insns_flags;
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    uint64_t msr_mask;
38
    uint8_t mmu_model;
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    uint8_t excp_model;
40
    uint8_t bus_model;
41
    uint8_t pad;
42
    int bfd_mach;
43
    void (*init_proc)(CPUPPCState *env);
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};
45

    
46
/* For user-mode emulation, we don't emulate any IRQ controller */
47
#if defined(CONFIG_USER_ONLY)
48
#define PPC_IRQ_INIT_FN(name)                                                 \
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static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env)         \
50
{                                                                             \
51
}
52
#else
53
#define PPC_IRQ_INIT_FN(name)                                                 \
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void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
55
#endif
56

    
57
PPC_IRQ_INIT_FN(401);
58
PPC_IRQ_INIT_FN(405);
59
PPC_IRQ_INIT_FN(6xx);
60
PPC_IRQ_INIT_FN(970);
61

    
62
/* Generic callbacks:
63
 * do nothing but store/retrieve spr value
64
 */
65
#ifdef PPC_DUMP_SPR_ACCESSES
66
static void spr_read_generic (void *opaque, int sprn)
67
{
68
    gen_op_load_dump_spr(sprn);
69
}
70

    
71
static void spr_write_generic (void *opaque, int sprn)
72
{
73
    gen_op_store_dump_spr(sprn);
74
}
75
#else
76
static void spr_read_generic (void *opaque, int sprn)
77
{
78
    gen_op_load_spr(sprn);
79
}
80

    
81
static void spr_write_generic (void *opaque, int sprn)
82
{
83
    gen_op_store_spr(sprn);
84
}
85
#endif
86

    
87
#if !defined(CONFIG_USER_ONLY)
88
static void spr_write_clear (void *opaque, int sprn)
89
{
90
    gen_op_mask_spr(sprn);
91
}
92
#endif
93

    
94
/* SPR common to all PowerPC */
95
/* XER */
96
static void spr_read_xer (void *opaque, int sprn)
97
{
98
    gen_op_load_xer();
99
}
100

    
101
static void spr_write_xer (void *opaque, int sprn)
102
{
103
    gen_op_store_xer();
104
}
105

    
106
/* LR */
107
static void spr_read_lr (void *opaque, int sprn)
108
{
109
    gen_op_load_lr();
110
}
111

    
112
static void spr_write_lr (void *opaque, int sprn)
113
{
114
    gen_op_store_lr();
115
}
116

    
117
/* CTR */
118
static void spr_read_ctr (void *opaque, int sprn)
119
{
120
    gen_op_load_ctr();
121
}
122

    
123
static void spr_write_ctr (void *opaque, int sprn)
124
{
125
    gen_op_store_ctr();
126
}
127

    
128
/* User read access to SPR */
129
/* USPRx */
130
/* UMMCRx */
131
/* UPMCx */
132
/* USIA */
133
/* UDECR */
134
static void spr_read_ureg (void *opaque, int sprn)
135
{
136
    gen_op_load_spr(sprn + 0x10);
137
}
138

    
139
/* SPR common to all non-embedded PowerPC */
140
/* DECR */
141
#if !defined(CONFIG_USER_ONLY)
142
static void spr_read_decr (void *opaque, int sprn)
143
{
144
    gen_op_load_decr();
145
}
146

    
147
static void spr_write_decr (void *opaque, int sprn)
148
{
149
    gen_op_store_decr();
150
}
151
#endif
152

    
153
/* SPR common to all non-embedded PowerPC, except 601 */
154
/* Time base */
155
static void spr_read_tbl (void *opaque, int sprn)
156
{
157
    gen_op_load_tbl();
158
}
159

    
160
static void spr_read_tbu (void *opaque, int sprn)
161
{
162
    gen_op_load_tbu();
163
}
164

    
165
#if !defined(CONFIG_USER_ONLY)
166
static void spr_write_tbl (void *opaque, int sprn)
167
{
168
    gen_op_store_tbl();
169
}
170

    
171
static void spr_write_tbu (void *opaque, int sprn)
172
{
173
    gen_op_store_tbu();
174
}
175
#endif
176

    
177
#if !defined(CONFIG_USER_ONLY)
178
/* IBAT0U...IBAT0U */
179
/* IBAT0L...IBAT7L */
180
static void spr_read_ibat (void *opaque, int sprn)
181
{
182
    gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
183
}
184

    
185
static void spr_read_ibat_h (void *opaque, int sprn)
186
{
187
    gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
188
}
189

    
190
static void spr_write_ibatu (void *opaque, int sprn)
191
{
192
    gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
193
}
194

    
195
static void spr_write_ibatu_h (void *opaque, int sprn)
196
{
197
    gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
198
}
199

    
200
static void spr_write_ibatl (void *opaque, int sprn)
201
{
202
    gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
203
}
204

    
205
static void spr_write_ibatl_h (void *opaque, int sprn)
206
{
207
    gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
208
}
209

    
210
/* DBAT0U...DBAT7U */
211
/* DBAT0L...DBAT7L */
212
static void spr_read_dbat (void *opaque, int sprn)
213
{
214
    gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
215
}
216

    
217
static void spr_read_dbat_h (void *opaque, int sprn)
218
{
219
    gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
220
}
221

    
222
static void spr_write_dbatu (void *opaque, int sprn)
223
{
224
    gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
225
}
226

    
227
static void spr_write_dbatu_h (void *opaque, int sprn)
228
{
229
    gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
230
}
231

    
232
static void spr_write_dbatl (void *opaque, int sprn)
233
{
234
    gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
235
}
236

    
237
static void spr_write_dbatl_h (void *opaque, int sprn)
238
{
239
    gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
240
}
241

    
242
/* SDR1 */
243
static void spr_read_sdr1 (void *opaque, int sprn)
244
{
245
    gen_op_load_sdr1();
246
}
247

    
248
static void spr_write_sdr1 (void *opaque, int sprn)
249
{
250
    gen_op_store_sdr1();
251
}
252

    
253
/* 64 bits PowerPC specific SPRs */
254
/* ASR */
255
/* Currently unused */
256
#if 0 && defined(TARGET_PPC64)
257
static void spr_read_asr (void *opaque, int sprn)
258
{
259
    gen_op_load_asr();
260
}
261

262
static void spr_write_asr (void *opaque, int sprn)
263
{
264
    DisasContext *ctx = opaque;
265

266
    gen_op_store_asr();
267
}
268
#endif
269
#endif
270

    
271
/* PowerPC 601 specific registers */
272
/* RTC */
273
static void spr_read_601_rtcl (void *opaque, int sprn)
274
{
275
    gen_op_load_601_rtcl();
276
}
277

    
278
static void spr_read_601_rtcu (void *opaque, int sprn)
279
{
280
    gen_op_load_601_rtcu();
281
}
282

    
283
#if !defined(CONFIG_USER_ONLY)
284
static void spr_write_601_rtcu (void *opaque, int sprn)
285
{
286
    gen_op_store_601_rtcu();
287
}
288

    
289
static void spr_write_601_rtcl (void *opaque, int sprn)
290
{
291
    gen_op_store_601_rtcl();
292
}
293
#endif
294

    
295
/* Unified bats */
296
#if !defined(CONFIG_USER_ONLY)
297
static void spr_read_601_ubat (void *opaque, int sprn)
298
{
299
    gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
300
}
301

    
302
static void spr_write_601_ubatu (void *opaque, int sprn)
303
{
304
    gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
305
}
306

    
307
static void spr_write_601_ubatl (void *opaque, int sprn)
308
{
309
    gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
310
}
311
#endif
312

    
313
/* PowerPC 40x specific registers */
314
#if !defined(CONFIG_USER_ONLY)
315
static void spr_read_40x_pit (void *opaque, int sprn)
316
{
317
    gen_op_load_40x_pit();
318
}
319

    
320
static void spr_write_40x_pit (void *opaque, int sprn)
321
{
322
    gen_op_store_40x_pit();
323
}
324

    
325
static void spr_write_40x_dbcr0 (void *opaque, int sprn)
326
{
327
    DisasContext *ctx = opaque;
328

    
329
    gen_op_store_40x_dbcr0();
330
    /* We must stop translation as we may have rebooted */
331
    GEN_STOP(ctx);
332
}
333

    
334
static void spr_write_40x_sler (void *opaque, int sprn)
335
{
336
    gen_op_store_40x_sler();
337
}
338

    
339
static void spr_write_booke_tcr (void *opaque, int sprn)
340
{
341
    gen_op_store_booke_tcr();
342
}
343

    
344
static void spr_write_booke_tsr (void *opaque, int sprn)
345
{
346
    gen_op_store_booke_tsr();
347
}
348
#endif
349

    
350
/* PowerPC 403 specific registers */
351
/* PBL1 / PBU1 / PBL2 / PBU2 */
352
#if !defined(CONFIG_USER_ONLY)
353
static void spr_read_403_pbr (void *opaque, int sprn)
354
{
355
    gen_op_load_403_pb(sprn - SPR_403_PBL1);
356
}
357

    
358
static void spr_write_403_pbr (void *opaque, int sprn)
359
{
360
    gen_op_store_403_pb(sprn - SPR_403_PBL1);
361
}
362

    
363
static void spr_write_pir (void *opaque, int sprn)
364
{
365
    gen_op_store_pir();
366
}
367
#endif
368

    
369
#if defined(CONFIG_USER_ONLY)
370
#define spr_register(env, num, name, uea_read, uea_write,                     \
371
                     oea_read, oea_write, initial_value)                      \
372
do {                                                                          \
373
     _spr_register(env, num, name, uea_read, uea_write, initial_value);       \
374
} while (0)
375
static inline void _spr_register (CPUPPCState *env, int num,
376
                                  const unsigned char *name,
377
                                  void (*uea_read)(void *opaque, int sprn),
378
                                  void (*uea_write)(void *opaque, int sprn),
379
                                  target_ulong initial_value)
380
#else
381
static inline void spr_register (CPUPPCState *env, int num,
382
                                 const unsigned char *name,
383
                                 void (*uea_read)(void *opaque, int sprn),
384
                                 void (*uea_write)(void *opaque, int sprn),
385
                                 void (*oea_read)(void *opaque, int sprn),
386
                                 void (*oea_write)(void *opaque, int sprn),
387
                                 target_ulong initial_value)
388
#endif
389
{
390
    ppc_spr_t *spr;
391

    
392
    spr = &env->spr_cb[num];
393
    if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
394
#if !defined(CONFIG_USER_ONLY)
395
        spr->oea_read != NULL || spr->oea_write != NULL ||
396
#endif
397
        spr->uea_read != NULL || spr->uea_write != NULL) {
398
        printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
399
        exit(1);
400
    }
401
#if defined(PPC_DEBUG_SPR)
402
    printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
403
           initial_value);
404
#endif
405
    spr->name = name;
406
    spr->uea_read = uea_read;
407
    spr->uea_write = uea_write;
408
#if !defined(CONFIG_USER_ONLY)
409
    spr->oea_read = oea_read;
410
    spr->oea_write = oea_write;
411
#endif
412
    env->spr[num] = initial_value;
413
}
414

    
415
/* Generic PowerPC SPRs */
416
static void gen_spr_generic (CPUPPCState *env)
417
{
418
    /* Integer processing */
419
    spr_register(env, SPR_XER, "XER",
420
                 &spr_read_xer, &spr_write_xer,
421
                 &spr_read_xer, &spr_write_xer,
422
                 0x00000000);
423
    /* Branch contol */
424
    spr_register(env, SPR_LR, "LR",
425
                 &spr_read_lr, &spr_write_lr,
426
                 &spr_read_lr, &spr_write_lr,
427
                 0x00000000);
428
    spr_register(env, SPR_CTR, "CTR",
429
                 &spr_read_ctr, &spr_write_ctr,
430
                 &spr_read_ctr, &spr_write_ctr,
431
                 0x00000000);
432
    /* Interrupt processing */
433
    spr_register(env, SPR_SRR0, "SRR0",
434
                 SPR_NOACCESS, SPR_NOACCESS,
435
                 &spr_read_generic, &spr_write_generic,
436
                 0x00000000);
437
    spr_register(env, SPR_SRR1, "SRR1",
438
                 SPR_NOACCESS, SPR_NOACCESS,
439
                 &spr_read_generic, &spr_write_generic,
440
                 0x00000000);
441
    /* Processor control */
442
    spr_register(env, SPR_SPRG0, "SPRG0",
443
                 SPR_NOACCESS, SPR_NOACCESS,
444
                 &spr_read_generic, &spr_write_generic,
445
                 0x00000000);
446
    spr_register(env, SPR_SPRG1, "SPRG1",
447
                 SPR_NOACCESS, SPR_NOACCESS,
448
                 &spr_read_generic, &spr_write_generic,
449
                 0x00000000);
450
    spr_register(env, SPR_SPRG2, "SPRG2",
451
                 SPR_NOACCESS, SPR_NOACCESS,
452
                 &spr_read_generic, &spr_write_generic,
453
                 0x00000000);
454
    spr_register(env, SPR_SPRG3, "SPRG3",
455
                 SPR_NOACCESS, SPR_NOACCESS,
456
                 &spr_read_generic, &spr_write_generic,
457
                 0x00000000);
458
}
459

    
460
/* SPR common to all non-embedded PowerPC, including 601 */
461
static void gen_spr_ne_601 (CPUPPCState *env)
462
{
463
    /* Exception processing */
464
    spr_register(env, SPR_DSISR, "DSISR",
465
                 SPR_NOACCESS, SPR_NOACCESS,
466
                 &spr_read_generic, &spr_write_generic,
467
                 0x00000000);
468
    spr_register(env, SPR_DAR, "DAR",
469
                 SPR_NOACCESS, SPR_NOACCESS,
470
                 &spr_read_generic, &spr_write_generic,
471
                 0x00000000);
472
    /* Timer */
473
    spr_register(env, SPR_DECR, "DECR",
474
                 SPR_NOACCESS, SPR_NOACCESS,
475
                 &spr_read_decr, &spr_write_decr,
476
                 0x00000000);
477
    /* Memory management */
478
    spr_register(env, SPR_SDR1, "SDR1",
479
                 SPR_NOACCESS, SPR_NOACCESS,
480
                 &spr_read_sdr1, &spr_write_sdr1,
481
                 0x00000000);
482
}
483

    
484
/* BATs 0-3 */
485
static void gen_low_BATs (CPUPPCState *env)
486
{
487
    spr_register(env, SPR_IBAT0U, "IBAT0U",
488
                 SPR_NOACCESS, SPR_NOACCESS,
489
                 &spr_read_ibat, &spr_write_ibatu,
490
                 0x00000000);
491
    spr_register(env, SPR_IBAT0L, "IBAT0L",
492
                 SPR_NOACCESS, SPR_NOACCESS,
493
                 &spr_read_ibat, &spr_write_ibatl,
494
                 0x00000000);
495
    spr_register(env, SPR_IBAT1U, "IBAT1U",
496
                 SPR_NOACCESS, SPR_NOACCESS,
497
                 &spr_read_ibat, &spr_write_ibatu,
498
                 0x00000000);
499
    spr_register(env, SPR_IBAT1L, "IBAT1L",
500
                 SPR_NOACCESS, SPR_NOACCESS,
501
                 &spr_read_ibat, &spr_write_ibatl,
502
                 0x00000000);
503
    spr_register(env, SPR_IBAT2U, "IBAT2U",
504
                 SPR_NOACCESS, SPR_NOACCESS,
505
                 &spr_read_ibat, &spr_write_ibatu,
506
                 0x00000000);
507
    spr_register(env, SPR_IBAT2L, "IBAT2L",
508
                 SPR_NOACCESS, SPR_NOACCESS,
509
                 &spr_read_ibat, &spr_write_ibatl,
510
                 0x00000000);
511
    spr_register(env, SPR_IBAT3U, "IBAT3U",
512
                 SPR_NOACCESS, SPR_NOACCESS,
513
                 &spr_read_ibat, &spr_write_ibatu,
514
                 0x00000000);
515
    spr_register(env, SPR_IBAT3L, "IBAT3L",
516
                 SPR_NOACCESS, SPR_NOACCESS,
517
                 &spr_read_ibat, &spr_write_ibatl,
518
                 0x00000000);
519
    spr_register(env, SPR_DBAT0U, "DBAT0U",
520
                 SPR_NOACCESS, SPR_NOACCESS,
521
                 &spr_read_dbat, &spr_write_dbatu,
522
                 0x00000000);
523
    spr_register(env, SPR_DBAT0L, "DBAT0L",
524
                 SPR_NOACCESS, SPR_NOACCESS,
525
                 &spr_read_dbat, &spr_write_dbatl,
526
                 0x00000000);
527
    spr_register(env, SPR_DBAT1U, "DBAT1U",
528
                 SPR_NOACCESS, SPR_NOACCESS,
529
                 &spr_read_dbat, &spr_write_dbatu,
530
                 0x00000000);
531
    spr_register(env, SPR_DBAT1L, "DBAT1L",
532
                 SPR_NOACCESS, SPR_NOACCESS,
533
                 &spr_read_dbat, &spr_write_dbatl,
534
                 0x00000000);
535
    spr_register(env, SPR_DBAT2U, "DBAT2U",
536
                 SPR_NOACCESS, SPR_NOACCESS,
537
                 &spr_read_dbat, &spr_write_dbatu,
538
                 0x00000000);
539
    spr_register(env, SPR_DBAT2L, "DBAT2L",
540
                 SPR_NOACCESS, SPR_NOACCESS,
541
                 &spr_read_dbat, &spr_write_dbatl,
542
                 0x00000000);
543
    spr_register(env, SPR_DBAT3U, "DBAT3U",
544
                 SPR_NOACCESS, SPR_NOACCESS,
545
                 &spr_read_dbat, &spr_write_dbatu,
546
                 0x00000000);
547
    spr_register(env, SPR_DBAT3L, "DBAT3L",
548
                 SPR_NOACCESS, SPR_NOACCESS,
549
                 &spr_read_dbat, &spr_write_dbatl,
550
                 0x00000000);
551
    env->nb_BATs += 4;
552
}
553

    
554
/* BATs 4-7 */
555
static void gen_high_BATs (CPUPPCState *env)
556
{
557
    spr_register(env, SPR_IBAT4U, "IBAT4U",
558
                 SPR_NOACCESS, SPR_NOACCESS,
559
                 &spr_read_ibat_h, &spr_write_ibatu_h,
560
                 0x00000000);
561
    spr_register(env, SPR_IBAT4L, "IBAT4L",
562
                 SPR_NOACCESS, SPR_NOACCESS,
563
                 &spr_read_ibat_h, &spr_write_ibatl_h,
564
                 0x00000000);
565
    spr_register(env, SPR_IBAT5U, "IBAT5U",
566
                 SPR_NOACCESS, SPR_NOACCESS,
567
                 &spr_read_ibat_h, &spr_write_ibatu_h,
568
                 0x00000000);
569
    spr_register(env, SPR_IBAT5L, "IBAT5L",
570
                 SPR_NOACCESS, SPR_NOACCESS,
571
                 &spr_read_ibat_h, &spr_write_ibatl_h,
572
                 0x00000000);
573
    spr_register(env, SPR_IBAT6U, "IBAT6U",
574
                 SPR_NOACCESS, SPR_NOACCESS,
575
                 &spr_read_ibat_h, &spr_write_ibatu_h,
576
                 0x00000000);
577
    spr_register(env, SPR_IBAT6L, "IBAT6L",
578
                 SPR_NOACCESS, SPR_NOACCESS,
579
                 &spr_read_ibat_h, &spr_write_ibatl_h,
580
                 0x00000000);
581
    spr_register(env, SPR_IBAT7U, "IBAT7U",
582
                 SPR_NOACCESS, SPR_NOACCESS,
583
                 &spr_read_ibat_h, &spr_write_ibatu_h,
584
                 0x00000000);
585
    spr_register(env, SPR_IBAT7L, "IBAT7L",
586
                 SPR_NOACCESS, SPR_NOACCESS,
587
                 &spr_read_ibat_h, &spr_write_ibatl_h,
588
                 0x00000000);
589
    spr_register(env, SPR_DBAT4U, "DBAT4U",
590
                 SPR_NOACCESS, SPR_NOACCESS,
591
                 &spr_read_dbat_h, &spr_write_dbatu_h,
592
                 0x00000000);
593
    spr_register(env, SPR_DBAT4L, "DBAT4L",
594
                 SPR_NOACCESS, SPR_NOACCESS,
595
                 &spr_read_dbat_h, &spr_write_dbatl_h,
596
                 0x00000000);
597
    spr_register(env, SPR_DBAT5U, "DBAT5U",
598
                 SPR_NOACCESS, SPR_NOACCESS,
599
                 &spr_read_dbat_h, &spr_write_dbatu_h,
600
                 0x00000000);
601
    spr_register(env, SPR_DBAT5L, "DBAT5L",
602
                 SPR_NOACCESS, SPR_NOACCESS,
603
                 &spr_read_dbat_h, &spr_write_dbatl_h,
604
                 0x00000000);
605
    spr_register(env, SPR_DBAT6U, "DBAT6U",
606
                 SPR_NOACCESS, SPR_NOACCESS,
607
                 &spr_read_dbat_h, &spr_write_dbatu_h,
608
                 0x00000000);
609
    spr_register(env, SPR_DBAT6L, "DBAT6L",
610
                 SPR_NOACCESS, SPR_NOACCESS,
611
                 &spr_read_dbat_h, &spr_write_dbatl_h,
612
                 0x00000000);
613
    spr_register(env, SPR_DBAT7U, "DBAT7U",
614
                 SPR_NOACCESS, SPR_NOACCESS,
615
                 &spr_read_dbat_h, &spr_write_dbatu_h,
616
                 0x00000000);
617
    spr_register(env, SPR_DBAT7L, "DBAT7L",
618
                 SPR_NOACCESS, SPR_NOACCESS,
619
                 &spr_read_dbat_h, &spr_write_dbatl_h,
620
                 0x00000000);
621
    env->nb_BATs += 4;
622
}
623

    
624
/* Generic PowerPC time base */
625
static void gen_tbl (CPUPPCState *env)
626
{
627
    spr_register(env, SPR_VTBL,  "TBL",
628
                 &spr_read_tbl, SPR_NOACCESS,
629
                 &spr_read_tbl, SPR_NOACCESS,
630
                 0x00000000);
631
    spr_register(env, SPR_TBL,   "TBL",
632
                 SPR_NOACCESS, SPR_NOACCESS,
633
                 SPR_NOACCESS, &spr_write_tbl,
634
                 0x00000000);
635
    spr_register(env, SPR_VTBU,  "TBU",
636
                 &spr_read_tbu, SPR_NOACCESS,
637
                 &spr_read_tbu, SPR_NOACCESS,
638
                 0x00000000);
639
    spr_register(env, SPR_TBU,   "TBU",
640
                 SPR_NOACCESS, SPR_NOACCESS,
641
                 SPR_NOACCESS, &spr_write_tbu,
642
                 0x00000000);
643
}
644

    
645
/* Softare table search registers */
646
static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
647
{
648
    env->nb_tlb = nb_tlbs;
649
    env->nb_ways = nb_ways;
650
    env->id_tlbs = 1;
651
    spr_register(env, SPR_DMISS, "DMISS",
652
                 SPR_NOACCESS, SPR_NOACCESS,
653
                 &spr_read_generic, SPR_NOACCESS,
654
                 0x00000000);
655
    spr_register(env, SPR_DCMP, "DCMP",
656
                 SPR_NOACCESS, SPR_NOACCESS,
657
                 &spr_read_generic, SPR_NOACCESS,
658
                 0x00000000);
659
    spr_register(env, SPR_HASH1, "HASH1",
660
                 SPR_NOACCESS, SPR_NOACCESS,
661
                 &spr_read_generic, SPR_NOACCESS,
662
                 0x00000000);
663
    spr_register(env, SPR_HASH2, "HASH2",
664
                 SPR_NOACCESS, SPR_NOACCESS,
665
                 &spr_read_generic, SPR_NOACCESS,
666
                 0x00000000);
667
    spr_register(env, SPR_IMISS, "IMISS",
668
                 SPR_NOACCESS, SPR_NOACCESS,
669
                 &spr_read_generic, SPR_NOACCESS,
670
                 0x00000000);
671
    spr_register(env, SPR_ICMP, "ICMP",
672
                 SPR_NOACCESS, SPR_NOACCESS,
673
                 &spr_read_generic, SPR_NOACCESS,
674
                 0x00000000);
675
    spr_register(env, SPR_RPA, "RPA",
676
                 SPR_NOACCESS, SPR_NOACCESS,
677
                 &spr_read_generic, &spr_write_generic,
678
                 0x00000000);
679
}
680

    
681
/* SPR common to MPC755 and G2 */
682
static void gen_spr_G2_755 (CPUPPCState *env)
683
{
684
    /* SGPRs */
685
    spr_register(env, SPR_SPRG4, "SPRG4",
686
                 SPR_NOACCESS, SPR_NOACCESS,
687
                 &spr_read_generic, &spr_write_generic,
688
                 0x00000000);
689
    spr_register(env, SPR_SPRG5, "SPRG5",
690
                 SPR_NOACCESS, SPR_NOACCESS,
691
                 &spr_read_generic, &spr_write_generic,
692
                 0x00000000);
693
    spr_register(env, SPR_SPRG6, "SPRG6",
694
                 SPR_NOACCESS, SPR_NOACCESS,
695
                 &spr_read_generic, &spr_write_generic,
696
                 0x00000000);
697
    spr_register(env, SPR_SPRG7, "SPRG7",
698
                 SPR_NOACCESS, SPR_NOACCESS,
699
                 &spr_read_generic, &spr_write_generic,
700
                 0x00000000);
701
    /* External access control */
702
    /* XXX : not implemented */
703
    spr_register(env, SPR_EAR, "EAR",
704
                 SPR_NOACCESS, SPR_NOACCESS,
705
                 &spr_read_generic, &spr_write_generic,
706
                 0x00000000);
707
}
708

    
709
/* SPR common to all 7xx PowerPC implementations */
710
static void gen_spr_7xx (CPUPPCState *env)
711
{
712
    /* Breakpoints */
713
    /* XXX : not implemented */
714
    spr_register(env, SPR_DABR, "DABR",
715
                 SPR_NOACCESS, SPR_NOACCESS,
716
                 &spr_read_generic, &spr_write_generic,
717
                 0x00000000);
718
    /* XXX : not implemented */
719
    spr_register(env, SPR_IABR, "IABR",
720
                 SPR_NOACCESS, SPR_NOACCESS,
721
                 &spr_read_generic, &spr_write_generic,
722
                 0x00000000);
723
    /* Cache management */
724
    /* XXX : not implemented */
725
    spr_register(env, SPR_ICTC, "ICTC",
726
                 SPR_NOACCESS, SPR_NOACCESS,
727
                 &spr_read_generic, &spr_write_generic,
728
                 0x00000000);
729
    /* XXX : not implemented */
730
    spr_register(env, SPR_L2CR, "L2CR",
731
                 SPR_NOACCESS, SPR_NOACCESS,
732
                 &spr_read_generic, &spr_write_generic,
733
                 0x00000000);
734
    /* Performance monitors */
735
    /* XXX : not implemented */
736
    spr_register(env, SPR_MMCR0, "MMCR0",
737
                 SPR_NOACCESS, SPR_NOACCESS,
738
                 &spr_read_generic, &spr_write_generic,
739
                 0x00000000);
740
    /* XXX : not implemented */
741
    spr_register(env, SPR_MMCR1, "MMCR1",
742
                 SPR_NOACCESS, SPR_NOACCESS,
743
                 &spr_read_generic, &spr_write_generic,
744
                 0x00000000);
745
    /* XXX : not implemented */
746
    spr_register(env, SPR_PMC1, "PMC1",
747
                 SPR_NOACCESS, SPR_NOACCESS,
748
                 &spr_read_generic, &spr_write_generic,
749
                 0x00000000);
750
    /* XXX : not implemented */
751
    spr_register(env, SPR_PMC2, "PMC2",
752
                 SPR_NOACCESS, SPR_NOACCESS,
753
                 &spr_read_generic, &spr_write_generic,
754
                 0x00000000);
755
    /* XXX : not implemented */
756
    spr_register(env, SPR_PMC3, "PMC3",
757
                 SPR_NOACCESS, SPR_NOACCESS,
758
                 &spr_read_generic, &spr_write_generic,
759
                 0x00000000);
760
    /* XXX : not implemented */
761
    spr_register(env, SPR_PMC4, "PMC4",
762
                 SPR_NOACCESS, SPR_NOACCESS,
763
                 &spr_read_generic, &spr_write_generic,
764
                 0x00000000);
765
    /* XXX : not implemented */
766
    spr_register(env, SPR_SIAR, "SIAR",
767
                 SPR_NOACCESS, SPR_NOACCESS,
768
                 &spr_read_generic, SPR_NOACCESS,
769
                 0x00000000);
770
    spr_register(env, SPR_UMMCR0, "UMMCR0",
771
                 &spr_read_ureg, SPR_NOACCESS,
772
                 &spr_read_ureg, SPR_NOACCESS,
773
                 0x00000000);
774
    spr_register(env, SPR_UMMCR1, "UMMCR1",
775
                 &spr_read_ureg, SPR_NOACCESS,
776
                 &spr_read_ureg, SPR_NOACCESS,
777
                 0x00000000);
778
    spr_register(env, SPR_UPMC1, "UPMC1",
779
                 &spr_read_ureg, SPR_NOACCESS,
780
                 &spr_read_ureg, SPR_NOACCESS,
781
                 0x00000000);
782
    spr_register(env, SPR_UPMC2, "UPMC2",
783
                 &spr_read_ureg, SPR_NOACCESS,
784
                 &spr_read_ureg, SPR_NOACCESS,
785
                 0x00000000);
786
    spr_register(env, SPR_UPMC3, "UPMC3",
787
                 &spr_read_ureg, SPR_NOACCESS,
788
                 &spr_read_ureg, SPR_NOACCESS,
789
                 0x00000000);
790
    spr_register(env, SPR_UPMC4, "UPMC4",
791
                 &spr_read_ureg, SPR_NOACCESS,
792
                 &spr_read_ureg, SPR_NOACCESS,
793
                 0x00000000);
794
    spr_register(env, SPR_USIAR, "USIAR",
795
                 &spr_read_ureg, SPR_NOACCESS,
796
                 &spr_read_ureg, SPR_NOACCESS,
797
                 0x00000000);
798
    /* External access control */
799
    /* XXX : not implemented */
800
    spr_register(env, SPR_EAR, "EAR",
801
                 SPR_NOACCESS, SPR_NOACCESS,
802
                 &spr_read_generic, &spr_write_generic,
803
                 0x00000000);
804
}
805

    
806
static void gen_spr_thrm (CPUPPCState *env)
807
{
808
    /* Thermal management */
809
    /* XXX : not implemented */
810
    spr_register(env, SPR_THRM1, "THRM1",
811
                 SPR_NOACCESS, SPR_NOACCESS,
812
                 &spr_read_generic, &spr_write_generic,
813
                 0x00000000);
814
    /* XXX : not implemented */
815
    spr_register(env, SPR_THRM2, "THRM2",
816
                 SPR_NOACCESS, SPR_NOACCESS,
817
                 &spr_read_generic, &spr_write_generic,
818
                 0x00000000);
819
    /* XXX : not implemented */
820
    spr_register(env, SPR_THRM3, "THRM3",
821
                 SPR_NOACCESS, SPR_NOACCESS,
822
                 &spr_read_generic, &spr_write_generic,
823
                 0x00000000);
824
}
825

    
826
/* SPR specific to PowerPC 604 implementation */
827
static void gen_spr_604 (CPUPPCState *env)
828
{
829
    /* Processor identification */
830
    spr_register(env, SPR_PIR, "PIR",
831
                 SPR_NOACCESS, SPR_NOACCESS,
832
                 &spr_read_generic, &spr_write_pir,
833
                 0x00000000);
834
    /* Breakpoints */
835
    /* XXX : not implemented */
836
    spr_register(env, SPR_IABR, "IABR",
837
                 SPR_NOACCESS, SPR_NOACCESS,
838
                 &spr_read_generic, &spr_write_generic,
839
                 0x00000000);
840
    /* XXX : not implemented */
841
    spr_register(env, SPR_DABR, "DABR",
842
                 SPR_NOACCESS, SPR_NOACCESS,
843
                 &spr_read_generic, &spr_write_generic,
844
                 0x00000000);
845
    /* Performance counters */
846
    /* XXX : not implemented */
847
    spr_register(env, SPR_MMCR0, "MMCR0",
848
                 SPR_NOACCESS, SPR_NOACCESS,
849
                 &spr_read_generic, &spr_write_generic,
850
                 0x00000000);
851
    /* XXX : not implemented */
852
    spr_register(env, SPR_MMCR1, "MMCR1",
853
                 SPR_NOACCESS, SPR_NOACCESS,
854
                 &spr_read_generic, &spr_write_generic,
855
                 0x00000000);
856
    /* XXX : not implemented */
857
    spr_register(env, SPR_PMC1, "PMC1",
858
                 SPR_NOACCESS, SPR_NOACCESS,
859
                 &spr_read_generic, &spr_write_generic,
860
                 0x00000000);
861
    /* XXX : not implemented */
862
    spr_register(env, SPR_PMC2, "PMC2",
863
                 SPR_NOACCESS, SPR_NOACCESS,
864
                 &spr_read_generic, &spr_write_generic,
865
                 0x00000000);
866
    /* XXX : not implemented */
867
    spr_register(env, SPR_PMC3, "PMC3",
868
                 SPR_NOACCESS, SPR_NOACCESS,
869
                 &spr_read_generic, &spr_write_generic,
870
                 0x00000000);
871
    /* XXX : not implemented */
872
    spr_register(env, SPR_PMC4, "PMC4",
873
                 SPR_NOACCESS, SPR_NOACCESS,
874
                 &spr_read_generic, &spr_write_generic,
875
                 0x00000000);
876
    /* XXX : not implemented */
877
    spr_register(env, SPR_SIAR, "SIAR",
878
                 SPR_NOACCESS, SPR_NOACCESS,
879
                 &spr_read_generic, SPR_NOACCESS,
880
                 0x00000000);
881
    /* XXX : not implemented */
882
    spr_register(env, SPR_SDA, "SDA",
883
                 SPR_NOACCESS, SPR_NOACCESS,
884
                 &spr_read_generic, SPR_NOACCESS,
885
                 0x00000000);
886
    /* External access control */
887
    /* XXX : not implemented */
888
    spr_register(env, SPR_EAR, "EAR",
889
                 SPR_NOACCESS, SPR_NOACCESS,
890
                 &spr_read_generic, &spr_write_generic,
891
                 0x00000000);
892
}
893

    
894
/* SPR specific to PowerPC 603 implementation */
895
static void gen_spr_603 (CPUPPCState *env)
896
{
897
    /* External access control */
898
    /* XXX : not implemented */
899
    spr_register(env, SPR_EAR, "EAR",
900
                 SPR_NOACCESS, SPR_NOACCESS,
901
                 &spr_read_generic, &spr_write_generic,
902
                 0x00000000);
903
}
904

    
905
/* SPR specific to PowerPC G2 implementation */
906
static void gen_spr_G2 (CPUPPCState *env)
907
{
908
    /* Memory base address */
909
    /* MBAR */
910
    spr_register(env, SPR_MBAR, "MBAR",
911
                 SPR_NOACCESS, SPR_NOACCESS,
912
                 &spr_read_generic, &spr_write_generic,
913
                 0x00000000);
914
    /* System version register */
915
    /* SVR */
916
    spr_register(env, SPR_SVR, "SVR",
917
                 SPR_NOACCESS, SPR_NOACCESS,
918
                 &spr_read_generic, SPR_NOACCESS,
919
                 0x00000000);
920
    /* Exception processing */
921
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
922
                 SPR_NOACCESS, SPR_NOACCESS,
923
                 &spr_read_generic, &spr_write_generic,
924
                 0x00000000);
925
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
926
                 SPR_NOACCESS, SPR_NOACCESS,
927
                 &spr_read_generic, &spr_write_generic,
928
                 0x00000000);
929
    /* Breakpoints */
930
    /* XXX : not implemented */
931
    spr_register(env, SPR_DABR, "DABR",
932
                 SPR_NOACCESS, SPR_NOACCESS,
933
                 &spr_read_generic, &spr_write_generic,
934
                 0x00000000);
935
    /* XXX : not implemented */
936
    spr_register(env, SPR_DABR2, "DABR2",
937
                 SPR_NOACCESS, SPR_NOACCESS,
938
                 &spr_read_generic, &spr_write_generic,
939
                 0x00000000);
940
    /* XXX : not implemented */
941
    spr_register(env, SPR_IABR, "IABR",
942
                 SPR_NOACCESS, SPR_NOACCESS,
943
                 &spr_read_generic, &spr_write_generic,
944
                 0x00000000);
945
    /* XXX : not implemented */
946
    spr_register(env, SPR_IABR2, "IABR2",
947
                 SPR_NOACCESS, SPR_NOACCESS,
948
                 &spr_read_generic, &spr_write_generic,
949
                 0x00000000);
950
    /* XXX : not implemented */
951
    spr_register(env, SPR_IBCR, "IBCR",
952
                 SPR_NOACCESS, SPR_NOACCESS,
953
                 &spr_read_generic, &spr_write_generic,
954
                 0x00000000);
955
    /* XXX : not implemented */
956
    spr_register(env, SPR_DBCR, "DBCR",
957
                 SPR_NOACCESS, SPR_NOACCESS,
958
                 &spr_read_generic, &spr_write_generic,
959
                 0x00000000);
960
}
961

    
962
/* SPR specific to PowerPC 602 implementation */
963
static void gen_spr_602 (CPUPPCState *env)
964
{
965
    /* ESA registers */
966
    /* XXX : not implemented */
967
    spr_register(env, SPR_SER, "SER",
968
                 SPR_NOACCESS, SPR_NOACCESS,
969
                 &spr_read_generic, &spr_write_generic,
970
                 0x00000000);
971
    /* XXX : not implemented */
972
    spr_register(env, SPR_SEBR, "SEBR",
973
                 SPR_NOACCESS, SPR_NOACCESS,
974
                 &spr_read_generic, &spr_write_generic,
975
                 0x00000000);
976
    /* XXX : not implemented */
977
    spr_register(env, SPR_ESASRR, "ESASRR",
978
                 SPR_NOACCESS, SPR_NOACCESS,
979
                 &spr_read_generic, &spr_write_generic,
980
                 0x00000000);
981
    /* Floating point status */
982
    /* XXX : not implemented */
983
    spr_register(env, SPR_SP, "SP",
984
                 SPR_NOACCESS, SPR_NOACCESS,
985
                 &spr_read_generic, &spr_write_generic,
986
                 0x00000000);
987
    /* XXX : not implemented */
988
    spr_register(env, SPR_LT, "LT",
989
                 SPR_NOACCESS, SPR_NOACCESS,
990
                 &spr_read_generic, &spr_write_generic,
991
                 0x00000000);
992
    /* Watchdog timer */
993
    /* XXX : not implemented */
994
    spr_register(env, SPR_TCR, "TCR",
995
                 SPR_NOACCESS, SPR_NOACCESS,
996
                 &spr_read_generic, &spr_write_generic,
997
                 0x00000000);
998
    /* Interrupt base */
999
    spr_register(env, SPR_IBR, "IBR",
1000
                 SPR_NOACCESS, SPR_NOACCESS,
1001
                 &spr_read_generic, &spr_write_generic,
1002
                 0x00000000);
1003
    /* XXX : not implemented */
1004
    spr_register(env, SPR_IABR, "IABR",
1005
                 SPR_NOACCESS, SPR_NOACCESS,
1006
                 &spr_read_generic, &spr_write_generic,
1007
                 0x00000000);
1008
}
1009

    
1010
/* SPR specific to PowerPC 601 implementation */
1011
static void gen_spr_601 (CPUPPCState *env)
1012
{
1013
    /* Multiplication/division register */
1014
    /* MQ */
1015
    spr_register(env, SPR_MQ, "MQ",
1016
                 &spr_read_generic, &spr_write_generic,
1017
                 &spr_read_generic, &spr_write_generic,
1018
                 0x00000000);
1019
    /* RTC registers */
1020
    spr_register(env, SPR_601_RTCU, "RTCU",
1021
                 SPR_NOACCESS, SPR_NOACCESS,
1022
                 SPR_NOACCESS, &spr_write_601_rtcu,
1023
                 0x00000000);
1024
    spr_register(env, SPR_601_VRTCU, "RTCU",
1025
                 &spr_read_601_rtcu, SPR_NOACCESS,
1026
                 &spr_read_601_rtcu, SPR_NOACCESS,
1027
                 0x00000000);
1028
    spr_register(env, SPR_601_RTCL, "RTCL",
1029
                 SPR_NOACCESS, SPR_NOACCESS,
1030
                 SPR_NOACCESS, &spr_write_601_rtcl,
1031
                 0x00000000);
1032
    spr_register(env, SPR_601_VRTCL, "RTCL",
1033
                 &spr_read_601_rtcl, SPR_NOACCESS,
1034
                 &spr_read_601_rtcl, SPR_NOACCESS,
1035
                 0x00000000);
1036
    /* Timer */
1037
#if 0 /* ? */
1038
    spr_register(env, SPR_601_UDECR, "UDECR",
1039
                 &spr_read_decr, SPR_NOACCESS,
1040
                 &spr_read_decr, SPR_NOACCESS,
1041
                 0x00000000);
1042
#endif
1043
    /* External access control */
1044
    /* XXX : not implemented */
1045
    spr_register(env, SPR_EAR, "EAR",
1046
                 SPR_NOACCESS, SPR_NOACCESS,
1047
                 &spr_read_generic, &spr_write_generic,
1048
                 0x00000000);
1049
    /* Memory management */
1050
    spr_register(env, SPR_IBAT0U, "IBAT0U",
1051
                 SPR_NOACCESS, SPR_NOACCESS,
1052
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1053
                 0x00000000);
1054
    spr_register(env, SPR_IBAT0L, "IBAT0L",
1055
                 SPR_NOACCESS, SPR_NOACCESS,
1056
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1057
                 0x00000000);
1058
    spr_register(env, SPR_IBAT1U, "IBAT1U",
1059
                 SPR_NOACCESS, SPR_NOACCESS,
1060
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1061
                 0x00000000);
1062
    spr_register(env, SPR_IBAT1L, "IBAT1L",
1063
                 SPR_NOACCESS, SPR_NOACCESS,
1064
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1065
                 0x00000000);
1066
    spr_register(env, SPR_IBAT2U, "IBAT2U",
1067
                 SPR_NOACCESS, SPR_NOACCESS,
1068
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1069
                 0x00000000);
1070
    spr_register(env, SPR_IBAT2L, "IBAT2L",
1071
                 SPR_NOACCESS, SPR_NOACCESS,
1072
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1073
                 0x00000000);
1074
    spr_register(env, SPR_IBAT3U, "IBAT3U",
1075
                 SPR_NOACCESS, SPR_NOACCESS,
1076
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1077
                 0x00000000);
1078
    spr_register(env, SPR_IBAT3L, "IBAT3L",
1079
                 SPR_NOACCESS, SPR_NOACCESS,
1080
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1081
                 0x00000000);
1082
    env->nb_BATs = 4;
1083
}
1084

    
1085
static void gen_spr_74xx (CPUPPCState *env)
1086
{
1087
    /* Processor identification */
1088
    spr_register(env, SPR_PIR, "PIR",
1089
                 SPR_NOACCESS, SPR_NOACCESS,
1090
                 &spr_read_generic, &spr_write_pir,
1091
                 0x00000000);
1092
    /* XXX : not implemented */
1093
    spr_register(env, SPR_MMCR2, "MMCR2",
1094
                 SPR_NOACCESS, SPR_NOACCESS,
1095
                 &spr_read_generic, &spr_write_generic,
1096
                 0x00000000);
1097
    spr_register(env, SPR_UMMCR2, "UMMCR2",
1098
                 &spr_read_ureg, SPR_NOACCESS,
1099
                 &spr_read_ureg, SPR_NOACCESS,
1100
                 0x00000000);
1101
    /* XXX: not implemented */
1102
    spr_register(env, SPR_BAMR, "BAMR",
1103
                 SPR_NOACCESS, SPR_NOACCESS,
1104
                 &spr_read_generic, &spr_write_generic,
1105
                 0x00000000);
1106
    spr_register(env, SPR_UBAMR, "UBAMR",
1107
                 &spr_read_ureg, SPR_NOACCESS,
1108
                 &spr_read_ureg, SPR_NOACCESS,
1109
                 0x00000000);
1110
    spr_register(env, SPR_MSSCR0, "MSSCR0",
1111
                 SPR_NOACCESS, SPR_NOACCESS,
1112
                 &spr_read_generic, &spr_write_generic,
1113
                 0x00000000);
1114
    /* Hardware implementation registers */
1115
    /* XXX : not implemented */
1116
    spr_register(env, SPR_HID0, "HID0",
1117
                 SPR_NOACCESS, SPR_NOACCESS,
1118
                 &spr_read_generic, &spr_write_generic,
1119
                 0x00000000);
1120
    /* XXX : not implemented */
1121
    spr_register(env, SPR_HID1, "HID1",
1122
                 SPR_NOACCESS, SPR_NOACCESS,
1123
                 &spr_read_generic, &spr_write_generic,
1124
                 0x00000000);
1125
    /* Altivec */
1126
    spr_register(env, SPR_VRSAVE, "VRSAVE",
1127
                 &spr_read_generic, &spr_write_generic,
1128
                 &spr_read_generic, &spr_write_generic,
1129
                 0x00000000);
1130
}
1131

    
1132
#if defined (TODO)
1133
static void gen_l3_ctrl (CPUPPCState *env)
1134
{
1135
    /* L3CR */
1136
    /* XXX : not implemented */
1137
    spr_register(env, SPR_L3CR, "L3CR",
1138
                 SPR_NOACCESS, SPR_NOACCESS,
1139
                 &spr_read_generic, &spr_write_generic,
1140
                 0x00000000);
1141
    /* L3ITCR0 */
1142
    spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1143
                 SPR_NOACCESS, SPR_NOACCESS,
1144
                 &spr_read_generic, &spr_write_generic,
1145
                 0x00000000);
1146
    /* L3ITCR1 */
1147
    spr_register(env, SPR_L3ITCR1, "L3ITCR1",
1148
                 SPR_NOACCESS, SPR_NOACCESS,
1149
                 &spr_read_generic, &spr_write_generic,
1150
                 0x00000000);
1151
    /* L3ITCR2 */
1152
    spr_register(env, SPR_L3ITCR2, "L3ITCR2",
1153
                 SPR_NOACCESS, SPR_NOACCESS,
1154
                 &spr_read_generic, &spr_write_generic,
1155
                 0x00000000);
1156
    /* L3ITCR3 */
1157
    spr_register(env, SPR_L3ITCR3, "L3ITCR3",
1158
                 SPR_NOACCESS, SPR_NOACCESS,
1159
                 &spr_read_generic, &spr_write_generic,
1160
                 0x00000000);
1161
    /* L3OHCR */
1162
    spr_register(env, SPR_L3OHCR, "L3OHCR",
1163
                 SPR_NOACCESS, SPR_NOACCESS,
1164
                 &spr_read_generic, &spr_write_generic,
1165
                 0x00000000);
1166
    /* L3PM */
1167
    spr_register(env, SPR_L3PM, "L3PM",
1168
                 SPR_NOACCESS, SPR_NOACCESS,
1169
                 &spr_read_generic, &spr_write_generic,
1170
                 0x00000000);
1171
}
1172
#endif /* TODO */
1173

    
1174
#if defined (TODO)
1175
static void gen_74xx_soft_tlb (CPUPPCState *env)
1176
{
1177
    /* XXX: TODO */
1178
    spr_register(env, SPR_PTEHI, "PTEHI",
1179
                 SPR_NOACCESS, SPR_NOACCESS,
1180
                 &spr_read_generic, &spr_write_generic,
1181
                 0x00000000);
1182
    spr_register(env, SPR_PTELO, "PTELO",
1183
                 SPR_NOACCESS, SPR_NOACCESS,
1184
                 &spr_read_generic, &spr_write_generic,
1185
                 0x00000000);
1186
    spr_register(env, SPR_TLBMISS, "TLBMISS",
1187
                 SPR_NOACCESS, SPR_NOACCESS,
1188
                 &spr_read_generic, &spr_write_generic,
1189
                 0x00000000);
1190
}
1191
#endif /* TODO */
1192

    
1193
/* PowerPC BookE SPR */
1194
static void gen_spr_BookE (CPUPPCState *env)
1195
{
1196
    /* Processor identification */
1197
    spr_register(env, SPR_BOOKE_PIR, "PIR",
1198
                 SPR_NOACCESS, SPR_NOACCESS,
1199
                 &spr_read_generic, &spr_write_pir,
1200
                 0x00000000);
1201
    /* Interrupt processing */
1202
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1203
                 SPR_NOACCESS, SPR_NOACCESS,
1204
                 &spr_read_generic, &spr_write_generic,
1205
                 0x00000000);
1206
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1207
                 SPR_NOACCESS, SPR_NOACCESS,
1208
                 &spr_read_generic, &spr_write_generic,
1209
                 0x00000000);
1210
#if 0
1211
    spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1212
                 SPR_NOACCESS, SPR_NOACCESS,
1213
                 &spr_read_generic, &spr_write_generic,
1214
                 0x00000000);
1215
    spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1216
                 SPR_NOACCESS, SPR_NOACCESS,
1217
                 &spr_read_generic, &spr_write_generic,
1218
                 0x00000000);
1219
#endif
1220
    /* Debug */
1221
    /* XXX : not implemented */
1222
    spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1223
                 SPR_NOACCESS, SPR_NOACCESS,
1224
                 &spr_read_generic, &spr_write_generic,
1225
                 0x00000000);
1226
    /* XXX : not implemented */
1227
    spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1228
                 SPR_NOACCESS, SPR_NOACCESS,
1229
                 &spr_read_generic, &spr_write_generic,
1230
                 0x00000000);
1231
    /* XXX : not implemented */
1232
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1233
                 SPR_NOACCESS, SPR_NOACCESS,
1234
                 &spr_read_generic, &spr_write_generic,
1235
                 0x00000000);
1236
    /* XXX : not implemented */
1237
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1238
                 SPR_NOACCESS, SPR_NOACCESS,
1239
                 &spr_read_generic, &spr_write_generic,
1240
                 0x00000000);
1241
    /* XXX : not implemented */
1242
    spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1243
                 SPR_NOACCESS, SPR_NOACCESS,
1244
                 &spr_read_generic, &spr_write_generic,
1245
                 0x00000000);
1246
    /* XXX : not implemented */
1247
    spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1248
                 SPR_NOACCESS, SPR_NOACCESS,
1249
                 &spr_read_generic, &spr_write_generic,
1250
                 0x00000000);
1251
    /* XXX : not implemented */
1252
    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1253
                 SPR_NOACCESS, SPR_NOACCESS,
1254
                 &spr_read_generic, &spr_write_generic,
1255
                 0x00000000);
1256
    /* XXX : not implemented */
1257
    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1258
                 SPR_NOACCESS, SPR_NOACCESS,
1259
                 &spr_read_generic, &spr_write_generic,
1260
                 0x00000000);
1261
    /* XXX : not implemented */
1262
    spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1263
                 SPR_NOACCESS, SPR_NOACCESS,
1264
                 &spr_read_generic, &spr_write_generic,
1265
                 0x00000000);
1266
    /* XXX : not implemented */
1267
    spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1268
                 SPR_NOACCESS, SPR_NOACCESS,
1269
                 &spr_read_generic, &spr_write_generic,
1270
                 0x00000000);
1271
    /* XXX : not implemented */
1272
    spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1273
                 SPR_NOACCESS, SPR_NOACCESS,
1274
                 &spr_read_generic, &spr_write_generic,
1275
                 0x00000000);
1276
    /* XXX : not implemented */
1277
    spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1278
                 SPR_NOACCESS, SPR_NOACCESS,
1279
                 &spr_read_generic, &spr_write_clear,
1280
                 0x00000000);
1281
    spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1282
                 SPR_NOACCESS, SPR_NOACCESS,
1283
                 &spr_read_generic, &spr_write_generic,
1284
                 0x00000000);
1285
    spr_register(env, SPR_BOOKE_ESR, "ESR",
1286
                 SPR_NOACCESS, SPR_NOACCESS,
1287
                 &spr_read_generic, &spr_write_generic,
1288
                 0x00000000);
1289
    spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1290
                 SPR_NOACCESS, SPR_NOACCESS,
1291
                 &spr_read_generic, &spr_write_generic,
1292
                 0x00000000);
1293
    /* Exception vectors */
1294
    spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1295
                 SPR_NOACCESS, SPR_NOACCESS,
1296
                 &spr_read_generic, &spr_write_generic,
1297
                 0x00000000);
1298
    spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1299
                 SPR_NOACCESS, SPR_NOACCESS,
1300
                 &spr_read_generic, &spr_write_generic,
1301
                 0x00000000);
1302
    spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1303
                 SPR_NOACCESS, SPR_NOACCESS,
1304
                 &spr_read_generic, &spr_write_generic,
1305
                 0x00000000);
1306
    spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1307
                 SPR_NOACCESS, SPR_NOACCESS,
1308
                 &spr_read_generic, &spr_write_generic,
1309
                 0x00000000);
1310
    spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1311
                 SPR_NOACCESS, SPR_NOACCESS,
1312
                 &spr_read_generic, &spr_write_generic,
1313
                 0x00000000);
1314
    spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1315
                 SPR_NOACCESS, SPR_NOACCESS,
1316
                 &spr_read_generic, &spr_write_generic,
1317
                 0x00000000);
1318
    spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1319
                 SPR_NOACCESS, SPR_NOACCESS,
1320
                 &spr_read_generic, &spr_write_generic,
1321
                 0x00000000);
1322
    spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1323
                 SPR_NOACCESS, SPR_NOACCESS,
1324
                 &spr_read_generic, &spr_write_generic,
1325
                 0x00000000);
1326
    spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1327
                 SPR_NOACCESS, SPR_NOACCESS,
1328
                 &spr_read_generic, &spr_write_generic,
1329
                 0x00000000);
1330
    spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1331
                 SPR_NOACCESS, SPR_NOACCESS,
1332
                 &spr_read_generic, &spr_write_generic,
1333
                 0x00000000);
1334
    spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1335
                 SPR_NOACCESS, SPR_NOACCESS,
1336
                 &spr_read_generic, &spr_write_generic,
1337
                 0x00000000);
1338
    spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1339
                 SPR_NOACCESS, SPR_NOACCESS,
1340
                 &spr_read_generic, &spr_write_generic,
1341
                 0x00000000);
1342
    spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1343
                 SPR_NOACCESS, SPR_NOACCESS,
1344
                 &spr_read_generic, &spr_write_generic,
1345
                 0x00000000);
1346
    spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1347
                 SPR_NOACCESS, SPR_NOACCESS,
1348
                 &spr_read_generic, &spr_write_generic,
1349
                 0x00000000);
1350
    spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1351
                 SPR_NOACCESS, SPR_NOACCESS,
1352
                 &spr_read_generic, &spr_write_generic,
1353
                 0x00000000);
1354
    spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1355
                 SPR_NOACCESS, SPR_NOACCESS,
1356
                 &spr_read_generic, &spr_write_generic,
1357
                 0x00000000);
1358
#if 0
1359
    spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1360
                 SPR_NOACCESS, SPR_NOACCESS,
1361
                 &spr_read_generic, &spr_write_generic,
1362
                 0x00000000);
1363
    spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1364
                 SPR_NOACCESS, SPR_NOACCESS,
1365
                 &spr_read_generic, &spr_write_generic,
1366
                 0x00000000);
1367
    spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1368
                 SPR_NOACCESS, SPR_NOACCESS,
1369
                 &spr_read_generic, &spr_write_generic,
1370
                 0x00000000);
1371
    spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1372
                 SPR_NOACCESS, SPR_NOACCESS,
1373
                 &spr_read_generic, &spr_write_generic,
1374
                 0x00000000);
1375
    spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1376
                 SPR_NOACCESS, SPR_NOACCESS,
1377
                 &spr_read_generic, &spr_write_generic,
1378
                 0x00000000);
1379
    spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1380
                 SPR_NOACCESS, SPR_NOACCESS,
1381
                 &spr_read_generic, &spr_write_generic,
1382
                 0x00000000);
1383
#endif
1384
    spr_register(env, SPR_BOOKE_PID, "PID",
1385
                 SPR_NOACCESS, SPR_NOACCESS,
1386
                 &spr_read_generic, &spr_write_generic,
1387
                 0x00000000);
1388
    spr_register(env, SPR_BOOKE_TCR, "TCR",
1389
                 SPR_NOACCESS, SPR_NOACCESS,
1390
                 &spr_read_generic, &spr_write_booke_tcr,
1391
                 0x00000000);
1392
    spr_register(env, SPR_BOOKE_TSR, "TSR",
1393
                 SPR_NOACCESS, SPR_NOACCESS,
1394
                 &spr_read_generic, &spr_write_booke_tsr,
1395
                 0x00000000);
1396
    /* Timer */
1397
    spr_register(env, SPR_DECR, "DECR",
1398
                 SPR_NOACCESS, SPR_NOACCESS,
1399
                 &spr_read_decr, &spr_write_decr,
1400
                 0x00000000);
1401
    spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1402
                 SPR_NOACCESS, SPR_NOACCESS,
1403
                 SPR_NOACCESS, &spr_write_generic,
1404
                 0x00000000);
1405
    /* SPRGs */
1406
    spr_register(env, SPR_USPRG0, "USPRG0",
1407
                 &spr_read_generic, &spr_write_generic,
1408
                 &spr_read_generic, &spr_write_generic,
1409
                 0x00000000);
1410
    spr_register(env, SPR_SPRG4, "SPRG4",
1411
                 SPR_NOACCESS, SPR_NOACCESS,
1412
                 &spr_read_generic, &spr_write_generic,
1413
                 0x00000000);
1414
    spr_register(env, SPR_USPRG4, "USPRG4",
1415
                 &spr_read_ureg, SPR_NOACCESS,
1416
                 &spr_read_ureg, SPR_NOACCESS,
1417
                 0x00000000);
1418
    spr_register(env, SPR_SPRG5, "SPRG5",
1419
                 SPR_NOACCESS, SPR_NOACCESS,
1420
                 &spr_read_generic, &spr_write_generic,
1421
                 0x00000000);
1422
    spr_register(env, SPR_USPRG5, "USPRG5",
1423
                 &spr_read_ureg, SPR_NOACCESS,
1424
                 &spr_read_ureg, SPR_NOACCESS,
1425
                 0x00000000);
1426
    spr_register(env, SPR_SPRG6, "SPRG6",
1427
                 SPR_NOACCESS, SPR_NOACCESS,
1428
                 &spr_read_generic, &spr_write_generic,
1429
                 0x00000000);
1430
    spr_register(env, SPR_USPRG6, "USPRG6",
1431
                 &spr_read_ureg, SPR_NOACCESS,
1432
                 &spr_read_ureg, SPR_NOACCESS,
1433
                 0x00000000);
1434
    spr_register(env, SPR_SPRG7, "SPRG7",
1435
                 SPR_NOACCESS, SPR_NOACCESS,
1436
                 &spr_read_generic, &spr_write_generic,
1437
                 0x00000000);
1438
    spr_register(env, SPR_USPRG7, "USPRG7",
1439
                 &spr_read_ureg, SPR_NOACCESS,
1440
                 &spr_read_ureg, SPR_NOACCESS,
1441
                 0x00000000);
1442
}
1443

    
1444
/* FSL storage control registers */
1445
#if defined(TODO)
1446
static void gen_spr_BookE_FSL (CPUPPCState *env)
1447
{
1448
    /* TLB assist registers */
1449
    spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1450
                 SPR_NOACCESS, SPR_NOACCESS,
1451
                 &spr_read_generic, &spr_write_generic,
1452
                 0x00000000);
1453
    spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1454
                 SPR_NOACCESS, SPR_NOACCESS,
1455
                 &spr_read_generic, &spr_write_generic,
1456
                 0x00000000);
1457
    spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1458
                 SPR_NOACCESS, SPR_NOACCESS,
1459
                 &spr_read_generic, &spr_write_generic,
1460
                 0x00000000);
1461
    spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1462
                 SPR_NOACCESS, SPR_NOACCESS,
1463
                 &spr_read_generic, &spr_write_generic,
1464
                 0x00000000);
1465
    spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1466
                 SPR_NOACCESS, SPR_NOACCESS,
1467
                 &spr_read_generic, &spr_write_generic,
1468
                 0x00000000);
1469
    spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1470
                 SPR_NOACCESS, SPR_NOACCESS,
1471
                 &spr_read_generic, &spr_write_generic,
1472
                 0x00000000);
1473
    spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1474
                 SPR_NOACCESS, SPR_NOACCESS,
1475
                 &spr_read_generic, &spr_write_generic,
1476
                 0x00000000);
1477
    if (env->nb_pids > 1) {
1478
        spr_register(env, SPR_BOOKE_PID1, "PID1",
1479
                     SPR_NOACCESS, SPR_NOACCESS,
1480
                     &spr_read_generic, &spr_write_generic,
1481
                     0x00000000);
1482
    }
1483
    if (env->nb_pids > 2) {
1484
        spr_register(env, SPR_BOOKE_PID2, "PID2",
1485
                     SPR_NOACCESS, SPR_NOACCESS,
1486
                     &spr_read_generic, &spr_write_generic,
1487
                     0x00000000);
1488
    }
1489
    spr_register(env, SPR_BOOKE_MMUCFG, "MMUCFG",
1490
                 SPR_NOACCESS, SPR_NOACCESS,
1491
                 &spr_read_generic, SPR_NOACCESS,
1492
                 0x00000000); /* TOFIX */
1493
    spr_register(env, SPR_BOOKE_MMUCSR0, "MMUCSR0",
1494
                 SPR_NOACCESS, SPR_NOACCESS,
1495
                 &spr_read_generic, &spr_write_generic,
1496
                 0x00000000); /* TOFIX */
1497
    switch (env->nb_ways) {
1498
    case 4:
1499
        spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1500
                     SPR_NOACCESS, SPR_NOACCESS,
1501
                     &spr_read_generic, SPR_NOACCESS,
1502
                     0x00000000); /* TOFIX */
1503
        /* Fallthru */
1504
    case 3:
1505
        spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1506
                     SPR_NOACCESS, SPR_NOACCESS,
1507
                     &spr_read_generic, SPR_NOACCESS,
1508
                     0x00000000); /* TOFIX */
1509
        /* Fallthru */
1510
    case 2:
1511
        spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1512
                     SPR_NOACCESS, SPR_NOACCESS,
1513
                     &spr_read_generic, SPR_NOACCESS,
1514
                     0x00000000); /* TOFIX */
1515
        /* Fallthru */
1516
    case 1:
1517
        spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1518
                     SPR_NOACCESS, SPR_NOACCESS,
1519
                     &spr_read_generic, SPR_NOACCESS,
1520
                     0x00000000); /* TOFIX */
1521
        /* Fallthru */
1522
    case 0:
1523
    default:
1524
        break;
1525
    }
1526
}
1527
#endif
1528

    
1529
/* SPR specific to PowerPC 440 implementation */
1530
static void gen_spr_440 (CPUPPCState *env)
1531
{
1532
    /* Cache control */
1533
    /* XXX : not implemented */
1534
    spr_register(env, SPR_440_DNV0, "DNV0",
1535
                 SPR_NOACCESS, SPR_NOACCESS,
1536
                 &spr_read_generic, &spr_write_generic,
1537
                 0x00000000);
1538
    /* XXX : not implemented */
1539
    spr_register(env, SPR_440_DNV1, "DNV1",
1540
                 SPR_NOACCESS, SPR_NOACCESS,
1541
                 &spr_read_generic, &spr_write_generic,
1542
                 0x00000000);
1543
    /* XXX : not implemented */
1544
    spr_register(env, SPR_440_DNV2, "DNV2",
1545
                 SPR_NOACCESS, SPR_NOACCESS,
1546
                 &spr_read_generic, &spr_write_generic,
1547
                 0x00000000);
1548
    /* XXX : not implemented */
1549
    spr_register(env, SPR_440_DNV3, "DNV3",
1550
                 SPR_NOACCESS, SPR_NOACCESS,
1551
                 &spr_read_generic, &spr_write_generic,
1552
                 0x00000000);
1553
    /* XXX : not implemented */
1554
    spr_register(env, SPR_440_DTV0, "DTV0",
1555
                 SPR_NOACCESS, SPR_NOACCESS,
1556
                 &spr_read_generic, &spr_write_generic,
1557
                 0x00000000);
1558
    /* XXX : not implemented */
1559
    spr_register(env, SPR_440_DTV1, "DTV1",
1560
                 SPR_NOACCESS, SPR_NOACCESS,
1561
                 &spr_read_generic, &spr_write_generic,
1562
                 0x00000000);
1563
    /* XXX : not implemented */
1564
    spr_register(env, SPR_440_DTV2, "DTV2",
1565
                 SPR_NOACCESS, SPR_NOACCESS,
1566
                 &spr_read_generic, &spr_write_generic,
1567
                 0x00000000);
1568
    /* XXX : not implemented */
1569
    spr_register(env, SPR_440_DTV3, "DTV3",
1570
                 SPR_NOACCESS, SPR_NOACCESS,
1571
                 &spr_read_generic, &spr_write_generic,
1572
                 0x00000000);
1573
    /* XXX : not implemented */
1574
    spr_register(env, SPR_440_DVLIM, "DVLIM",
1575
                 SPR_NOACCESS, SPR_NOACCESS,
1576
                 &spr_read_generic, &spr_write_generic,
1577
                 0x00000000);
1578
    /* XXX : not implemented */
1579
    spr_register(env, SPR_440_INV0, "INV0",
1580
                 SPR_NOACCESS, SPR_NOACCESS,
1581
                 &spr_read_generic, &spr_write_generic,
1582
                 0x00000000);
1583
    /* XXX : not implemented */
1584
    spr_register(env, SPR_440_INV1, "INV1",
1585
                 SPR_NOACCESS, SPR_NOACCESS,
1586
                 &spr_read_generic, &spr_write_generic,
1587
                 0x00000000);
1588
    /* XXX : not implemented */
1589
    spr_register(env, SPR_440_INV2, "INV2",
1590
                 SPR_NOACCESS, SPR_NOACCESS,
1591
                 &spr_read_generic, &spr_write_generic,
1592
                 0x00000000);
1593
    /* XXX : not implemented */
1594
    spr_register(env, SPR_440_INV3, "INV3",
1595
                 SPR_NOACCESS, SPR_NOACCESS,
1596
                 &spr_read_generic, &spr_write_generic,
1597
                 0x00000000);
1598
    /* XXX : not implemented */
1599
    spr_register(env, SPR_440_ITV0, "ITV0",
1600
                 SPR_NOACCESS, SPR_NOACCESS,
1601
                 &spr_read_generic, &spr_write_generic,
1602
                 0x00000000);
1603
    /* XXX : not implemented */
1604
    spr_register(env, SPR_440_ITV1, "ITV1",
1605
                 SPR_NOACCESS, SPR_NOACCESS,
1606
                 &spr_read_generic, &spr_write_generic,
1607
                 0x00000000);
1608
    /* XXX : not implemented */
1609
    spr_register(env, SPR_440_ITV2, "ITV2",
1610
                 SPR_NOACCESS, SPR_NOACCESS,
1611
                 &spr_read_generic, &spr_write_generic,
1612
                 0x00000000);
1613
    /* XXX : not implemented */
1614
    spr_register(env, SPR_440_ITV3, "ITV3",
1615
                 SPR_NOACCESS, SPR_NOACCESS,
1616
                 &spr_read_generic, &spr_write_generic,
1617
                 0x00000000);
1618
    /* XXX : not implemented */
1619
    spr_register(env, SPR_440_IVLIM, "IVLIM",
1620
                 SPR_NOACCESS, SPR_NOACCESS,
1621
                 &spr_read_generic, &spr_write_generic,
1622
                 0x00000000);
1623
    /* Cache debug */
1624
    /* XXX : not implemented */
1625
    spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1626
                 SPR_NOACCESS, SPR_NOACCESS,
1627
                 &spr_read_generic, SPR_NOACCESS,
1628
                 0x00000000);
1629
    /* XXX : not implemented */
1630
    spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1631
                 SPR_NOACCESS, SPR_NOACCESS,
1632
                 &spr_read_generic, SPR_NOACCESS,
1633
                 0x00000000);
1634
    /* XXX : not implemented */
1635
    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1636
                 SPR_NOACCESS, SPR_NOACCESS,
1637
                 &spr_read_generic, SPR_NOACCESS,
1638
                 0x00000000);
1639
    /* XXX : not implemented */
1640
    spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1641
                 SPR_NOACCESS, SPR_NOACCESS,
1642
                 &spr_read_generic, SPR_NOACCESS,
1643
                 0x00000000);
1644
    /* XXX : not implemented */
1645
    spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1646
                 SPR_NOACCESS, SPR_NOACCESS,
1647
                 &spr_read_generic, SPR_NOACCESS,
1648
                 0x00000000);
1649
    /* XXX : not implemented */
1650
    spr_register(env, SPR_440_DBDR, "DBDR",
1651
                 SPR_NOACCESS, SPR_NOACCESS,
1652
                 &spr_read_generic, &spr_write_generic,
1653
                 0x00000000);
1654
    /* Processor control */
1655
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1656
                 SPR_NOACCESS, SPR_NOACCESS,
1657
                 &spr_read_generic, &spr_write_generic,
1658
                 0x00000000);
1659
    spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1660
                 SPR_NOACCESS, SPR_NOACCESS,
1661
                 &spr_read_generic, SPR_NOACCESS,
1662
                 0x00000000);
1663
    /* Storage control */
1664
    spr_register(env, SPR_440_MMUCR, "MMUCR",
1665
                 SPR_NOACCESS, SPR_NOACCESS,
1666
                 &spr_read_generic, &spr_write_generic,
1667
                 0x00000000);
1668
}
1669

    
1670
/* SPR shared between PowerPC 40x implementations */
1671
static void gen_spr_40x (CPUPPCState *env)
1672
{
1673
    /* Cache */
1674
    /* XXX : not implemented */
1675
    spr_register(env, SPR_40x_DCCR, "DCCR",
1676
                 SPR_NOACCESS, SPR_NOACCESS,
1677
                 &spr_read_generic, &spr_write_generic,
1678
                 0x00000000);
1679
    /* XXX : not implemented */
1680
    spr_register(env, SPR_40x_ICCR, "ICCR",
1681
                 SPR_NOACCESS, SPR_NOACCESS,
1682
                 &spr_read_generic, &spr_write_generic,
1683
                 0x00000000);
1684
    /* XXX : not implemented */
1685
    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1686
                 SPR_NOACCESS, SPR_NOACCESS,
1687
                 &spr_read_generic, SPR_NOACCESS,
1688
                 0x00000000);
1689
    /* Exception */
1690
    spr_register(env, SPR_40x_DEAR, "DEAR",
1691
                 SPR_NOACCESS, SPR_NOACCESS,
1692
                 &spr_read_generic, &spr_write_generic,
1693
                 0x00000000);
1694
    spr_register(env, SPR_40x_ESR, "ESR",
1695
                 SPR_NOACCESS, SPR_NOACCESS,
1696
                 &spr_read_generic, &spr_write_generic,
1697
                 0x00000000);
1698
    spr_register(env, SPR_40x_EVPR, "EVPR",
1699
                 SPR_NOACCESS, SPR_NOACCESS,
1700
                 &spr_read_generic, &spr_write_generic,
1701
                 0x00000000);
1702
    spr_register(env, SPR_40x_SRR2, "SRR2",
1703
                 &spr_read_generic, &spr_write_generic,
1704
                 &spr_read_generic, &spr_write_generic,
1705
                 0x00000000);
1706
    spr_register(env, SPR_40x_SRR3, "SRR3",
1707
                 &spr_read_generic, &spr_write_generic,
1708
                 &spr_read_generic, &spr_write_generic,
1709
                 0x00000000);
1710
    /* Timers */
1711
    spr_register(env, SPR_40x_PIT, "PIT",
1712
                 SPR_NOACCESS, SPR_NOACCESS,
1713
                 &spr_read_40x_pit, &spr_write_40x_pit,
1714
                 0x00000000);
1715
    spr_register(env, SPR_40x_TCR, "TCR",
1716
                 SPR_NOACCESS, SPR_NOACCESS,
1717
                 &spr_read_generic, &spr_write_booke_tcr,
1718
                 0x00000000);
1719
    spr_register(env, SPR_40x_TSR, "TSR",
1720
                 SPR_NOACCESS, SPR_NOACCESS,
1721
                 &spr_read_generic, &spr_write_booke_tsr,
1722
                 0x00000000);
1723
}
1724

    
1725
/* SPR specific to PowerPC 405 implementation */
1726
static void gen_spr_405 (CPUPPCState *env)
1727
{
1728
    /* MMU */
1729
    spr_register(env, SPR_40x_PID, "PID",
1730
                 SPR_NOACCESS, SPR_NOACCESS,
1731
                 &spr_read_generic, &spr_write_generic,
1732
                 0x00000000);
1733
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1734
                 SPR_NOACCESS, SPR_NOACCESS,
1735
                 &spr_read_generic, &spr_write_generic,
1736
                 0x00700000);
1737
    /* Debug interface */
1738
    /* XXX : not implemented */
1739
    spr_register(env, SPR_40x_DBCR0, "DBCR0",
1740
                 SPR_NOACCESS, SPR_NOACCESS,
1741
                 &spr_read_generic, &spr_write_40x_dbcr0,
1742
                 0x00000000);
1743
    /* XXX : not implemented */
1744
    spr_register(env, SPR_405_DBCR1, "DBCR1",
1745
                 SPR_NOACCESS, SPR_NOACCESS,
1746
                 &spr_read_generic, &spr_write_generic,
1747
                 0x00000000);
1748
    /* XXX : not implemented */
1749
    spr_register(env, SPR_40x_DBSR, "DBSR",
1750
                 SPR_NOACCESS, SPR_NOACCESS,
1751
                 &spr_read_generic, &spr_write_clear,
1752
                 /* Last reset was system reset */
1753
                 0x00000300);
1754
    /* XXX : not implemented */
1755
    spr_register(env, SPR_40x_DAC1, "DAC1",
1756
                 SPR_NOACCESS, SPR_NOACCESS,
1757
                 &spr_read_generic, &spr_write_generic,
1758
                 0x00000000);
1759
    spr_register(env, SPR_40x_DAC2, "DAC2",
1760
                 SPR_NOACCESS, SPR_NOACCESS,
1761
                 &spr_read_generic, &spr_write_generic,
1762
                 0x00000000);
1763
    /* XXX : not implemented */
1764
    spr_register(env, SPR_405_DVC1, "DVC1",
1765
                 SPR_NOACCESS, SPR_NOACCESS,
1766
                 &spr_read_generic, &spr_write_generic,
1767
                 0x00000000);
1768
    /* XXX : not implemented */
1769
    spr_register(env, SPR_405_DVC2, "DVC2",
1770
                 SPR_NOACCESS, SPR_NOACCESS,
1771
                 &spr_read_generic, &spr_write_generic,
1772
                 0x00000000);
1773
    /* XXX : not implemented */
1774
    spr_register(env, SPR_40x_IAC1, "IAC1",
1775
                 SPR_NOACCESS, SPR_NOACCESS,
1776
                 &spr_read_generic, &spr_write_generic,
1777
                 0x00000000);
1778
    spr_register(env, SPR_40x_IAC2, "IAC2",
1779
                 SPR_NOACCESS, SPR_NOACCESS,
1780
                 &spr_read_generic, &spr_write_generic,
1781
                 0x00000000);
1782
    /* XXX : not implemented */
1783
    spr_register(env, SPR_405_IAC3, "IAC3",
1784
                 SPR_NOACCESS, SPR_NOACCESS,
1785
                 &spr_read_generic, &spr_write_generic,
1786
                 0x00000000);
1787
    /* XXX : not implemented */
1788
    spr_register(env, SPR_405_IAC4, "IAC4",
1789
                 SPR_NOACCESS, SPR_NOACCESS,
1790
                 &spr_read_generic, &spr_write_generic,
1791
                 0x00000000);
1792
    /* Storage control */
1793
    spr_register(env, SPR_405_SLER, "SLER",
1794
                 SPR_NOACCESS, SPR_NOACCESS,
1795
                 &spr_read_generic, &spr_write_40x_sler,
1796
                 0x00000000);
1797
    spr_register(env, SPR_40x_ZPR, "ZPR",
1798
                 SPR_NOACCESS, SPR_NOACCESS,
1799
                 &spr_read_generic, &spr_write_generic,
1800
                 0x00000000);
1801
    /* XXX : not implemented */
1802
    spr_register(env, SPR_405_SU0R, "SU0R",
1803
                 SPR_NOACCESS, SPR_NOACCESS,
1804
                 &spr_read_generic, &spr_write_generic,
1805
                 0x00000000);
1806
    /* SPRG */
1807
    spr_register(env, SPR_USPRG0, "USPRG0",
1808
                 &spr_read_ureg, SPR_NOACCESS,
1809
                 &spr_read_ureg, SPR_NOACCESS,
1810
                 0x00000000);
1811
    spr_register(env, SPR_SPRG4, "SPRG4",
1812
                 SPR_NOACCESS, SPR_NOACCESS,
1813
                 &spr_read_generic, &spr_write_generic,
1814
                 0x00000000);
1815
    spr_register(env, SPR_USPRG4, "USPRG4",
1816
                 &spr_read_ureg, SPR_NOACCESS,
1817
                 &spr_read_ureg, SPR_NOACCESS,
1818
                 0x00000000);
1819
    spr_register(env, SPR_SPRG5, "SPRG5",
1820
                 SPR_NOACCESS, SPR_NOACCESS,
1821
                 spr_read_generic, &spr_write_generic,
1822
                 0x00000000);
1823
    spr_register(env, SPR_USPRG5, "USPRG5",
1824
                 &spr_read_ureg, SPR_NOACCESS,
1825
                 &spr_read_ureg, SPR_NOACCESS,
1826
                 0x00000000);
1827
    spr_register(env, SPR_SPRG6, "SPRG6",
1828
                 SPR_NOACCESS, SPR_NOACCESS,
1829
                 spr_read_generic, &spr_write_generic,
1830
                 0x00000000);
1831
    spr_register(env, SPR_USPRG6, "USPRG6",
1832
                 &spr_read_ureg, SPR_NOACCESS,
1833
                 &spr_read_ureg, SPR_NOACCESS,
1834
                 0x00000000);
1835
    spr_register(env, SPR_SPRG7, "SPRG7",
1836
                 SPR_NOACCESS, SPR_NOACCESS,
1837
                 spr_read_generic, &spr_write_generic,
1838
                 0x00000000);
1839
    spr_register(env, SPR_USPRG7, "USPRG7",
1840
                 &spr_read_ureg, SPR_NOACCESS,
1841
                 &spr_read_ureg, SPR_NOACCESS,
1842
                 0x00000000);
1843
}
1844

    
1845
/* SPR shared between PowerPC 401 & 403 implementations */
1846
static void gen_spr_401_403 (CPUPPCState *env)
1847
{
1848
    /* Time base */
1849
    spr_register(env, SPR_403_VTBL,  "TBL",
1850
                 &spr_read_tbl, SPR_NOACCESS,
1851
                 &spr_read_tbl, SPR_NOACCESS,
1852
                 0x00000000);
1853
    spr_register(env, SPR_403_TBL,   "TBL",
1854
                 SPR_NOACCESS, SPR_NOACCESS,
1855
                 SPR_NOACCESS, &spr_write_tbl,
1856
                 0x00000000);
1857
    spr_register(env, SPR_403_VTBU,  "TBU",
1858
                 &spr_read_tbu, SPR_NOACCESS,
1859
                 &spr_read_tbu, SPR_NOACCESS,
1860
                 0x00000000);
1861
    spr_register(env, SPR_403_TBU,   "TBU",
1862
                 SPR_NOACCESS, SPR_NOACCESS,
1863
                 SPR_NOACCESS, &spr_write_tbu,
1864
                 0x00000000);
1865
    /* Debug */
1866
    /* XXX: not implemented */
1867
    spr_register(env, SPR_403_CDBCR, "CDBCR",
1868
                 SPR_NOACCESS, SPR_NOACCESS,
1869
                 &spr_read_generic, &spr_write_generic,
1870
                 0x00000000);
1871
}
1872

    
1873
/* SPR specific to PowerPC 401 implementation */
1874
static void gen_spr_401 (CPUPPCState *env)
1875
{
1876
    /* Debug interface */
1877
    /* XXX : not implemented */
1878
    spr_register(env, SPR_40x_DBCR0, "DBCR",
1879
                 SPR_NOACCESS, SPR_NOACCESS,
1880
                 &spr_read_generic, &spr_write_40x_dbcr0,
1881
                 0x00000000);
1882
    /* XXX : not implemented */
1883
    spr_register(env, SPR_40x_DBSR, "DBSR",
1884
                 SPR_NOACCESS, SPR_NOACCESS,
1885
                 &spr_read_generic, &spr_write_clear,
1886
                 /* Last reset was system reset */
1887
                 0x00000300);
1888
    /* XXX : not implemented */
1889
    spr_register(env, SPR_40x_DAC1, "DAC",
1890
                 SPR_NOACCESS, SPR_NOACCESS,
1891
                 &spr_read_generic, &spr_write_generic,
1892
                 0x00000000);
1893
    /* XXX : not implemented */
1894
    spr_register(env, SPR_40x_IAC1, "IAC",
1895
                 SPR_NOACCESS, SPR_NOACCESS,
1896
                 &spr_read_generic, &spr_write_generic,
1897
                 0x00000000);
1898
    /* Storage control */
1899
    spr_register(env, SPR_405_SLER, "SLER",
1900
                 SPR_NOACCESS, SPR_NOACCESS,
1901
                 &spr_read_generic, &spr_write_40x_sler,
1902
                 0x00000000);
1903
}
1904

    
1905
static void gen_spr_401x2 (CPUPPCState *env)
1906
{
1907
    gen_spr_401(env);
1908
    spr_register(env, SPR_40x_PID, "PID",
1909
                 SPR_NOACCESS, SPR_NOACCESS,
1910
                 &spr_read_generic, &spr_write_generic,
1911
                 0x00000000);
1912
    spr_register(env, SPR_40x_ZPR, "ZPR",
1913
                 SPR_NOACCESS, SPR_NOACCESS,
1914
                 &spr_read_generic, &spr_write_generic,
1915
                 0x00000000);
1916
}
1917

    
1918
/* SPR specific to PowerPC 403 implementation */
1919
static void gen_spr_403 (CPUPPCState *env)
1920
{
1921
    /* Debug interface */
1922
    /* XXX : not implemented */
1923
    spr_register(env, SPR_40x_DBCR0, "DBCR0",
1924
                 SPR_NOACCESS, SPR_NOACCESS,
1925
                 &spr_read_generic, &spr_write_40x_dbcr0,
1926
                 0x00000000);
1927
    /* XXX : not implemented */
1928
    spr_register(env, SPR_40x_DBSR, "DBSR",
1929
                 SPR_NOACCESS, SPR_NOACCESS,
1930
                 &spr_read_generic, &spr_write_clear,
1931
                 /* Last reset was system reset */
1932
                 0x00000300);
1933
    /* XXX : not implemented */
1934
    spr_register(env, SPR_40x_DAC1, "DAC1",
1935
                 SPR_NOACCESS, SPR_NOACCESS,
1936
                 &spr_read_generic, &spr_write_generic,
1937
                 0x00000000);
1938
    spr_register(env, SPR_40x_DAC2, "DAC2",
1939
                 SPR_NOACCESS, SPR_NOACCESS,
1940
                 &spr_read_generic, &spr_write_generic,
1941
                 0x00000000);
1942
    /* XXX : not implemented */
1943
    spr_register(env, SPR_40x_IAC1, "IAC1",
1944
                 SPR_NOACCESS, SPR_NOACCESS,
1945
                 &spr_read_generic, &spr_write_generic,
1946
                 0x00000000);
1947
    spr_register(env, SPR_40x_IAC2, "IAC2",
1948
                 SPR_NOACCESS, SPR_NOACCESS,
1949
                 &spr_read_generic, &spr_write_generic,
1950
                 0x00000000);
1951
}
1952

    
1953
static void gen_spr_403_real (CPUPPCState *env)
1954
{
1955
    spr_register(env, SPR_403_PBL1,  "PBL1",
1956
                 SPR_NOACCESS, SPR_NOACCESS,
1957
                 &spr_read_403_pbr, &spr_write_403_pbr,
1958
                 0x00000000);
1959
    spr_register(env, SPR_403_PBU1,  "PBU1",
1960
                 SPR_NOACCESS, SPR_NOACCESS,
1961
                 &spr_read_403_pbr, &spr_write_403_pbr,
1962
                 0x00000000);
1963
    spr_register(env, SPR_403_PBL2,  "PBL2",
1964
                 SPR_NOACCESS, SPR_NOACCESS,
1965
                 &spr_read_403_pbr, &spr_write_403_pbr,
1966
                 0x00000000);
1967
    spr_register(env, SPR_403_PBU2,  "PBU2",
1968
                 SPR_NOACCESS, SPR_NOACCESS,
1969
                 &spr_read_403_pbr, &spr_write_403_pbr,
1970
                 0x00000000);
1971
}
1972

    
1973
static void gen_spr_403_mmu (CPUPPCState *env)
1974
{
1975
    /* MMU */
1976
    spr_register(env, SPR_40x_PID, "PID",
1977
                 SPR_NOACCESS, SPR_NOACCESS,
1978
                 &spr_read_generic, &spr_write_generic,
1979
                 0x00000000);
1980
    spr_register(env, SPR_40x_ZPR, "ZPR",
1981
                 SPR_NOACCESS, SPR_NOACCESS,
1982
                 &spr_read_generic, &spr_write_generic,
1983
                 0x00000000);
1984
}
1985

    
1986
/* SPR specific to PowerPC compression coprocessor extension */
1987
static void gen_spr_compress (CPUPPCState *env)
1988
{
1989
    spr_register(env, SPR_401_SKR, "SKR",
1990
                 SPR_NOACCESS, SPR_NOACCESS,
1991
                 &spr_read_generic, &spr_write_generic,
1992
                 0x00000000);
1993
}
1994

    
1995
#if defined (TARGET_PPC64)
1996
#if defined (TODO)
1997
/* SPR specific to PowerPC 620 */
1998
static void gen_spr_620 (CPUPPCState *env)
1999
{
2000
    spr_register(env, SPR_620_PMR0, "PMR0",
2001
                 SPR_NOACCESS, SPR_NOACCESS,
2002
                 &spr_read_generic, &spr_write_generic,
2003
                 0x00000000);
2004
    spr_register(env, SPR_620_PMR1, "PMR1",
2005
                 SPR_NOACCESS, SPR_NOACCESS,
2006
                 &spr_read_generic, &spr_write_generic,
2007
                 0x00000000);
2008
    spr_register(env, SPR_620_PMR2, "PMR2",
2009
                 SPR_NOACCESS, SPR_NOACCESS,
2010
                 &spr_read_generic, &spr_write_generic,
2011
                 0x00000000);
2012
    spr_register(env, SPR_620_PMR3, "PMR3",
2013
                 SPR_NOACCESS, SPR_NOACCESS,
2014
                 &spr_read_generic, &spr_write_generic,
2015
                 0x00000000);
2016
    spr_register(env, SPR_620_PMR4, "PMR4",
2017
                 SPR_NOACCESS, SPR_NOACCESS,
2018
                 &spr_read_generic, &spr_write_generic,
2019
                 0x00000000);
2020
    spr_register(env, SPR_620_PMR5, "PMR5",
2021
                 SPR_NOACCESS, SPR_NOACCESS,
2022
                 &spr_read_generic, &spr_write_generic,
2023
                 0x00000000);
2024
    spr_register(env, SPR_620_PMR6, "PMR6",
2025
                 SPR_NOACCESS, SPR_NOACCESS,
2026
                 &spr_read_generic, &spr_write_generic,
2027
                 0x00000000);
2028
    spr_register(env, SPR_620_PMR7, "PMR7",
2029
                 SPR_NOACCESS, SPR_NOACCESS,
2030
                 &spr_read_generic, &spr_write_generic,
2031
                 0x00000000);
2032
    spr_register(env, SPR_620_PMR8, "PMR8",
2033
                 SPR_NOACCESS, SPR_NOACCESS,
2034
                 &spr_read_generic, &spr_write_generic,
2035
                 0x00000000);
2036
    spr_register(env, SPR_620_PMR9, "PMR9",
2037
                 SPR_NOACCESS, SPR_NOACCESS,
2038
                 &spr_read_generic, &spr_write_generic,
2039
                 0x00000000);
2040
    spr_register(env, SPR_620_PMRA, "PMR10",
2041
                 SPR_NOACCESS, SPR_NOACCESS,
2042
                 &spr_read_generic, &spr_write_generic,
2043
                 0x00000000);
2044
    spr_register(env, SPR_620_PMRB, "PMR11",
2045
                 SPR_NOACCESS, SPR_NOACCESS,
2046
                 &spr_read_generic, &spr_write_generic,
2047
                 0x00000000);
2048
    spr_register(env, SPR_620_PMRC, "PMR12",
2049
                 SPR_NOACCESS, SPR_NOACCESS,
2050
                 &spr_read_generic, &spr_write_generic,
2051
                 0x00000000);
2052
    spr_register(env, SPR_620_PMRD, "PMR13",
2053
                 SPR_NOACCESS, SPR_NOACCESS,
2054
                 &spr_read_generic, &spr_write_generic,
2055
                 0x00000000);
2056
    spr_register(env, SPR_620_PMRE, "PMR14",
2057
                 SPR_NOACCESS, SPR_NOACCESS,
2058
                 &spr_read_generic, &spr_write_generic,
2059
                 0x00000000);
2060
    spr_register(env, SPR_620_PMRF, "PMR15",
2061
                 SPR_NOACCESS, SPR_NOACCESS,
2062
                 &spr_read_generic, &spr_write_generic,
2063
                 0x00000000);
2064
    spr_register(env, SPR_620_HID8, "HID8",
2065
                 SPR_NOACCESS, SPR_NOACCESS,
2066
                 &spr_read_generic, &spr_write_generic,
2067
                 0x00000000);
2068
    spr_register(env, SPR_620_HID9, "HID9",
2069
                 SPR_NOACCESS, SPR_NOACCESS,
2070
                 &spr_read_generic, &spr_write_generic,
2071
                 0x00000000);
2072
}
2073
#endif
2074
#endif /* defined (TARGET_PPC64) */
2075

    
2076
// XXX: TODO
2077
/*
2078
 * AMR     => SPR 29 (Power 2.04)
2079
 * CTRL    => SPR 136 (Power 2.04)
2080
 * CTRL    => SPR 152 (Power 2.04)
2081
 * SCOMC   => SPR 276 (64 bits ?)
2082
 * SCOMD   => SPR 277 (64 bits ?)
2083
 * ASR     => SPR 280 (64 bits)
2084
 * TBU40   => SPR 286 (Power 2.04 hypv)
2085
 * HSPRG0  => SPR 304 (Power 2.04 hypv)
2086
 * HSPRG1  => SPR 305 (Power 2.04 hypv)
2087
 * HDSISR  => SPR 306 (Power 2.04 hypv)
2088
 * HDAR    => SPR 307 (Power 2.04 hypv)
2089
 * PURR    => SPR 309 (Power 2.04 hypv)
2090
 * HDEC    => SPR 310 (Power 2.04 hypv)
2091
 * HIOR    => SPR 311 (hypv)
2092
 * RMOR    => SPR 312 (970)
2093
 * HRMOR   => SPR 313 (Power 2.04 hypv)
2094
 * HSRR0   => SPR 314 (Power 2.04 hypv)
2095
 * HSRR1   => SPR 315 (Power 2.04 hypv)
2096
 * LPCR    => SPR 316 (970)
2097
 * LPIDR   => SPR 317 (970)
2098
 * SPEFSCR => SPR 512 (Power 2.04 emb)
2099
 * ATBL    => SPR 526 (Power 2.04 emb)
2100
 * ATBU    => SPR 527 (Power 2.04 emb)
2101
 * EPR     => SPR 702 (Power 2.04 emb)
2102
 * perf    => 768-783 (Power 2.04)
2103
 * perf    => 784-799 (Power 2.04)
2104
 * PPR     => SPR 896 (Power 2.04)
2105
 * EPLC    => SPR 947 (Power 2.04 emb)
2106
 * EPSC    => SPR 948 (Power 2.04 emb)
2107
 * DABRX   => 1015    (Power 2.04 hypv)
2108
 * FPECR   => SPR 1022 (?)
2109
 * ... and more (thermal management, performance counters, ...)
2110
 */
2111

    
2112
/*****************************************************************************/
2113
/* Exception vectors models                                                  */
2114
static void init_excp_4xx_real (CPUPPCState *env)
2115
{
2116
#if !defined(CONFIG_USER_ONLY)
2117
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2118
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2119
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2120
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2121
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2122
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2123
    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2124
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2125
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2126
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2127
#endif
2128
}
2129

    
2130
static void init_excp_4xx_softmmu (CPUPPCState *env)
2131
{
2132
#if !defined(CONFIG_USER_ONLY)
2133
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2134
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2135
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2136
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2137
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2138
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2139
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2140
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2141
    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2142
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2143
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2144
    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2145
    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2146
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2147
#endif
2148
}
2149

    
2150
static void init_excp_BookE (CPUPPCState *env)
2151
{
2152
#if !defined(CONFIG_USER_ONLY)
2153
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2154
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2155
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2156
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2157
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2158
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2159
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2160
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2161
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2162
    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2163
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2164
    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2165
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2166
    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2167
    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2168
    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2169
    env->excp_prefix = 0x00000000;
2170
    env->ivor_mask = 0x0000FFE0;
2171
    env->ivpr_mask = 0xFFFF0000;
2172
#endif
2173
}
2174

    
2175
static void init_excp_601 (CPUPPCState *env)
2176
{
2177
#if !defined(CONFIG_USER_ONLY)
2178
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2179
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2180
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2181
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2182
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2183
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2184
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2185
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2186
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2187
    env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
2188
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2189
    env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
2190
    env->excp_prefix = 0xFFF00000;
2191
#endif
2192
}
2193

    
2194
static void init_excp_602 (CPUPPCState *env)
2195
{
2196
#if !defined(CONFIG_USER_ONLY)
2197
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2198
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2199
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2200
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2201
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2202
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2203
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2204
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2205
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2206
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2207
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2208
    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2209
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2210
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2211
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2212
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2213
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2214
    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
2215
    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
2216
    env->excp_prefix = 0xFFF00000;
2217
#endif
2218
}
2219

    
2220
static void init_excp_603 (CPUPPCState *env)
2221
{
2222
#if !defined(CONFIG_USER_ONLY)
2223
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2224
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2225
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2226
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2227
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2228
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2229
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2230
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2231
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2232
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2233
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2234
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2235
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2236
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2237
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2238
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2239
#endif
2240
}
2241

    
2242
static void init_excp_G2 (CPUPPCState *env)
2243
{
2244
#if !defined(CONFIG_USER_ONLY)
2245
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2246
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2247
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2248
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2249
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2250
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2251
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2252
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2253
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2254
    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2255
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2256
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2257
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2258
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2259
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2260
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2261
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2262
#endif
2263
}
2264

    
2265
static void init_excp_604 (CPUPPCState *env)
2266
{
2267
#if !defined(CONFIG_USER_ONLY)
2268
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2269
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2270
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2271
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2272
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2273
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2274
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2275
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2276
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2277
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2278
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2279
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2280
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2281
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2282
#endif
2283
}
2284

    
2285
#if defined (TODO)
2286
static void init_excp_620 (CPUPPCState *env)
2287
{
2288
#if !defined(CONFIG_USER_ONLY)
2289
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2290
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2291
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2292
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2293
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2294
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2295
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2296
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2297
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2298
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2299
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2300
    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2301
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2302
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2303
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2304
#endif
2305
}
2306
#endif /* defined (TODO) */
2307

    
2308
static void init_excp_7x0 (CPUPPCState *env)
2309
{
2310
#if !defined(CONFIG_USER_ONLY)
2311
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2312
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2313
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2314
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2315
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2316
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2317
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2318
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2319
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2320
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2321
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2322
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2323
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2324
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2325
#endif
2326
}
2327

    
2328
static void init_excp_750FX (CPUPPCState *env)
2329
{
2330
#if !defined(CONFIG_USER_ONLY)
2331
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2332
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2333
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2334
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2335
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2336
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2337
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2338
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2339
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2340
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2341
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2342
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2343
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2344
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2345
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2346
#endif
2347
}
2348

    
2349
static void init_excp_7400 (CPUPPCState *env)
2350
{
2351
#if !defined(CONFIG_USER_ONLY)
2352
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2353
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2354
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2355
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2356
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2357
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2358
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2359
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2360
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2361
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2362
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2363
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2364
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2365
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2366
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2367
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
2368
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
2369
#endif
2370
}
2371

    
2372
#if defined (TODO)
2373
static void init_excp_7450 (CPUPPCState *env)
2374
{
2375
#if !defined(CONFIG_USER_ONLY)
2376
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2377
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2378
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2379
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2380
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2381
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2382
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2383
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2384
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2385
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2386
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2387
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2388
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2389
    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2390
    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2391
    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2392
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2393
    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2394
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
2395
#endif
2396
}
2397
#endif /* defined (TODO) */
2398

    
2399
#if defined (TARGET_PPC64)
2400
static void init_excp_970 (CPUPPCState *env)
2401
{
2402
#if !defined(CONFIG_USER_ONLY)
2403
    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2404
    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2405
    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2406
    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
2407
    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2408
    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
2409
    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2410
    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2411
    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2412
    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2413
    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2414
#if defined(TARGET_PPC64H) /* PowerPC 64 with hypervisor mode support */
2415
    env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
2416
#endif
2417
    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2418
    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2419
    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2420
    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
2421
    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2422
    env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
2423
    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
2424
    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
2425
#endif
2426
}
2427
#endif
2428

    
2429
/*****************************************************************************/
2430
/* PowerPC implementations definitions                                       */
2431

    
2432
/* PowerPC 40x instruction set                                               */
2433
#define POWERPC_INSNS_EMB    (PPC_INSNS_BASE | PPC_EMB_COMMON)
2434

    
2435
/* PowerPC 401                                                               */
2436
#define POWERPC_INSNS_401    (POWERPC_INSNS_EMB |                             \
2437
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2438
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2439
#define POWERPC_MSRM_401     (0x00000000000FD201ULL)
2440
#define POWERPC_MMU_401      (POWERPC_MMU_REAL_4xx)
2441
#define POWERPC_EXCP_401     (POWERPC_EXCP_40x)
2442
#define POWERPC_INPUT_401    (PPC_FLAGS_INPUT_401)
2443
#define POWERPC_BFDM_401     (bfd_mach_ppc_403)
2444

    
2445
static void init_proc_401 (CPUPPCState *env)
2446
{
2447
    gen_spr_40x(env);
2448
    gen_spr_401_403(env);
2449
    gen_spr_401(env);
2450
    /* Bus access control */
2451
    spr_register(env, SPR_40x_SGR, "SGR",
2452
                 SPR_NOACCESS, SPR_NOACCESS,
2453
                 &spr_read_generic, &spr_write_generic,
2454
                 0xFFFFFFFF);
2455
    /* XXX : not implemented */
2456
    spr_register(env, SPR_40x_DCWR, "DCWR",
2457
                 SPR_NOACCESS, SPR_NOACCESS,
2458
                 &spr_read_generic, &spr_write_generic,
2459
                 0x00000000);
2460
    init_excp_4xx_real(env);
2461
    /* XXX: TODO: allocate internal IRQ controller */
2462
}
2463

    
2464
/* PowerPC 401x2                                                             */
2465
#define POWERPC_INSNS_401x2  (POWERPC_INSNS_EMB |                             \
2466
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2467
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2468
                              PPC_CACHE_DCBA | PPC_MFTB |                     \
2469
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2470
#define POWERPC_MSRM_401x2   (0x00000000001FD231ULL)
2471
#define POWERPC_MMU_401x2    (POWERPC_MMU_SOFT_4xx_Z)
2472
#define POWERPC_EXCP_401x2   (POWERPC_EXCP_40x)
2473
#define POWERPC_INPUT_401x2  (PPC_FLAGS_INPUT_401)
2474
#define POWERPC_BFDM_401x2   (bfd_mach_ppc_403)
2475

    
2476
static void init_proc_401x2 (CPUPPCState *env)
2477
{
2478
    gen_spr_40x(env);
2479
    gen_spr_401_403(env);
2480
    gen_spr_401x2(env);
2481
    gen_spr_compress(env);
2482
    /* Bus access control */
2483
    spr_register(env, SPR_40x_SGR, "SGR",
2484
                 SPR_NOACCESS, SPR_NOACCESS,
2485
                 &spr_read_generic, &spr_write_generic,
2486
                 0xFFFFFFFF);
2487
    /* XXX : not implemented */
2488
    spr_register(env, SPR_40x_DCWR, "DCWR",
2489
                 SPR_NOACCESS, SPR_NOACCESS,
2490
                 &spr_read_generic, &spr_write_generic,
2491
                 0x00000000);
2492
    /* Memory management */
2493
    env->nb_tlb = 64;
2494
    env->nb_ways = 1;
2495
    env->id_tlbs = 0;
2496
    init_excp_4xx_softmmu(env);
2497
    /* XXX: TODO: allocate internal IRQ controller */
2498
}
2499

    
2500
/* PowerPC 401x3                                                             */
2501
#if defined(TODO)
2502
#define POWERPC_INSNS_401x3  (POWERPC_INSNS_EMB |                             \
2503
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2504
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2505
                              PPC_CACHE_DCBA | PPC_MFTB |                     \
2506
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2507
#define POWERPC_MSRM_401x3   (0x00000000001FD631ULL)
2508
#define POWERPC_MMU_401x3    (POWERPC_MMU_SOFT_4xx_Z)
2509
#define POWERPC_EXCP_401x3   (POWERPC_EXCP_40x)
2510
#define POWERPC_INPUT_401x3  (PPC_FLAGS_INPUT_401)
2511
#define POWERPC_BFDM_401x3   (bfd_mach_ppc_403)
2512

    
2513
static void init_proc_401x3 (CPUPPCState *env)
2514
{
2515
    init_excp_4xx_softmmu(env);
2516
}
2517
#endif /* TODO */
2518

    
2519
/* IOP480                                                                    */
2520
#define POWERPC_INSNS_IOP480 (POWERPC_INSNS_EMB |                             \
2521
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2522
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2523
                              PPC_CACHE_DCBA |                                \
2524
                              PPC_4xx_COMMON | PPC_40x_EXCP |  PPC_40x_ICBT)
2525
#define POWERPC_MSRM_IOP480  (0x00000000001FD231ULL)
2526
#define POWERPC_MMU_IOP480   (POWERPC_MMU_SOFT_4xx_Z)
2527
#define POWERPC_EXCP_IOP480  (POWERPC_EXCP_40x)
2528
#define POWERPC_INPUT_IOP480 (PPC_FLAGS_INPUT_401)
2529
#define POWERPC_BFDM_IOP480  (bfd_mach_ppc_403)
2530

    
2531
static void init_proc_IOP480 (CPUPPCState *env)
2532
{
2533
    gen_spr_40x(env);
2534
    gen_spr_401_403(env);
2535
    gen_spr_401x2(env);
2536
    gen_spr_compress(env);
2537
    /* Bus access control */
2538
    spr_register(env, SPR_40x_SGR, "SGR",
2539
                 SPR_NOACCESS, SPR_NOACCESS,
2540
                 &spr_read_generic, &spr_write_generic,
2541
                 0xFFFFFFFF);
2542
    /* XXX : not implemented */
2543
    spr_register(env, SPR_40x_DCWR, "DCWR",
2544
                 SPR_NOACCESS, SPR_NOACCESS,
2545
                 &spr_read_generic, &spr_write_generic,
2546
                 0x00000000);
2547
    /* Memory management */
2548
    env->nb_tlb = 64;
2549
    env->nb_ways = 1;
2550
    env->id_tlbs = 0;
2551
    init_excp_4xx_softmmu(env);
2552
    /* XXX: TODO: allocate internal IRQ controller */
2553
}
2554

    
2555
/* PowerPC 403                                                               */
2556
#define POWERPC_INSNS_403    (POWERPC_INSNS_EMB |                             \
2557
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2558
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2559
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2560
#define POWERPC_MSRM_403     (0x000000000007D00DULL)
2561
#define POWERPC_MMU_403      (POWERPC_MMU_REAL_4xx)
2562
#define POWERPC_EXCP_403     (POWERPC_EXCP_40x)
2563
#define POWERPC_INPUT_403    (PPC_FLAGS_INPUT_401)
2564
#define POWERPC_BFDM_403     (bfd_mach_ppc_403)
2565

    
2566
static void init_proc_403 (CPUPPCState *env)
2567
{
2568
    gen_spr_40x(env);
2569
    gen_spr_401_403(env);
2570
    gen_spr_403(env);
2571
    gen_spr_403_real(env);
2572
    init_excp_4xx_real(env);
2573
    /* XXX: TODO: allocate internal IRQ controller */
2574
}
2575

    
2576
/* PowerPC 403 GCX                                                           */
2577
#define POWERPC_INSNS_403GCX (POWERPC_INSNS_EMB |                             \
2578
                              PPC_MEM_SYNC | PPC_MEM_EIEIO |                  \
2579
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2580
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT)
2581
#define POWERPC_MSRM_403GCX  (0x000000000007D00DULL)
2582
#define POWERPC_MMU_403GCX   (POWERPC_MMU_SOFT_4xx_Z)
2583
#define POWERPC_EXCP_403GCX  (POWERPC_EXCP_40x)
2584
#define POWERPC_INPUT_403GCX (PPC_FLAGS_INPUT_401)
2585
#define POWERPC_BFDM_403GCX  (bfd_mach_ppc_403)
2586

    
2587
static void init_proc_403GCX (CPUPPCState *env)
2588
{
2589
    gen_spr_40x(env);
2590
    gen_spr_401_403(env);
2591
    gen_spr_403(env);
2592
    gen_spr_403_real(env);
2593
    gen_spr_403_mmu(env);
2594
    /* Bus access control */
2595
    spr_register(env, SPR_40x_SGR, "SGR",
2596
                 SPR_NOACCESS, SPR_NOACCESS,
2597
                 &spr_read_generic, &spr_write_generic,
2598
                 0xFFFFFFFF);
2599
    /* XXX : not implemented */
2600
    spr_register(env, SPR_40x_DCWR, "DCWR",
2601
                 SPR_NOACCESS, SPR_NOACCESS,
2602
                 &spr_read_generic, &spr_write_generic,
2603
                 0x00000000);
2604
    /* Memory management */
2605
    env->nb_tlb = 64;
2606
    env->nb_ways = 1;
2607
    env->id_tlbs = 0;
2608
    init_excp_4xx_softmmu(env);
2609
    /* XXX: TODO: allocate internal IRQ controller */
2610
}
2611

    
2612
/* PowerPC 405                                                               */
2613
#define POWERPC_INSNS_405    (POWERPC_INSNS_EMB | PPC_MFTB |                  \
2614
                              PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_CACHE_DCBA | \
2615
                              PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | \
2616
                              PPC_4xx_COMMON | PPC_40x_EXCP | PPC_40x_ICBT |  \
2617
                              PPC_405_MAC)
2618
#define POWERPC_MSRM_405     (0x000000000006E630ULL)
2619
#define POWERPC_MMU_405      (POWERPC_MMU_SOFT_4xx)
2620
#define POWERPC_EXCP_405     (POWERPC_EXCP_40x)
2621
#define POWERPC_INPUT_405    (PPC_FLAGS_INPUT_405)
2622
#define POWERPC_BFDM_405     (bfd_mach_ppc_403)
2623

    
2624
static void init_proc_405 (CPUPPCState *env)
2625
{
2626
    /* Time base */
2627
    gen_tbl(env);
2628
    gen_spr_40x(env);
2629
    gen_spr_405(env);
2630
    /* Bus access control */
2631
    spr_register(env, SPR_40x_SGR, "SGR",
2632
                 SPR_NOACCESS, SPR_NOACCESS,
2633
                 &spr_read_generic, &spr_write_generic,
2634
                 0xFFFFFFFF);
2635
    /* XXX : not implemented */
2636
    spr_register(env, SPR_40x_DCWR, "DCWR",
2637
                 SPR_NOACCESS, SPR_NOACCESS,
2638
                 &spr_read_generic, &spr_write_generic,
2639
                 0x00000000);
2640
    /* Memory management */
2641
    env->nb_tlb = 64;
2642
    env->nb_ways = 1;
2643
    env->id_tlbs = 0;
2644
    init_excp_4xx_softmmu(env);
2645
    /* Allocate hardware IRQ controller */
2646
    ppc405_irq_init(env);
2647
}
2648

    
2649
/* PowerPC 440 EP                                                            */
2650
#define POWERPC_INSNS_440EP  (POWERPC_INSNS_EMB |                             \
2651
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2652
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
2653
                              PPC_440_SPEC | PPC_RFMCI)
2654
#define POWERPC_MSRM_440EP   (0x000000000006D630ULL)
2655
#define POWERPC_MMU_440EP    (POWERPC_MMU_BOOKE)
2656
#define POWERPC_EXCP_440EP   (POWERPC_EXCP_BOOKE)
2657
#define POWERPC_INPUT_440EP  (PPC_FLAGS_INPUT_BookE)
2658
#define POWERPC_BFDM_440EP   (bfd_mach_ppc_403)
2659

    
2660
static void init_proc_440EP (CPUPPCState *env)
2661
{
2662
    /* Time base */
2663
    gen_tbl(env);
2664
    gen_spr_BookE(env);
2665
    gen_spr_440(env);
2666
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2667
                 SPR_NOACCESS, SPR_NOACCESS,
2668
                 &spr_read_generic, &spr_write_generic,
2669
                 0x00000000);
2670
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2671
                 SPR_NOACCESS, SPR_NOACCESS,
2672
                 &spr_read_generic, &spr_write_generic,
2673
                 0x00000000);
2674
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2675
                 SPR_NOACCESS, SPR_NOACCESS,
2676
                 &spr_read_generic, &spr_write_generic,
2677
                 0x00000000);
2678
    spr_register(env, SPR_440_CCR1, "CCR1",
2679
                 SPR_NOACCESS, SPR_NOACCESS,
2680
                 &spr_read_generic, &spr_write_generic,
2681
                 0x00000000);
2682
    /* Memory management */
2683
    env->nb_tlb = 64;
2684
    env->nb_ways = 1;
2685
    env->id_tlbs = 0;
2686
    init_excp_BookE(env);
2687
    /* XXX: TODO: allocate internal IRQ controller */
2688
}
2689

    
2690
/* PowerPC 440 GP                                                            */
2691
#define POWERPC_INSNS_440GP  (POWERPC_INSNS_EMB |                             \
2692
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2693
                              PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON |    \
2694
                              PPC_405_MAC | PPC_440_SPEC)
2695
#define POWERPC_MSRM_440GP   (0x000000000006FF30ULL)
2696
#define POWERPC_MMU_440GP    (POWERPC_MMU_BOOKE)
2697
#define POWERPC_EXCP_440GP   (POWERPC_EXCP_BOOKE)
2698
#define POWERPC_INPUT_440GP  (PPC_FLAGS_INPUT_BookE)
2699
#define POWERPC_BFDM_440GP   (bfd_mach_ppc_403)
2700

    
2701
static void init_proc_440GP (CPUPPCState *env)
2702
{
2703
    /* Time base */
2704
    gen_tbl(env);
2705
    gen_spr_BookE(env);
2706
    gen_spr_440(env);
2707
    /* Memory management */
2708
    env->nb_tlb = 64;
2709
    env->nb_ways = 1;
2710
    env->id_tlbs = 0;
2711
    init_excp_BookE(env);
2712
    /* XXX: TODO: allocate internal IRQ controller */
2713
}
2714

    
2715
/* PowerPC 440x4                                                             */
2716
#if defined(TODO)
2717
#define POWERPC_INSNS_440x4  (POWERPC_INSNS_EMB |                             \
2718
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2719
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
2720
                              PPC_440_SPEC)
2721
#define POWERPC_MSRM_440x4   (0x000000000006FF30ULL)
2722
#define POWERPC_MMU_440x4    (POWERPC_MMU_BOOKE)
2723
#define POWERPC_EXCP_440x4   (POWERPC_EXCP_BOOKE)
2724
#define POWERPC_INPUT_440x4  (PPC_FLAGS_INPUT_BookE)
2725
#define POWERPC_BFDM_440x4   (bfd_mach_ppc_403)
2726

    
2727
static void init_proc_440x4 (CPUPPCState *env)
2728
{
2729
    /* Time base */
2730
    gen_tbl(env);
2731
    gen_spr_BookE(env);
2732
    gen_spr_440(env);
2733
    /* Memory management */
2734
    env->nb_tlb = 64;
2735
    env->nb_ways = 1;
2736
    env->id_tlbs = 0;
2737
    init_excp_BookE(env);
2738
    /* XXX: TODO: allocate internal IRQ controller */
2739
}
2740
#endif /* TODO */
2741

    
2742
/* PowerPC 440x5                                                             */
2743
#define POWERPC_INSNS_440x5  (POWERPC_INSNS_EMB |                             \
2744
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2745
                              PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |      \
2746
                              PPC_440_SPEC | PPC_RFMCI)
2747
#define POWERPC_MSRM_440x5   (0x000000000006FF30ULL)
2748
#define POWERPC_MMU_440x5    (POWERPC_MMU_BOOKE)
2749
#define POWERPC_EXCP_440x5   (POWERPC_EXCP_BOOKE)
2750
#define POWERPC_INPUT_440x5  (PPC_FLAGS_INPUT_BookE)
2751
#define POWERPC_BFDM_440x5   (bfd_mach_ppc_403)
2752

    
2753
static void init_proc_440x5 (CPUPPCState *env)
2754
{
2755
    /* Time base */
2756
    gen_tbl(env);
2757
    gen_spr_BookE(env);
2758
    gen_spr_440(env);
2759
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2760
                 SPR_NOACCESS, SPR_NOACCESS,
2761
                 &spr_read_generic, &spr_write_generic,
2762
                 0x00000000);
2763
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2764
                 SPR_NOACCESS, SPR_NOACCESS,
2765
                 &spr_read_generic, &spr_write_generic,
2766
                 0x00000000);
2767
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2768
                 SPR_NOACCESS, SPR_NOACCESS,
2769
                 &spr_read_generic, &spr_write_generic,
2770
                 0x00000000);
2771
    spr_register(env, SPR_440_CCR1, "CCR1",
2772
                 SPR_NOACCESS, SPR_NOACCESS,
2773
                 &spr_read_generic, &spr_write_generic,
2774
                 0x00000000);
2775
    /* Memory management */
2776
    env->nb_tlb = 64;
2777
    env->nb_ways = 1;
2778
    env->id_tlbs = 0;
2779
    init_excp_BookE(env);
2780
    /* XXX: TODO: allocate internal IRQ controller */
2781
}
2782

    
2783
/* PowerPC 460 (guessed)                                                     */
2784
#if defined(TODO)
2785
#define POWERPC_INSNS_460F   (POWERPC_INSNS_EMB |                             \
2786
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2787
                              PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON |    \
2788
                              PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
2789
#define POWERPC_MSRM_460     (0x000000000006FF30ULL)
2790
#define POWERPC_MMU_460      (POWERPC_MMU_BOOKE)
2791
#define POWERPC_EXCP_460     (POWERPC_EXCP_BOOKE)
2792
#define POWERPC_INPUT_460    (PPC_FLAGS_INPUT_BookE)
2793
#define POWERPC_BFDM_460     (bfd_mach_ppc_403)
2794

    
2795
static void init_proc_460 (CPUPPCState *env)
2796
{
2797
    /* Time base */
2798
    gen_tbl(env);
2799
    gen_spr_BookE(env);
2800
    gen_spr_440(env);
2801
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2802
                 SPR_NOACCESS, SPR_NOACCESS,
2803
                 &spr_read_generic, &spr_write_generic,
2804
                 0x00000000);
2805
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2806
                 SPR_NOACCESS, SPR_NOACCESS,
2807
                 &spr_read_generic, &spr_write_generic,
2808
                 0x00000000);
2809
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2810
                 SPR_NOACCESS, SPR_NOACCESS,
2811
                 &spr_read_generic, &spr_write_generic,
2812
                 0x00000000);
2813
    spr_register(env, SPR_440_CCR1, "CCR1",
2814
                 SPR_NOACCESS, SPR_NOACCESS,
2815
                 &spr_read_generic, &spr_write_generic,
2816
                 0x00000000);
2817
    spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
2818
                 &spr_read_generic, &spr_write_generic,
2819
                 &spr_read_generic, &spr_write_generic,
2820
                 0x00000000);
2821
    /* Memory management */
2822
    env->nb_tlb = 64;
2823
    env->nb_ways = 1;
2824
    env->id_tlbs = 0;
2825
    init_excp_BookE(env);
2826
    /* XXX: TODO: allocate internal IRQ controller */
2827
}
2828
#endif /* TODO */
2829

    
2830
/* PowerPC 460F (guessed)                                                    */
2831
#if defined(TODO)
2832
#define POWERPC_INSNS_460F   (POWERPC_INSNS_EMB |                             \
2833
                              PPC_CACHE_DCBA | PPC_MEM_TLBSYNC |              \
2834
                              PPC_FLOAT | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES |  \
2835
                              PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |            \
2836
                              PPC_FLOAT_STFIWX |                              \
2837
                              PPC_BOOKE | PPC_BOOKE_EXT | PPC_4xx_COMMON |    \
2838
                              PPC_405_MAC | PPC_440_SPEC | PPC_DCRUX)
2839
#define POWERPC_MSRM_460     (0x000000000006FF30ULL)
2840
#define POWERPC_MMU_460F     (POWERPC_MMU_BOOKE)
2841
#define POWERPC_EXCP_460F    (POWERPC_EXCP_BOOKE)
2842
#define POWERPC_INPUT_460F   (PPC_FLAGS_INPUT_BookE)
2843
#define POWERPC_BFDM_460F    (bfd_mach_ppc_403)
2844

    
2845
static void init_proc_460F (CPUPPCState *env)
2846
{
2847
    /* Time base */
2848
    gen_tbl(env);
2849
    gen_spr_BookE(env);
2850
    gen_spr_440(env);
2851
    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2852
                 SPR_NOACCESS, SPR_NOACCESS,
2853
                 &spr_read_generic, &spr_write_generic,
2854
                 0x00000000);
2855
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2856
                 SPR_NOACCESS, SPR_NOACCESS,
2857
                 &spr_read_generic, &spr_write_generic,
2858
                 0x00000000);
2859
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2860
                 SPR_NOACCESS, SPR_NOACCESS,
2861
                 &spr_read_generic, &spr_write_generic,
2862
                 0x00000000);
2863
    spr_register(env, SPR_440_CCR1, "CCR1",
2864
                 SPR_NOACCESS, SPR_NOACCESS,
2865
                 &spr_read_generic, &spr_write_generic,
2866
                 0x00000000);
2867
    spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
2868
                 &spr_read_generic, &spr_write_generic,
2869
                 &spr_read_generic, &spr_write_generic,
2870
                 0x00000000);
2871
    /* Memory management */
2872
    env->nb_tlb = 64;
2873
    env->nb_ways = 1;
2874
    env->id_tlbs = 0;
2875
    init_excp_BookE(env);
2876
    /* XXX: TODO: allocate internal IRQ controller */
2877
}
2878
#endif /* TODO */
2879

    
2880
/* Generic BookE PowerPC                                                     */
2881
#if defined(TODO)
2882
#define POWERPC_INSNS_BookE  (POWERPC_INSNS_EMB |                             \
2883
                              PPC_MEM_EIEIO | PPC_MEM_TLBSYNC |               \
2884
                              PPC_CACHE_DCBA |                                \
2885
                              PPC_FLOAT | PPC_FLOAT_FSQRT |                   \
2886
                              PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |            \
2887
                              PPC_FLOAT_FSEL | PPC_FLOAT_STFIW |              \
2888
                              PPC_BOOKE)
2889
#define POWERPC_MSRM_BookE   (0x000000000006D630ULL)
2890
#define POWERPC_MMU_BookE    (POWERPC_MMU_BOOKE)
2891
#define POWERPC_EXCP_BookE   (POWERPC_EXCP_BOOKE)
2892
#define POWERPC_INPUT_BookE  (PPC_FLAGS_INPUT_BookE)
2893
#define POWERPC_BFDM_BookE   (bfd_mach_ppc_403)
2894

    
2895
static void init_proc_BookE (CPUPPCState *env)
2896
{
2897
    init_excp_BookE(env);
2898
}
2899
#endif /* TODO */
2900

    
2901
/* e200 core                                                                 */
2902
#if defined(TODO)
2903
#endif /* TODO */
2904

    
2905
/* e300 core                                                                 */
2906
#if defined(TODO)
2907
#endif /* TODO */
2908

    
2909
/* e500 core                                                                 */
2910
#if defined(TODO)
2911
#define POWERPC_INSNS_e500   (POWERPC_INSNS_EMB |                             \
2912
                              PPC_MEM_EIEIO | PPC_MEM_TLBSYNC |               \
2913
                              PPC_CACHE_DCBA |                                \
2914
                              PPC_BOOKE | PPC_E500_VECTOR)
2915
#define POWERPC_MMU_e500     (POWERPC_MMU_SOFT_4xx)
2916
#define POWERPC_EXCP_e500    (POWERPC_EXCP_40x)
2917
#define POWERPC_INPUT_e500   (PPC_FLAGS_INPUT_BookE)
2918
#define POWERPC_BFDM_e500    (bfd_mach_ppc_403)
2919

    
2920
static void init_proc_e500 (CPUPPCState *env)
2921
{
2922
    /* Time base */
2923
    gen_tbl(env);
2924
    gen_spr_BookE(env);
2925
    /* Memory management */
2926
    gen_spr_BookE_FSL(env);
2927
    env->nb_tlb = 64;
2928
    env->nb_ways = 1;
2929
    env->id_tlbs = 0;
2930
    init_excp_BookE(env);
2931
    /* XXX: TODO: allocate internal IRQ controller */
2932
}
2933
#endif /* TODO */
2934

    
2935
/* e600 core                                                                 */
2936
#if defined(TODO)
2937
#endif /* TODO */
2938

    
2939
/* Non-embedded PowerPC                                                      */
2940
/* Base instructions set for all 6xx/7xx/74xx/970 PowerPC                    */
2941
#define POWERPC_INSNS_6xx    (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC |     \
2942
                              PPC_MEM_EIEIO | PPC_SEGMENT | PPC_MEM_TLBIE)
2943
/* Instructions common to all 6xx/7xx/74xx/970 PowerPC except 601 & 602      */
2944
#define POWERPC_INSNS_WORKS  (POWERPC_INSNS_6xx | PPC_FLOAT_FSQRT |           \
2945
                              PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |            \
2946
                              PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX |             \
2947
                              PPC_MEM_TLBSYNC | PPC_MFTB)
2948

    
2949
/* POWER : same as 601, without mfmsr, mfsr                                  */
2950
#if defined(TODO)
2951
#define POWERPC_INSNS_POWER  (XXX_TODO)
2952
/* POWER RSC (from RAD6000) */
2953
#define POWERPC_MSRM_POWER   (0x00000000FEF0ULL)
2954
#endif /* TODO */
2955

    
2956
/* PowerPC 601                                                               */
2957
#define POWERPC_INSNS_601    (POWERPC_INSNS_6xx | PPC_EXTERN | PPC_POWER_BR)
2958
#define POWERPC_MSRM_601     (0x000000000000FE70ULL)
2959
//#define POWERPC_MMU_601      (POWERPC_MMU_601)
2960
//#define POWERPC_EXCP_601     (POWERPC_EXCP_601)
2961
#define POWERPC_INPUT_601    (PPC_FLAGS_INPUT_6xx)
2962
#define POWERPC_BFDM_601     (bfd_mach_ppc_601)
2963

    
2964
static void init_proc_601 (CPUPPCState *env)
2965
{
2966
    gen_spr_ne_601(env);
2967
    gen_spr_601(env);
2968
    /* Hardware implementation registers */
2969
    /* XXX : not implemented */
2970
    spr_register(env, SPR_HID0, "HID0",
2971
                 SPR_NOACCESS, SPR_NOACCESS,
2972
                 &spr_read_generic, &spr_write_generic,
2973
                 0x00000000);
2974
    /* XXX : not implemented */
2975
    spr_register(env, SPR_HID1, "HID1",
2976
                 SPR_NOACCESS, SPR_NOACCESS,
2977
                 &spr_read_generic, &spr_write_generic,
2978
                 0x00000000);
2979
    /* XXX : not implemented */
2980
    spr_register(env, SPR_601_HID2, "HID2",
2981
                 SPR_NOACCESS, SPR_NOACCESS,
2982
                 &spr_read_generic, &spr_write_generic,
2983
                 0x00000000);
2984
    /* XXX : not implemented */
2985
    spr_register(env, SPR_601_HID5, "HID5",
2986
                 SPR_NOACCESS, SPR_NOACCESS,
2987
                 &spr_read_generic, &spr_write_generic,
2988
                 0x00000000);
2989
    /* XXX : not implemented */
2990
    spr_register(env, SPR_601_HID15, "HID15",
2991
                 SPR_NOACCESS, SPR_NOACCESS,
2992
                 &spr_read_generic, &spr_write_generic,
2993
                 0x00000000);
2994
    /* Memory management */
2995
    env->nb_tlb = 64;
2996
    env->nb_ways = 2;
2997
    env->id_tlbs = 0;
2998
    env->id_tlbs = 0;
2999
    init_excp_601(env);
3000
    /* XXX: TODO: allocate internal IRQ controller */
3001
}
3002

    
3003
/* PowerPC 602                                                               */
3004
#define POWERPC_INSNS_602    (POWERPC_INSNS_6xx | PPC_MFTB |                  \
3005
                              PPC_FLOAT_FRES | PPC_FLOAT_FRSQRTE |            \
3006
                              PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX |             \
3007
                              PPC_6xx_TLB | PPC_MEM_TLBSYNC | PPC_602_SPEC)
3008
#define POWERPC_MSRM_602     (0x000000000033FF73ULL)
3009
#define POWERPC_MMU_602      (POWERPC_MMU_SOFT_6xx)
3010
//#define POWERPC_EXCP_602     (POWERPC_EXCP_602)
3011
#define POWERPC_INPUT_602    (PPC_FLAGS_INPUT_6xx)
3012
#define POWERPC_BFDM_602     (bfd_mach_ppc_602)
3013

    
3014
static void init_proc_602 (CPUPPCState *env)
3015
{
3016
    gen_spr_ne_601(env);
3017
    gen_spr_602(env);
3018
    /* Time base */
3019
    gen_tbl(env);
3020
    /* hardware implementation registers */
3021
    /* XXX : not implemented */
3022
    spr_register(env, SPR_HID0, "HID0",
3023
                 SPR_NOACCESS, SPR_NOACCESS,
3024
                 &spr_read_generic, &spr_write_generic,
3025
                 0x00000000);
3026
    /* XXX : not implemented */
3027
    spr_register(env, SPR_HID1, "HID1",
3028
                 SPR_NOACCESS, SPR_NOACCESS,
3029
                 &spr_read_generic, &spr_write_generic,
3030
                 0x00000000);
3031
    /* Memory management */
3032
    gen_low_BATs(env);
3033
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3034
    init_excp_602(env);
3035
    /* Allocate hardware IRQ controller */
3036
    ppc6xx_irq_init(env);
3037
}
3038

    
3039
/* PowerPC 603                                                               */
3040
#define POWERPC_INSNS_603    (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3041
#define POWERPC_MSRM_603     (0x000000000001FF73ULL)
3042
#define POWERPC_MMU_603      (POWERPC_MMU_SOFT_6xx)
3043
//#define POWERPC_EXCP_603     (POWERPC_EXCP_603)
3044
#define POWERPC_INPUT_603    (PPC_FLAGS_INPUT_6xx)
3045
#define POWERPC_BFDM_603     (bfd_mach_ppc_603)
3046

    
3047
static void init_proc_603 (CPUPPCState *env)
3048
{
3049
    gen_spr_ne_601(env);
3050
    gen_spr_603(env);
3051
    /* Time base */
3052
    gen_tbl(env);
3053
    /* hardware implementation registers */
3054
    /* XXX : not implemented */
3055
    spr_register(env, SPR_HID0, "HID0",
3056
                 SPR_NOACCESS, SPR_NOACCESS,
3057
                 &spr_read_generic, &spr_write_generic,
3058
                 0x00000000);
3059
    /* XXX : not implemented */
3060
    spr_register(env, SPR_HID1, "HID1",
3061
                 SPR_NOACCESS, SPR_NOACCESS,
3062
                 &spr_read_generic, &spr_write_generic,
3063
                 0x00000000);
3064
    /* Memory management */
3065
    gen_low_BATs(env);
3066
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3067
    init_excp_603(env);
3068
    /* Allocate hardware IRQ controller */
3069
    ppc6xx_irq_init(env);
3070
}
3071

    
3072
/* PowerPC 603e                                                              */
3073
#define POWERPC_INSNS_603E   (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3074
#define POWERPC_MSRM_603E    (0x000000000007FF73ULL)
3075
#define POWERPC_MMU_603E     (POWERPC_MMU_SOFT_6xx)
3076
//#define POWERPC_EXCP_603E    (POWERPC_EXCP_603E)
3077
#define POWERPC_INPUT_603E   (PPC_FLAGS_INPUT_6xx)
3078
#define POWERPC_BFDM_603E    (bfd_mach_ppc_ec603e)
3079

    
3080
static void init_proc_603E (CPUPPCState *env)
3081
{
3082
    gen_spr_ne_601(env);
3083
    gen_spr_603(env);
3084
    /* Time base */
3085
    gen_tbl(env);
3086
    /* hardware implementation registers */
3087
    /* XXX : not implemented */
3088
    spr_register(env, SPR_HID0, "HID0",
3089
                 SPR_NOACCESS, SPR_NOACCESS,
3090
                 &spr_read_generic, &spr_write_generic,
3091
                 0x00000000);
3092
    /* XXX : not implemented */
3093
    spr_register(env, SPR_HID1, "HID1",
3094
                 SPR_NOACCESS, SPR_NOACCESS,
3095
                 &spr_read_generic, &spr_write_generic,
3096
                 0x00000000);
3097
    /* XXX : not implemented */
3098
    spr_register(env, SPR_IABR, "IABR",
3099
                 SPR_NOACCESS, SPR_NOACCESS,
3100
                 &spr_read_generic, &spr_write_generic,
3101
                 0x00000000);
3102
    /* Memory management */
3103
    gen_low_BATs(env);
3104
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3105
    init_excp_603(env);
3106
    /* Allocate hardware IRQ controller */
3107
    ppc6xx_irq_init(env);
3108
}
3109

    
3110
/* PowerPC G2                                                                */
3111
#define POWERPC_INSNS_G2     (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3112
#define POWERPC_MSRM_G2      (0x000000000006FFF2ULL)
3113
#define POWERPC_MMU_G2       (POWERPC_MMU_SOFT_6xx)
3114
//#define POWERPC_EXCP_G2      (POWERPC_EXCP_G2)
3115
#define POWERPC_INPUT_G2     (PPC_FLAGS_INPUT_6xx)
3116
#define POWERPC_BFDM_G2      (bfd_mach_ppc_ec603e)
3117

    
3118
static void init_proc_G2 (CPUPPCState *env)
3119
{
3120
    gen_spr_ne_601(env);
3121
    gen_spr_G2_755(env);
3122
    gen_spr_G2(env);
3123
    /* Time base */
3124
    gen_tbl(env);
3125
    /* Hardware implementation register */
3126
    /* XXX : not implemented */
3127
    spr_register(env, SPR_HID0, "HID0",
3128
                 SPR_NOACCESS, SPR_NOACCESS,
3129
                 &spr_read_generic, &spr_write_generic,
3130
                 0x00000000);
3131
    /* XXX : not implemented */
3132
    spr_register(env, SPR_HID1, "HID1",
3133
                 SPR_NOACCESS, SPR_NOACCESS,
3134
                 &spr_read_generic, &spr_write_generic,
3135
                 0x00000000);
3136
    /* XXX : not implemented */
3137
    spr_register(env, SPR_HID2, "HID2",
3138
                 SPR_NOACCESS, SPR_NOACCESS,
3139
                 &spr_read_generic, &spr_write_generic,
3140
                 0x00000000);
3141
    /* Memory management */
3142
    gen_low_BATs(env);
3143
    gen_high_BATs(env);
3144
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3145
    init_excp_G2(env);
3146
    /* Allocate hardware IRQ controller */
3147
    ppc6xx_irq_init(env);
3148
}
3149

    
3150
/* PowerPC G2LE                                                              */
3151
#define POWERPC_INSNS_G2LE   (POWERPC_INSNS_WORKS | PPC_6xx_TLB | PPC_EXTERN)
3152
#define POWERPC_MSRM_G2LE    (0x000000000007FFF3ULL)
3153
#define POWERPC_MMU_G2LE     (POWERPC_MMU_SOFT_6xx)
3154
#define POWERPC_EXCP_G2LE    (POWERPC_EXCP_G2)
3155
#define POWERPC_INPUT_G2LE   (PPC_FLAGS_INPUT_6xx)
3156
#define POWERPC_BFDM_G2LE    (bfd_mach_ppc_ec603e)
3157

    
3158
static void init_proc_G2LE (CPUPPCState *env)
3159
{
3160
    gen_spr_ne_601(env);
3161
    gen_spr_G2_755(env);
3162
    gen_spr_G2(env);
3163
    /* Time base */
3164
    gen_tbl(env);
3165
    /* Hardware implementation register */
3166
    /* XXX : not implemented */
3167
    spr_register(env, SPR_HID0, "HID0",
3168
                 SPR_NOACCESS, SPR_NOACCESS,
3169
                 &spr_read_generic, &spr_write_generic,
3170
                 0x00000000);
3171
    /* XXX : not implemented */
3172
    spr_register(env, SPR_HID1, "HID1",
3173
                 SPR_NOACCESS, SPR_NOACCESS,
3174
                 &spr_read_generic, &spr_write_generic,
3175
                 0x00000000);
3176
    /* XXX : not implemented */
3177
    spr_register(env, SPR_HID2, "HID2",
3178
                 SPR_NOACCESS, SPR_NOACCESS,
3179
                 &spr_read_generic, &spr_write_generic,
3180
                 0x00000000);
3181
    /* Memory management */
3182
    gen_low_BATs(env);
3183
    gen_high_BATs(env);
3184
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3185
    init_excp_G2(env);
3186
    /* Allocate hardware IRQ controller */
3187
    ppc6xx_irq_init(env);
3188
}
3189

    
3190
/* PowerPC 604                                                               */
3191
#define POWERPC_INSNS_604    (POWERPC_INSNS_WORKS | PPC_EXTERN)
3192
#define POWERPC_MSRM_604     (0x000000000005FF77ULL)
3193
#define POWERPC_MMU_604      (POWERPC_MMU_32B)
3194
//#define POWERPC_EXCP_604     (POWERPC_EXCP_604)
3195
#define POWERPC_INPUT_604    (PPC_FLAGS_INPUT_6xx)
3196
#define POWERPC_BFDM_604     (bfd_mach_ppc_604)
3197

    
3198
static void init_proc_604 (CPUPPCState *env)
3199
{
3200
    gen_spr_ne_601(env);
3201
    gen_spr_604(env);
3202
    /* Time base */
3203
    gen_tbl(env);
3204
    /* Hardware implementation registers */
3205
    /* XXX : not implemented */
3206
    spr_register(env, SPR_HID0, "HID0",
3207
                 SPR_NOACCESS, SPR_NOACCESS,
3208
                 &spr_read_generic, &spr_write_generic,
3209
                 0x00000000);
3210
    /* XXX : not implemented */
3211
    spr_register(env, SPR_HID1, "HID1",
3212
                 SPR_NOACCESS, SPR_NOACCESS,
3213
                 &spr_read_generic, &spr_write_generic,
3214
                 0x00000000);
3215
    /* Memory management */
3216
    gen_low_BATs(env);
3217
    init_excp_604(env);
3218
    /* Allocate hardware IRQ controller */
3219
    ppc6xx_irq_init(env);
3220
}
3221

    
3222
/* PowerPC 740/750 (aka G3)                                                  */
3223
#define POWERPC_INSNS_7x0    (POWERPC_INSNS_WORKS | PPC_EXTERN)
3224
#define POWERPC_MSRM_7x0     (0x000000000007FF77ULL)
3225
#define POWERPC_MMU_7x0      (POWERPC_MMU_32B)
3226
//#define POWERPC_EXCP_7x0     (POWERPC_EXCP_7x0)
3227
#define POWERPC_INPUT_7x0    (PPC_FLAGS_INPUT_6xx)
3228
#define POWERPC_BFDM_7x0     (bfd_mach_ppc_750)
3229

    
3230
static void init_proc_7x0 (CPUPPCState *env)
3231
{
3232
    gen_spr_ne_601(env);
3233
    gen_spr_7xx(env);
3234
    /* Time base */
3235
    gen_tbl(env);
3236
    /* Thermal management */
3237
    gen_spr_thrm(env);
3238
    /* Hardware implementation registers */
3239
    /* XXX : not implemented */
3240
    spr_register(env, SPR_HID0, "HID0",
3241
                 SPR_NOACCESS, SPR_NOACCESS,
3242
                 &spr_read_generic, &spr_write_generic,
3243
                 0x00000000);
3244
    /* XXX : not implemented */
3245
    spr_register(env, SPR_HID1, "HID1",
3246
                 SPR_NOACCESS, SPR_NOACCESS,
3247
                 &spr_read_generic, &spr_write_generic,
3248
                 0x00000000);
3249
    /* Memory management */
3250
    gen_low_BATs(env);
3251
    init_excp_7x0(env);
3252
    /* Allocate hardware IRQ controller */
3253
    ppc6xx_irq_init(env);
3254
}
3255

    
3256
/* PowerPC 750FX/GX                                                          */
3257
#define POWERPC_INSNS_750fx  (POWERPC_INSNS_WORKS | PPC_EXTERN)
3258
#define POWERPC_MSRM_750fx   (0x000000000007FF77ULL)
3259
#define POWERPC_MMU_750fx    (POWERPC_MMU_32B)
3260
#define POWERPC_EXCP_750fx   (POWERPC_EXCP_7x0)
3261
#define POWERPC_INPUT_750fx  (PPC_FLAGS_INPUT_6xx)
3262
#define POWERPC_BFDM_750fx   (bfd_mach_ppc_750)
3263

    
3264
static void init_proc_750fx (CPUPPCState *env)
3265
{
3266
    gen_spr_ne_601(env);
3267
    gen_spr_7xx(env);
3268
    /* Time base */
3269
    gen_tbl(env);
3270
    /* Thermal management */
3271
    gen_spr_thrm(env);
3272
    /* Hardware implementation registers */
3273
    /* XXX : not implemented */
3274
    spr_register(env, SPR_HID0, "HID0",
3275
                 SPR_NOACCESS, SPR_NOACCESS,
3276
                 &spr_read_generic, &spr_write_generic,
3277
                 0x00000000);
3278
    /* XXX : not implemented */
3279
    spr_register(env, SPR_HID1, "HID1",
3280
                 SPR_NOACCESS, SPR_NOACCESS,
3281
                 &spr_read_generic, &spr_write_generic,
3282
                 0x00000000);
3283
    /* XXX : not implemented */
3284
    spr_register(env, SPR_750_HID2, "HID2",
3285
                 SPR_NOACCESS, SPR_NOACCESS,
3286
                 &spr_read_generic, &spr_write_generic,
3287
                 0x00000000);
3288
    /* Memory management */
3289
    gen_low_BATs(env);
3290
    /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3291
    gen_high_BATs(env);
3292
    init_excp_750FX(env);
3293
    /* Allocate hardware IRQ controller */
3294
    ppc6xx_irq_init(env);
3295
}
3296

    
3297
/* PowerPC 745/755                                                           */
3298
#define POWERPC_INSNS_7x5    (POWERPC_INSNS_WORKS | PPC_EXTERN | PPC_6xx_TLB)
3299
#define POWERPC_MSRM_7x5     (0x000000000007FF77ULL)
3300
#define POWERPC_MMU_7x5      (POWERPC_MMU_SOFT_6xx)
3301
//#define POWERPC_EXCP_7x5     (POWERPC_EXCP_7x5)
3302
#define POWERPC_INPUT_7x5    (PPC_FLAGS_INPUT_6xx)
3303
#define POWERPC_BFDM_7x5     (bfd_mach_ppc_750)
3304

    
3305
static void init_proc_7x5 (CPUPPCState *env)
3306
{
3307
    gen_spr_ne_601(env);
3308
    gen_spr_G2_755(env);
3309
    /* Time base */
3310
    gen_tbl(env);
3311
    /* L2 cache control */
3312
    /* XXX : not implemented */
3313
    spr_register(env, SPR_ICTC, "ICTC",
3314
                 SPR_NOACCESS, SPR_NOACCESS,
3315
                 &spr_read_generic, &spr_write_generic,
3316
                 0x00000000);
3317
    /* XXX : not implemented */
3318
    spr_register(env, SPR_L2PMCR, "L2PMCR",
3319
                 SPR_NOACCESS, SPR_NOACCESS,
3320
                 &spr_read_generic, &spr_write_generic,
3321
                 0x00000000);
3322
    /* Hardware implementation registers */
3323
    /* XXX : not implemented */
3324
    spr_register(env, SPR_HID0, "HID0",
3325
                 SPR_NOACCESS, SPR_NOACCESS,
3326
                 &spr_read_generic, &spr_write_generic,
3327
                 0x00000000);
3328
    /* XXX : not implemented */
3329
    spr_register(env, SPR_HID1, "HID1",
3330
                 SPR_NOACCESS, SPR_NOACCESS,
3331
                 &spr_read_generic, &spr_write_generic,
3332
                 0x00000000);
3333
    /* XXX : not implemented */
3334
    spr_register(env, SPR_HID2, "HID2",
3335
                 SPR_NOACCESS, SPR_NOACCESS,
3336
                 &spr_read_generic, &spr_write_generic,
3337
                 0x00000000);
3338
    /* Memory management */
3339
    gen_low_BATs(env);
3340
    gen_high_BATs(env);
3341
    gen_6xx_7xx_soft_tlb(env, 64, 2);
3342
    /* Allocate hardware IRQ controller */
3343
    ppc6xx_irq_init(env);
3344
}
3345

    
3346
/* PowerPC 7400 (aka G4)                                                     */
3347
#define POWERPC_INSNS_7400   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3348
                              PPC_EXTERN | PPC_MEM_TLBIA |                    \
3349
                              PPC_ALTIVEC)
3350
#define POWERPC_MSRM_7400    (0x000000000205FF77ULL)
3351
#define POWERPC_MMU_7400     (POWERPC_MMU_32B)
3352
#define POWERPC_EXCP_7400    (POWERPC_EXCP_74xx)
3353
#define POWERPC_INPUT_7400   (PPC_FLAGS_INPUT_6xx)
3354
#define POWERPC_BFDM_7400    (bfd_mach_ppc_7400)
3355

    
3356
static void init_proc_7400 (CPUPPCState *env)
3357
{
3358
    gen_spr_ne_601(env);
3359
    gen_spr_7xx(env);
3360
    /* Time base */
3361
    gen_tbl(env);
3362
    /* 74xx specific SPR */
3363
    gen_spr_74xx(env);
3364
    /* Thermal management */
3365
    gen_spr_thrm(env);
3366
    /* Memory management */
3367
    gen_low_BATs(env);
3368
    init_excp_7400(env);
3369
    /* Allocate hardware IRQ controller */
3370
    ppc6xx_irq_init(env);
3371
}
3372

    
3373
/* PowerPC 7410 (aka G4)                                                     */
3374
#define POWERPC_INSNS_7410   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3375
                              PPC_EXTERN | PPC_MEM_TLBIA |                    \
3376
                              PPC_ALTIVEC)
3377
#define POWERPC_MSRM_7410    (0x000000000205FF77ULL)
3378
#define POWERPC_MMU_7410     (POWERPC_MMU_32B)
3379
#define POWERPC_EXCP_7410    (POWERPC_EXCP_74xx)
3380
#define POWERPC_INPUT_7410   (PPC_FLAGS_INPUT_6xx)
3381
#define POWERPC_BFDM_7410    (bfd_mach_ppc_7400)
3382

    
3383
static void init_proc_7410 (CPUPPCState *env)
3384
{
3385
    gen_spr_ne_601(env);
3386
    gen_spr_7xx(env);
3387
    /* Time base */
3388
    gen_tbl(env);
3389
    /* 74xx specific SPR */
3390
    gen_spr_74xx(env);
3391
    /* Thermal management */
3392
    gen_spr_thrm(env);
3393
    /* L2PMCR */
3394
    /* XXX : not implemented */
3395
    spr_register(env, SPR_L2PMCR, "L2PMCR",
3396
                 SPR_NOACCESS, SPR_NOACCESS,
3397
                 &spr_read_generic, &spr_write_generic,
3398
                 0x00000000);
3399
    /* LDSTDB */
3400
    /* XXX : not implemented */
3401
    spr_register(env, SPR_LDSTDB, "LDSTDB",
3402
                 SPR_NOACCESS, SPR_NOACCESS,
3403
                 &spr_read_generic, &spr_write_generic,
3404
                 0x00000000);
3405
    /* Memory management */
3406
    gen_low_BATs(env);
3407
    init_excp_7400(env);
3408
    /* Allocate hardware IRQ controller */
3409
    ppc6xx_irq_init(env);
3410
}
3411

    
3412
/* PowerPC 7440 (aka G4)                                                     */
3413
#if defined (TODO)
3414
#define POWERPC_INSNS_7440   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3415
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3416
                              PPC_ALTIVEC)
3417
#define POWERPC_MSRM_7440    (0x000000000205FF77ULL)
3418
#define POWERPC_MMU_7440     (POWERPC_MMU_SOFT_74xx)
3419
#define POWERPC_EXCP_7440    (POWERPC_EXCP_74xx)
3420
#define POWERPC_INPUT_7440   (PPC_FLAGS_INPUT_6xx)
3421
#define POWERPC_BFDM_7440    (bfd_mach_ppc_7400)
3422

    
3423
static void init_proc_7440 (CPUPPCState *env)
3424
{
3425
    gen_spr_ne_601(env);
3426
    gen_spr_7xx(env);
3427
    /* Time base */
3428
    gen_tbl(env);
3429
    /* 74xx specific SPR */
3430
    gen_spr_74xx(env);
3431
    /* LDSTCR */
3432
    /* XXX : not implemented */
3433
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3434
                 SPR_NOACCESS, SPR_NOACCESS,
3435
                 &spr_read_generic, &spr_write_generic,
3436
                 0x00000000);
3437
    /* ICTRL */
3438
    /* XXX : not implemented */
3439
    spr_register(env, SPR_ICTRL, "ICTRL",
3440
                 SPR_NOACCESS, SPR_NOACCESS,
3441
                 &spr_read_generic, &spr_write_generic,
3442
                 0x00000000);
3443
    /* MSSSR0 */
3444
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3445
                 SPR_NOACCESS, SPR_NOACCESS,
3446
                 &spr_read_generic, &spr_write_generic,
3447
                 0x00000000);
3448
    /* PMC */
3449
    /* XXX : not implemented */
3450
    spr_register(env, SPR_PMC5, "PMC5",
3451
                 SPR_NOACCESS, SPR_NOACCESS,
3452
                 &spr_read_generic, &spr_write_generic,
3453
                 0x00000000);
3454
    spr_register(env, SPR_UPMC5, "UPMC5",
3455
                 &spr_read_ureg, SPR_NOACCESS,
3456
                 &spr_read_ureg, SPR_NOACCESS,
3457
                 0x00000000);
3458
    spr_register(env, SPR_PMC6, "PMC6",
3459
                 SPR_NOACCESS, SPR_NOACCESS,
3460
                 &spr_read_generic, &spr_write_generic,
3461
                 0x00000000);
3462
    spr_register(env, SPR_UPMC6, "UPMC6",
3463
                 &spr_read_ureg, SPR_NOACCESS,
3464
                 &spr_read_ureg, SPR_NOACCESS,
3465
                 0x00000000);
3466
    /* Memory management */
3467
    gen_low_BATs(env);
3468
    gen_74xx_soft_tlb(env);
3469
    /* Allocate hardware IRQ controller */
3470
    ppc6xx_irq_init(env);
3471
}
3472
#endif /* TODO */
3473

    
3474
/* PowerPC 7450 (aka G4)                                                     */
3475
#if defined (TODO)
3476
#define POWERPC_INSNS_7450   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3477
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3478
                              PPC_ALTIVEC)
3479
#define POWERPC_MSRM_7450    (0x000000000205FF77ULL)
3480
#define POWERPC_MMU_7450     (POWERPC_MMU_SOFT_74xx)
3481
#define POWERPC_EXCP_7450    (POWERPC_EXCP_74xx)
3482
#define POWERPC_INPUT_7450   (PPC_FLAGS_INPUT_6xx)
3483
#define POWERPC_BFDM_7450    (bfd_mach_ppc_7400)
3484

    
3485
static void init_proc_7450 (CPUPPCState *env)
3486
{
3487
    gen_spr_ne_601(env);
3488
    gen_spr_7xx(env);
3489
    /* Time base */
3490
    gen_tbl(env);
3491
    /* 74xx specific SPR */
3492
    gen_spr_74xx(env);
3493
    /* Level 3 cache control */
3494
    gen_l3_ctrl(env);
3495
    /* LDSTCR */
3496
    /* XXX : not implemented */
3497
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3498
                 SPR_NOACCESS, SPR_NOACCESS,
3499
                 &spr_read_generic, &spr_write_generic,
3500
                 0x00000000);
3501
    /* ICTRL */
3502
    /* XXX : not implemented */
3503
    spr_register(env, SPR_ICTRL, "ICTRL",
3504
                 SPR_NOACCESS, SPR_NOACCESS,
3505
                 &spr_read_generic, &spr_write_generic,
3506
                 0x00000000);
3507
    /* MSSSR0 */
3508
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3509
                 SPR_NOACCESS, SPR_NOACCESS,
3510
                 &spr_read_generic, &spr_write_generic,
3511
                 0x00000000);
3512
    /* PMC */
3513
    /* XXX : not implemented */
3514
    spr_register(env, SPR_PMC5, "PMC5",
3515
                 SPR_NOACCESS, SPR_NOACCESS,
3516
                 &spr_read_generic, &spr_write_generic,
3517
                 0x00000000);
3518
    spr_register(env, SPR_UPMC5, "UPMC5",
3519
                 &spr_read_ureg, SPR_NOACCESS,
3520
                 &spr_read_ureg, SPR_NOACCESS,
3521
                 0x00000000);
3522
    spr_register(env, SPR_PMC6, "PMC6",
3523
                 SPR_NOACCESS, SPR_NOACCESS,
3524
                 &spr_read_generic, &spr_write_generic,
3525
                 0x00000000);
3526
    spr_register(env, SPR_UPMC6, "UPMC6",
3527
                 &spr_read_ureg, SPR_NOACCESS,
3528
                 &spr_read_ureg, SPR_NOACCESS,
3529
                 0x00000000);
3530
    /* Memory management */
3531
    gen_low_BATs(env);
3532
    gen_74xx_soft_tlb(env);
3533
    init_excp_7450(env);
3534
    /* Allocate hardware IRQ controller */
3535
    ppc6xx_irq_init(env);
3536
}
3537
#endif /* TODO */
3538

    
3539
/* PowerPC 7445 (aka G4)                                                     */
3540
#if defined (TODO)
3541
#define POWERPC_INSNS_7445   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3542
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3543
                              PPC_ALTIVEC)
3544
#define POWERPC_MSRM_7445    (0x000000000205FF77ULL)
3545
#define POWERPC_MMU_7445     (POWERPC_MMU_SOFT_74xx)
3546
#define POWERPC_EXCP_7445    (POWERPC_EXCP_74xx)
3547
#define POWERPC_INPUT_7445   (PPC_FLAGS_INPUT_6xx)
3548
#define POWERPC_BFDM_7445    (bfd_mach_ppc_7400)
3549

    
3550
static void init_proc_7445 (CPUPPCState *env)
3551
{
3552
    gen_spr_ne_601(env);
3553
    gen_spr_7xx(env);
3554
    /* Time base */
3555
    gen_tbl(env);
3556
    /* 74xx specific SPR */
3557
    gen_spr_74xx(env);
3558
    /* LDSTCR */
3559
    /* XXX : not implemented */
3560
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3561
                 SPR_NOACCESS, SPR_NOACCESS,
3562
                 &spr_read_generic, &spr_write_generic,
3563
                 0x00000000);
3564
    /* ICTRL */
3565
    /* XXX : not implemented */
3566
    spr_register(env, SPR_ICTRL, "ICTRL",
3567
                 SPR_NOACCESS, SPR_NOACCESS,
3568
                 &spr_read_generic, &spr_write_generic,
3569
                 0x00000000);
3570
    /* MSSSR0 */
3571
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3572
                 SPR_NOACCESS, SPR_NOACCESS,
3573
                 &spr_read_generic, &spr_write_generic,
3574
                 0x00000000);
3575
    /* PMC */
3576
    /* XXX : not implemented */
3577
    spr_register(env, SPR_PMC5, "PMC5",
3578
                 SPR_NOACCESS, SPR_NOACCESS,
3579
                 &spr_read_generic, &spr_write_generic,
3580
                 0x00000000);
3581
    spr_register(env, SPR_UPMC5, "UPMC5",
3582
                 &spr_read_ureg, SPR_NOACCESS,
3583
                 &spr_read_ureg, SPR_NOACCESS,
3584
                 0x00000000);
3585
    spr_register(env, SPR_PMC6, "PMC6",
3586
                 SPR_NOACCESS, SPR_NOACCESS,
3587
                 &spr_read_generic, &spr_write_generic,
3588
                 0x00000000);
3589
    spr_register(env, SPR_UPMC6, "UPMC6",
3590
                 &spr_read_ureg, SPR_NOACCESS,
3591
                 &spr_read_ureg, SPR_NOACCESS,
3592
                 0x00000000);
3593
    /* SPRGs */
3594
    spr_register(env, SPR_SPRG4, "SPRG4",
3595
                 SPR_NOACCESS, SPR_NOACCESS,
3596
                 &spr_read_generic, &spr_write_generic,
3597
                 0x00000000);
3598
    spr_register(env, SPR_USPRG4, "USPRG4",
3599
                 &spr_read_ureg, SPR_NOACCESS,
3600
                 &spr_read_ureg, SPR_NOACCESS,
3601
                 0x00000000);
3602
    spr_register(env, SPR_SPRG5, "SPRG5",
3603
                 SPR_NOACCESS, SPR_NOACCESS,
3604
                 &spr_read_generic, &spr_write_generic,
3605
                 0x00000000);
3606
    spr_register(env, SPR_USPRG5, "USPRG5",
3607
                 &spr_read_ureg, SPR_NOACCESS,
3608
                 &spr_read_ureg, SPR_NOACCESS,
3609
                 0x00000000);
3610
    spr_register(env, SPR_SPRG6, "SPRG6",
3611
                 SPR_NOACCESS, SPR_NOACCESS,
3612
                 &spr_read_generic, &spr_write_generic,
3613
                 0x00000000);
3614
    spr_register(env, SPR_USPRG6, "USPRG6",
3615
                 &spr_read_ureg, SPR_NOACCESS,
3616
                 &spr_read_ureg, SPR_NOACCESS,
3617
                 0x00000000);
3618
    spr_register(env, SPR_SPRG7, "SPRG7",
3619
                 SPR_NOACCESS, SPR_NOACCESS,
3620
                 &spr_read_generic, &spr_write_generic,
3621
                 0x00000000);
3622
    spr_register(env, SPR_USPRG7, "USPRG7",
3623
                 &spr_read_ureg, SPR_NOACCESS,
3624
                 &spr_read_ureg, SPR_NOACCESS,
3625
                 0x00000000);
3626
    /* Memory management */
3627
    gen_low_BATs(env);
3628
    gen_high_BATs(env);
3629
    gen_74xx_soft_tlb(env);
3630
    init_excp_7450(env);
3631
    /* Allocate hardware IRQ controller */
3632
    ppc6xx_irq_init(env);
3633
}
3634
#endif /* TODO */
3635

    
3636
/* PowerPC 7455 (aka G4)                                                     */
3637
#if defined (TODO)
3638
#define POWERPC_INSNS_7455   (POWERPC_INSNS_WORKS | PPC_CACHE_DCBA |          \
3639
                              PPC_EXTERN | PPC_74xx_TLB | PPC_MEM_TLBIA |     \
3640
                              PPC_ALTIVEC)
3641
#define POWERPC_MSRM_7455    (0x000000000205FF77ULL)
3642
#define POWERPC_MMU_7455     (POWERPC_MMU_SOFT_74xx)
3643
#define POWERPC_EXCP_7455    (POWERPC_EXCP_74xx)
3644
#define POWERPC_INPUT_7455   (PPC_FLAGS_INPUT_6xx)
3645
#define POWERPC_BFDM_7455    (bfd_mach_ppc_7400)
3646

    
3647
static void init_proc_7455 (CPUPPCState *env)
3648
{
3649
    gen_spr_ne_601(env);
3650
    gen_spr_7xx(env);
3651
    /* Time base */
3652
    gen_tbl(env);
3653
    /* 74xx specific SPR */
3654
    gen_spr_74xx(env);
3655
    /* Level 3 cache control */
3656
    gen_l3_ctrl(env);
3657
    /* LDSTCR */
3658
    /* XXX : not implemented */
3659
    spr_register(env, SPR_LDSTCR, "LDSTCR",
3660
                 SPR_NOACCESS, SPR_NOACCESS,
3661
                 &spr_read_generic, &spr_write_generic,
3662
                 0x00000000);
3663
    /* ICTRL */
3664
    /* XXX : not implemented */
3665
    spr_register(env, SPR_ICTRL, "ICTRL",
3666
                 SPR_NOACCESS, SPR_NOACCESS,
3667
                 &spr_read_generic, &spr_write_generic,
3668
                 0x00000000);
3669
    /* MSSSR0 */
3670
    spr_register(env, SPR_MSSSR0, "MSSSR0",
3671
                 SPR_NOACCESS, SPR_NOACCESS,
3672
                 &spr_read_generic, &spr_write_generic,
3673
                 0x00000000);
3674
    /* PMC */
3675
    /* XXX : not implemented */
3676
    spr_register(env, SPR_PMC5, "PMC5",
3677
                 SPR_NOACCESS, SPR_NOACCESS,
3678
                 &spr_read_generic, &spr_write_generic,
3679
                 0x00000000);
3680
    spr_register(env, SPR_UPMC5, "UPMC5",
3681
                 &spr_read_ureg, SPR_NOACCESS,
3682
                 &spr_read_ureg, SPR_NOACCESS,
3683
                 0x00000000);
3684
    spr_register(env, SPR_PMC6, "PMC6",
3685
                 SPR_NOACCESS, SPR_NOACCESS,
3686
                 &spr_read_generic, &spr_write_generic,
3687
                 0x00000000);
3688
    spr_register(env, SPR_UPMC6, "UPMC6",
3689
                 &spr_read_ureg, SPR_NOACCESS,
3690
                 &spr_read_ureg, SPR_NOACCESS,
3691
                 0x00000000);
3692
    /* SPRGs */
3693
    spr_register(env, SPR_SPRG4, "SPRG4",
3694
                 SPR_NOACCESS, SPR_NOACCESS,
3695
                 &spr_read_generic, &spr_write_generic,
3696
                 0x00000000);
3697
    spr_register(env, SPR_USPRG4, "USPRG4",
3698
                 &spr_read_ureg, SPR_NOACCESS,
3699
                 &spr_read_ureg, SPR_NOACCESS,
3700
                 0x00000000);
3701
    spr_register(env, SPR_SPRG5, "SPRG5",
3702
                 SPR_NOACCESS, SPR_NOACCESS,
3703
                 &spr_read_generic, &spr_write_generic,
3704
                 0x00000000);
3705
    spr_register(env, SPR_USPRG5, "USPRG5",
3706
                 &spr_read_ureg, SPR_NOACCESS,
3707
                 &spr_read_ureg, SPR_NOACCESS,
3708
                 0x00000000);
3709
    spr_register(env, SPR_SPRG6, "SPRG6",
3710
                 SPR_NOACCESS, SPR_NOACCESS,
3711
                 &spr_read_generic, &spr_write_generic,
3712
                 0x00000000);
3713
    spr_register(env, SPR_USPRG6, "USPRG6",
3714
                 &spr_read_ureg, SPR_NOACCESS,
3715
                 &spr_read_ureg, SPR_NOACCESS,
3716
                 0x00000000);
3717
    spr_register(env, SPR_SPRG7, "SPRG7",
3718
                 SPR_NOACCESS, SPR_NOACCESS,
3719
                 &spr_read_generic, &spr_write_generic,
3720
                 0x00000000);
3721
    spr_register(env, SPR_USPRG7, "USPRG7",
3722
                 &spr_read_ureg, SPR_NOACCESS,
3723
                 &spr_read_ureg, SPR_NOACCESS,
3724
                 0x00000000);
3725
    /* Memory management */
3726
    gen_low_BATs(env);
3727
    gen_high_BATs(env);
3728
    gen_74xx_soft_tlb(env);
3729
    init_excp_7450(env);
3730
    /* Allocate hardware IRQ controller */
3731
    ppc6xx_irq_init(env);
3732
}
3733
#endif /* TODO */
3734

    
3735
#if defined (TARGET_PPC64)
3736
/* PowerPC 970                                                               */
3737
#define POWERPC_INSNS_970    (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT |         \
3738
                              PPC_64B | PPC_ALTIVEC |                         \
3739
                              PPC_64_BRIDGE | PPC_SLBI)
3740
#define POWERPC_MSRM_970     (0x900000000204FF36ULL)
3741
#define POWERPC_MMU_970      (POWERPC_MMU_64BRIDGE)
3742
//#define POWERPC_EXCP_970     (POWERPC_EXCP_970)
3743
#define POWERPC_INPUT_970    (PPC_FLAGS_INPUT_970)
3744
#define POWERPC_BFDM_970     (bfd_mach_ppc64)
3745

    
3746
static void init_proc_970 (CPUPPCState *env)
3747
{
3748
    gen_spr_ne_601(env);
3749
    gen_spr_7xx(env);
3750
    /* Time base */
3751
    gen_tbl(env);
3752
    /* Hardware implementation registers */
3753
    /* XXX : not implemented */
3754
    spr_register(env, SPR_HID0, "HID0",
3755
                 SPR_NOACCESS, SPR_NOACCESS,
3756
                 &spr_read_generic, &spr_write_generic,
3757
                 0x00000000);
3758
    /* XXX : not implemented */
3759
    spr_register(env, SPR_HID1, "HID1",
3760
                 SPR_NOACCESS, SPR_NOACCESS,
3761
                 &spr_read_generic, &spr_write_generic,
3762
                 0x00000000);
3763
    /* XXX : not implemented */
3764
    spr_register(env, SPR_750_HID2, "HID2",
3765
                 SPR_NOACCESS, SPR_NOACCESS,
3766
                 &spr_read_generic, &spr_write_generic,
3767
                 0x00000000);
3768
    /* Memory management */
3769
    /* XXX: not correct */
3770
    gen_low_BATs(env);
3771
#if 0 // TODO
3772
    env->slb_nr = 32;
3773
#endif
3774
    init_excp_970(env);
3775
    /* Allocate hardware IRQ controller */
3776
    ppc970_irq_init(env);
3777
}
3778

    
3779
/* PowerPC 970FX (aka G5)                                                    */
3780
#define POWERPC_INSNS_970FX  (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT |         \
3781
                              PPC_64B | PPC_ALTIVEC |                         \
3782
                              PPC_64_BRIDGE | PPC_SLBI)
3783
#define POWERPC_MSRM_970FX   (0x800000000204FF36ULL)
3784
#define POWERPC_MMU_970FX    (POWERPC_MMU_64BRIDGE)
3785
#define POWERPC_EXCP_970FX   (POWERPC_EXCP_970)
3786
#define POWERPC_INPUT_970FX  (PPC_FLAGS_INPUT_970)
3787
#define POWERPC_BFDM_970FX   (bfd_mach_ppc64)
3788

    
3789
static void init_proc_970FX (CPUPPCState *env)
3790
{
3791
    gen_spr_ne_601(env);
3792
    gen_spr_7xx(env);
3793
    /* Time base */
3794
    gen_tbl(env);
3795
    /* Hardware implementation registers */
3796
    /* XXX : not implemented */
3797
    spr_register(env, SPR_HID0, "HID0",
3798
                 SPR_NOACCESS, SPR_NOACCESS,
3799
                 &spr_read_generic, &spr_write_generic,
3800
                 0x00000000);
3801
    /* XXX : not implemented */
3802
    spr_register(env, SPR_HID1, "HID1",
3803
                 SPR_NOACCESS, SPR_NOACCESS,
3804
                 &spr_read_generic, &spr_write_generic,
3805
                 0x00000000);
3806
    /* XXX : not implemented */
3807
    spr_register(env, SPR_750_HID2, "HID2",
3808
                 SPR_NOACCESS, SPR_NOACCESS,
3809
                 &spr_read_generic, &spr_write_generic,
3810
                 0x00000000);
3811
    /* Memory management */
3812
    /* XXX: not correct */
3813
    gen_low_BATs(env);
3814
#if 0 // TODO
3815
    env->slb_nr = 32;
3816
#endif
3817
    init_excp_970(env);
3818
    /* Allocate hardware IRQ controller */
3819
    ppc970_irq_init(env);
3820
}
3821

    
3822
/* PowerPC 970 GX                                                            */
3823
#define POWERPC_INSNS_970GX  (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT |         \
3824
                              PPC_64B | PPC_ALTIVEC |                         \
3825
                              PPC_64_BRIDGE | PPC_SLBI)
3826
#define POWERPC_MSRM_970GX   (0x800000000204FF36ULL)
3827
#define POWERPC_MMU_970GX    (POWERPC_MMU_64BRIDGE)
3828
#define POWERPC_EXCP_970GX   (POWERPC_EXCP_970)
3829
#define POWERPC_INPUT_970GX  (PPC_FLAGS_INPUT_970)
3830
#define POWERPC_BFDM_970GX   (bfd_mach_ppc64)
3831

    
3832
static void init_proc_970GX (CPUPPCState *env)
3833
{
3834
    gen_spr_ne_601(env);
3835
    gen_spr_7xx(env);
3836
    /* Time base */
3837
    gen_tbl(env);
3838
    /* Hardware implementation registers */
3839
    /* XXX : not implemented */
3840
    spr_register(env, SPR_HID0, "HID0",
3841
                 SPR_NOACCESS, SPR_NOACCESS,
3842
                 &spr_read_generic, &spr_write_generic,
3843
                 0x00000000);
3844
    /* XXX : not implemented */
3845
    spr_register(env, SPR_HID1, "HID1",
3846
                 SPR_NOACCESS, SPR_NOACCESS,
3847
                 &spr_read_generic, &spr_write_generic,
3848
                 0x00000000);
3849
    /* XXX : not implemented */
3850
    spr_register(env, SPR_750_HID2, "HID2",
3851
                 SPR_NOACCESS, SPR_NOACCESS,
3852
                 &spr_read_generic, &spr_write_generic,
3853
                 0x00000000);
3854
    /* Memory management */
3855
    /* XXX: not correct */
3856
    gen_low_BATs(env);
3857
#if 0 // TODO
3858
    env->slb_nr = 32;
3859
#endif
3860
    init_excp_970(env);
3861
    /* Allocate hardware IRQ controller */
3862
    ppc970_irq_init(env);
3863
}
3864

    
3865
/* PowerPC 620                                                               */
3866
#if defined (TODO)
3867
#define POWERPC_INSNS_620    (POWERPC_INSNS_WORKS | PPC_FLOAT_FSQRT |         \
3868
                              PPC_64B | PPC_SLBI)
3869
#define POWERPC_MSRM_620     (0x800000000005FF73ULL)
3870
#define POWERPC_MMU_620      (POWERPC_MMU_64B)
3871
#define POWERPC_EXCP_620     (POWERPC_EXCP_970)
3872
#define POWERPC_INPUT_620    (PPC_FLAGS_INPUT_970)
3873
#define POWERPC_BFDM_620     (bfd_mach_ppc64)
3874

    
3875
static void init_proc_620 (CPUPPCState *env)
3876
{
3877
    gen_spr_ne_601(env);
3878
    gen_spr_620(env);
3879
    /* Time base */
3880
    gen_tbl(env);
3881
    /* Hardware implementation registers */
3882
    /* XXX : not implemented */
3883
    spr_register(env, SPR_HID0, "HID0",
3884
                 SPR_NOACCESS, SPR_NOACCESS,
3885
                 &spr_read_generic, &spr_write_generic,
3886
                 0x00000000);
3887
    /* Memory management */
3888
    gen_low_BATs(env);
3889
    gen_high_BATs(env);
3890
    init_excp_620(env);
3891
    /* XXX: TODO: initialize internal interrupt controller */
3892
}
3893
#endif /* TODO */
3894
#endif /* defined (TARGET_PPC64) */
3895

    
3896
/* Default 32 bits PowerPC target will be 604 */
3897
#define CPU_POWERPC_PPC32     CPU_POWERPC_604
3898
#define POWERPC_INSNS_PPC32   POWERPC_INSNS_604
3899
#define POWERPC_MSRM_PPC32    POWERPC_MSRM_604
3900
#define POWERPC_MMU_PPC32     POWERPC_MMU_604
3901
#define POWERPC_EXCP_PPC32    POWERPC_EXCP_604
3902
#define POWERPC_INPUT_PPC32   POWERPC_INPUT_604
3903
#define init_proc_PPC32       init_proc_604
3904
#define POWERPC_BFDM_PPC32    POWERPC_BFDM_604
3905

    
3906
/* Default 64 bits PowerPC target will be 970 FX */
3907
#define CPU_POWERPC_PPC64     CPU_POWERPC_970FX
3908
#define POWERPC_INSNS_PPC64   POWERPC_INSNS_970FX
3909
#define POWERPC_MSRM_PPC64    POWERPC_MSRM_970FX
3910
#define POWERPC_MMU_PPC64     POWERPC_MMU_970FX
3911
#define POWERPC_EXCP_PPC64    POWERPC_EXCP_970FX
3912
#define POWERPC_INPUT_PPC64   POWERPC_INPUT_970FX
3913
#define init_proc_PPC64       init_proc_970FX
3914
#define POWERPC_BFDM_PPC64    POWERPC_BFDM_970FX
3915

    
3916
/* Default PowerPC target will be PowerPC 32 */
3917
#if defined (TARGET_PPC64) && 0 // XXX: TODO
3918
#define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC64
3919
#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC64
3920
#define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC64
3921
#define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC64
3922
#define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC64
3923
#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC64
3924
#define init_proc_DEFAULT     init_proc_PPC64
3925
#define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC64
3926
#else
3927
#define CPU_POWERPC_DEFAULT   CPU_POWERPC_PPC32
3928
#define POWERPC_INSNS_DEFAULT POWERPC_INSNS_PPC32
3929
#define POWERPC_MSRM_DEFAULT  POWERPC_MSRM_PPC32
3930
#define POWERPC_MMU_DEFAULT   POWERPC_MMU_PPC32
3931
#define POWERPC_EXCP_DEFAULT  POWERPC_EXCP_PPC32
3932
#define POWERPC_INPUT_DEFAULT POWERPC_INPUT_PPC32
3933
#define init_proc_DEFAULT     init_proc_PPC32
3934
#define POWERPC_BFDM_DEFAULT  POWERPC_BFDM_PPC32
3935
#endif
3936

    
3937
/*****************************************************************************/
3938
/* PVR definitions for most known PowerPC                                    */
3939
enum {
3940
    /* PowerPC 401 family */
3941
    /* Generic PowerPC 401 */
3942
#define CPU_POWERPC_401       CPU_POWERPC_401G2
3943
    /* PowerPC 401 cores */
3944
    CPU_POWERPC_401A1       = 0x00210000,
3945
    CPU_POWERPC_401B2       = 0x00220000,
3946
#if 0
3947
    CPU_POWERPC_401B3       = xxx,
3948
#endif
3949
    CPU_POWERPC_401C2       = 0x00230000,
3950
    CPU_POWERPC_401D2       = 0x00240000,
3951
    CPU_POWERPC_401E2       = 0x00250000,
3952
    CPU_POWERPC_401F2       = 0x00260000,
3953
    CPU_POWERPC_401G2       = 0x00270000,
3954
    /* PowerPC 401 microcontrolers */
3955
#if 0
3956
    CPU_POWERPC_401GF       = xxx,
3957
#endif
3958
#define CPU_POWERPC_IOP480    CPU_POWERPC_401B2
3959
    /* IBM Processor for Network Resources */
3960
    CPU_POWERPC_COBRA       = 0x10100000, /* XXX: 405 ? */
3961
#if 0
3962
    CPU_POWERPC_XIPCHIP     = xxx,
3963
#endif
3964
    /* PowerPC 403 family */
3965
    /* Generic PowerPC 403 */
3966
#define CPU_POWERPC_403       CPU_POWERPC_403GC
3967
    /* PowerPC 403 microcontrollers */
3968
    CPU_POWERPC_403GA       = 0x00200011,
3969
    CPU_POWERPC_403GB       = 0x00200100,
3970
    CPU_POWERPC_403GC       = 0x00200200,
3971
    CPU_POWERPC_403GCX      = 0x00201400,
3972
#if 0
3973
    CPU_POWERPC_403GP       = xxx,
3974
#endif
3975
    /* PowerPC 405 family */
3976
    /* Generic PowerPC 405 */
3977
#define CPU_POWERPC_405       CPU_POWERPC_405D4
3978
    /* PowerPC 405 cores */
3979
#if 0
3980
    CPU_POWERPC_405A3       = xxx,
3981
#endif
3982
#if 0
3983
    CPU_POWERPC_405A4       = xxx,
3984
#endif
3985
#if 0
3986
    CPU_POWERPC_405B3       = xxx,
3987
#endif
3988
#if 0
3989
    CPU_POWERPC_405B4       = xxx,
3990
#endif
3991
#if 0
3992
    CPU_POWERPC_405C3       = xxx,
3993
#endif
3994
#if 0
3995
    CPU_POWERPC_405C4       = xxx,
3996
#endif
3997
    CPU_POWERPC_405D2       = 0x20010000,
3998
#if 0
3999
    CPU_POWERPC_405D3       = xxx,
4000
#endif
4001
    CPU_POWERPC_405D4       = 0x41810000,
4002
#if 0
4003
    CPU_POWERPC_405D5       = xxx,
4004
#endif
4005
#if 0
4006
    CPU_POWERPC_405E4       = xxx,
4007
#endif
4008
#if 0
4009
    CPU_POWERPC_405F4       = xxx,
4010
#endif
4011
#if 0
4012
    CPU_POWERPC_405F5       = xxx,
4013
#endif
4014
#if 0
4015
    CPU_POWERPC_405F6       = xxx,
4016
#endif
4017
    /* PowerPC 405 microcontrolers */
4018
    /* XXX: missing 0x200108a0 */
4019
#define CPU_POWERPC_405CR     CPU_POWERPC_405CRc
4020
    CPU_POWERPC_405CRa      = 0x40110041,
4021
    CPU_POWERPC_405CRb      = 0x401100C5,
4022
    CPU_POWERPC_405CRc      = 0x40110145,
4023
    CPU_POWERPC_405EP       = 0x51210950,
4024
#if 0
4025
    CPU_POWERPC_405EXr      = xxx,
4026
#endif
4027
    CPU_POWERPC_405EZ       = 0x41511460, /* 0x51210950 ? */
4028
#if 0
4029
    CPU_POWERPC_405FX       = xxx,
4030
#endif
4031
#define CPU_POWERPC_405GP     CPU_POWERPC_405GPd
4032
    CPU_POWERPC_405GPa      = 0x40110000,
4033
    CPU_POWERPC_405GPb      = 0x40110040,
4034
    CPU_POWERPC_405GPc      = 0x40110082,
4035
    CPU_POWERPC_405GPd      = 0x401100C4,
4036
#define CPU_POWERPC_405GPe    CPU_POWERPC_405CRc
4037
    CPU_POWERPC_405GPR      = 0x50910951,
4038
#if 0
4039
    CPU_POWERPC_405H        = xxx,
4040
#endif
4041
#if 0
4042
    CPU_POWERPC_405L        = xxx,
4043
#endif
4044
    CPU_POWERPC_405LP       = 0x41F10000,
4045
#if 0
4046
    CPU_POWERPC_405PM       = xxx,
4047
#endif
4048
#if 0
4049
    CPU_POWERPC_405PS       = xxx,
4050
#endif
4051
#if 0
4052
    CPU_POWERPC_405S        = xxx,
4053
#endif
4054
    /* IBM network processors */
4055
    CPU_POWERPC_NPE405H     = 0x414100C0,
4056
    CPU_POWERPC_NPE405H2    = 0x41410140,
4057
    CPU_POWERPC_NPE405L     = 0x416100C0,
4058
    CPU_POWERPC_NPE4GS3     = 0x40B10000,
4059
#if 0
4060
    CPU_POWERPC_NPCxx1      = xxx,
4061
#endif
4062
#if 0
4063
    CPU_POWERPC_NPR161      = xxx,
4064
#endif
4065
#if 0
4066
    CPU_POWERPC_LC77700     = xxx,
4067
#endif
4068
    /* IBM STBxxx (PowerPC 401/403/405 core based microcontrollers) */
4069
#if 0
4070
    CPU_POWERPC_STB01000    = xxx,
4071
#endif
4072
#if 0
4073
    CPU_POWERPC_STB01010    = xxx,
4074
#endif
4075
#if 0
4076
    CPU_POWERPC_STB0210     = xxx, /* 401B3 */
4077
#endif
4078
    CPU_POWERPC_STB03       = 0x40310000, /* 0x40130000 ? */
4079
#if 0
4080
    CPU_POWERPC_STB043      = xxx,
4081
#endif
4082
#if 0
4083
    CPU_POWERPC_STB045      = xxx,
4084
#endif
4085
    CPU_POWERPC_STB04       = 0x41810000,
4086
    CPU_POWERPC_STB25       = 0x51510950,
4087
#if 0
4088
    CPU_POWERPC_STB130      = xxx,
4089
#endif
4090
    /* Xilinx cores */
4091
    CPU_POWERPC_X2VP4       = 0x20010820,
4092
#define CPU_POWERPC_X2VP7     CPU_POWERPC_X2VP4
4093
    CPU_POWERPC_X2VP20      = 0x20010860,
4094
#define CPU_POWERPC_X2VP50    CPU_POWERPC_X2VP20
4095
#if 0
4096
    CPU_POWERPC_ZL10310     = xxx,
4097
#endif
4098
#if 0
4099
    CPU_POWERPC_ZL10311     = xxx,
4100
#endif
4101
#if 0
4102
    CPU_POWERPC_ZL10320     = xxx,
4103
#endif
4104
#if 0
4105
    CPU_POWERPC_ZL10321     = xxx,
4106
#endif
4107
    /* PowerPC 440 family */
4108
    /* Generic PowerPC 440 */
4109
#define CPU_POWERPC_440       CPU_POWERPC_440GXf
4110
    /* PowerPC 440 cores */
4111
#if 0
4112
    CPU_POWERPC_440A4       = xxx,
4113
#endif
4114
#if 0
4115
    CPU_POWERPC_440A5       = xxx,
4116
#endif
4117
#if 0
4118
    CPU_POWERPC_440B4       = xxx,
4119
#endif
4120
#if 0
4121
    CPU_POWERPC_440F5       = xxx,
4122
#endif
4123
#if 0
4124
    CPU_POWERPC_440G5       = xxx,
4125
#endif
4126
#if 0
4127
    CPU_POWERPC_440H4       = xxx,
4128
#endif
4129
#if 0
4130
    CPU_POWERPC_440H6       = xxx,
4131
#endif
4132
    /* PowerPC 440 microcontrolers */
4133
#define CPU_POWERPC_440EP     CPU_POWERPC_440EPb
4134
    CPU_POWERPC_440EPa      = 0x42221850,
4135
    CPU_POWERPC_440EPb      = 0x422218D3,
4136
#define CPU_POWERPC_440GP     CPU_POWERPC_440GPc
4137
    CPU_POWERPC_440GPb      = 0x40120440,
4138
    CPU_POWERPC_440GPc      = 0x40120481,
4139
#define CPU_POWERPC_440GR     CPU_POWERPC_440GRa
4140
#define CPU_POWERPC_440GRa    CPU_POWERPC_440EPb
4141
    CPU_POWERPC_440GRX      = 0x200008D0,
4142
#define CPU_POWERPC_440EPX    CPU_POWERPC_440GRX
4143
#define CPU_POWERPC_440GX     CPU_POWERPC_440GXf
4144
    CPU_POWERPC_440GXa      = 0x51B21850,
4145
    CPU_POWERPC_440GXb      = 0x51B21851,
4146
    CPU_POWERPC_440GXc      = 0x51B21892,
4147
    CPU_POWERPC_440GXf      = 0x51B21894,
4148
#if 0
4149
    CPU_POWERPC_440S        = xxx,
4150
#endif
4151
    CPU_POWERPC_440SP       = 0x53221850,
4152
    CPU_POWERPC_440SP2      = 0x53221891,
4153
    CPU_POWERPC_440SPE      = 0x53421890,
4154
    /* PowerPC 460 family */
4155
#if 0
4156
    /* Generic PowerPC 464 */
4157
#define CPU_POWERPC_464       CPU_POWERPC_464H90
4158
#endif
4159
    /* PowerPC 464 microcontrolers */
4160
#if 0
4161
    CPU_POWERPC_464H90      = xxx,
4162
#endif
4163
#if 0
4164
    CPU_POWERPC_464H90FP    = xxx,
4165
#endif
4166
    /* Freescale embedded PowerPC cores */
4167
    /* e200 family */
4168
#define CPU_POWERPC_e200      CPU_POWERPC_e200z6
4169
#if 0
4170
    CPU_POWERPC_e200z0      = xxx,
4171
#endif
4172
#if 0
4173
    CPU_POWERPC_e200z3      = xxx,
4174
#endif
4175
    CPU_POWERPC_e200z5      = 0x81000000,
4176
    CPU_POWERPC_e200z6      = 0x81120000,
4177
    /* e300 family */
4178
#define CPU_POWERPC_e300      CPU_POWERPC_e300c3
4179
    CPU_POWERPC_e300c1      = 0x00830000,
4180
    CPU_POWERPC_e300c2      = 0x00840000,
4181
    CPU_POWERPC_e300c3      = 0x00850000,
4182
    /* e500 family */
4183
#define CPU_POWERPC_e500      CPU_POWERPC_e500_v22
4184
    CPU_POWERPC_e500_v11    = 0x80200010,
4185
    CPU_POWERPC_e500_v12    = 0x80200020,
4186
    CPU_POWERPC_e500_v21    = 0x80210010,
4187
    CPU_POWERPC_e500_v22    = 0x80210020,
4188
#if 0
4189
    CPU_POWERPC_e500mc      = xxx,
4190
#endif
4191
    /* e600 family */
4192
    CPU_POWERPC_e600        = 0x80040010,
4193
    /* PowerPC MPC 5xx cores */
4194
    CPU_POWERPC_5xx         = 0x00020020,
4195
    /* PowerPC MPC 8xx cores (aka PowerQUICC) */
4196
    CPU_POWERPC_8xx         = 0x00500000,
4197
    /* PowerPC MPC 8xxx cores (aka PowerQUICC-II) */
4198
    CPU_POWERPC_82xx_HIP3   = 0x00810101,
4199
    CPU_POWERPC_82xx_HIP4   = 0x80811014,
4200
    CPU_POWERPC_827x        = 0x80822013,
4201
    /* PowerPC 6xx cores */
4202
    CPU_POWERPC_601         = 0x00010001,
4203
    CPU_POWERPC_601a        = 0x00010002,
4204
    CPU_POWERPC_602         = 0x00050100,
4205
    CPU_POWERPC_603         = 0x00030100,
4206
#define CPU_POWERPC_603E      CPU_POWERPC_603E_v41
4207
    CPU_POWERPC_603E_v11    = 0x00060101,
4208
    CPU_POWERPC_603E_v12    = 0x00060102,
4209
    CPU_POWERPC_603E_v13    = 0x00060103,
4210
    CPU_POWERPC_603E_v14    = 0x00060104,
4211
    CPU_POWERPC_603E_v22    = 0x00060202,
4212
    CPU_POWERPC_603E_v3     = 0x00060300,
4213
    CPU_POWERPC_603E_v4     = 0x00060400,
4214
    CPU_POWERPC_603E_v41    = 0x00060401,
4215
    CPU_POWERPC_603E7t      = 0x00071201,
4216
    CPU_POWERPC_603E7v      = 0x00070100,
4217
    CPU_POWERPC_603E7v1     = 0x00070101,
4218
    CPU_POWERPC_603E7v2     = 0x00070201,
4219
    CPU_POWERPC_603E7       = 0x00070200,
4220
    CPU_POWERPC_603P        = 0x00070000,
4221
#define CPU_POWERPC_603R      CPU_POWERPC_603E7t
4222
    CPU_POWERPC_G2          = 0x00810011,
4223
#if 0 // Linux pretends the MSB is zero...
4224
    CPU_POWERPC_G2H4        = 0x80811010,
4225
    CPU_POWERPC_G2gp        = 0x80821010,
4226
    CPU_POWERPC_G2ls        = 0x90810010,
4227
    CPU_POWERPC_G2LE        = 0x80820010,
4228
    CPU_POWERPC_G2LEgp      = 0x80822010,
4229
    CPU_POWERPC_G2LEls      = 0xA0822010,
4230
#else
4231
    CPU_POWERPC_G2H4        = 0x00811010,
4232
    CPU_POWERPC_G2gp        = 0x00821010,
4233
    CPU_POWERPC_G2ls        = 0x10810010,
4234
    CPU_POWERPC_G2LE        = 0x00820010,
4235
    CPU_POWERPC_G2LEgp      = 0x00822010,
4236
    CPU_POWERPC_G2LEls      = 0x20822010,
4237
#endif
4238
    CPU_POWERPC_604         = 0x00040103,
4239
#define CPU_POWERPC_604E      CPU_POWERPC_604E_v24
4240
    CPU_POWERPC_604E_v10    = 0x00090100, /* Also 2110 & 2120 */
4241
    CPU_POWERPC_604E_v22    = 0x00090202,
4242
    CPU_POWERPC_604E_v24    = 0x00090204,
4243
    CPU_POWERPC_604R        = 0x000a0101, /* Also 0x00093102 */
4244
#if 0
4245
    CPU_POWERPC_604EV       = xxx,
4246
#endif
4247
    /* PowerPC 740/750 cores (aka G3) */
4248
    /* XXX: missing 0x00084202 */
4249
#define CPU_POWERPC_7x0       CPU_POWERPC_7x0_v31
4250
    CPU_POWERPC_7x0_v20     = 0x00080200,
4251
    CPU_POWERPC_7x0_v21     = 0x00080201,
4252
    CPU_POWERPC_7x0_v22     = 0x00080202,
4253
    CPU_POWERPC_7x0_v30     = 0x00080300,
4254
    CPU_POWERPC_7x0_v31     = 0x00080301,
4255
    CPU_POWERPC_740E        = 0x00080100,
4256
    CPU_POWERPC_7x0P        = 0x10080000,
4257
    /* XXX: missing 0x00087010 (CL ?) */
4258
    CPU_POWERPC_750CL       = 0x00087200,
4259
#define CPU_POWERPC_750CX     CPU_POWERPC_750CX_v22
4260
    CPU_POWERPC_750CX_v21   = 0x00082201,
4261
    CPU_POWERPC_750CX_v22   = 0x00082202,
4262
#define CPU_POWERPC_750CXE    CPU_POWERPC_750CXE_v31b
4263
    CPU_POWERPC_750CXE_v21  = 0x00082211,
4264
    CPU_POWERPC_750CXE_v22  = 0x00082212,
4265
    CPU_POWERPC_750CXE_v23  = 0x00082213,
4266
    CPU_POWERPC_750CXE_v24  = 0x00082214,
4267
    CPU_POWERPC_750CXE_v24b = 0x00083214,
4268
    CPU_POWERPC_750CXE_v31  = 0x00083211,
4269
    CPU_POWERPC_750CXE_v31b = 0x00083311,
4270
    CPU_POWERPC_750CXR      = 0x00083410,
4271
    CPU_POWERPC_750E        = 0x00080200,
4272
    CPU_POWERPC_750FL       = 0x700A0203,
4273
#define CPU_POWERPC_750FX     CPU_POWERPC_750FX_v23
4274
    CPU_POWERPC_750FX_v10   = 0x70000100,
4275
    CPU_POWERPC_750FX_v20   = 0x70000200,
4276
    CPU_POWERPC_750FX_v21   = 0x70000201,
4277
    CPU_POWERPC_750FX_v22   = 0x70000202,
4278
    CPU_POWERPC_750FX_v23   = 0x70000203,
4279
    CPU_POWERPC_750GL       = 0x70020102,
4280
#define CPU_POWERPC_750GX     CPU_POWERPC_750GX_v12
4281
    CPU_POWERPC_750GX_v10   = 0x70020100,
4282
    CPU_POWERPC_750GX_v11   = 0x70020101,
4283
    CPU_POWERPC_750GX_v12   = 0x70020102,
4284
#define CPU_POWERPC_750L      CPU_POWERPC_750L_v32 /* Aka LoneStar */
4285
    CPU_POWERPC_750L_v22    = 0x00088202,
4286
    CPU_POWERPC_750L_v30    = 0x00088300,
4287
    CPU_POWERPC_750L_v32    = 0x00088302,
4288
    /* PowerPC 745/755 cores */
4289
#define CPU_POWERPC_7x5       CPU_POWERPC_7x5_v28
4290
    CPU_POWERPC_7x5_v10     = 0x00083100,
4291
    CPU_POWERPC_7x5_v11     = 0x00083101,
4292
    CPU_POWERPC_7x5_v20     = 0x00083200,
4293
    CPU_POWERPC_7x5_v21     = 0x00083201,
4294
    CPU_POWERPC_7x5_v22     = 0x00083202, /* aka D */
4295
    CPU_POWERPC_7x5_v23     = 0x00083203, /* aka E */
4296
    CPU_POWERPC_7x5_v24     = 0x00083204,
4297
    CPU_POWERPC_7x5_v25     = 0x00083205,
4298
    CPU_POWERPC_7x5_v26     = 0x00083206,
4299
    CPU_POWERPC_7x5_v27     = 0x00083207,
4300
    CPU_POWERPC_7x5_v28     = 0x00083208,
4301
#if 0
4302
    CPU_POWERPC_7x5P        = xxx,
4303
#endif
4304
    /* PowerPC 74xx cores (aka G4) */
4305
    /* XXX: missing 0x000C1101 */
4306
#define CPU_POWERPC_7400      CPU_POWERPC_7400_v29
4307
    CPU_POWERPC_7400_v10    = 0x000C0100,
4308
    CPU_POWERPC_7400_v11    = 0x000C0101,
4309
    CPU_POWERPC_7400_v20    = 0x000C0200,
4310
    CPU_POWERPC_7400_v22    = 0x000C0202,
4311
    CPU_POWERPC_7400_v26    = 0x000C0206,
4312
    CPU_POWERPC_7400_v27    = 0x000C0207,
4313
    CPU_POWERPC_7400_v28    = 0x000C0208,
4314
    CPU_POWERPC_7400_v29    = 0x000C0209,
4315
#define CPU_POWERPC_7410      CPU_POWERPC_7410_v14
4316
    CPU_POWERPC_7410_v10    = 0x800C1100,
4317
    CPU_POWERPC_7410_v11    = 0x800C1101,
4318
    CPU_POWERPC_7410_v12    = 0x800C1102, /* aka C */
4319
    CPU_POWERPC_7410_v13    = 0x800C1103, /* aka D */
4320
    CPU_POWERPC_7410_v14    = 0x800C1104, /* aka E */
4321
#define CPU_POWERPC_7448      CPU_POWERPC_7448_v21
4322
    CPU_POWERPC_7448_v10    = 0x80040100,
4323
    CPU_POWERPC_7448_v11    = 0x80040101,
4324
    CPU_POWERPC_7448_v20    = 0x80040200,
4325
    CPU_POWERPC_7448_v21    = 0x80040201,
4326
#define CPU_POWERPC_7450      CPU_POWERPC_7450_v21
4327
    CPU_POWERPC_7450_v10    = 0x80000100,
4328
    CPU_POWERPC_7450_v11    = 0x80000101,
4329
    CPU_POWERPC_7450_v12    = 0x80000102,
4330
    CPU_POWERPC_7450_v20    = 0x80000200, /* aka D: 2.04 */
4331
    CPU_POWERPC_7450_v21    = 0x80000201, /* aka E */
4332
    CPU_POWERPC_74x1        = 0x80000203,
4333
    CPU_POWERPC_74x1G       = 0x80000210, /* aka G: 2.3 */
4334
    /* XXX: missing 0x80010200 */
4335
#define CPU_POWERPC_74x5      CPU_POWERPC_74x5_v32
4336
    CPU_POWERPC_74x5_v10    = 0x80010100,
4337
    CPU_POWERPC_74x5_v21    = 0x80010201, /* aka C: 2.1 */
4338
    CPU_POWERPC_74x5_v32    = 0x80010302,
4339
    CPU_POWERPC_74x5_v33    = 0x80010303, /* aka F: 3.3 */
4340
    CPU_POWERPC_74x5_v34    = 0x80010304, /* aka G: 3.4 */
4341
#define CPU_POWERPC_74x7      CPU_POWERPC_74x7_v12
4342
    CPU_POWERPC_74x7_v10    = 0x80020100, /* aka A: 1.0 */
4343
    CPU_POWERPC_74x7_v11    = 0x80030101, /* aka B: 1.1 */
4344
    CPU_POWERPC_74x7_v12    = 0x80020102, /* aka C: 1.2 */
4345
    /* 64 bits PowerPC */
4346
    CPU_POWERPC_620         = 0x00140000,
4347
    CPU_POWERPC_630         = 0x00400000,
4348
    CPU_POWERPC_631         = 0x00410104,
4349
    CPU_POWERPC_POWER4      = 0x00350000,
4350
    CPU_POWERPC_POWER4P     = 0x00380000,
4351
    CPU_POWERPC_POWER5      = 0x003A0203,
4352
#define CPU_POWERPC_POWER5GR  CPU_POWERPC_POWER5
4353
    CPU_POWERPC_POWER5P     = 0x003B0000,
4354
#define CPU_POWERPC_POWER5GS  CPU_POWERPC_POWER5P
4355
    CPU_POWERPC_POWER6      = 0x003E0000,
4356
    CPU_POWERPC_POWER6_5    = 0x0F000001, /* POWER6 running POWER5 mode */
4357
    CPU_POWERPC_POWER6A     = 0x0F000002,
4358
    CPU_POWERPC_970         = 0x00390202,
4359
#define CPU_POWERPC_970FX     CPU_POWERPC_970FX_v31
4360
    CPU_POWERPC_970FX_v10   = 0x00391100,
4361
    CPU_POWERPC_970FX_v20   = 0x003C0200,
4362
    CPU_POWERPC_970FX_v21   = 0x003C0201,
4363
    CPU_POWERPC_970FX_v30   = 0x003C0300,
4364
    CPU_POWERPC_970FX_v31   = 0x003C0301,
4365
    CPU_POWERPC_970GX       = 0x00450000,
4366
#define CPU_POWERPC_970MP     CPU_POWERPC_970MP_v11
4367
    CPU_POWERPC_970MP_v10   = 0x00440100,
4368
    CPU_POWERPC_970MP_v11   = 0x00440101,
4369
#define CPU_POWERPC_CELL      CPU_POWERPC_CELL_v32
4370
    CPU_POWERPC_CELL_v10    = 0x00700100,
4371
    CPU_POWERPC_CELL_v20    = 0x00700400,
4372
    CPU_POWERPC_CELL_v30    = 0x00700500,
4373
    CPU_POWERPC_CELL_v31    = 0x00700501,
4374
#define CPU_POWERPC_CELL_v32  CPU_POWERPC_CELL_v31
4375
    CPU_POWERPC_RS64        = 0x00330000,
4376
    CPU_POWERPC_RS64II      = 0x00340000,
4377
    CPU_POWERPC_RS64III     = 0x00360000,
4378
    CPU_POWERPC_RS64IV      = 0x00370000,
4379
    /* Original POWER */
4380
    /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
4381
     * POWER2 (RIOS2) & RSC2 (P2SC) here
4382
     */
4383
#if 0
4384
    CPU_POWER           = xxx, /* 0x20000 ? 0x30000 for RSC ? */
4385
#endif
4386
#if 0
4387
    CPU_POWER2          = xxx, /* 0x40000 ? */
4388
#endif
4389
    /* PA Semi core */
4390
    CPU_POWERPC_PA6T        = 0x00900000,
4391
};
4392

    
4393
/* System version register (used on MPC 8xxx)                                */
4394
enum {
4395
    PPC_SVR_8540      = 0x80300000,
4396
    PPC_SVR_8541E     = 0x807A0010,
4397
    PPC_SVR_8543v10   = 0x80320010,
4398
    PPC_SVR_8543v11   = 0x80320011,
4399
    PPC_SVR_8543v20   = 0x80320020,
4400
    PPC_SVR_8543Ev10  = 0x803A0010,
4401
    PPC_SVR_8543Ev11  = 0x803A0011,
4402
    PPC_SVR_8543Ev20  = 0x803A0020,
4403
    PPC_SVR_8545      = 0x80310220,
4404
    PPC_SVR_8545E     = 0x80390220,
4405
    PPC_SVR_8547E     = 0x80390120,
4406
    PPC_SCR_8548v10   = 0x80310010,
4407
    PPC_SCR_8548v11   = 0x80310011,
4408
    PPC_SCR_8548v20   = 0x80310020,
4409
    PPC_SVR_8548Ev10  = 0x80390010,
4410
    PPC_SVR_8548Ev11  = 0x80390011,
4411
    PPC_SVR_8548Ev20  = 0x80390020,
4412
    PPC_SVR_8555E     = 0x80790010,
4413
    PPC_SVR_8560v10   = 0x80700010,
4414
    PPC_SVR_8560v20   = 0x80700020,
4415
};
4416

    
4417
/*****************************************************************************/
4418
/* PowerPC CPU definitions                                                   */
4419
#define POWERPC_DEF(_name, _pvr, _pvr_mask, _type)                            \
4420
    {                                                                         \
4421
        .name        = _name,                                                 \
4422
        .pvr         = _pvr,                                                  \
4423
        .pvr_mask    = _pvr_mask,                                             \
4424
        .insns_flags = glue(POWERPC_INSNS_,_type),                            \
4425
        .msr_mask    = glue(POWERPC_MSRM_,_type),                             \
4426
        .mmu_model   = glue(POWERPC_MMU_,_type),                              \
4427
        .excp_model  = glue(POWERPC_EXCP_,_type),                             \
4428
        .bus_model   = glue(POWERPC_INPUT_,_type),                            \
4429
        .bfd_mach    = glue(POWERPC_BFDM_,_type),                             \
4430
        .init_proc   = &glue(init_proc_,_type),                               \
4431
    }
4432

    
4433
static ppc_def_t ppc_defs[] = {
4434
    /* Embedded PowerPC                                                      */
4435
    /* PowerPC 401 family                                                    */
4436
    /* Generic PowerPC 401 */
4437
    POWERPC_DEF("401",         CPU_POWERPC_401,         0xFFFF0000, 401),
4438
    /* PowerPC 401 cores                                                     */
4439
    /* PowerPC 401A1 */
4440
    POWERPC_DEF("401A1",       CPU_POWERPC_401A1,       0xFFFFFFFF, 401),
4441
    /* PowerPC 401B2                                                         */
4442
    POWERPC_DEF("401B2",       CPU_POWERPC_401B2,       0xFFFFFFFF, 401x2),
4443
#if defined (TODO)
4444
    /* PowerPC 401B3                                                         */
4445
    POWERPC_DEF("401B3",       CPU_POWERPC_401B3,       0xFFFFFFFF, 401x3),
4446
#endif
4447
    /* PowerPC 401C2                                                         */
4448
    POWERPC_DEF("401C2",       CPU_POWERPC_401C2,       0xFFFFFFFF, 401x2),
4449
    /* PowerPC 401D2                                                         */
4450
    POWERPC_DEF("401D2",       CPU_POWERPC_401D2,       0xFFFFFFFF, 401x2),
4451
    /* PowerPC 401E2                                                         */
4452
    POWERPC_DEF("401E2",       CPU_POWERPC_401E2,       0xFFFFFFFF, 401x2),
4453
    /* PowerPC 401F2                                                         */
4454
    POWERPC_DEF("401F2",       CPU_POWERPC_401F2,       0xFFFFFFFF, 401x2),
4455
    /* PowerPC 401G2                                                         */
4456
    /* XXX: to be checked */
4457
    POWERPC_DEF("401G2",       CPU_POWERPC_401G2,       0xFFFFFFFF, 401x2),
4458
    /* PowerPC 401 microcontrolers                                           */
4459
#if defined (TODO)
4460
    /* PowerPC 401GF                                                         */
4461
    POWERPC_DEF("401GF",       CPU_POWERPC_401GF,       0xFFFFFFFF, 401),
4462
#endif
4463
    /* IOP480 (401 microcontroler)                                           */
4464
    POWERPC_DEF("IOP480",      CPU_POWERPC_IOP480,      0xFFFFFFFF, IOP480),
4465
    /* IBM Processor for Network Resources                                   */
4466
    POWERPC_DEF("Cobra",       CPU_POWERPC_COBRA,       0xFFFFFFFF, 401),
4467
#if defined (TODO)
4468
    POWERPC_DEF("Xipchip",     CPU_POWERPC_XIPCHIP,     0xFFFFFFFF, 401),
4469
#endif
4470
    /* PowerPC 403 family                                                    */
4471
    /* Generic PowerPC 403                                                   */
4472
    POWERPC_DEF("403",         CPU_POWERPC_403,         0xFFFF0000, 403),
4473
    /* PowerPC 403 microcontrolers                                           */
4474
    /* PowerPC 403 GA                                                        */
4475
    POWERPC_DEF("403GA",       CPU_POWERPC_403GA,       0xFFFFFFFF, 403),
4476
    /* PowerPC 403 GB                                                        */
4477
    POWERPC_DEF("403GB",       CPU_POWERPC_403GB,       0xFFFFFFFF, 403),
4478
    /* PowerPC 403 GC                                                        */
4479
    POWERPC_DEF("403GC",       CPU_POWERPC_403GC,       0xFFFFFFFF, 403),
4480
    /* PowerPC 403 GCX                                                       */
4481
    POWERPC_DEF("403GCX",      CPU_POWERPC_403GCX,      0xFFFFFFFF, 403GCX),
4482
#if defined (TODO)
4483
    /* PowerPC 403 GP                                                        */
4484
    POWERPC_DEF("403GP",       CPU_POWERPC_403GP,       0xFFFFFFFF, 403),
4485
#endif
4486
    /* PowerPC 405 family                                                    */
4487
    /* Generic PowerPC 405                                                   */
4488
    POWERPC_DEF("405",         CPU_POWERPC_405,         0xFFFF0000, 405),
4489
    /* PowerPC 405 cores                                                     */
4490
#if defined (TODO)
4491
    /* PowerPC 405 A3                                                        */
4492
    POWERPC_DEF("405A3",       CPU_POWERPC_405A3,       0xFFFFFFFF, 405),
4493
#endif
4494
#if defined (TODO)
4495
    /* PowerPC 405 A4                                                        */
4496
    POWERPC_DEF("405A4",       CPU_POWERPC_405A4,       0xFFFFFFFF, 405),
4497
#endif
4498
#if defined (TODO)
4499
    /* PowerPC 405 B3                                                        */
4500
    POWERPC_DEF("405B3",       CPU_POWERPC_405B3,       0xFFFFFFFF, 405),
4501
#endif
4502
#if defined (TODO)
4503
    /* PowerPC 405 B4                                                        */
4504
    POWERPC_DEF("405B4",       CPU_POWERPC_405B4,       0xFFFFFFFF, 405),
4505
#endif
4506
#if defined (TODO)
4507
    /* PowerPC 405 C3                                                        */
4508
    POWERPC_DEF("405C3",       CPU_POWERPC_405C3,       0xFFFFFFFF, 405),
4509
#endif
4510
#if defined (TODO)
4511
    /* PowerPC 405 C4                                                        */
4512
    POWERPC_DEF("405C4",       CPU_POWERPC_405C4,       0xFFFFFFFF, 405),
4513
#endif
4514
    /* PowerPC 405 D2                                                        */
4515
    POWERPC_DEF("405D2",       CPU_POWERPC_405D2,       0xFFFFFFFF, 405),
4516
#if defined (TODO)
4517
    /* PowerPC 405 D3                                                        */
4518
    POWERPC_DEF("405D3",       CPU_POWERPC_405D3,       0xFFFFFFFF, 405),
4519
#endif
4520
    /* PowerPC 405 D4                                                        */
4521
    POWERPC_DEF("405D4",       CPU_POWERPC_405D4,       0xFFFFFFFF, 405),
4522
#if defined (TODO)
4523
    /* PowerPC 405 D5                                                        */
4524
    POWERPC_DEF("405D5",       CPU_POWERPC_405D5,       0xFFFFFFFF, 405),
4525
#endif
4526
#if defined (TODO)
4527
    /* PowerPC 405 E4                                                        */
4528
    POWERPC_DEF("405E4",       CPU_POWERPC_405E4,       0xFFFFFFFF, 405),
4529
#endif
4530
#if defined (TODO)
4531
    /* PowerPC 405 F4                                                        */
4532
    POWERPC_DEF("405F4",       CPU_POWERPC_405F4,       0xFFFFFFFF, 405),
4533
#endif
4534
#if defined (TODO)
4535
    /* PowerPC 405 F5                                                        */
4536
    POWERPC_DEF("405F5",       CPU_POWERPC_405F5,       0xFFFFFFFF, 405),
4537
#endif
4538
#if defined (TODO)
4539
    /* PowerPC 405 F6                                                        */
4540
    POWERPC_DEF("405F6",       CPU_POWERPC_405F6,       0xFFFFFFFF, 405),
4541
#endif
4542
    /* PowerPC 405 microcontrolers                                           */
4543
    /* PowerPC 405 CR                                                        */
4544
    POWERPC_DEF("405CR",       CPU_POWERPC_405CR,       0xFFFFFFFF, 405),
4545
    /* PowerPC 405 CRa                                                       */
4546
    POWERPC_DEF("405CRa",      CPU_POWERPC_405CRa,      0xFFFFFFFF, 405),
4547
    /* PowerPC 405 CRb                                                       */
4548
    POWERPC_DEF("405CRb",      CPU_POWERPC_405CRb,      0xFFFFFFFF, 405),
4549
    /* PowerPC 405 CRc                                                       */
4550
    POWERPC_DEF("405CRc",      CPU_POWERPC_405CRc,      0xFFFFFFFF, 405),
4551
    /* PowerPC 405 EP                                                        */
4552
    POWERPC_DEF("405EP",       CPU_POWERPC_405EP,       0xFFFFFFFF, 405),
4553
#if defined(TODO)
4554
    /* PowerPC 405 EXr                                                       */
4555
    POWERPC_DEF("405EXr",      CPU_POWERPC_405EXr,      0xFFFFFFFF, 405),
4556
#endif
4557
    /* PowerPC 405 EZ                                                        */
4558
    POWERPC_DEF("405EZ",       CPU_POWERPC_405EZ,       0xFFFFFFFF, 405),
4559
#if defined(TODO)
4560
    /* PowerPC 405 FX                                                        */
4561
    POWERPC_DEF("405FX",       CPU_POWERPC_405FX,       0xFFFFFFFF, 405),
4562
#endif
4563
    /* PowerPC 405 GP                                                        */
4564
    POWERPC_DEF("405GP",       CPU_POWERPC_405GP,       0xFFFFFFFF, 405),
4565
    /* PowerPC 405 GPa                                                       */
4566
    POWERPC_DEF("405GPa",      CPU_POWERPC_405GPa,      0xFFFFFFFF, 405),
4567
    /* PowerPC 405 GPb                                                       */
4568
    POWERPC_DEF("405GPb",      CPU_POWERPC_405GPb,      0xFFFFFFFF, 405),
4569
    /* PowerPC 405 GPc                                                       */
4570
    POWERPC_DEF("405GPc",      CPU_POWERPC_405GPc,      0xFFFFFFFF, 405),
4571
    /* PowerPC 405 GPd                                                       */
4572
    POWERPC_DEF("405GPd",      CPU_POWERPC_405GPd,      0xFFFFFFFF, 405),
4573
    /* PowerPC 405 GPe                                                       */
4574
    POWERPC_DEF("405GPe",      CPU_POWERPC_405GPe,      0xFFFFFFFF, 405),
4575
    /* PowerPC 405 GPR                                                       */
4576
    POWERPC_DEF("405GPR",      CPU_POWERPC_405GPR,      0xFFFFFFFF, 405),
4577
#if defined(TODO)
4578
    /* PowerPC 405 H                                                         */
4579
    POWERPC_DEF("405H",        CPU_POWERPC_405H,        0xFFFFFFFF, 405),
4580
#endif
4581
#if defined(TODO)
4582
    /* PowerPC 405 L                                                         */
4583
    POWERPC_DEF("405L",        CPU_POWERPC_405L,        0xFFFFFFFF, 405),
4584
#endif
4585
    /* PowerPC 405 LP                                                        */
4586
    POWERPC_DEF("405LP",       CPU_POWERPC_405LP,       0xFFFFFFFF, 405),
4587
#if defined(TODO)
4588
    /* PowerPC 405 PM                                                        */
4589
    POWERPC_DEF("405PM",       CPU_POWERPC_405PM,       0xFFFFFFFF, 405),
4590
#endif
4591
#if defined(TODO)
4592
    /* PowerPC 405 PS                                                        */
4593
    POWERPC_DEF("405PS",       CPU_POWERPC_405PS,       0xFFFFFFFF, 405),
4594
#endif
4595
#if defined(TODO)
4596
    /* PowerPC 405 S                                                         */
4597
    POWERPC_DEF("405S",        CPU_POWERPC_405S,        0xFFFFFFFF, 405),
4598
#endif
4599
    /* Npe405 H                                                              */
4600
    POWERPC_DEF("Npe405H",     CPU_POWERPC_NPE405H,     0xFFFFFFFF, 405),
4601
    /* Npe405 H2                                                             */
4602
    POWERPC_DEF("Npe405H2",    CPU_POWERPC_NPE405H2,    0xFFFFFFFF, 405),
4603
    /* Npe405 L                                                              */
4604
    POWERPC_DEF("Npe405L",     CPU_POWERPC_NPE405L,     0xFFFFFFFF, 405),
4605
    /* Npe4GS3                                                               */
4606
    POWERPC_DEF("Npe4GS3",     CPU_POWERPC_NPE4GS3,     0xFFFFFFFF, 405),
4607
#if defined (TODO)
4608
    POWERPC_DEF("Npcxx1",      CPU_POWERPC_NPCxx1,      0xFFFFFFFF, 405),
4609
#endif
4610
#if defined (TODO)
4611
    POWERPC_DEF("Npr161",      CPU_POWERPC_NPR161,      0xFFFFFFFF, 405),
4612
#endif
4613
#if defined (TODO)
4614
    /* PowerPC LC77700 (Sanyo)                                               */
4615
    POWERPC_DEF("LC77700",     CPU_POWERPC_LC77700,     0xFFFFFFFF, 405),
4616
#endif
4617
    /* PowerPC 401/403/405 based set-top-box microcontrolers                 */
4618
#if defined (TODO)
4619
    /* STB010000                                                             */
4620
    POWERPC_DEF("STB01000",    CPU_POWERPC_STB01000,    0xFFFFFFFF, 401x2),
4621
#endif
4622
#if defined (TODO)
4623
    /* STB01010                                                              */
4624
    POWERPC_DEF("STB01010",    CPU_POWERPC_STB01010,    0xFFFFFFFF, 401x2),
4625
#endif
4626
#if defined (TODO)
4627
    /* STB0210                                                               */
4628
    POWERPC_DEF("STB0210",     CPU_POWERPC_STB0210,     0xFFFFFFFF, 401x3),
4629
#endif
4630
    /* STB03xx                                                               */
4631
    POWERPC_DEF("STB03",       CPU_POWERPC_STB03,       0xFFFFFFFF, 405),
4632
#if defined (TODO)
4633
    /* STB043x                                                               */
4634
    POWERPC_DEF("STB043",      CPU_POWERPC_STB043,      0xFFFFFFFF, 405),
4635
#endif
4636
#if defined (TODO)
4637
    /* STB045x                                                               */
4638
    POWERPC_DEF("STB045",      CPU_POWERPC_STB045,      0xFFFFFFFF, 405),
4639
#endif
4640
    /* STB04xx                                                               */
4641
    POWERPC_DEF("STB04",       CPU_POWERPC_STB04,       0xFFFF0000, 405),
4642
    /* STB25xx                                                               */
4643
    POWERPC_DEF("STB25",       CPU_POWERPC_STB25,       0xFFFFFFFF, 405),
4644
#if defined (TODO)
4645
    /* STB130                                                                */
4646
    POWERPC_DEF("STB130",      CPU_POWERPC_STB130,      0xFFFFFFFF, 405),
4647
#endif
4648
    /* Xilinx PowerPC 405 cores                                              */
4649
    POWERPC_DEF("x2vp4",       CPU_POWERPC_X2VP4,       0xFFFFFFFF, 405),
4650
    POWERPC_DEF("x2vp7",       CPU_POWERPC_X2VP7,       0xFFFFFFFF, 405),
4651
    POWERPC_DEF("x2vp20",      CPU_POWERPC_X2VP20,      0xFFFFFFFF, 405),
4652
    POWERPC_DEF("x2vp50",      CPU_POWERPC_X2VP50,      0xFFFFFFFF, 405),
4653
#if defined (TODO)
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