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/*
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* Alpha emulation cpu translation for qemu.
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdint.h> |
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#include <stdlib.h> |
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#include <stdio.h> |
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#include "cpu.h" |
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#include "exec-all.h" |
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#include "disas.h" |
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#include "host-utils.h" |
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#include "helper.h" |
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#include "tcg-op.h" |
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#include "qemu-common.h" |
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#define DO_SINGLE_STEP
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#define GENERATE_NOP
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#define ALPHA_DEBUG_DISAS
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#define DO_TB_FLUSH
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typedef struct DisasContext DisasContext; |
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struct DisasContext {
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uint64_t pc; |
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int mem_idx;
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#if !defined (CONFIG_USER_ONLY)
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int pal_mode;
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#endif
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uint32_t amask; |
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}; |
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/* global register indexes */
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static TCGv cpu_env;
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static TCGv cpu_ir[31]; |
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static TCGv cpu_pc;
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/* dyngen register indexes */
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static TCGv cpu_T[3]; |
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/* register names */
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static char cpu_reg_names[10*4+21*5]; |
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#include "gen-icount.h" |
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static void alpha_translate_init(void) |
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{ |
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int i;
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char *p;
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static int done_init = 0; |
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if (done_init)
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return;
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cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
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#if TARGET_LONG_BITS > HOST_LONG_BITS
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cpu_T[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
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offsetof(CPUState, t0), "T0");
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cpu_T[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
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offsetof(CPUState, t1), "T1");
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cpu_T[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
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offsetof(CPUState, t2), "T2");
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#else
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cpu_T[0] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG1, "T0"); |
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cpu_T[1] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG2, "T1"); |
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cpu_T[2] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG3, "T2"); |
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#endif
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p = cpu_reg_names; |
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for (i = 0; i < 31; i++) { |
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sprintf(p, "ir%d", i);
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cpu_ir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
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offsetof(CPUState, ir[i]), p); |
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p += (i < 10) ? 4 : 5; |
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} |
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cpu_pc = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, |
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offsetof(CPUState, pc), "pc");
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/* register helpers */
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#undef DEF_HELPER
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#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); |
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#include "helper.h" |
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done_init = 1;
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} |
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static always_inline void gen_op_nop (void) |
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{ |
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#if defined(GENERATE_NOP)
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gen_op_no_op(); |
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#endif
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} |
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#define GEN32(func, NAME) \
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static GenOpFunc *NAME ## _table [32] = { \ |
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NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ |
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NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ |
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NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ |
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NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ |
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NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \ |
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NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ |
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NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ |
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NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ |
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}; \ |
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static always_inline void func (int n) \ |
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{ \ |
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NAME ## _table[n](); \ |
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} |
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/* FIR moves */
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/* Special hacks for fir31 */
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#define gen_op_load_FT0_fir31 gen_op_reset_FT0
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#define gen_op_load_FT1_fir31 gen_op_reset_FT1
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#define gen_op_load_FT2_fir31 gen_op_reset_FT2
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#define gen_op_store_FT0_fir31 gen_op_nop
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#define gen_op_store_FT1_fir31 gen_op_nop
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#define gen_op_store_FT2_fir31 gen_op_nop
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#define gen_op_cmov_fir31 gen_op_nop
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GEN32(gen_op_load_FT0_fir, gen_op_load_FT0_fir); |
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GEN32(gen_op_load_FT1_fir, gen_op_load_FT1_fir); |
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GEN32(gen_op_load_FT2_fir, gen_op_load_FT2_fir); |
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GEN32(gen_op_store_FT0_fir, gen_op_store_FT0_fir); |
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GEN32(gen_op_store_FT1_fir, gen_op_store_FT1_fir); |
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GEN32(gen_op_store_FT2_fir, gen_op_store_FT2_fir); |
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GEN32(gen_op_cmov_fir, gen_op_cmov_fir); |
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static always_inline void gen_load_fir (DisasContext *ctx, int firn, int Tn) |
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{ |
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switch (Tn) {
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case 0: |
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gen_op_load_FT0_fir(firn); |
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break;
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case 1: |
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gen_op_load_FT1_fir(firn); |
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break;
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case 2: |
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gen_op_load_FT2_fir(firn); |
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break;
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} |
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} |
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static always_inline void gen_store_fir (DisasContext *ctx, int firn, int Tn) |
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{ |
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switch (Tn) {
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case 0: |
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gen_op_store_FT0_fir(firn); |
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break;
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case 1: |
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gen_op_store_FT1_fir(firn); |
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break;
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case 2: |
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gen_op_store_FT2_fir(firn); |
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break;
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} |
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} |
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/* Memory moves */
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#if defined(CONFIG_USER_ONLY)
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#define OP_LD_TABLE(width) \
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static GenOpFunc *gen_op_ld##width[] = { \ |
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&gen_op_ld##width##_raw, \ |
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} |
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#define OP_ST_TABLE(width) \
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static GenOpFunc *gen_op_st##width[] = { \ |
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&gen_op_st##width##_raw, \ |
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} |
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#else
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#define OP_LD_TABLE(width) \
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static GenOpFunc *gen_op_ld##width[] = { \ |
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&gen_op_ld##width##_kernel, \ |
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&gen_op_ld##width##_executive, \ |
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&gen_op_ld##width##_supervisor, \ |
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&gen_op_ld##width##_user, \ |
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} |
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#define OP_ST_TABLE(width) \
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static GenOpFunc *gen_op_st##width[] = { \ |
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&gen_op_st##width##_kernel, \ |
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&gen_op_st##width##_executive, \ |
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&gen_op_st##width##_supervisor, \ |
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&gen_op_st##width##_user, \ |
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} |
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#endif
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#define GEN_LD(width) \
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OP_LD_TABLE(width); \ |
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static always_inline void gen_ld##width (DisasContext *ctx) \ |
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{ \ |
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(*gen_op_ld##width[ctx->mem_idx])(); \ |
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} |
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#define GEN_ST(width) \
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OP_ST_TABLE(width); \ |
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static always_inline void gen_st##width (DisasContext *ctx) \ |
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{ \ |
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(*gen_op_st##width[ctx->mem_idx])(); \ |
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} |
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GEN_LD(bu); |
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GEN_ST(b); |
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GEN_LD(wu); |
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GEN_ST(w); |
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GEN_LD(l); |
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GEN_ST(l); |
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GEN_LD(q); |
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GEN_ST(q); |
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GEN_LD(q_u); |
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GEN_ST(q_u); |
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GEN_LD(l_l); |
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GEN_ST(l_c); |
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GEN_LD(q_l); |
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GEN_ST(q_c); |
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#if 0 /* currently unused */
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GEN_LD(f);
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GEN_ST(f);
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GEN_LD(g);
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GEN_ST(g);
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#endif /* 0 */
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GEN_LD(s); |
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GEN_ST(s); |
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GEN_LD(t); |
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GEN_ST(t); |
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static always_inline void _gen_op_bcond (DisasContext *ctx) |
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{ |
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#if 0 // Qemu does not know how to do this...
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gen_op_bcond(ctx->pc);
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#else
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gen_op_bcond(ctx->pc >> 32, ctx->pc);
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#endif
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} |
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static always_inline void gen_excp (DisasContext *ctx, |
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int exception, int error_code) |
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{ |
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TCGv tmp1, tmp2; |
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tcg_gen_movi_i64(cpu_pc, ctx->pc); |
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tmp1 = tcg_const_i32(exception); |
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tmp2 = tcg_const_i32(error_code); |
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tcg_gen_helper_0_2(helper_excp, tmp1, tmp2); |
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tcg_temp_free(tmp2); |
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tcg_temp_free(tmp1); |
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} |
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static always_inline void gen_invalid (DisasContext *ctx) |
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{ |
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gen_excp(ctx, EXCP_OPCDEC, 0);
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} |
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static always_inline void gen_load_mem (DisasContext *ctx, |
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void (*gen_load_op)(DisasContext *ctx),
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int ra, int rb, int32_t disp16, |
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int clear)
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{ |
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if (ra == 31 && disp16 == 0) { |
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/* UNOP */
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gen_op_nop(); |
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} else {
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if (rb != 31) |
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tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
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else
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tcg_gen_movi_i64(cpu_T[0], disp16);
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if (clear)
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tcg_gen_andi_i64(cpu_T[0], cpu_T[0], ~0x7); |
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(*gen_load_op)(ctx); |
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if (ra != 31) |
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tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]);
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} |
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} |
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static always_inline void gen_store_mem (DisasContext *ctx, |
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void (*gen_store_op)(DisasContext *ctx),
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int ra, int rb, int32_t disp16, |
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int clear)
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{ |
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if (rb != 31) |
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tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
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else
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tcg_gen_movi_i64(cpu_T[0], disp16);
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if (clear)
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tcg_gen_andi_i64(cpu_T[0], cpu_T[0], ~0x7); |
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if (ra != 31) |
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tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
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else
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tcg_gen_movi_i64(cpu_T[1], 0); |
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(*gen_store_op)(ctx); |
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} |
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static always_inline void gen_load_fmem (DisasContext *ctx, |
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void (*gen_load_fop)(DisasContext *ctx),
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int ra, int rb, int32_t disp16) |
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{ |
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if (rb != 31) |
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tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
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else
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tcg_gen_movi_i64(cpu_T[0], disp16);
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(*gen_load_fop)(ctx); |
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gen_store_fir(ctx, ra, 1);
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} |
318 |
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static always_inline void gen_store_fmem (DisasContext *ctx, |
320 |
void (*gen_store_fop)(DisasContext *ctx),
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int ra, int rb, int32_t disp16) |
322 |
{ |
323 |
if (rb != 31) |
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tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
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else
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tcg_gen_movi_i64(cpu_T[0], disp16);
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gen_load_fir(ctx, ra, 1);
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(*gen_store_fop)(ctx); |
329 |
} |
330 |
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static always_inline void gen_bcond (DisasContext *ctx, |
332 |
TCGCond cond, |
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int ra, int32_t disp16, int mask) |
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{ |
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int l1, l2;
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l1 = gen_new_label(); |
338 |
l2 = gen_new_label(); |
339 |
if (likely(ra != 31)) { |
340 |
if (mask) {
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TCGv tmp = tcg_temp_new(TCG_TYPE_I64); |
342 |
tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);
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tcg_gen_brcondi_i64(cond, tmp, 0, l1);
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tcg_temp_free(tmp); |
345 |
} else
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tcg_gen_brcondi_i64(cond, cpu_ir[ra], 0, l1);
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} else {
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/* Very uncommon case - Do not bother to optimize. */
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TCGv tmp = tcg_const_i64(0);
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tcg_gen_brcondi_i64(cond, tmp, 0, l1);
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tcg_temp_free(tmp); |
352 |
} |
353 |
tcg_gen_movi_i64(cpu_pc, ctx->pc); |
354 |
tcg_gen_br(l2); |
355 |
gen_set_label(l1); |
356 |
tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2));
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357 |
gen_set_label(l2); |
358 |
} |
359 |
|
360 |
static always_inline void gen_fbcond (DisasContext *ctx, |
361 |
void (*gen_test_op)(void), |
362 |
int ra, int32_t disp16)
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{ |
364 |
tcg_gen_movi_i64(cpu_T[1], ctx->pc + (int64_t)(disp16 << 2)); |
365 |
gen_load_fir(ctx, ra, 0);
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(*gen_test_op)(); |
367 |
_gen_op_bcond(ctx); |
368 |
} |
369 |
|
370 |
static always_inline void gen_arith3 (DisasContext *ctx, |
371 |
void (*gen_arith_op)(void), |
372 |
int ra, int rb, int rc, |
373 |
int islit, uint8_t lit)
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374 |
{ |
375 |
if (ra != 31) |
376 |
tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
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else
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378 |
tcg_gen_movi_i64(cpu_T[0], 0); |
379 |
if (islit)
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380 |
tcg_gen_movi_i64(cpu_T[1], lit);
|
381 |
else
|
382 |
tcg_gen_mov_i64(cpu_T[1], cpu_ir[rb]);
|
383 |
(*gen_arith_op)(); |
384 |
if (rc != 31) |
385 |
tcg_gen_mov_i64(cpu_ir[rc], cpu_T[0]);
|
386 |
} |
387 |
|
388 |
static always_inline void gen_cmov (DisasContext *ctx, |
389 |
TCGCond inv_cond, |
390 |
int ra, int rb, int rc, |
391 |
int islit, uint8_t lit, int mask) |
392 |
{ |
393 |
int l1;
|
394 |
|
395 |
if (unlikely(rc == 31)) |
396 |
return;
|
397 |
|
398 |
l1 = gen_new_label(); |
399 |
|
400 |
if (ra != 31) { |
401 |
if (mask) {
|
402 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64); |
403 |
tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);
|
404 |
tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);
|
405 |
tcg_temp_free(tmp); |
406 |
} else
|
407 |
tcg_gen_brcondi_i64(inv_cond, cpu_ir[ra], 0, l1);
|
408 |
} else {
|
409 |
/* Very uncommon case - Do not bother to optimize. */
|
410 |
TCGv tmp = tcg_const_i64(0);
|
411 |
tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);
|
412 |
tcg_temp_free(tmp); |
413 |
} |
414 |
|
415 |
if (islit)
|
416 |
tcg_gen_movi_i64(cpu_ir[rc], lit); |
417 |
else
|
418 |
tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
419 |
gen_set_label(l1); |
420 |
} |
421 |
|
422 |
static always_inline void gen_farith2 (DisasContext *ctx, |
423 |
void (*gen_arith_fop)(void), |
424 |
int rb, int rc) |
425 |
{ |
426 |
gen_load_fir(ctx, rb, 0);
|
427 |
(*gen_arith_fop)(); |
428 |
gen_store_fir(ctx, rc, 0);
|
429 |
} |
430 |
|
431 |
static always_inline void gen_farith3 (DisasContext *ctx, |
432 |
void (*gen_arith_fop)(void), |
433 |
int ra, int rb, int rc) |
434 |
{ |
435 |
gen_load_fir(ctx, ra, 0);
|
436 |
gen_load_fir(ctx, rb, 1);
|
437 |
(*gen_arith_fop)(); |
438 |
gen_store_fir(ctx, rc, 0);
|
439 |
} |
440 |
|
441 |
static always_inline void gen_fcmov (DisasContext *ctx, |
442 |
void (*gen_test_fop)(void), |
443 |
int ra, int rb, int rc) |
444 |
{ |
445 |
gen_load_fir(ctx, ra, 0);
|
446 |
gen_load_fir(ctx, rb, 1);
|
447 |
(*gen_test_fop)(); |
448 |
gen_op_cmov_fir(rc); |
449 |
} |
450 |
|
451 |
static always_inline void gen_fti (DisasContext *ctx, |
452 |
void (*gen_move_fop)(void), |
453 |
int ra, int rc) |
454 |
{ |
455 |
gen_load_fir(ctx, rc, 0);
|
456 |
(*gen_move_fop)(); |
457 |
if (ra != 31) |
458 |
tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
|
459 |
} |
460 |
|
461 |
static always_inline void gen_itf (DisasContext *ctx, |
462 |
void (*gen_move_fop)(void), |
463 |
int ra, int rc) |
464 |
{ |
465 |
if (ra != 31) |
466 |
tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
|
467 |
else
|
468 |
tcg_gen_movi_i64(cpu_T[0], 0); |
469 |
(*gen_move_fop)(); |
470 |
gen_store_fir(ctx, rc, 0);
|
471 |
} |
472 |
|
473 |
/* EXTWH, EXTWH, EXTLH, EXTQH */
|
474 |
static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), |
475 |
int ra, int rb, int rc, |
476 |
int islit, uint8_t lit)
|
477 |
{ |
478 |
if (unlikely(rc == 31)) |
479 |
return;
|
480 |
|
481 |
if (ra != 31) { |
482 |
if (islit) {
|
483 |
if (lit != 0) |
484 |
tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 64 - ((lit & 7) * 8)); |
485 |
else
|
486 |
tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]); |
487 |
} else {
|
488 |
TCGv tmp1, tmp2; |
489 |
tmp1 = tcg_temp_new(TCG_TYPE_I64); |
490 |
tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7);
|
491 |
tcg_gen_shli_i64(tmp1, tmp1, 3);
|
492 |
tmp2 = tcg_const_i64(64);
|
493 |
tcg_gen_sub_i64(tmp1, tmp2, tmp1); |
494 |
tcg_temp_free(tmp2); |
495 |
tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], tmp1); |
496 |
tcg_temp_free(tmp1); |
497 |
} |
498 |
if (tcg_gen_ext_i64)
|
499 |
tcg_gen_ext_i64(cpu_ir[rc], cpu_ir[rc]); |
500 |
} else
|
501 |
tcg_gen_movi_i64(cpu_ir[rc], 0);
|
502 |
} |
503 |
|
504 |
/* EXTBL, EXTWL, EXTWL, EXTLL, EXTQL */
|
505 |
static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), |
506 |
int ra, int rb, int rc, |
507 |
int islit, uint8_t lit)
|
508 |
{ |
509 |
if (unlikely(rc == 31)) |
510 |
return;
|
511 |
|
512 |
if (ra != 31) { |
513 |
if (islit) {
|
514 |
tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], (lit & 7) * 8); |
515 |
} else {
|
516 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64); |
517 |
tcg_gen_andi_i64(tmp, cpu_ir[rb], 7);
|
518 |
tcg_gen_shli_i64(tmp, tmp, 3);
|
519 |
tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], tmp); |
520 |
tcg_temp_free(tmp); |
521 |
} |
522 |
if (tcg_gen_ext_i64)
|
523 |
tcg_gen_ext_i64(cpu_ir[rc], cpu_ir[rc]); |
524 |
} else
|
525 |
tcg_gen_movi_i64(cpu_ir[rc], 0);
|
526 |
} |
527 |
|
528 |
/* Code to call byte manipulation helpers, used by:
|
529 |
INSWH, INSLH, INSQH, INSBL, INSWL, INSLL, INSQL,
|
530 |
MSKWH, MSKLH, MSKQH, MSKBL, MSKWL, MSKLL, MSKQL,
|
531 |
ZAP, ZAPNOT
|
532 |
|
533 |
WARNING: it assumes that when ra31 is used, the result is 0.
|
534 |
*/
|
535 |
static always_inline void gen_byte_manipulation(void *helper, |
536 |
int ra, int rb, int rc, |
537 |
int islit, uint8_t lit)
|
538 |
{ |
539 |
if (unlikely(rc == 31)) |
540 |
return;
|
541 |
|
542 |
if (ra != 31) { |
543 |
if (islit) {
|
544 |
TCGv tmp = tcg_const_i64(lit); |
545 |
tcg_gen_helper_1_2(helper, cpu_ir[rc], cpu_ir[ra], tmp); |
546 |
tcg_temp_free(tmp); |
547 |
} else
|
548 |
tcg_gen_helper_1_2(helper, cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
549 |
} else
|
550 |
tcg_gen_movi_i64(cpu_ir[rc], 0);
|
551 |
} |
552 |
|
553 |
static always_inline void gen_cmp(TCGCond cond, |
554 |
int ra, int rb, int rc, |
555 |
int islit, int8_t lit)
|
556 |
{ |
557 |
int l1, l2;
|
558 |
TCGv tmp; |
559 |
|
560 |
if (unlikely(rc == 31)) |
561 |
return;
|
562 |
|
563 |
l1 = gen_new_label(); |
564 |
l2 = gen_new_label(); |
565 |
|
566 |
if (ra != 31) { |
567 |
tmp = tcg_temp_new(TCG_TYPE_I64); |
568 |
tcg_gen_mov_i64(tmp, cpu_ir[ra]); |
569 |
} else
|
570 |
tmp = tcg_const_i64(0);
|
571 |
if (islit)
|
572 |
tcg_gen_brcondi_i64(cond, tmp, lit, l1); |
573 |
else
|
574 |
tcg_gen_brcond_i64(cond, tmp, cpu_ir[rb], l1); |
575 |
|
576 |
tcg_gen_movi_i64(cpu_ir[rc], 0);
|
577 |
tcg_gen_br(l2); |
578 |
gen_set_label(l1); |
579 |
tcg_gen_movi_i64(cpu_ir[rc], 1);
|
580 |
gen_set_label(l2); |
581 |
} |
582 |
|
583 |
static always_inline int translate_one (DisasContext *ctx, uint32_t insn) |
584 |
{ |
585 |
uint32_t palcode; |
586 |
int32_t disp21, disp16, disp12; |
587 |
uint16_t fn11, fn16; |
588 |
uint8_t opc, ra, rb, rc, sbz, fpfn, fn7, fn2, islit; |
589 |
uint8_t lit; |
590 |
int ret;
|
591 |
|
592 |
/* Decode all instruction fields */
|
593 |
opc = insn >> 26;
|
594 |
ra = (insn >> 21) & 0x1F; |
595 |
rb = (insn >> 16) & 0x1F; |
596 |
rc = insn & 0x1F;
|
597 |
sbz = (insn >> 13) & 0x07; |
598 |
islit = (insn >> 12) & 1; |
599 |
if (rb == 31 && !islit) { |
600 |
islit = 1;
|
601 |
lit = 0;
|
602 |
} else
|
603 |
lit = (insn >> 13) & 0xFF; |
604 |
palcode = insn & 0x03FFFFFF;
|
605 |
disp21 = ((int32_t)((insn & 0x001FFFFF) << 11)) >> 11; |
606 |
disp16 = (int16_t)(insn & 0x0000FFFF);
|
607 |
disp12 = (int32_t)((insn & 0x00000FFF) << 20) >> 20; |
608 |
fn16 = insn & 0x0000FFFF;
|
609 |
fn11 = (insn >> 5) & 0x000007FF; |
610 |
fpfn = fn11 & 0x3F;
|
611 |
fn7 = (insn >> 5) & 0x0000007F; |
612 |
fn2 = (insn >> 5) & 0x00000003; |
613 |
ret = 0;
|
614 |
#if defined ALPHA_DEBUG_DISAS
|
615 |
if (logfile != NULL) { |
616 |
fprintf(logfile, "opc %02x ra %d rb %d rc %d disp16 %04x\n",
|
617 |
opc, ra, rb, rc, disp16); |
618 |
} |
619 |
#endif
|
620 |
switch (opc) {
|
621 |
case 0x00: |
622 |
/* CALL_PAL */
|
623 |
if (palcode >= 0x80 && palcode < 0xC0) { |
624 |
/* Unprivileged PAL call */
|
625 |
gen_excp(ctx, EXCP_CALL_PAL + ((palcode & 0x1F) << 6), 0); |
626 |
#if !defined (CONFIG_USER_ONLY)
|
627 |
} else if (palcode < 0x40) { |
628 |
/* Privileged PAL code */
|
629 |
if (ctx->mem_idx & 1) |
630 |
goto invalid_opc;
|
631 |
else
|
632 |
gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x1F) << 6), 0); |
633 |
#endif
|
634 |
} else {
|
635 |
/* Invalid PAL call */
|
636 |
goto invalid_opc;
|
637 |
} |
638 |
ret = 3;
|
639 |
break;
|
640 |
case 0x01: |
641 |
/* OPC01 */
|
642 |
goto invalid_opc;
|
643 |
case 0x02: |
644 |
/* OPC02 */
|
645 |
goto invalid_opc;
|
646 |
case 0x03: |
647 |
/* OPC03 */
|
648 |
goto invalid_opc;
|
649 |
case 0x04: |
650 |
/* OPC04 */
|
651 |
goto invalid_opc;
|
652 |
case 0x05: |
653 |
/* OPC05 */
|
654 |
goto invalid_opc;
|
655 |
case 0x06: |
656 |
/* OPC06 */
|
657 |
goto invalid_opc;
|
658 |
case 0x07: |
659 |
/* OPC07 */
|
660 |
goto invalid_opc;
|
661 |
case 0x08: |
662 |
/* LDA */
|
663 |
if (likely(ra != 31)) { |
664 |
if (rb != 31) |
665 |
tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16); |
666 |
else
|
667 |
tcg_gen_movi_i64(cpu_ir[ra], disp16); |
668 |
} |
669 |
break;
|
670 |
case 0x09: |
671 |
/* LDAH */
|
672 |
if (likely(ra != 31)) { |
673 |
if (rb != 31) |
674 |
tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16 << 16);
|
675 |
else
|
676 |
tcg_gen_movi_i64(cpu_ir[ra], disp16 << 16);
|
677 |
} |
678 |
break;
|
679 |
case 0x0A: |
680 |
/* LDBU */
|
681 |
if (!(ctx->amask & AMASK_BWX))
|
682 |
goto invalid_opc;
|
683 |
gen_load_mem(ctx, &gen_ldbu, ra, rb, disp16, 0);
|
684 |
break;
|
685 |
case 0x0B: |
686 |
/* LDQ_U */
|
687 |
gen_load_mem(ctx, &gen_ldq_u, ra, rb, disp16, 1);
|
688 |
break;
|
689 |
case 0x0C: |
690 |
/* LDWU */
|
691 |
if (!(ctx->amask & AMASK_BWX))
|
692 |
goto invalid_opc;
|
693 |
gen_load_mem(ctx, &gen_ldwu, ra, rb, disp16, 0);
|
694 |
break;
|
695 |
case 0x0D: |
696 |
/* STW */
|
697 |
if (!(ctx->amask & AMASK_BWX))
|
698 |
goto invalid_opc;
|
699 |
gen_store_mem(ctx, &gen_stw, ra, rb, disp16, 0);
|
700 |
break;
|
701 |
case 0x0E: |
702 |
/* STB */
|
703 |
if (!(ctx->amask & AMASK_BWX))
|
704 |
goto invalid_opc;
|
705 |
gen_store_mem(ctx, &gen_stb, ra, rb, disp16, 0);
|
706 |
break;
|
707 |
case 0x0F: |
708 |
/* STQ_U */
|
709 |
gen_store_mem(ctx, &gen_stq_u, ra, rb, disp16, 1);
|
710 |
break;
|
711 |
case 0x10: |
712 |
switch (fn7) {
|
713 |
case 0x00: |
714 |
/* ADDL */
|
715 |
if (likely(rc != 31)) { |
716 |
if (ra != 31) { |
717 |
if (islit) {
|
718 |
tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
719 |
tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
720 |
} else {
|
721 |
tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
722 |
tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
723 |
} |
724 |
} else {
|
725 |
if (islit)
|
726 |
tcg_gen_movi_i64(cpu_ir[rc], lit); |
727 |
else
|
728 |
tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]); |
729 |
} |
730 |
} |
731 |
break;
|
732 |
case 0x02: |
733 |
/* S4ADDL */
|
734 |
if (likely(rc != 31)) { |
735 |
if (ra != 31) { |
736 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64); |
737 |
tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
|
738 |
if (islit)
|
739 |
tcg_gen_addi_i64(tmp, tmp, lit); |
740 |
else
|
741 |
tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]); |
742 |
tcg_gen_ext32s_i64(cpu_ir[rc], tmp); |
743 |
tcg_temp_free(tmp); |
744 |
} else {
|
745 |
if (islit)
|
746 |
tcg_gen_movi_i64(cpu_ir[rc], lit); |
747 |
else
|
748 |
tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]); |
749 |
} |
750 |
} |
751 |
break;
|
752 |
case 0x09: |
753 |
/* SUBL */
|
754 |
if (likely(rc != 31)) { |
755 |
if (ra != 31) { |
756 |
if (islit)
|
757 |
tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
758 |
else
|
759 |
tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
760 |
tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
761 |
} else {
|
762 |
if (islit)
|
763 |
tcg_gen_movi_i64(cpu_ir[rc], -lit); |
764 |
else {
|
765 |
tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
766 |
tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
767 |
} |
768 |
} |
769 |
break;
|
770 |
case 0x0B: |
771 |
/* S4SUBL */
|
772 |
if (likely(rc != 31)) { |
773 |
if (ra != 31) { |
774 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64); |
775 |
tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
|
776 |
if (islit)
|
777 |
tcg_gen_subi_i64(tmp, tmp, lit); |
778 |
else
|
779 |
tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]); |
780 |
tcg_gen_ext32s_i64(cpu_ir[rc], tmp); |
781 |
tcg_temp_free(tmp); |
782 |
} else {
|
783 |
if (islit)
|
784 |
tcg_gen_movi_i64(cpu_ir[rc], -lit); |
785 |
else {
|
786 |
tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
787 |
tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
788 |
} |
789 |
} |
790 |
} |
791 |
break;
|
792 |
case 0x0F: |
793 |
/* CMPBGE */
|
794 |
gen_arith3(ctx, &gen_op_cmpbge, ra, rb, rc, islit, lit); |
795 |
break;
|
796 |
case 0x12: |
797 |
/* S8ADDL */
|
798 |
if (likely(rc != 31)) { |
799 |
if (ra != 31) { |
800 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64); |
801 |
tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
|
802 |
if (islit)
|
803 |
tcg_gen_addi_i64(tmp, tmp, lit); |
804 |
else
|
805 |
tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]); |
806 |
tcg_gen_ext32s_i64(cpu_ir[rc], tmp); |
807 |
tcg_temp_free(tmp); |
808 |
} else {
|
809 |
if (islit)
|
810 |
tcg_gen_movi_i64(cpu_ir[rc], lit); |
811 |
else
|
812 |
tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]); |
813 |
} |
814 |
} |
815 |
break;
|
816 |
case 0x1B: |
817 |
/* S8SUBL */
|
818 |
if (likely(rc != 31)) { |
819 |
if (ra != 31) { |
820 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64); |
821 |
tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
|
822 |
if (islit)
|
823 |
tcg_gen_subi_i64(tmp, tmp, lit); |
824 |
else
|
825 |
tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]); |
826 |
tcg_gen_ext32s_i64(cpu_ir[rc], tmp); |
827 |
tcg_temp_free(tmp); |
828 |
} else {
|
829 |
if (islit)
|
830 |
tcg_gen_movi_i64(cpu_ir[rc], -lit); |
831 |
else
|
832 |
tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
833 |
tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
834 |
} |
835 |
} |
836 |
} |
837 |
break;
|
838 |
case 0x1D: |
839 |
/* CMPULT */
|
840 |
gen_cmp(TCG_COND_LTU, ra, rb, rc, islit, lit); |
841 |
break;
|
842 |
case 0x20: |
843 |
/* ADDQ */
|
844 |
if (likely(rc != 31)) { |
845 |
if (ra != 31) { |
846 |
if (islit)
|
847 |
tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
848 |
else
|
849 |
tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
850 |
} else {
|
851 |
if (islit)
|
852 |
tcg_gen_movi_i64(cpu_ir[rc], lit); |
853 |
else
|
854 |
tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
855 |
} |
856 |
} |
857 |
break;
|
858 |
case 0x22: |
859 |
/* S4ADDQ */
|
860 |
if (likely(rc != 31)) { |
861 |
if (ra != 31) { |
862 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64); |
863 |
tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
|
864 |
if (islit)
|
865 |
tcg_gen_addi_i64(cpu_ir[rc], tmp, lit); |
866 |
else
|
867 |
tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]); |
868 |
tcg_temp_free(tmp); |
869 |
} else {
|
870 |
if (islit)
|
871 |
tcg_gen_movi_i64(cpu_ir[rc], lit); |
872 |
else
|
873 |
tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
874 |
} |
875 |
} |
876 |
break;
|
877 |
case 0x29: |
878 |
/* SUBQ */
|
879 |
if (likely(rc != 31)) { |
880 |
if (ra != 31) { |
881 |
if (islit)
|
882 |
tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
883 |
else
|
884 |
tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
885 |
} else {
|
886 |
if (islit)
|
887 |
tcg_gen_movi_i64(cpu_ir[rc], -lit); |
888 |
else
|
889 |
tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
890 |
} |
891 |
} |
892 |
break;
|
893 |
case 0x2B: |
894 |
/* S4SUBQ */
|
895 |
if (likely(rc != 31)) { |
896 |
if (ra != 31) { |
897 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64); |
898 |
tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
|
899 |
if (islit)
|
900 |
tcg_gen_subi_i64(cpu_ir[rc], tmp, lit); |
901 |
else
|
902 |
tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]); |
903 |
tcg_temp_free(tmp); |
904 |
} else {
|
905 |
if (islit)
|
906 |
tcg_gen_movi_i64(cpu_ir[rc], -lit); |
907 |
else
|
908 |
tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
909 |
} |
910 |
} |
911 |
break;
|
912 |
case 0x2D: |
913 |
/* CMPEQ */
|
914 |
gen_cmp(TCG_COND_EQ, ra, rb, rc, islit, lit); |
915 |
break;
|
916 |
case 0x32: |
917 |
/* S8ADDQ */
|
918 |
if (likely(rc != 31)) { |
919 |
if (ra != 31) { |
920 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64); |
921 |
tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
|
922 |
if (islit)
|
923 |
tcg_gen_addi_i64(cpu_ir[rc], tmp, lit); |
924 |
else
|
925 |
tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]); |
926 |
tcg_temp_free(tmp); |
927 |
} else {
|
928 |
if (islit)
|
929 |
tcg_gen_movi_i64(cpu_ir[rc], lit); |
930 |
else
|
931 |
tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
932 |
} |
933 |
} |
934 |
break;
|
935 |
case 0x3B: |
936 |
/* S8SUBQ */
|
937 |
if (likely(rc != 31)) { |
938 |
if (ra != 31) { |
939 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64); |
940 |
tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
|
941 |
if (islit)
|
942 |
tcg_gen_subi_i64(cpu_ir[rc], tmp, lit); |
943 |
else
|
944 |
tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]); |
945 |
tcg_temp_free(tmp); |
946 |
} else {
|
947 |
if (islit)
|
948 |
tcg_gen_movi_i64(cpu_ir[rc], -lit); |
949 |
else
|
950 |
tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]); |
951 |
} |
952 |
} |
953 |
break;
|
954 |
case 0x3D: |
955 |
/* CMPULE */
|
956 |
gen_cmp(TCG_COND_LEU, ra, rb, rc, islit, lit); |
957 |
break;
|
958 |
case 0x40: |
959 |
/* ADDL/V */
|
960 |
gen_arith3(ctx, &gen_op_addlv, ra, rb, rc, islit, lit); |
961 |
break;
|
962 |
case 0x49: |
963 |
/* SUBL/V */
|
964 |
gen_arith3(ctx, &gen_op_sublv, ra, rb, rc, islit, lit); |
965 |
break;
|
966 |
case 0x4D: |
967 |
/* CMPLT */
|
968 |
gen_cmp(TCG_COND_LT, ra, rb, rc, islit, lit); |
969 |
break;
|
970 |
case 0x60: |
971 |
/* ADDQ/V */
|
972 |
gen_arith3(ctx, &gen_op_addqv, ra, rb, rc, islit, lit); |
973 |
break;
|
974 |
case 0x69: |
975 |
/* SUBQ/V */
|
976 |
gen_arith3(ctx, &gen_op_subqv, ra, rb, rc, islit, lit); |
977 |
break;
|
978 |
case 0x6D: |
979 |
/* CMPLE */
|
980 |
gen_cmp(TCG_COND_LE, ra, rb, rc, islit, lit); |
981 |
break;
|
982 |
default:
|
983 |
goto invalid_opc;
|
984 |
} |
985 |
break;
|
986 |
case 0x11: |
987 |
switch (fn7) {
|
988 |
case 0x00: |
989 |
/* AND */
|
990 |
if (likely(rc != 31)) { |
991 |
if (ra == 31) |
992 |
tcg_gen_movi_i64(cpu_ir[rc], 0);
|
993 |
else if (islit) |
994 |
tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], lit); |
995 |
else
|
996 |
tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
997 |
} |
998 |
break;
|
999 |
case 0x08: |
1000 |
/* BIC */
|
1001 |
if (likely(rc != 31)) { |
1002 |
if (ra != 31) { |
1003 |
if (islit)
|
1004 |
tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], ~lit); |
1005 |
else {
|
1006 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64); |
1007 |
tcg_gen_not_i64(tmp, cpu_ir[rb]); |
1008 |
tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], tmp); |
1009 |
tcg_temp_free(tmp); |
1010 |
} |
1011 |
} else
|
1012 |
tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1013 |
} |
1014 |
break;
|
1015 |
case 0x14: |
1016 |
/* CMOVLBS */
|
1017 |
gen_cmov(ctx, TCG_COND_EQ, ra, rb, rc, islit, lit, 1);
|
1018 |
break;
|
1019 |
case 0x16: |
1020 |
/* CMOVLBC */
|
1021 |
gen_cmov(ctx, TCG_COND_NE, ra, rb, rc, islit, lit, 1);
|
1022 |
break;
|
1023 |
case 0x20: |
1024 |
/* BIS */
|
1025 |
if (likely(rc != 31)) { |
1026 |
if (ra != 31) { |
1027 |
if (islit)
|
1028 |
tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1029 |
else
|
1030 |
tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1031 |
} else {
|
1032 |
if (islit)
|
1033 |
tcg_gen_movi_i64(cpu_ir[rc], lit); |
1034 |
else
|
1035 |
tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
1036 |
} |
1037 |
} |
1038 |
break;
|
1039 |
case 0x24: |
1040 |
/* CMOVEQ */
|
1041 |
gen_cmov(ctx, TCG_COND_NE, ra, rb, rc, islit, lit, 0);
|
1042 |
break;
|
1043 |
case 0x26: |
1044 |
/* CMOVNE */
|
1045 |
gen_cmov(ctx, TCG_COND_EQ, ra, rb, rc, islit, lit, 0);
|
1046 |
break;
|
1047 |
case 0x28: |
1048 |
/* ORNOT */
|
1049 |
if (likely(rc != 31)) { |
1050 |
if (ra != 31) { |
1051 |
if (islit)
|
1052 |
tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], ~lit); |
1053 |
else {
|
1054 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64); |
1055 |
tcg_gen_not_i64(tmp, cpu_ir[rb]); |
1056 |
tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], tmp); |
1057 |
tcg_temp_free(tmp); |
1058 |
} |
1059 |
} else {
|
1060 |
if (islit)
|
1061 |
tcg_gen_movi_i64(cpu_ir[rc], ~lit); |
1062 |
else
|
1063 |
tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]); |
1064 |
} |
1065 |
} |
1066 |
break;
|
1067 |
case 0x40: |
1068 |
/* XOR */
|
1069 |
if (likely(rc != 31)) { |
1070 |
if (ra != 31) { |
1071 |
if (islit)
|
1072 |
tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1073 |
else
|
1074 |
tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1075 |
} else {
|
1076 |
if (islit)
|
1077 |
tcg_gen_movi_i64(cpu_ir[rc], lit); |
1078 |
else
|
1079 |
tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]); |
1080 |
} |
1081 |
} |
1082 |
break;
|
1083 |
case 0x44: |
1084 |
/* CMOVLT */
|
1085 |
gen_cmov(ctx, TCG_COND_GE, ra, rb, rc, islit, lit, 0);
|
1086 |
break;
|
1087 |
case 0x46: |
1088 |
/* CMOVGE */
|
1089 |
gen_cmov(ctx, TCG_COND_LT, ra, rb, rc, islit, lit, 0);
|
1090 |
break;
|
1091 |
case 0x48: |
1092 |
/* EQV */
|
1093 |
if (likely(rc != 31)) { |
1094 |
if (ra != 31) { |
1095 |
if (islit)
|
1096 |
tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], ~lit); |
1097 |
else {
|
1098 |
TCGv tmp = tcg_temp_new(TCG_TYPE_I64); |
1099 |
tcg_gen_not_i64(tmp, cpu_ir[rb]); |
1100 |
tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], tmp); |
1101 |
tcg_temp_free(tmp); |
1102 |
} |
1103 |
} else {
|
1104 |
if (islit)
|
1105 |
tcg_gen_movi_i64(cpu_ir[rc], ~lit); |
1106 |
else
|
1107 |
tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]); |
1108 |
} |
1109 |
} |
1110 |
break;
|
1111 |
case 0x61: |
1112 |
/* AMASK */
|
1113 |
if (likely(rc != 31)) { |
1114 |
if (islit)
|
1115 |
tcg_gen_movi_i64(cpu_ir[rc], helper_amask(lit)); |
1116 |
else
|
1117 |
tcg_gen_helper_1_1(helper_amask, cpu_ir[rc], cpu_ir[rb]); |
1118 |
} |
1119 |
break;
|
1120 |
case 0x64: |
1121 |
/* CMOVLE */
|
1122 |
gen_cmov(ctx, TCG_COND_GT, ra, rb, rc, islit, lit, 0);
|
1123 |
break;
|
1124 |
case 0x66: |
1125 |
/* CMOVGT */
|
1126 |
gen_cmov(ctx, TCG_COND_LE, ra, rb, rc, islit, lit, 0);
|
1127 |
break;
|
1128 |
case 0x6C: |
1129 |
/* IMPLVER */
|
1130 |
if (rc != 31) |
1131 |
tcg_gen_helper_1_0(helper_load_implver, cpu_ir[rc]); |
1132 |
break;
|
1133 |
default:
|
1134 |
goto invalid_opc;
|
1135 |
} |
1136 |
break;
|
1137 |
case 0x12: |
1138 |
switch (fn7) {
|
1139 |
case 0x02: |
1140 |
/* MSKBL */
|
1141 |
gen_byte_manipulation(helper_mskbl, ra, rb, rc, islit, lit); |
1142 |
break;
|
1143 |
case 0x06: |
1144 |
/* EXTBL */
|
1145 |
gen_ext_l(&tcg_gen_ext8u_i64, ra, rb, rc, islit, lit); |
1146 |
break;
|
1147 |
case 0x0B: |
1148 |
/* INSBL */
|
1149 |
gen_byte_manipulation(helper_insbl, ra, rb, rc, islit, lit); |
1150 |
break;
|
1151 |
case 0x12: |
1152 |
/* MSKWL */
|
1153 |
gen_byte_manipulation(helper_mskwl, ra, rb, rc, islit, lit); |
1154 |
break;
|
1155 |
case 0x16: |
1156 |
/* EXTWL */
|
1157 |
gen_ext_l(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit); |
1158 |
break;
|
1159 |
case 0x1B: |
1160 |
/* INSWL */
|
1161 |
gen_byte_manipulation(helper_inswl, ra, rb, rc, islit, lit); |
1162 |
break;
|
1163 |
case 0x22: |
1164 |
/* MSKLL */
|
1165 |
gen_byte_manipulation(helper_mskll, ra, rb, rc, islit, lit); |
1166 |
break;
|
1167 |
case 0x26: |
1168 |
/* EXTLL */
|
1169 |
gen_ext_l(&tcg_gen_ext32u_i64, ra, rb, rc, islit, lit); |
1170 |
break;
|
1171 |
case 0x2B: |
1172 |
/* INSLL */
|
1173 |
gen_byte_manipulation(helper_insll, ra, rb, rc, islit, lit); |
1174 |
break;
|
1175 |
case 0x30: |
1176 |
/* ZAP */
|
1177 |
gen_byte_manipulation(helper_zap, ra, rb, rc, islit, lit); |
1178 |
break;
|
1179 |
case 0x31: |
1180 |
/* ZAPNOT */
|
1181 |
gen_byte_manipulation(helper_zapnot, ra, rb, rc, islit, lit); |
1182 |
break;
|
1183 |
case 0x32: |
1184 |
/* MSKQL */
|
1185 |
gen_byte_manipulation(helper_mskql, ra, rb, rc, islit, lit); |
1186 |
break;
|
1187 |
case 0x34: |
1188 |
/* SRL */
|
1189 |
if (likely(rc != 31)) { |
1190 |
if (ra != 31) { |
1191 |
if (islit)
|
1192 |
tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
|
1193 |
else {
|
1194 |
TCGv shift = tcg_temp_new(TCG_TYPE_I64); |
1195 |
tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
|
1196 |
tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], shift); |
1197 |
tcg_temp_free(shift); |
1198 |
} |
1199 |
} else
|
1200 |
tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1201 |
} |
1202 |
break;
|
1203 |
case 0x36: |
1204 |
/* EXTQL */
|
1205 |
gen_ext_l(NULL, ra, rb, rc, islit, lit);
|
1206 |
break;
|
1207 |
case 0x39: |
1208 |
/* SLL */
|
1209 |
if (likely(rc != 31)) { |
1210 |
if (ra != 31) { |
1211 |
if (islit)
|
1212 |
tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
|
1213 |
else {
|
1214 |
TCGv shift = tcg_temp_new(TCG_TYPE_I64); |
1215 |
tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
|
1216 |
tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], shift); |
1217 |
tcg_temp_free(shift); |
1218 |
} |
1219 |
} else
|
1220 |
tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1221 |
} |
1222 |
break;
|
1223 |
case 0x3B: |
1224 |
/* INSQL */
|
1225 |
gen_byte_manipulation(helper_insql, ra, rb, rc, islit, lit); |
1226 |
break;
|
1227 |
case 0x3C: |
1228 |
/* SRA */
|
1229 |
if (likely(rc != 31)) { |
1230 |
if (ra != 31) { |
1231 |
if (islit)
|
1232 |
tcg_gen_sari_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
|
1233 |
else {
|
1234 |
TCGv shift = tcg_temp_new(TCG_TYPE_I64); |
1235 |
tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
|
1236 |
tcg_gen_sar_i64(cpu_ir[rc], cpu_ir[ra], shift); |
1237 |
tcg_temp_free(shift); |
1238 |
} |
1239 |
} else
|
1240 |
tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1241 |
} |
1242 |
break;
|
1243 |
case 0x52: |
1244 |
/* MSKWH */
|
1245 |
gen_byte_manipulation(helper_mskwh, ra, rb, rc, islit, lit); |
1246 |
break;
|
1247 |
case 0x57: |
1248 |
/* INSWH */
|
1249 |
gen_byte_manipulation(helper_inswh, ra, rb, rc, islit, lit); |
1250 |
break;
|
1251 |
case 0x5A: |
1252 |
/* EXTWH */
|
1253 |
gen_ext_h(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit); |
1254 |
break;
|
1255 |
case 0x62: |
1256 |
/* MSKLH */
|
1257 |
gen_byte_manipulation(helper_msklh, ra, rb, rc, islit, lit); |
1258 |
break;
|
1259 |
case 0x67: |
1260 |
/* INSLH */
|
1261 |
gen_byte_manipulation(helper_inslh, ra, rb, rc, islit, lit); |
1262 |
break;
|
1263 |
case 0x6A: |
1264 |
/* EXTLH */
|
1265 |
gen_ext_h(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit); |
1266 |
break;
|
1267 |
case 0x72: |
1268 |
/* MSKQH */
|
1269 |
gen_byte_manipulation(helper_mskqh, ra, rb, rc, islit, lit); |
1270 |
break;
|
1271 |
case 0x77: |
1272 |
/* INSQH */
|
1273 |
gen_byte_manipulation(helper_insqh, ra, rb, rc, islit, lit); |
1274 |
break;
|
1275 |
case 0x7A: |
1276 |
/* EXTQH */
|
1277 |
gen_ext_h(NULL, ra, rb, rc, islit, lit);
|
1278 |
break;
|
1279 |
default:
|
1280 |
goto invalid_opc;
|
1281 |
} |
1282 |
break;
|
1283 |
case 0x13: |
1284 |
switch (fn7) {
|
1285 |
case 0x00: |
1286 |
/* MULL */
|
1287 |
if (likely(rc != 31)) { |
1288 |
if (ra == 31) |
1289 |
tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1290 |
else {
|
1291 |
if (islit)
|
1292 |
tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1293 |
else
|
1294 |
tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1295 |
tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]); |
1296 |
} |
1297 |
} |
1298 |
break;
|
1299 |
case 0x20: |
1300 |
/* MULQ */
|
1301 |
if (likely(rc != 31)) { |
1302 |
if (ra == 31) |
1303 |
tcg_gen_movi_i64(cpu_ir[rc], 0);
|
1304 |
else if (islit) |
1305 |
tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit); |
1306 |
else
|
1307 |
tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); |
1308 |
} |
1309 |
break;
|
1310 |
case 0x30: |
1311 |
/* UMULH */
|
1312 |
gen_arith3(ctx, &gen_op_umulh, ra, rb, rc, islit, lit); |
1313 |
break;
|
1314 |
case 0x40: |
1315 |
/* MULL/V */
|
1316 |
gen_arith3(ctx, &gen_op_mullv, ra, rb, rc, islit, lit); |
1317 |
break;
|
1318 |
case 0x60: |
1319 |
/* MULQ/V */
|
1320 |
gen_arith3(ctx, &gen_op_mulqv, ra, rb, rc, islit, lit); |
1321 |
break;
|
1322 |
default:
|
1323 |
goto invalid_opc;
|
1324 |
} |
1325 |
break;
|
1326 |
case 0x14: |
1327 |
switch (fpfn) { /* f11 & 0x3F */ |
1328 |
case 0x04: |
1329 |
/* ITOFS */
|
1330 |
if (!(ctx->amask & AMASK_FIX))
|
1331 |
goto invalid_opc;
|
1332 |
gen_itf(ctx, &gen_op_itofs, ra, rc); |
1333 |
break;
|
1334 |
case 0x0A: |
1335 |
/* SQRTF */
|
1336 |
if (!(ctx->amask & AMASK_FIX))
|
1337 |
goto invalid_opc;
|
1338 |
gen_farith2(ctx, &gen_op_sqrtf, rb, rc); |
1339 |
break;
|
1340 |
case 0x0B: |
1341 |
/* SQRTS */
|
1342 |
if (!(ctx->amask & AMASK_FIX))
|
1343 |
goto invalid_opc;
|
1344 |
gen_farith2(ctx, &gen_op_sqrts, rb, rc); |
1345 |
break;
|
1346 |
case 0x14: |
1347 |
/* ITOFF */
|
1348 |
if (!(ctx->amask & AMASK_FIX))
|
1349 |
goto invalid_opc;
|
1350 |
#if 0 // TODO
|
1351 |
gen_itf(ctx, &gen_op_itoff, ra, rc);
|
1352 |
#else
|
1353 |
goto invalid_opc;
|
1354 |
#endif
|
1355 |
break;
|
1356 |
case 0x24: |
1357 |
/* ITOFT */
|
1358 |
if (!(ctx->amask & AMASK_FIX))
|
1359 |
goto invalid_opc;
|
1360 |
gen_itf(ctx, &gen_op_itoft, ra, rc); |
1361 |
break;
|
1362 |
case 0x2A: |
1363 |
/* SQRTG */
|
1364 |
if (!(ctx->amask & AMASK_FIX))
|
1365 |
goto invalid_opc;
|
1366 |
gen_farith2(ctx, &gen_op_sqrtg, rb, rc); |
1367 |
break;
|
1368 |
case 0x02B: |
1369 |
/* SQRTT */
|
1370 |
if (!(ctx->amask & AMASK_FIX))
|
1371 |
goto invalid_opc;
|
1372 |
gen_farith2(ctx, &gen_op_sqrtt, rb, rc); |
1373 |
break;
|
1374 |
default:
|
1375 |
goto invalid_opc;
|
1376 |
} |
1377 |
break;
|
1378 |
case 0x15: |
1379 |
/* VAX floating point */
|
1380 |
/* XXX: rounding mode and trap are ignored (!) */
|
1381 |
switch (fpfn) { /* f11 & 0x3F */ |
1382 |
case 0x00: |
1383 |
/* ADDF */
|
1384 |
gen_farith3(ctx, &gen_op_addf, ra, rb, rc); |
1385 |
break;
|
1386 |
case 0x01: |
1387 |
/* SUBF */
|
1388 |
gen_farith3(ctx, &gen_op_subf, ra, rb, rc); |
1389 |
break;
|
1390 |
case 0x02: |
1391 |
/* MULF */
|
1392 |
gen_farith3(ctx, &gen_op_mulf, ra, rb, rc); |
1393 |
break;
|
1394 |
case 0x03: |
1395 |
/* DIVF */
|
1396 |
gen_farith3(ctx, &gen_op_divf, ra, rb, rc); |
1397 |
break;
|
1398 |
case 0x1E: |
1399 |
/* CVTDG */
|
1400 |
#if 0 // TODO
|
1401 |
gen_farith2(ctx, &gen_op_cvtdg, rb, rc);
|
1402 |
#else
|
1403 |
goto invalid_opc;
|
1404 |
#endif
|
1405 |
break;
|
1406 |
case 0x20: |
1407 |
/* ADDG */
|
1408 |
gen_farith3(ctx, &gen_op_addg, ra, rb, rc); |
1409 |
break;
|
1410 |
case 0x21: |
1411 |
/* SUBG */
|
1412 |
gen_farith3(ctx, &gen_op_subg, ra, rb, rc); |
1413 |
break;
|
1414 |
case 0x22: |
1415 |
/* MULG */
|
1416 |
gen_farith3(ctx, &gen_op_mulg, ra, rb, rc); |
1417 |
break;
|
1418 |
case 0x23: |
1419 |
/* DIVG */
|
1420 |
gen_farith3(ctx, &gen_op_divg, ra, rb, rc); |
1421 |
break;
|
1422 |
case 0x25: |
1423 |
/* CMPGEQ */
|
1424 |
gen_farith3(ctx, &gen_op_cmpgeq, ra, rb, rc); |
1425 |
break;
|
1426 |
case 0x26: |
1427 |
/* CMPGLT */
|
1428 |
gen_farith3(ctx, &gen_op_cmpglt, ra, rb, rc); |
1429 |
break;
|
1430 |
case 0x27: |
1431 |
/* CMPGLE */
|
1432 |
gen_farith3(ctx, &gen_op_cmpgle, ra, rb, rc); |
1433 |
break;
|
1434 |
case 0x2C: |
1435 |
/* CVTGF */
|
1436 |
gen_farith2(ctx, &gen_op_cvtgf, rb, rc); |
1437 |
break;
|
1438 |
case 0x2D: |
1439 |
/* CVTGD */
|
1440 |
#if 0 // TODO
|
1441 |
gen_farith2(ctx, &gen_op_cvtgd, rb, rc);
|
1442 |
#else
|
1443 |
goto invalid_opc;
|
1444 |
#endif
|
1445 |
break;
|
1446 |
case 0x2F: |
1447 |
/* CVTGQ */
|
1448 |
gen_farith2(ctx, &gen_op_cvtgq, rb, rc); |
1449 |
break;
|
1450 |
case 0x3C: |
1451 |
/* CVTQF */
|
1452 |
gen_farith2(ctx, &gen_op_cvtqf, rb, rc); |
1453 |
break;
|
1454 |
case 0x3E: |
1455 |
/* CVTQG */
|
1456 |
gen_farith2(ctx, &gen_op_cvtqg, rb, rc); |
1457 |
break;
|
1458 |
default:
|
1459 |
goto invalid_opc;
|
1460 |
} |
1461 |
break;
|
1462 |
case 0x16: |
1463 |
/* IEEE floating-point */
|
1464 |
/* XXX: rounding mode and traps are ignored (!) */
|
1465 |
switch (fpfn) { /* f11 & 0x3F */ |
1466 |
case 0x00: |
1467 |
/* ADDS */
|
1468 |
gen_farith3(ctx, &gen_op_adds, ra, rb, rc); |
1469 |
break;
|
1470 |
case 0x01: |
1471 |
/* SUBS */
|
1472 |
gen_farith3(ctx, &gen_op_subs, ra, rb, rc); |
1473 |
break;
|
1474 |
case 0x02: |
1475 |
/* MULS */
|
1476 |
gen_farith3(ctx, &gen_op_muls, ra, rb, rc); |
1477 |
break;
|
1478 |
case 0x03: |
1479 |
/* DIVS */
|
1480 |
gen_farith3(ctx, &gen_op_divs, ra, rb, rc); |
1481 |
break;
|
1482 |
case 0x20: |
1483 |
/* ADDT */
|
1484 |
gen_farith3(ctx, &gen_op_addt, ra, rb, rc); |
1485 |
break;
|
1486 |
case 0x21: |
1487 |
/* SUBT */
|
1488 |
gen_farith3(ctx, &gen_op_subt, ra, rb, rc); |
1489 |
break;
|
1490 |
case 0x22: |
1491 |
/* MULT */
|
1492 |
gen_farith3(ctx, &gen_op_mult, ra, rb, rc); |
1493 |
break;
|
1494 |
case 0x23: |
1495 |
/* DIVT */
|
1496 |
gen_farith3(ctx, &gen_op_divt, ra, rb, rc); |
1497 |
break;
|
1498 |
case 0x24: |
1499 |
/* CMPTUN */
|
1500 |
gen_farith3(ctx, &gen_op_cmptun, ra, rb, rc); |
1501 |
break;
|
1502 |
case 0x25: |
1503 |
/* CMPTEQ */
|
1504 |
gen_farith3(ctx, &gen_op_cmpteq, ra, rb, rc); |
1505 |
break;
|
1506 |
case 0x26: |
1507 |
/* CMPTLT */
|
1508 |
gen_farith3(ctx, &gen_op_cmptlt, ra, rb, rc); |
1509 |
break;
|
1510 |
case 0x27: |
1511 |
/* CMPTLE */
|
1512 |
gen_farith3(ctx, &gen_op_cmptle, ra, rb, rc); |
1513 |
break;
|
1514 |
case 0x2C: |
1515 |
/* XXX: incorrect */
|
1516 |
if (fn11 == 0x2AC) { |
1517 |
/* CVTST */
|
1518 |
gen_farith2(ctx, &gen_op_cvtst, rb, rc); |
1519 |
} else {
|
1520 |
/* CVTTS */
|
1521 |
gen_farith2(ctx, &gen_op_cvtts, rb, rc); |
1522 |
} |
1523 |
break;
|
1524 |
case 0x2F: |
1525 |
/* CVTTQ */
|
1526 |
gen_farith2(ctx, &gen_op_cvttq, rb, rc); |
1527 |
break;
|
1528 |
case 0x3C: |
1529 |
/* CVTQS */
|
1530 |
gen_farith2(ctx, &gen_op_cvtqs, rb, rc); |
1531 |
break;
|
1532 |
case 0x3E: |
1533 |
/* CVTQT */
|
1534 |
gen_farith2(ctx, &gen_op_cvtqt, rb, rc); |
1535 |
break;
|
1536 |
default:
|
1537 |
goto invalid_opc;
|
1538 |
} |
1539 |
break;
|
1540 |
case 0x17: |
1541 |
switch (fn11) {
|
1542 |
case 0x010: |
1543 |
/* CVTLQ */
|
1544 |
gen_farith2(ctx, &gen_op_cvtlq, rb, rc); |
1545 |
break;
|
1546 |
case 0x020: |
1547 |
/* CPYS */
|
1548 |
if (ra == rb) {
|
1549 |
if (ra == 31 && rc == 31) { |
1550 |
/* FNOP */
|
1551 |
gen_op_nop(); |
1552 |
} else {
|
1553 |
/* FMOV */
|
1554 |
gen_load_fir(ctx, rb, 0);
|
1555 |
gen_store_fir(ctx, rc, 0);
|
1556 |
} |
1557 |
} else {
|
1558 |
gen_farith3(ctx, &gen_op_cpys, ra, rb, rc); |
1559 |
} |
1560 |
break;
|
1561 |
case 0x021: |
1562 |
/* CPYSN */
|
1563 |
gen_farith2(ctx, &gen_op_cpysn, rb, rc); |
1564 |
break;
|
1565 |
case 0x022: |
1566 |
/* CPYSE */
|
1567 |
gen_farith2(ctx, &gen_op_cpyse, rb, rc); |
1568 |
break;
|
1569 |
case 0x024: |
1570 |
/* MT_FPCR */
|
1571 |
gen_load_fir(ctx, ra, 0);
|
1572 |
gen_op_store_fpcr(); |
1573 |
break;
|
1574 |
case 0x025: |
1575 |
/* MF_FPCR */
|
1576 |
gen_op_load_fpcr(); |
1577 |
gen_store_fir(ctx, ra, 0);
|
1578 |
break;
|
1579 |
case 0x02A: |
1580 |
/* FCMOVEQ */
|
1581 |
gen_fcmov(ctx, &gen_op_cmpfeq, ra, rb, rc); |
1582 |
break;
|
1583 |
case 0x02B: |
1584 |
/* FCMOVNE */
|
1585 |
gen_fcmov(ctx, &gen_op_cmpfne, ra, rb, rc); |
1586 |
break;
|
1587 |
case 0x02C: |
1588 |
/* FCMOVLT */
|
1589 |
gen_fcmov(ctx, &gen_op_cmpflt, ra, rb, rc); |
1590 |
break;
|
1591 |
case 0x02D: |
1592 |
/* FCMOVGE */
|
1593 |
gen_fcmov(ctx, &gen_op_cmpfge, ra, rb, rc); |
1594 |
break;
|
1595 |
case 0x02E: |
1596 |
/* FCMOVLE */
|
1597 |
gen_fcmov(ctx, &gen_op_cmpfle, ra, rb, rc); |
1598 |
break;
|
1599 |
case 0x02F: |
1600 |
/* FCMOVGT */
|
1601 |
gen_fcmov(ctx, &gen_op_cmpfgt, ra, rb, rc); |
1602 |
break;
|
1603 |
case 0x030: |
1604 |
/* CVTQL */
|
1605 |
gen_farith2(ctx, &gen_op_cvtql, rb, rc); |
1606 |
break;
|
1607 |
case 0x130: |
1608 |
/* CVTQL/V */
|
1609 |
gen_farith2(ctx, &gen_op_cvtqlv, rb, rc); |
1610 |
break;
|
1611 |
case 0x530: |
1612 |
/* CVTQL/SV */
|
1613 |
gen_farith2(ctx, &gen_op_cvtqlsv, rb, rc); |
1614 |
break;
|
1615 |
default:
|
1616 |
goto invalid_opc;
|
1617 |
} |
1618 |
break;
|
1619 |
case 0x18: |
1620 |
switch ((uint16_t)disp16) {
|
1621 |
case 0x0000: |
1622 |
/* TRAPB */
|
1623 |
/* No-op. Just exit from the current tb */
|
1624 |
ret = 2;
|
1625 |
break;
|
1626 |
case 0x0400: |
1627 |
/* EXCB */
|
1628 |
/* No-op. Just exit from the current tb */
|
1629 |
ret = 2;
|
1630 |
break;
|
1631 |
case 0x4000: |
1632 |
/* MB */
|
1633 |
/* No-op */
|
1634 |
break;
|
1635 |
case 0x4400: |
1636 |
/* WMB */
|
1637 |
/* No-op */
|
1638 |
break;
|
1639 |
case 0x8000: |
1640 |
/* FETCH */
|
1641 |
/* No-op */
|
1642 |
break;
|
1643 |
case 0xA000: |
1644 |
/* FETCH_M */
|
1645 |
/* No-op */
|
1646 |
break;
|
1647 |
case 0xC000: |
1648 |
/* RPCC */
|
1649 |
if (ra != 31) |
1650 |
tcg_gen_helper_1_0(helper_load_pcc, cpu_ir[ra]); |
1651 |
break;
|
1652 |
case 0xE000: |
1653 |
/* RC */
|
1654 |
if (ra != 31) |
1655 |
tcg_gen_helper_1_0(helper_rc, cpu_ir[ra]); |
1656 |
break;
|
1657 |
case 0xE800: |
1658 |
/* ECB */
|
1659 |
/* XXX: TODO: evict tb cache at address rb */
|
1660 |
#if 0
|
1661 |
ret = 2;
|
1662 |
#else
|
1663 |
goto invalid_opc;
|
1664 |
#endif
|
1665 |
break;
|
1666 |
case 0xF000: |
1667 |
/* RS */
|
1668 |
if (ra != 31) |
1669 |
tcg_gen_helper_1_0(helper_rs, cpu_ir[ra]); |
1670 |
break;
|
1671 |
case 0xF800: |
1672 |
/* WH64 */
|
1673 |
/* No-op */
|
1674 |
break;
|
1675 |
default:
|
1676 |
goto invalid_opc;
|
1677 |
} |
1678 |
break;
|
1679 |
case 0x19: |
1680 |
/* HW_MFPR (PALcode) */
|
1681 |
#if defined (CONFIG_USER_ONLY)
|
1682 |
goto invalid_opc;
|
1683 |
#else
|
1684 |
if (!ctx->pal_mode)
|
1685 |
goto invalid_opc;
|
1686 |
gen_op_mfpr(insn & 0xFF);
|
1687 |
if (ra != 31) |
1688 |
tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
|
1689 |
break;
|
1690 |
#endif
|
1691 |
case 0x1A: |
1692 |
if (ra != 31) |
1693 |
tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); |
1694 |
if (rb != 31) |
1695 |
tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3);
|
1696 |
else
|
1697 |
tcg_gen_movi_i64(cpu_pc, 0);
|
1698 |
/* Those four jumps only differ by the branch prediction hint */
|
1699 |
switch (fn2) {
|
1700 |
case 0x0: |
1701 |
/* JMP */
|
1702 |
break;
|
1703 |
case 0x1: |
1704 |
/* JSR */
|
1705 |
break;
|
1706 |
case 0x2: |
1707 |
/* RET */
|
1708 |
break;
|
1709 |
case 0x3: |
1710 |
/* JSR_COROUTINE */
|
1711 |
break;
|
1712 |
} |
1713 |
ret = 1;
|
1714 |
break;
|
1715 |
case 0x1B: |
1716 |
/* HW_LD (PALcode) */
|
1717 |
#if defined (CONFIG_USER_ONLY)
|
1718 |
goto invalid_opc;
|
1719 |
#else
|
1720 |
if (!ctx->pal_mode)
|
1721 |
goto invalid_opc;
|
1722 |
if (rb != 31) |
1723 |
tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
|
1724 |
else
|
1725 |
tcg_gen_movi_i64(cpu_T[0], 0); |
1726 |
tcg_gen_movi_i64(cpu_T[1], disp12);
|
1727 |
tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
1728 |
switch ((insn >> 12) & 0xF) { |
1729 |
case 0x0: |
1730 |
/* Longword physical access */
|
1731 |
gen_op_ldl_raw(); |
1732 |
break;
|
1733 |
case 0x1: |
1734 |
/* Quadword physical access */
|
1735 |
gen_op_ldq_raw(); |
1736 |
break;
|
1737 |
case 0x2: |
1738 |
/* Longword physical access with lock */
|
1739 |
gen_op_ldl_l_raw(); |
1740 |
break;
|
1741 |
case 0x3: |
1742 |
/* Quadword physical access with lock */
|
1743 |
gen_op_ldq_l_raw(); |
1744 |
break;
|
1745 |
case 0x4: |
1746 |
/* Longword virtual PTE fetch */
|
1747 |
gen_op_ldl_kernel(); |
1748 |
break;
|
1749 |
case 0x5: |
1750 |
/* Quadword virtual PTE fetch */
|
1751 |
gen_op_ldq_kernel(); |
1752 |
break;
|
1753 |
case 0x6: |
1754 |
/* Invalid */
|
1755 |
goto invalid_opc;
|
1756 |
case 0x7: |
1757 |
/* Invalid */
|
1758 |
goto invalid_opc;
|
1759 |
case 0x8: |
1760 |
/* Longword virtual access */
|
1761 |
gen_op_ld_phys_to_virt(); |
1762 |
gen_op_ldl_raw(); |
1763 |
break;
|
1764 |
case 0x9: |
1765 |
/* Quadword virtual access */
|
1766 |
gen_op_ld_phys_to_virt(); |
1767 |
gen_op_ldq_raw(); |
1768 |
break;
|
1769 |
case 0xA: |
1770 |
/* Longword virtual access with protection check */
|
1771 |
gen_ldl(ctx); |
1772 |
break;
|
1773 |
case 0xB: |
1774 |
/* Quadword virtual access with protection check */
|
1775 |
gen_ldq(ctx); |
1776 |
break;
|
1777 |
case 0xC: |
1778 |
/* Longword virtual access with altenate access mode */
|
1779 |
gen_op_set_alt_mode(); |
1780 |
gen_op_ld_phys_to_virt(); |
1781 |
gen_op_ldl_raw(); |
1782 |
gen_op_restore_mode(); |
1783 |
break;
|
1784 |
case 0xD: |
1785 |
/* Quadword virtual access with altenate access mode */
|
1786 |
gen_op_set_alt_mode(); |
1787 |
gen_op_ld_phys_to_virt(); |
1788 |
gen_op_ldq_raw(); |
1789 |
gen_op_restore_mode(); |
1790 |
break;
|
1791 |
case 0xE: |
1792 |
/* Longword virtual access with alternate access mode and
|
1793 |
* protection checks
|
1794 |
*/
|
1795 |
gen_op_set_alt_mode(); |
1796 |
gen_op_ldl_data(); |
1797 |
gen_op_restore_mode(); |
1798 |
break;
|
1799 |
case 0xF: |
1800 |
/* Quadword virtual access with alternate access mode and
|
1801 |
* protection checks
|
1802 |
*/
|
1803 |
gen_op_set_alt_mode(); |
1804 |
gen_op_ldq_data(); |
1805 |
gen_op_restore_mode(); |
1806 |
break;
|
1807 |
} |
1808 |
if (ra != 31) |
1809 |
tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]);
|
1810 |
break;
|
1811 |
#endif
|
1812 |
case 0x1C: |
1813 |
switch (fn7) {
|
1814 |
case 0x00: |
1815 |
/* SEXTB */
|
1816 |
if (!(ctx->amask & AMASK_BWX))
|
1817 |
goto invalid_opc;
|
1818 |
if (likely(rc != 31)) { |
1819 |
if (islit)
|
1820 |
tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int8_t)lit)); |
1821 |
else
|
1822 |
tcg_gen_ext8s_i64(cpu_ir[rc], cpu_ir[rb]); |
1823 |
} |
1824 |
break;
|
1825 |
case 0x01: |
1826 |
/* SEXTW */
|
1827 |
if (!(ctx->amask & AMASK_BWX))
|
1828 |
goto invalid_opc;
|
1829 |
if (likely(rc != 31)) { |
1830 |
if (islit)
|
1831 |
tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int16_t)lit)); |
1832 |
else
|
1833 |
tcg_gen_ext16s_i64(cpu_ir[rc], cpu_ir[rb]); |
1834 |
} |
1835 |
break;
|
1836 |
case 0x30: |
1837 |
/* CTPOP */
|
1838 |
if (!(ctx->amask & AMASK_CIX))
|
1839 |
goto invalid_opc;
|
1840 |
if (likely(rc != 31)) { |
1841 |
if (islit)
|
1842 |
tcg_gen_movi_i64(cpu_ir[rc], ctpop64(lit)); |
1843 |
else
|
1844 |
tcg_gen_helper_1_1(helper_ctpop, cpu_ir[rc], cpu_ir[rb]); |
1845 |
} |
1846 |
break;
|
1847 |
case 0x31: |
1848 |
/* PERR */
|
1849 |
if (!(ctx->amask & AMASK_MVI))
|
1850 |
goto invalid_opc;
|
1851 |
/* XXX: TODO */
|
1852 |
goto invalid_opc;
|
1853 |
break;
|
1854 |
case 0x32: |
1855 |
/* CTLZ */
|
1856 |
if (!(ctx->amask & AMASK_CIX))
|
1857 |
goto invalid_opc;
|
1858 |
if (likely(rc != 31)) { |
1859 |
if (islit)
|
1860 |
tcg_gen_movi_i64(cpu_ir[rc], clz64(lit)); |
1861 |
else
|
1862 |
tcg_gen_helper_1_1(helper_ctlz, cpu_ir[rc], cpu_ir[rb]); |
1863 |
} |
1864 |
break;
|
1865 |
case 0x33: |
1866 |
/* CTTZ */
|
1867 |
if (!(ctx->amask & AMASK_CIX))
|
1868 |
goto invalid_opc;
|
1869 |
if (likely(rc != 31)) { |
1870 |
if (islit)
|
1871 |
tcg_gen_movi_i64(cpu_ir[rc], ctz64(lit)); |
1872 |
else
|
1873 |
tcg_gen_helper_1_1(helper_cttz, cpu_ir[rc], cpu_ir[rb]); |
1874 |
} |
1875 |
break;
|
1876 |
case 0x34: |
1877 |
/* UNPKBW */
|
1878 |
if (!(ctx->amask & AMASK_MVI))
|
1879 |
goto invalid_opc;
|
1880 |
/* XXX: TODO */
|
1881 |
goto invalid_opc;
|
1882 |
break;
|
1883 |
case 0x35: |
1884 |
/* UNPKWL */
|
1885 |
if (!(ctx->amask & AMASK_MVI))
|
1886 |
goto invalid_opc;
|
1887 |
/* XXX: TODO */
|
1888 |
goto invalid_opc;
|
1889 |
break;
|
1890 |
case 0x36: |
1891 |
/* PKWB */
|
1892 |
if (!(ctx->amask & AMASK_MVI))
|
1893 |
goto invalid_opc;
|
1894 |
/* XXX: TODO */
|
1895 |
goto invalid_opc;
|
1896 |
break;
|
1897 |
case 0x37: |
1898 |
/* PKLB */
|
1899 |
if (!(ctx->amask & AMASK_MVI))
|
1900 |
goto invalid_opc;
|
1901 |
/* XXX: TODO */
|
1902 |
goto invalid_opc;
|
1903 |
break;
|
1904 |
case 0x38: |
1905 |
/* MINSB8 */
|
1906 |
if (!(ctx->amask & AMASK_MVI))
|
1907 |
goto invalid_opc;
|
1908 |
/* XXX: TODO */
|
1909 |
goto invalid_opc;
|
1910 |
break;
|
1911 |
case 0x39: |
1912 |
/* MINSW4 */
|
1913 |
if (!(ctx->amask & AMASK_MVI))
|
1914 |
goto invalid_opc;
|
1915 |
/* XXX: TODO */
|
1916 |
goto invalid_opc;
|
1917 |
break;
|
1918 |
case 0x3A: |
1919 |
/* MINUB8 */
|
1920 |
if (!(ctx->amask & AMASK_MVI))
|
1921 |
goto invalid_opc;
|
1922 |
/* XXX: TODO */
|
1923 |
goto invalid_opc;
|
1924 |
break;
|
1925 |
case 0x3B: |
1926 |
/* MINUW4 */
|
1927 |
if (!(ctx->amask & AMASK_MVI))
|
1928 |
goto invalid_opc;
|
1929 |
/* XXX: TODO */
|
1930 |
goto invalid_opc;
|
1931 |
break;
|
1932 |
case 0x3C: |
1933 |
/* MAXUB8 */
|
1934 |
if (!(ctx->amask & AMASK_MVI))
|
1935 |
goto invalid_opc;
|
1936 |
/* XXX: TODO */
|
1937 |
goto invalid_opc;
|
1938 |
break;
|
1939 |
case 0x3D: |
1940 |
/* MAXUW4 */
|
1941 |
if (!(ctx->amask & AMASK_MVI))
|
1942 |
goto invalid_opc;
|
1943 |
/* XXX: TODO */
|
1944 |
goto invalid_opc;
|
1945 |
break;
|
1946 |
case 0x3E: |
1947 |
/* MAXSB8 */
|
1948 |
if (!(ctx->amask & AMASK_MVI))
|
1949 |
goto invalid_opc;
|
1950 |
/* XXX: TODO */
|
1951 |
goto invalid_opc;
|
1952 |
break;
|
1953 |
case 0x3F: |
1954 |
/* MAXSW4 */
|
1955 |
if (!(ctx->amask & AMASK_MVI))
|
1956 |
goto invalid_opc;
|
1957 |
/* XXX: TODO */
|
1958 |
goto invalid_opc;
|
1959 |
break;
|
1960 |
case 0x70: |
1961 |
/* FTOIT */
|
1962 |
if (!(ctx->amask & AMASK_FIX))
|
1963 |
goto invalid_opc;
|
1964 |
gen_fti(ctx, &gen_op_ftoit, ra, rb); |
1965 |
break;
|
1966 |
case 0x78: |
1967 |
/* FTOIS */
|
1968 |
if (!(ctx->amask & AMASK_FIX))
|
1969 |
goto invalid_opc;
|
1970 |
gen_fti(ctx, &gen_op_ftois, ra, rb); |
1971 |
break;
|
1972 |
default:
|
1973 |
goto invalid_opc;
|
1974 |
} |
1975 |
break;
|
1976 |
case 0x1D: |
1977 |
/* HW_MTPR (PALcode) */
|
1978 |
#if defined (CONFIG_USER_ONLY)
|
1979 |
goto invalid_opc;
|
1980 |
#else
|
1981 |
if (!ctx->pal_mode)
|
1982 |
goto invalid_opc;
|
1983 |
if (ra != 31) |
1984 |
tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
|
1985 |
else
|
1986 |
tcg_gen_movi_i64(cpu_T[0], 0); |
1987 |
gen_op_mtpr(insn & 0xFF);
|
1988 |
ret = 2;
|
1989 |
break;
|
1990 |
#endif
|
1991 |
case 0x1E: |
1992 |
/* HW_REI (PALcode) */
|
1993 |
#if defined (CONFIG_USER_ONLY)
|
1994 |
goto invalid_opc;
|
1995 |
#else
|
1996 |
if (!ctx->pal_mode)
|
1997 |
goto invalid_opc;
|
1998 |
if (rb == 31) { |
1999 |
/* "Old" alpha */
|
2000 |
gen_op_hw_rei(); |
2001 |
} else {
|
2002 |
if (ra != 31) |
2003 |
tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
|
2004 |
else
|
2005 |
tcg_gen_movi_i64(cpu_T[0], 0); |
2006 |
tcg_gen_movi_i64(cpu_T[1], (((int64_t)insn << 51) >> 51)); |
2007 |
tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]); |
2008 |
gen_op_hw_ret(); |
2009 |
} |
2010 |
ret = 2;
|
2011 |
break;
|
2012 |
#endif
|
2013 |
case 0x1F: |
2014 |
/* HW_ST (PALcode) */
|
2015 |
#if defined (CONFIG_USER_ONLY)
|
2016 |
goto invalid_opc;
|
2017 |
#else
|
2018 |
if (!ctx->pal_mode)
|
2019 |
goto invalid_opc;
|
2020 |
if (ra != 31) |
2021 |
tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp12);
|
2022 |
else
|
2023 |
tcg_gen_movi_i64(cpu_T[0], disp12);
|
2024 |
if (ra != 31) |
2025 |
tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
|
2026 |
else
|
2027 |
tcg_gen_movi_i64(cpu_T[1], 0); |
2028 |
switch ((insn >> 12) & 0xF) { |
2029 |
case 0x0: |
2030 |
/* Longword physical access */
|
2031 |
gen_op_stl_raw(); |
2032 |
break;
|
2033 |
case 0x1: |
2034 |
/* Quadword physical access */
|
2035 |
gen_op_stq_raw(); |
2036 |
break;
|
2037 |
case 0x2: |
2038 |
/* Longword physical access with lock */
|
2039 |
gen_op_stl_c_raw(); |
2040 |
break;
|
2041 |
case 0x3: |
2042 |
/* Quadword physical access with lock */
|
2043 |
gen_op_stq_c_raw(); |
2044 |
break;
|
2045 |
case 0x4: |
2046 |
/* Longword virtual access */
|
2047 |
gen_op_st_phys_to_virt(); |
2048 |
gen_op_stl_raw(); |
2049 |
break;
|
2050 |
case 0x5: |
2051 |
/* Quadword virtual access */
|
2052 |
gen_op_st_phys_to_virt(); |
2053 |
gen_op_stq_raw(); |
2054 |
break;
|
2055 |
case 0x6: |
2056 |
/* Invalid */
|
2057 |
goto invalid_opc;
|
2058 |
case 0x7: |
2059 |
/* Invalid */
|
2060 |
goto invalid_opc;
|
2061 |
case 0x8: |
2062 |
/* Invalid */
|
2063 |
goto invalid_opc;
|
2064 |
case 0x9: |
2065 |
/* Invalid */
|
2066 |
goto invalid_opc;
|
2067 |
case 0xA: |
2068 |
/* Invalid */
|
2069 |
goto invalid_opc;
|
2070 |
case 0xB: |
2071 |
/* Invalid */
|
2072 |
goto invalid_opc;
|
2073 |
case 0xC: |
2074 |
/* Longword virtual access with alternate access mode */
|
2075 |
gen_op_set_alt_mode(); |
2076 |
gen_op_st_phys_to_virt(); |
2077 |
gen_op_ldl_raw(); |
2078 |
gen_op_restore_mode(); |
2079 |
break;
|
2080 |
case 0xD: |
2081 |
/* Quadword virtual access with alternate access mode */
|
2082 |
gen_op_set_alt_mode(); |
2083 |
gen_op_st_phys_to_virt(); |
2084 |
gen_op_ldq_raw(); |
2085 |
gen_op_restore_mode(); |
2086 |
break;
|
2087 |
case 0xE: |
2088 |
/* Invalid */
|
2089 |
goto invalid_opc;
|
2090 |
case 0xF: |
2091 |
/* Invalid */
|
2092 |
goto invalid_opc;
|
2093 |
} |
2094 |
ret = 2;
|
2095 |
break;
|
2096 |
#endif
|
2097 |
case 0x20: |
2098 |
/* LDF */
|
2099 |
#if 0 // TODO
|
2100 |
gen_load_fmem(ctx, &gen_ldf, ra, rb, disp16);
|
2101 |
#else
|
2102 |
goto invalid_opc;
|
2103 |
#endif
|
2104 |
break;
|
2105 |
case 0x21: |
2106 |
/* LDG */
|
2107 |
#if 0 // TODO
|
2108 |
gen_load_fmem(ctx, &gen_ldg, ra, rb, disp16);
|
2109 |
#else
|
2110 |
goto invalid_opc;
|
2111 |
#endif
|
2112 |
break;
|
2113 |
case 0x22: |
2114 |
/* LDS */
|
2115 |
gen_load_fmem(ctx, &gen_lds, ra, rb, disp16); |
2116 |
break;
|
2117 |
case 0x23: |
2118 |
/* LDT */
|
2119 |
gen_load_fmem(ctx, &gen_ldt, ra, rb, disp16); |
2120 |
break;
|
2121 |
case 0x24: |
2122 |
/* STF */
|
2123 |
#if 0 // TODO
|
2124 |
gen_store_fmem(ctx, &gen_stf, ra, rb, disp16);
|
2125 |
#else
|
2126 |
goto invalid_opc;
|
2127 |
#endif
|
2128 |
break;
|
2129 |
case 0x25: |
2130 |
/* STG */
|
2131 |
#if 0 // TODO
|
2132 |
gen_store_fmem(ctx, &gen_stg, ra, rb, disp16);
|
2133 |
#else
|
2134 |
goto invalid_opc;
|
2135 |
#endif
|
2136 |
break;
|
2137 |
case 0x26: |
2138 |
/* STS */
|
2139 |
gen_store_fmem(ctx, &gen_sts, ra, rb, disp16); |
2140 |
break;
|
2141 |
case 0x27: |
2142 |
/* STT */
|
2143 |
gen_store_fmem(ctx, &gen_stt, ra, rb, disp16); |
2144 |
break;
|
2145 |
case 0x28: |
2146 |
/* LDL */
|
2147 |
gen_load_mem(ctx, &gen_ldl, ra, rb, disp16, 0);
|
2148 |
break;
|
2149 |
case 0x29: |
2150 |
/* LDQ */
|
2151 |
gen_load_mem(ctx, &gen_ldq, ra, rb, disp16, 0);
|
2152 |
break;
|
2153 |
case 0x2A: |
2154 |
/* LDL_L */
|
2155 |
gen_load_mem(ctx, &gen_ldl_l, ra, rb, disp16, 0);
|
2156 |
break;
|
2157 |
case 0x2B: |
2158 |
/* LDQ_L */
|
2159 |
gen_load_mem(ctx, &gen_ldq_l, ra, rb, disp16, 0);
|
2160 |
break;
|
2161 |
case 0x2C: |
2162 |
/* STL */
|
2163 |
gen_store_mem(ctx, &gen_stl, ra, rb, disp16, 0);
|
2164 |
break;
|
2165 |
case 0x2D: |
2166 |
/* STQ */
|
2167 |
gen_store_mem(ctx, &gen_stq, ra, rb, disp16, 0);
|
2168 |
break;
|
2169 |
case 0x2E: |
2170 |
/* STL_C */
|
2171 |
gen_store_mem(ctx, &gen_stl_c, ra, rb, disp16, 0);
|
2172 |
break;
|
2173 |
case 0x2F: |
2174 |
/* STQ_C */
|
2175 |
gen_store_mem(ctx, &gen_stq_c, ra, rb, disp16, 0);
|
2176 |
break;
|
2177 |
case 0x30: |
2178 |
/* BR */
|
2179 |
if (ra != 31) |
2180 |
tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); |
2181 |
tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
|
2182 |
ret = 1;
|
2183 |
break;
|
2184 |
case 0x31: |
2185 |
/* FBEQ */
|
2186 |
gen_fbcond(ctx, &gen_op_cmpfeq, ra, disp16); |
2187 |
ret = 1;
|
2188 |
break;
|
2189 |
case 0x32: |
2190 |
/* FBLT */
|
2191 |
gen_fbcond(ctx, &gen_op_cmpflt, ra, disp16); |
2192 |
ret = 1;
|
2193 |
break;
|
2194 |
case 0x33: |
2195 |
/* FBLE */
|
2196 |
gen_fbcond(ctx, &gen_op_cmpfle, ra, disp16); |
2197 |
ret = 1;
|
2198 |
break;
|
2199 |
case 0x34: |
2200 |
/* BSR */
|
2201 |
if (ra != 31) |
2202 |
tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); |
2203 |
tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
|
2204 |
ret = 1;
|
2205 |
break;
|
2206 |
case 0x35: |
2207 |
/* FBNE */
|
2208 |
gen_fbcond(ctx, &gen_op_cmpfne, ra, disp16); |
2209 |
ret = 1;
|
2210 |
break;
|
2211 |
case 0x36: |
2212 |
/* FBGE */
|
2213 |
gen_fbcond(ctx, &gen_op_cmpfge, ra, disp16); |
2214 |
ret = 1;
|
2215 |
break;
|
2216 |
case 0x37: |
2217 |
/* FBGT */
|
2218 |
gen_fbcond(ctx, &gen_op_cmpfgt, ra, disp16); |
2219 |
ret = 1;
|
2220 |
break;
|
2221 |
case 0x38: |
2222 |
/* BLBC */
|
2223 |
gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 1);
|
2224 |
ret = 1;
|
2225 |
break;
|
2226 |
case 0x39: |
2227 |
/* BEQ */
|
2228 |
gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 0);
|
2229 |
ret = 1;
|
2230 |
break;
|
2231 |
case 0x3A: |
2232 |
/* BLT */
|
2233 |
gen_bcond(ctx, TCG_COND_LT, ra, disp16, 0);
|
2234 |
ret = 1;
|
2235 |
break;
|
2236 |
case 0x3B: |
2237 |
/* BLE */
|
2238 |
gen_bcond(ctx, TCG_COND_LE, ra, disp16, 0);
|
2239 |
ret = 1;
|
2240 |
break;
|
2241 |
case 0x3C: |
2242 |
/* BLBS */
|
2243 |
gen_bcond(ctx, TCG_COND_NE, ra, disp16, 1);
|
2244 |
ret = 1;
|
2245 |
break;
|
2246 |
case 0x3D: |
2247 |
/* BNE */
|
2248 |
gen_bcond(ctx, TCG_COND_NE, ra, disp16, 0);
|
2249 |
ret = 1;
|
2250 |
break;
|
2251 |
case 0x3E: |
2252 |
/* BGE */
|
2253 |
gen_bcond(ctx, TCG_COND_GE, ra, disp16, 0);
|
2254 |
ret = 1;
|
2255 |
break;
|
2256 |
case 0x3F: |
2257 |
/* BGT */
|
2258 |
gen_bcond(ctx, TCG_COND_GT, ra, disp16, 0);
|
2259 |
ret = 1;
|
2260 |
break;
|
2261 |
invalid_opc:
|
2262 |
gen_invalid(ctx); |
2263 |
ret = 3;
|
2264 |
break;
|
2265 |
} |
2266 |
|
2267 |
return ret;
|
2268 |
} |
2269 |
|
2270 |
static always_inline void gen_intermediate_code_internal (CPUState *env, |
2271 |
TranslationBlock *tb, |
2272 |
int search_pc)
|
2273 |
{ |
2274 |
#if defined ALPHA_DEBUG_DISAS
|
2275 |
static int insn_count; |
2276 |
#endif
|
2277 |
DisasContext ctx, *ctxp = &ctx; |
2278 |
target_ulong pc_start; |
2279 |
uint32_t insn; |
2280 |
uint16_t *gen_opc_end; |
2281 |
int j, lj = -1; |
2282 |
int ret;
|
2283 |
int num_insns;
|
2284 |
int max_insns;
|
2285 |
|
2286 |
pc_start = tb->pc; |
2287 |
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
2288 |
ctx.pc = pc_start; |
2289 |
ctx.amask = env->amask; |
2290 |
#if defined (CONFIG_USER_ONLY)
|
2291 |
ctx.mem_idx = 0;
|
2292 |
#else
|
2293 |
ctx.mem_idx = ((env->ps >> 3) & 3); |
2294 |
ctx.pal_mode = env->ipr[IPR_EXC_ADDR] & 1;
|
2295 |
#endif
|
2296 |
num_insns = 0;
|
2297 |
max_insns = tb->cflags & CF_COUNT_MASK; |
2298 |
if (max_insns == 0) |
2299 |
max_insns = CF_COUNT_MASK; |
2300 |
|
2301 |
gen_icount_start(); |
2302 |
for (ret = 0; ret == 0;) { |
2303 |
if (env->nb_breakpoints > 0) { |
2304 |
for(j = 0; j < env->nb_breakpoints; j++) { |
2305 |
if (env->breakpoints[j] == ctx.pc) {
|
2306 |
gen_excp(&ctx, EXCP_DEBUG, 0);
|
2307 |
break;
|
2308 |
} |
2309 |
} |
2310 |
} |
2311 |
if (search_pc) {
|
2312 |
j = gen_opc_ptr - gen_opc_buf; |
2313 |
if (lj < j) {
|
2314 |
lj++; |
2315 |
while (lj < j)
|
2316 |
gen_opc_instr_start[lj++] = 0;
|
2317 |
gen_opc_pc[lj] = ctx.pc; |
2318 |
gen_opc_instr_start[lj] = 1;
|
2319 |
gen_opc_icount[lj] = num_insns; |
2320 |
} |
2321 |
} |
2322 |
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
2323 |
gen_io_start(); |
2324 |
#if defined ALPHA_DEBUG_DISAS
|
2325 |
insn_count++; |
2326 |
if (logfile != NULL) { |
2327 |
fprintf(logfile, "pc " TARGET_FMT_lx " mem_idx %d\n", |
2328 |
ctx.pc, ctx.mem_idx); |
2329 |
} |
2330 |
#endif
|
2331 |
insn = ldl_code(ctx.pc); |
2332 |
#if defined ALPHA_DEBUG_DISAS
|
2333 |
insn_count++; |
2334 |
if (logfile != NULL) { |
2335 |
fprintf(logfile, "opcode %08x %d\n", insn, insn_count);
|
2336 |
} |
2337 |
#endif
|
2338 |
num_insns++; |
2339 |
ctx.pc += 4;
|
2340 |
ret = translate_one(ctxp, insn); |
2341 |
if (ret != 0) |
2342 |
break;
|
2343 |
/* if we reach a page boundary or are single stepping, stop
|
2344 |
* generation
|
2345 |
*/
|
2346 |
if (((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) || |
2347 |
(env->singlestep_enabled) || |
2348 |
num_insns >= max_insns) { |
2349 |
break;
|
2350 |
} |
2351 |
#if defined (DO_SINGLE_STEP)
|
2352 |
break;
|
2353 |
#endif
|
2354 |
} |
2355 |
if (ret != 1 && ret != 3) { |
2356 |
tcg_gen_movi_i64(cpu_pc, ctx.pc); |
2357 |
} |
2358 |
#if defined (DO_TB_FLUSH)
|
2359 |
tcg_gen_helper_0_0(helper_tb_flush); |
2360 |
#endif
|
2361 |
if (tb->cflags & CF_LAST_IO)
|
2362 |
gen_io_end(); |
2363 |
/* Generate the return instruction */
|
2364 |
tcg_gen_exit_tb(0);
|
2365 |
gen_icount_end(tb, num_insns); |
2366 |
*gen_opc_ptr = INDEX_op_end; |
2367 |
if (search_pc) {
|
2368 |
j = gen_opc_ptr - gen_opc_buf; |
2369 |
lj++; |
2370 |
while (lj <= j)
|
2371 |
gen_opc_instr_start[lj++] = 0;
|
2372 |
} else {
|
2373 |
tb->size = ctx.pc - pc_start; |
2374 |
tb->icount = num_insns; |
2375 |
} |
2376 |
#if defined ALPHA_DEBUG_DISAS
|
2377 |
if (loglevel & CPU_LOG_TB_CPU) {
|
2378 |
cpu_dump_state(env, logfile, fprintf, 0);
|
2379 |
} |
2380 |
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
2381 |
fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
|
2382 |
target_disas(logfile, pc_start, ctx.pc - pc_start, 1);
|
2383 |
fprintf(logfile, "\n");
|
2384 |
} |
2385 |
#endif
|
2386 |
} |
2387 |
|
2388 |
void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) |
2389 |
{ |
2390 |
gen_intermediate_code_internal(env, tb, 0);
|
2391 |
} |
2392 |
|
2393 |
void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) |
2394 |
{ |
2395 |
gen_intermediate_code_internal(env, tb, 1);
|
2396 |
} |
2397 |
|
2398 |
CPUAlphaState * cpu_alpha_init (const char *cpu_model) |
2399 |
{ |
2400 |
CPUAlphaState *env; |
2401 |
uint64_t hwpcb; |
2402 |
|
2403 |
env = qemu_mallocz(sizeof(CPUAlphaState));
|
2404 |
if (!env)
|
2405 |
return NULL; |
2406 |
cpu_exec_init(env); |
2407 |
alpha_translate_init(); |
2408 |
tlb_flush(env, 1);
|
2409 |
/* XXX: should not be hardcoded */
|
2410 |
env->implver = IMPLVER_2106x; |
2411 |
env->ps = 0x1F00;
|
2412 |
#if defined (CONFIG_USER_ONLY)
|
2413 |
env->ps |= 1 << 3; |
2414 |
#endif
|
2415 |
pal_init(env); |
2416 |
/* Initialize IPR */
|
2417 |
hwpcb = env->ipr[IPR_PCBB]; |
2418 |
env->ipr[IPR_ASN] = 0;
|
2419 |
env->ipr[IPR_ASTEN] = 0;
|
2420 |
env->ipr[IPR_ASTSR] = 0;
|
2421 |
env->ipr[IPR_DATFX] = 0;
|
2422 |
/* XXX: fix this */
|
2423 |
// env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
|
2424 |
// env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
|
2425 |
// env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
|
2426 |
// env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
|
2427 |
env->ipr[IPR_FEN] = 0;
|
2428 |
env->ipr[IPR_IPL] = 31;
|
2429 |
env->ipr[IPR_MCES] = 0;
|
2430 |
env->ipr[IPR_PERFMON] = 0; /* Implementation specific */ |
2431 |
// env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
|
2432 |
env->ipr[IPR_SISR] = 0;
|
2433 |
env->ipr[IPR_VIRBND] = -1ULL;
|
2434 |
|
2435 |
return env;
|
2436 |
} |
2437 |
|
2438 |
void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
2439 |
unsigned long searched_pc, int pc_pos, void *puc) |
2440 |
{ |
2441 |
env->pc = gen_opc_pc[pc_pos]; |
2442 |
} |