root / hw / pci / pci.c @ e00387d5
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/*
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* QEMU PCI bus manager
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/hw.h" |
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#include "hw/pci/pci.h" |
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#include "hw/pci/pci_bridge.h" |
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#include "hw/pci/pci_bus.h" |
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#include "monitor/monitor.h" |
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#include "net/net.h" |
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#include "sysemu/sysemu.h" |
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#include "hw/loader.h" |
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#include "qemu/range.h" |
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#include "qmp-commands.h" |
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#include "hw/pci/msi.h" |
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#include "hw/pci/msix.h" |
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#include "exec/address-spaces.h" |
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//#define DEBUG_PCI
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#ifdef DEBUG_PCI
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# define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
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#else
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# define PCI_DPRINTF(format, ...) do { } while (0) |
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#endif
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static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); |
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static char *pcibus_get_dev_path(DeviceState *dev); |
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static char *pcibus_get_fw_dev_path(DeviceState *dev); |
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static int pcibus_reset(BusState *qbus); |
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static Property pci_props[] = {
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DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), |
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DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
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DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1), |
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DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
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QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
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DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
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QEMU_PCI_CAP_SERR_BITNR, true),
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DEFINE_PROP_END_OF_LIST() |
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}; |
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static void pci_bus_class_init(ObjectClass *klass, void *data) |
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{ |
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BusClass *k = BUS_CLASS(klass); |
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k->print_dev = pcibus_dev_print; |
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k->get_dev_path = pcibus_get_dev_path; |
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k->get_fw_dev_path = pcibus_get_fw_dev_path; |
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k->reset = pcibus_reset; |
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} |
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static const TypeInfo pci_bus_info = { |
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.name = TYPE_PCI_BUS, |
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.parent = TYPE_BUS, |
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.instance_size = sizeof(PCIBus),
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.class_init = pci_bus_class_init, |
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}; |
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static const TypeInfo pcie_bus_info = { |
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.name = TYPE_PCIE_BUS, |
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.parent = TYPE_PCI_BUS, |
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}; |
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static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); |
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static void pci_update_mappings(PCIDevice *d); |
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static void pci_set_irq(void *opaque, int irq_num, int level); |
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static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom); |
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static void pci_del_option_rom(PCIDevice *pdev); |
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static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
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static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
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struct PCIHostBus {
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int domain;
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struct PCIBus *bus;
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QLIST_ENTRY(PCIHostBus) next; |
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}; |
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static QLIST_HEAD(, PCIHostBus) host_buses;
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static const VMStateDescription vmstate_pcibus = { |
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.name = "PCIBUS",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) { |
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VMSTATE_INT32_EQUAL(nirq, PCIBus), |
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VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static int pci_bar(PCIDevice *d, int reg) |
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{ |
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uint8_t type; |
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if (reg != PCI_ROM_SLOT)
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return PCI_BASE_ADDRESS_0 + reg * 4; |
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type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
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return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
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} |
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static inline int pci_irq_state(PCIDevice *d, int irq_num) |
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{ |
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return (d->irq_state >> irq_num) & 0x1; |
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} |
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static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) |
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{ |
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d->irq_state &= ~(0x1 << irq_num);
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d->irq_state |= level << irq_num; |
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} |
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static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) |
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{ |
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PCIBus *bus; |
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for (;;) {
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bus = pci_dev->bus; |
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irq_num = bus->map_irq(pci_dev, irq_num); |
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if (bus->set_irq)
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break;
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pci_dev = bus->parent_dev; |
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} |
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bus->irq_count[irq_num] += change; |
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bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
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} |
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int pci_bus_get_irq_level(PCIBus *bus, int irq_num) |
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{ |
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assert(irq_num >= 0);
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assert(irq_num < bus->nirq); |
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return !!bus->irq_count[irq_num];
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} |
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/* Update interrupt status bit in config space on interrupt
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* state change. */
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static void pci_update_irq_status(PCIDevice *dev) |
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{ |
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if (dev->irq_state) {
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dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; |
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} else {
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dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; |
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} |
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} |
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void pci_device_deassert_intx(PCIDevice *dev)
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{ |
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int i;
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for (i = 0; i < PCI_NUM_PINS; ++i) { |
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qemu_set_irq(dev->irq[i], 0);
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} |
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} |
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/*
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* This function is called on #RST and FLR.
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* FLR if PCI_EXP_DEVCTL_BCR_FLR is set
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*/
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void pci_device_reset(PCIDevice *dev)
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{ |
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int r;
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qdev_reset_all(&dev->qdev); |
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dev->irq_state = 0;
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pci_update_irq_status(dev); |
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pci_device_deassert_intx(dev); |
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/* Clear all writable bits */
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pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, |
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pci_get_word(dev->wmask + PCI_COMMAND) | |
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pci_get_word(dev->w1cmask + PCI_COMMAND)); |
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pci_word_test_and_clear_mask(dev->config + PCI_STATUS, |
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pci_get_word(dev->wmask + PCI_STATUS) | |
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pci_get_word(dev->w1cmask + PCI_STATUS)); |
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dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
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dev->config[PCI_INTERRUPT_LINE] = 0x0;
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for (r = 0; r < PCI_NUM_REGIONS; ++r) { |
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PCIIORegion *region = &dev->io_regions[r]; |
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if (!region->size) {
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continue;
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} |
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if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
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region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
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pci_set_quad(dev->config + pci_bar(dev, r), region->type); |
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} else {
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pci_set_long(dev->config + pci_bar(dev, r), region->type); |
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} |
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} |
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pci_update_mappings(dev); |
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msi_reset(dev); |
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msix_reset(dev); |
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} |
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/*
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* Trigger pci bus reset under a given bus.
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* To be called on RST# assert.
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*/
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void pci_bus_reset(PCIBus *bus)
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{ |
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int i;
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for (i = 0; i < bus->nirq; i++) { |
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bus->irq_count[i] = 0;
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} |
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for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
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if (bus->devices[i]) {
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pci_device_reset(bus->devices[i]); |
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} |
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} |
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} |
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static int pcibus_reset(BusState *qbus) |
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{ |
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pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus)); |
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/* topology traverse is done by pci_bus_reset().
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Tell qbus/qdev walker not to traverse the tree */
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return 1; |
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} |
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static void pci_host_bus_register(int domain, PCIBus *bus) |
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{ |
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struct PCIHostBus *host;
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host = g_malloc0(sizeof(*host));
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host->domain = domain; |
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host->bus = bus; |
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QLIST_INSERT_HEAD(&host_buses, host, next); |
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} |
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PCIBus *pci_find_root_bus(int domain)
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{ |
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struct PCIHostBus *host;
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QLIST_FOREACH(host, &host_buses, next) { |
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if (host->domain == domain) {
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return host->bus;
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} |
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} |
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return NULL; |
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} |
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int pci_find_domain(const PCIBus *bus) |
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{ |
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PCIDevice *d; |
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struct PCIHostBus *host;
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/* obtain root bus */
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while ((d = bus->parent_dev) != NULL) { |
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bus = d->bus; |
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} |
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QLIST_FOREACH(host, &host_buses, next) { |
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if (host->bus == bus) {
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return host->domain;
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} |
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} |
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abort(); /* should not be reached */
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return -1; |
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} |
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static void pci_bus_init(PCIBus *bus, DeviceState *parent, |
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const char *name, |
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MemoryRegion *address_space_mem, |
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MemoryRegion *address_space_io, |
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uint8_t devfn_min) |
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{ |
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assert(PCI_FUNC(devfn_min) == 0);
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bus->devfn_min = devfn_min; |
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bus->address_space_mem = address_space_mem; |
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bus->address_space_io = address_space_io; |
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/* host bridge */
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QLIST_INIT(&bus->child); |
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pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */ |
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vmstate_register(NULL, -1, &vmstate_pcibus, bus); |
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} |
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bool pci_bus_is_express(PCIBus *bus)
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{ |
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return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS);
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} |
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bool pci_bus_is_root(PCIBus *bus)
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{ |
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return !bus->parent_dev;
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} |
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void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
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const char *name, |
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MemoryRegion *address_space_mem, |
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MemoryRegion *address_space_io, |
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uint8_t devfn_min, const char *typename) |
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{ |
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qbus_create_inplace(bus, typename, parent, name); |
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pci_bus_init(bus, parent, name, address_space_mem, |
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address_space_io, devfn_min); |
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} |
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PCIBus *pci_bus_new(DeviceState *parent, const char *name, |
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MemoryRegion *address_space_mem, |
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MemoryRegion *address_space_io, |
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uint8_t devfn_min, const char *typename) |
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{ |
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PCIBus *bus; |
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bus = PCI_BUS(qbus_create(typename, parent, name)); |
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pci_bus_init(bus, parent, name, address_space_mem, |
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address_space_io, devfn_min); |
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return bus;
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} |
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void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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void *irq_opaque, int nirq) |
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{ |
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bus->set_irq = set_irq; |
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bus->map_irq = map_irq; |
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bus->irq_opaque = irq_opaque; |
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bus->nirq = nirq; |
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bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); |
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} |
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void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
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{ |
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bus->qbus.allow_hotplug = 1;
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bus->hotplug = hotplug; |
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bus->hotplug_qdev = qdev; |
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} |
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PCIBus *pci_register_bus(DeviceState *parent, const char *name, |
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pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
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void *irq_opaque,
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MemoryRegion *address_space_mem, |
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MemoryRegion *address_space_io, |
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uint8_t devfn_min, int nirq, const char *typename) |
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{ |
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PCIBus *bus; |
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bus = pci_bus_new(parent, name, address_space_mem, |
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address_space_io, devfn_min, typename); |
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pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); |
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return bus;
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} |
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int pci_bus_num(PCIBus *s)
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{ |
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if (pci_bus_is_root(s))
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return 0; /* pci host bridge */ |
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return s->parent_dev->config[PCI_SECONDARY_BUS];
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} |
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static int get_pci_config_device(QEMUFile *f, void *pv, size_t size) |
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{ |
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PCIDevice *s = container_of(pv, PCIDevice, config); |
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uint8_t *config; |
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int i;
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|
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assert(size == pci_config_size(s)); |
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config = g_malloc(size); |
381 |
|
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qemu_get_buffer(f, config, size); |
383 |
for (i = 0; i < size; ++i) { |
384 |
if ((config[i] ^ s->config[i]) &
|
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s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { |
386 |
g_free(config); |
387 |
return -EINVAL;
|
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} |
389 |
} |
390 |
memcpy(s->config, config, size); |
391 |
|
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pci_update_mappings(s); |
393 |
|
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memory_region_set_enabled(&s->bus_master_enable_region, |
395 |
pci_get_word(s->config + PCI_COMMAND) |
396 |
& PCI_COMMAND_MASTER); |
397 |
|
398 |
g_free(config); |
399 |
return 0; |
400 |
} |
401 |
|
402 |
/* just put buffer */
|
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static void put_pci_config_device(QEMUFile *f, void *pv, size_t size) |
404 |
{ |
405 |
const uint8_t **v = pv;
|
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assert(size == pci_config_size(container_of(pv, PCIDevice, config))); |
407 |
qemu_put_buffer(f, *v, size); |
408 |
} |
409 |
|
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static VMStateInfo vmstate_info_pci_config = {
|
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.name = "pci config",
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.get = get_pci_config_device, |
413 |
.put = put_pci_config_device, |
414 |
}; |
415 |
|
416 |
static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size) |
417 |
{ |
418 |
PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
419 |
uint32_t irq_state[PCI_NUM_PINS]; |
420 |
int i;
|
421 |
for (i = 0; i < PCI_NUM_PINS; ++i) { |
422 |
irq_state[i] = qemu_get_be32(f); |
423 |
if (irq_state[i] != 0x1 && irq_state[i] != 0) { |
424 |
fprintf(stderr, "irq state %d: must be 0 or 1.\n",
|
425 |
irq_state[i]); |
426 |
return -EINVAL;
|
427 |
} |
428 |
} |
429 |
|
430 |
for (i = 0; i < PCI_NUM_PINS; ++i) { |
431 |
pci_set_irq_state(s, i, irq_state[i]); |
432 |
} |
433 |
|
434 |
return 0; |
435 |
} |
436 |
|
437 |
static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size) |
438 |
{ |
439 |
int i;
|
440 |
PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
441 |
|
442 |
for (i = 0; i < PCI_NUM_PINS; ++i) { |
443 |
qemu_put_be32(f, pci_irq_state(s, i)); |
444 |
} |
445 |
} |
446 |
|
447 |
static VMStateInfo vmstate_info_pci_irq_state = {
|
448 |
.name = "pci irq state",
|
449 |
.get = get_pci_irq_state, |
450 |
.put = put_pci_irq_state, |
451 |
}; |
452 |
|
453 |
const VMStateDescription vmstate_pci_device = {
|
454 |
.name = "PCIDevice",
|
455 |
.version_id = 2,
|
456 |
.minimum_version_id = 1,
|
457 |
.minimum_version_id_old = 1,
|
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.fields = (VMStateField []) { |
459 |
VMSTATE_INT32_LE(version_id, PCIDevice), |
460 |
VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
|
461 |
vmstate_info_pci_config, |
462 |
PCI_CONFIG_SPACE_SIZE), |
463 |
VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
|
464 |
vmstate_info_pci_irq_state, |
465 |
PCI_NUM_PINS * sizeof(int32_t)),
|
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VMSTATE_END_OF_LIST() |
467 |
} |
468 |
}; |
469 |
|
470 |
const VMStateDescription vmstate_pcie_device = {
|
471 |
.name = "PCIEDevice",
|
472 |
.version_id = 2,
|
473 |
.minimum_version_id = 1,
|
474 |
.minimum_version_id_old = 1,
|
475 |
.fields = (VMStateField []) { |
476 |
VMSTATE_INT32_LE(version_id, PCIDevice), |
477 |
VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
|
478 |
vmstate_info_pci_config, |
479 |
PCIE_CONFIG_SPACE_SIZE), |
480 |
VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
|
481 |
vmstate_info_pci_irq_state, |
482 |
PCI_NUM_PINS * sizeof(int32_t)),
|
483 |
VMSTATE_END_OF_LIST() |
484 |
} |
485 |
}; |
486 |
|
487 |
static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) |
488 |
{ |
489 |
return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
|
490 |
} |
491 |
|
492 |
void pci_device_save(PCIDevice *s, QEMUFile *f)
|
493 |
{ |
494 |
/* Clear interrupt status bit: it is implicit
|
495 |
* in irq_state which we are saving.
|
496 |
* This makes us compatible with old devices
|
497 |
* which never set or clear this bit. */
|
498 |
s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; |
499 |
vmstate_save_state(f, pci_get_vmstate(s), s); |
500 |
/* Restore the interrupt status bit. */
|
501 |
pci_update_irq_status(s); |
502 |
} |
503 |
|
504 |
int pci_device_load(PCIDevice *s, QEMUFile *f)
|
505 |
{ |
506 |
int ret;
|
507 |
ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id); |
508 |
/* Restore the interrupt status bit. */
|
509 |
pci_update_irq_status(s); |
510 |
return ret;
|
511 |
} |
512 |
|
513 |
static void pci_set_default_subsystem_id(PCIDevice *pci_dev) |
514 |
{ |
515 |
pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, |
516 |
pci_default_sub_vendor_id); |
517 |
pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, |
518 |
pci_default_sub_device_id); |
519 |
} |
520 |
|
521 |
/*
|
522 |
* Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
|
523 |
* [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
|
524 |
*/
|
525 |
static int pci_parse_devaddr(const char *addr, int *domp, int *busp, |
526 |
unsigned int *slotp, unsigned int *funcp) |
527 |
{ |
528 |
const char *p; |
529 |
char *e;
|
530 |
unsigned long val; |
531 |
unsigned long dom = 0, bus = 0; |
532 |
unsigned int slot = 0; |
533 |
unsigned int func = 0; |
534 |
|
535 |
p = addr; |
536 |
val = strtoul(p, &e, 16);
|
537 |
if (e == p)
|
538 |
return -1; |
539 |
if (*e == ':') { |
540 |
bus = val; |
541 |
p = e + 1;
|
542 |
val = strtoul(p, &e, 16);
|
543 |
if (e == p)
|
544 |
return -1; |
545 |
if (*e == ':') { |
546 |
dom = bus; |
547 |
bus = val; |
548 |
p = e + 1;
|
549 |
val = strtoul(p, &e, 16);
|
550 |
if (e == p)
|
551 |
return -1; |
552 |
} |
553 |
} |
554 |
|
555 |
slot = val; |
556 |
|
557 |
if (funcp != NULL) { |
558 |
if (*e != '.') |
559 |
return -1; |
560 |
|
561 |
p = e + 1;
|
562 |
val = strtoul(p, &e, 16);
|
563 |
if (e == p)
|
564 |
return -1; |
565 |
|
566 |
func = val; |
567 |
} |
568 |
|
569 |
/* if funcp == NULL func is 0 */
|
570 |
if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) |
571 |
return -1; |
572 |
|
573 |
if (*e)
|
574 |
return -1; |
575 |
|
576 |
*domp = dom; |
577 |
*busp = bus; |
578 |
*slotp = slot; |
579 |
if (funcp != NULL) |
580 |
*funcp = func; |
581 |
return 0; |
582 |
} |
583 |
|
584 |
int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp, |
585 |
unsigned *slotp)
|
586 |
{ |
587 |
/* strip legacy tag */
|
588 |
if (!strncmp(addr, "pci_addr=", 9)) { |
589 |
addr += 9;
|
590 |
} |
591 |
if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) { |
592 |
monitor_printf(mon, "Invalid pci address\n");
|
593 |
return -1; |
594 |
} |
595 |
return 0; |
596 |
} |
597 |
|
598 |
PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr) |
599 |
{ |
600 |
int dom, bus;
|
601 |
unsigned slot;
|
602 |
|
603 |
if (!devaddr) {
|
604 |
*devfnp = -1;
|
605 |
return pci_find_bus_nr(pci_find_root_bus(0), 0); |
606 |
} |
607 |
|
608 |
if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) { |
609 |
return NULL; |
610 |
} |
611 |
|
612 |
*devfnp = PCI_DEVFN(slot, 0);
|
613 |
return pci_find_bus_nr(pci_find_root_bus(dom), bus);
|
614 |
} |
615 |
|
616 |
static void pci_init_cmask(PCIDevice *dev) |
617 |
{ |
618 |
pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
|
619 |
pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
|
620 |
dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; |
621 |
dev->cmask[PCI_REVISION_ID] = 0xff;
|
622 |
dev->cmask[PCI_CLASS_PROG] = 0xff;
|
623 |
pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
|
624 |
dev->cmask[PCI_HEADER_TYPE] = 0xff;
|
625 |
dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
|
626 |
} |
627 |
|
628 |
static void pci_init_wmask(PCIDevice *dev) |
629 |
{ |
630 |
int config_size = pci_config_size(dev);
|
631 |
|
632 |
dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
|
633 |
dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
|
634 |
pci_set_word(dev->wmask + PCI_COMMAND, |
635 |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | |
636 |
PCI_COMMAND_INTX_DISABLE); |
637 |
if (dev->cap_present & QEMU_PCI_CAP_SERR) {
|
638 |
pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); |
639 |
} |
640 |
|
641 |
memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
|
642 |
config_size - PCI_CONFIG_HEADER_SIZE); |
643 |
} |
644 |
|
645 |
static void pci_init_w1cmask(PCIDevice *dev) |
646 |
{ |
647 |
/*
|
648 |
* Note: It's okay to set w1cmask even for readonly bits as
|
649 |
* long as their value is hardwired to 0.
|
650 |
*/
|
651 |
pci_set_word(dev->w1cmask + PCI_STATUS, |
652 |
PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | |
653 |
PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | |
654 |
PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); |
655 |
} |
656 |
|
657 |
static void pci_init_mask_bridge(PCIDevice *d) |
658 |
{ |
659 |
/* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
|
660 |
PCI_SEC_LETENCY_TIMER */
|
661 |
memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); |
662 |
|
663 |
/* base and limit */
|
664 |
d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
|
665 |
d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
|
666 |
pci_set_word(d->wmask + PCI_MEMORY_BASE, |
667 |
PCI_MEMORY_RANGE_MASK & 0xffff);
|
668 |
pci_set_word(d->wmask + PCI_MEMORY_LIMIT, |
669 |
PCI_MEMORY_RANGE_MASK & 0xffff);
|
670 |
pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, |
671 |
PCI_PREF_RANGE_MASK & 0xffff);
|
672 |
pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, |
673 |
PCI_PREF_RANGE_MASK & 0xffff);
|
674 |
|
675 |
/* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
|
676 |
memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); |
677 |
|
678 |
/* Supported memory and i/o types */
|
679 |
d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; |
680 |
d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; |
681 |
pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, |
682 |
PCI_PREF_RANGE_TYPE_64); |
683 |
pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, |
684 |
PCI_PREF_RANGE_TYPE_64); |
685 |
|
686 |
/*
|
687 |
* TODO: Bridges default to 10-bit VGA decoding but we currently only
|
688 |
* implement 16-bit decoding (no alias support).
|
689 |
*/
|
690 |
pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, |
691 |
PCI_BRIDGE_CTL_PARITY | |
692 |
PCI_BRIDGE_CTL_SERR | |
693 |
PCI_BRIDGE_CTL_ISA | |
694 |
PCI_BRIDGE_CTL_VGA | |
695 |
PCI_BRIDGE_CTL_VGA_16BIT | |
696 |
PCI_BRIDGE_CTL_MASTER_ABORT | |
697 |
PCI_BRIDGE_CTL_BUS_RESET | |
698 |
PCI_BRIDGE_CTL_FAST_BACK | |
699 |
PCI_BRIDGE_CTL_DISCARD | |
700 |
PCI_BRIDGE_CTL_SEC_DISCARD | |
701 |
PCI_BRIDGE_CTL_DISCARD_SERR); |
702 |
/* Below does not do anything as we never set this bit, put here for
|
703 |
* completeness. */
|
704 |
pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, |
705 |
PCI_BRIDGE_CTL_DISCARD_STATUS); |
706 |
d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; |
707 |
d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; |
708 |
pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, |
709 |
PCI_PREF_RANGE_TYPE_MASK); |
710 |
pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, |
711 |
PCI_PREF_RANGE_TYPE_MASK); |
712 |
} |
713 |
|
714 |
static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev) |
715 |
{ |
716 |
uint8_t slot = PCI_SLOT(dev->devfn); |
717 |
uint8_t func; |
718 |
|
719 |
if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
|
720 |
dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; |
721 |
} |
722 |
|
723 |
/*
|
724 |
* multifunction bit is interpreted in two ways as follows.
|
725 |
* - all functions must set the bit to 1.
|
726 |
* Example: Intel X53
|
727 |
* - function 0 must set the bit, but the rest function (> 0)
|
728 |
* is allowed to leave the bit to 0.
|
729 |
* Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
|
730 |
*
|
731 |
* So OS (at least Linux) checks the bit of only function 0,
|
732 |
* and doesn't see the bit of function > 0.
|
733 |
*
|
734 |
* The below check allows both interpretation.
|
735 |
*/
|
736 |
if (PCI_FUNC(dev->devfn)) {
|
737 |
PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
|
738 |
if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
|
739 |
/* function 0 should set multifunction bit */
|
740 |
error_report("PCI: single function device can't be populated "
|
741 |
"in function %x.%x", slot, PCI_FUNC(dev->devfn));
|
742 |
return -1; |
743 |
} |
744 |
return 0; |
745 |
} |
746 |
|
747 |
if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
|
748 |
return 0; |
749 |
} |
750 |
/* function 0 indicates single function, so function > 0 must be NULL */
|
751 |
for (func = 1; func < PCI_FUNC_MAX; ++func) { |
752 |
if (bus->devices[PCI_DEVFN(slot, func)]) {
|
753 |
error_report("PCI: %x.0 indicates single function, "
|
754 |
"but %x.%x is already populated.",
|
755 |
slot, slot, func); |
756 |
return -1; |
757 |
} |
758 |
} |
759 |
return 0; |
760 |
} |
761 |
|
762 |
static void pci_config_alloc(PCIDevice *pci_dev) |
763 |
{ |
764 |
int config_size = pci_config_size(pci_dev);
|
765 |
|
766 |
pci_dev->config = g_malloc0(config_size); |
767 |
pci_dev->cmask = g_malloc0(config_size); |
768 |
pci_dev->wmask = g_malloc0(config_size); |
769 |
pci_dev->w1cmask = g_malloc0(config_size); |
770 |
pci_dev->used = g_malloc0(config_size); |
771 |
} |
772 |
|
773 |
static void pci_config_free(PCIDevice *pci_dev) |
774 |
{ |
775 |
g_free(pci_dev->config); |
776 |
g_free(pci_dev->cmask); |
777 |
g_free(pci_dev->wmask); |
778 |
g_free(pci_dev->w1cmask); |
779 |
g_free(pci_dev->used); |
780 |
} |
781 |
|
782 |
/* -1 for devfn means auto assign */
|
783 |
static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
|
784 |
const char *name, int devfn) |
785 |
{ |
786 |
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); |
787 |
PCIConfigReadFunc *config_read = pc->config_read; |
788 |
PCIConfigWriteFunc *config_write = pc->config_write; |
789 |
AddressSpace *dma_as; |
790 |
|
791 |
if (devfn < 0) { |
792 |
for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
|
793 |
devfn += PCI_FUNC_MAX) { |
794 |
if (!bus->devices[devfn])
|
795 |
goto found;
|
796 |
} |
797 |
error_report("PCI: no slot/function available for %s, all in use", name);
|
798 |
return NULL; |
799 |
found: ;
|
800 |
} else if (bus->devices[devfn]) { |
801 |
error_report("PCI: slot %d function %d not available for %s, in use by %s",
|
802 |
PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name); |
803 |
return NULL; |
804 |
} |
805 |
|
806 |
pci_dev->bus = bus; |
807 |
if (bus->iommu_fn) {
|
808 |
dma_as = bus->iommu_fn(bus, bus->iommu_opaque, devfn); |
809 |
} else {
|
810 |
/* FIXME: inherit memory region from bus creator */
|
811 |
dma_as = &address_space_memory; |
812 |
} |
813 |
|
814 |
memory_region_init_alias(&pci_dev->bus_master_enable_region, "bus master",
|
815 |
dma_as->root, 0, memory_region_size(dma_as->root));
|
816 |
memory_region_set_enabled(&pci_dev->bus_master_enable_region, false);
|
817 |
address_space_init(&pci_dev->bus_master_as, &pci_dev->bus_master_enable_region); |
818 |
pci_dev->dma = g_new(DMAContext, 1);
|
819 |
dma_context_init(pci_dev->dma, &pci_dev->bus_master_as); |
820 |
|
821 |
pci_dev->devfn = devfn; |
822 |
pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
|
823 |
pci_dev->irq_state = 0;
|
824 |
pci_config_alloc(pci_dev); |
825 |
|
826 |
pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); |
827 |
pci_config_set_device_id(pci_dev->config, pc->device_id); |
828 |
pci_config_set_revision(pci_dev->config, pc->revision); |
829 |
pci_config_set_class(pci_dev->config, pc->class_id); |
830 |
|
831 |
if (!pc->is_bridge) {
|
832 |
if (pc->subsystem_vendor_id || pc->subsystem_id) {
|
833 |
pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, |
834 |
pc->subsystem_vendor_id); |
835 |
pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, |
836 |
pc->subsystem_id); |
837 |
} else {
|
838 |
pci_set_default_subsystem_id(pci_dev); |
839 |
} |
840 |
} else {
|
841 |
/* subsystem_vendor_id/subsystem_id are only for header type 0 */
|
842 |
assert(!pc->subsystem_vendor_id); |
843 |
assert(!pc->subsystem_id); |
844 |
} |
845 |
pci_init_cmask(pci_dev); |
846 |
pci_init_wmask(pci_dev); |
847 |
pci_init_w1cmask(pci_dev); |
848 |
if (pc->is_bridge) {
|
849 |
pci_init_mask_bridge(pci_dev); |
850 |
} |
851 |
if (pci_init_multifunction(bus, pci_dev)) {
|
852 |
pci_config_free(pci_dev); |
853 |
return NULL; |
854 |
} |
855 |
|
856 |
if (!config_read)
|
857 |
config_read = pci_default_read_config; |
858 |
if (!config_write)
|
859 |
config_write = pci_default_write_config; |
860 |
pci_dev->config_read = config_read; |
861 |
pci_dev->config_write = config_write; |
862 |
bus->devices[devfn] = pci_dev; |
863 |
pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS); |
864 |
pci_dev->version_id = 2; /* Current pci device vmstate version */ |
865 |
return pci_dev;
|
866 |
} |
867 |
|
868 |
static void do_pci_unregister_device(PCIDevice *pci_dev) |
869 |
{ |
870 |
qemu_free_irqs(pci_dev->irq); |
871 |
pci_dev->bus->devices[pci_dev->devfn] = NULL;
|
872 |
pci_config_free(pci_dev); |
873 |
|
874 |
address_space_destroy(&pci_dev->bus_master_as); |
875 |
memory_region_destroy(&pci_dev->bus_master_enable_region); |
876 |
g_free(pci_dev->dma); |
877 |
pci_dev->dma = NULL;
|
878 |
} |
879 |
|
880 |
static void pci_unregister_io_regions(PCIDevice *pci_dev) |
881 |
{ |
882 |
PCIIORegion *r; |
883 |
int i;
|
884 |
|
885 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
886 |
r = &pci_dev->io_regions[i]; |
887 |
if (!r->size || r->addr == PCI_BAR_UNMAPPED)
|
888 |
continue;
|
889 |
memory_region_del_subregion(r->address_space, r->memory); |
890 |
} |
891 |
|
892 |
pci_unregister_vga(pci_dev); |
893 |
} |
894 |
|
895 |
static int pci_unregister_device(DeviceState *dev) |
896 |
{ |
897 |
PCIDevice *pci_dev = PCI_DEVICE(dev); |
898 |
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); |
899 |
|
900 |
pci_unregister_io_regions(pci_dev); |
901 |
pci_del_option_rom(pci_dev); |
902 |
|
903 |
if (pc->exit) {
|
904 |
pc->exit(pci_dev); |
905 |
} |
906 |
|
907 |
do_pci_unregister_device(pci_dev); |
908 |
return 0; |
909 |
} |
910 |
|
911 |
void pci_register_bar(PCIDevice *pci_dev, int region_num, |
912 |
uint8_t type, MemoryRegion *memory) |
913 |
{ |
914 |
PCIIORegion *r; |
915 |
uint32_t addr; |
916 |
uint64_t wmask; |
917 |
pcibus_t size = memory_region_size(memory); |
918 |
|
919 |
assert(region_num >= 0);
|
920 |
assert(region_num < PCI_NUM_REGIONS); |
921 |
if (size & (size-1)) { |
922 |
fprintf(stderr, "ERROR: PCI region size must be pow2 "
|
923 |
"type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size); |
924 |
exit(1);
|
925 |
} |
926 |
|
927 |
r = &pci_dev->io_regions[region_num]; |
928 |
r->addr = PCI_BAR_UNMAPPED; |
929 |
r->size = size; |
930 |
r->type = type; |
931 |
r->memory = NULL;
|
932 |
|
933 |
wmask = ~(size - 1);
|
934 |
addr = pci_bar(pci_dev, region_num); |
935 |
if (region_num == PCI_ROM_SLOT) {
|
936 |
/* ROM enable bit is writable */
|
937 |
wmask |= PCI_ROM_ADDRESS_ENABLE; |
938 |
} |
939 |
pci_set_long(pci_dev->config + addr, type); |
940 |
if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
|
941 |
r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
942 |
pci_set_quad(pci_dev->wmask + addr, wmask); |
943 |
pci_set_quad(pci_dev->cmask + addr, ~0ULL);
|
944 |
} else {
|
945 |
pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
|
946 |
pci_set_long(pci_dev->cmask + addr, 0xffffffff);
|
947 |
} |
948 |
pci_dev->io_regions[region_num].memory = memory; |
949 |
pci_dev->io_regions[region_num].address_space |
950 |
= type & PCI_BASE_ADDRESS_SPACE_IO |
951 |
? pci_dev->bus->address_space_io |
952 |
: pci_dev->bus->address_space_mem; |
953 |
} |
954 |
|
955 |
static void pci_update_vga(PCIDevice *pci_dev) |
956 |
{ |
957 |
uint16_t cmd; |
958 |
|
959 |
if (!pci_dev->has_vga) {
|
960 |
return;
|
961 |
} |
962 |
|
963 |
cmd = pci_get_word(pci_dev->config + PCI_COMMAND); |
964 |
|
965 |
memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], |
966 |
cmd & PCI_COMMAND_MEMORY); |
967 |
memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], |
968 |
cmd & PCI_COMMAND_IO); |
969 |
memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], |
970 |
cmd & PCI_COMMAND_IO); |
971 |
} |
972 |
|
973 |
void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
|
974 |
MemoryRegion *io_lo, MemoryRegion *io_hi) |
975 |
{ |
976 |
assert(!pci_dev->has_vga); |
977 |
|
978 |
assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); |
979 |
pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; |
980 |
memory_region_add_subregion_overlap(pci_dev->bus->address_space_mem, |
981 |
QEMU_PCI_VGA_MEM_BASE, mem, 1);
|
982 |
|
983 |
assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); |
984 |
pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; |
985 |
memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, |
986 |
QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1);
|
987 |
|
988 |
assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); |
989 |
pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; |
990 |
memory_region_add_subregion_overlap(pci_dev->bus->address_space_io, |
991 |
QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1);
|
992 |
pci_dev->has_vga = true;
|
993 |
|
994 |
pci_update_vga(pci_dev); |
995 |
} |
996 |
|
997 |
void pci_unregister_vga(PCIDevice *pci_dev)
|
998 |
{ |
999 |
if (!pci_dev->has_vga) {
|
1000 |
return;
|
1001 |
} |
1002 |
|
1003 |
memory_region_del_subregion(pci_dev->bus->address_space_mem, |
1004 |
pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); |
1005 |
memory_region_del_subregion(pci_dev->bus->address_space_io, |
1006 |
pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); |
1007 |
memory_region_del_subregion(pci_dev->bus->address_space_io, |
1008 |
pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); |
1009 |
pci_dev->has_vga = false;
|
1010 |
} |
1011 |
|
1012 |
pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
|
1013 |
{ |
1014 |
return pci_dev->io_regions[region_num].addr;
|
1015 |
} |
1016 |
|
1017 |
static pcibus_t pci_bar_address(PCIDevice *d,
|
1018 |
int reg, uint8_t type, pcibus_t size)
|
1019 |
{ |
1020 |
pcibus_t new_addr, last_addr; |
1021 |
int bar = pci_bar(d, reg);
|
1022 |
uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); |
1023 |
|
1024 |
if (type & PCI_BASE_ADDRESS_SPACE_IO) {
|
1025 |
if (!(cmd & PCI_COMMAND_IO)) {
|
1026 |
return PCI_BAR_UNMAPPED;
|
1027 |
} |
1028 |
new_addr = pci_get_long(d->config + bar) & ~(size - 1);
|
1029 |
last_addr = new_addr + size - 1;
|
1030 |
/* NOTE: we have only 64K ioports on PC */
|
1031 |
if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) { |
1032 |
return PCI_BAR_UNMAPPED;
|
1033 |
} |
1034 |
return new_addr;
|
1035 |
} |
1036 |
|
1037 |
if (!(cmd & PCI_COMMAND_MEMORY)) {
|
1038 |
return PCI_BAR_UNMAPPED;
|
1039 |
} |
1040 |
if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
|
1041 |
new_addr = pci_get_quad(d->config + bar); |
1042 |
} else {
|
1043 |
new_addr = pci_get_long(d->config + bar); |
1044 |
} |
1045 |
/* the ROM slot has a specific enable bit */
|
1046 |
if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
|
1047 |
return PCI_BAR_UNMAPPED;
|
1048 |
} |
1049 |
new_addr &= ~(size - 1);
|
1050 |
last_addr = new_addr + size - 1;
|
1051 |
/* NOTE: we do not support wrapping */
|
1052 |
/* XXX: as we cannot support really dynamic
|
1053 |
mappings, we handle specific values as invalid
|
1054 |
mappings. */
|
1055 |
if (last_addr <= new_addr || new_addr == 0 || |
1056 |
last_addr == PCI_BAR_UNMAPPED) { |
1057 |
return PCI_BAR_UNMAPPED;
|
1058 |
} |
1059 |
|
1060 |
/* Now pcibus_t is 64bit.
|
1061 |
* Check if 32 bit BAR wraps around explicitly.
|
1062 |
* Without this, PC ide doesn't work well.
|
1063 |
* TODO: remove this work around.
|
1064 |
*/
|
1065 |
if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
|
1066 |
return PCI_BAR_UNMAPPED;
|
1067 |
} |
1068 |
|
1069 |
/*
|
1070 |
* OS is allowed to set BAR beyond its addressable
|
1071 |
* bits. For example, 32 bit OS can set 64bit bar
|
1072 |
* to >4G. Check it. TODO: we might need to support
|
1073 |
* it in the future for e.g. PAE.
|
1074 |
*/
|
1075 |
if (last_addr >= HWADDR_MAX) {
|
1076 |
return PCI_BAR_UNMAPPED;
|
1077 |
} |
1078 |
|
1079 |
return new_addr;
|
1080 |
} |
1081 |
|
1082 |
static void pci_update_mappings(PCIDevice *d) |
1083 |
{ |
1084 |
PCIIORegion *r; |
1085 |
int i;
|
1086 |
pcibus_t new_addr; |
1087 |
|
1088 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
1089 |
r = &d->io_regions[i]; |
1090 |
|
1091 |
/* this region isn't registered */
|
1092 |
if (!r->size)
|
1093 |
continue;
|
1094 |
|
1095 |
new_addr = pci_bar_address(d, i, r->type, r->size); |
1096 |
|
1097 |
/* This bar isn't changed */
|
1098 |
if (new_addr == r->addr)
|
1099 |
continue;
|
1100 |
|
1101 |
/* now do the real mapping */
|
1102 |
if (r->addr != PCI_BAR_UNMAPPED) {
|
1103 |
memory_region_del_subregion(r->address_space, r->memory); |
1104 |
} |
1105 |
r->addr = new_addr; |
1106 |
if (r->addr != PCI_BAR_UNMAPPED) {
|
1107 |
memory_region_add_subregion_overlap(r->address_space, |
1108 |
r->addr, r->memory, 1);
|
1109 |
} |
1110 |
} |
1111 |
|
1112 |
pci_update_vga(d); |
1113 |
} |
1114 |
|
1115 |
static inline int pci_irq_disabled(PCIDevice *d) |
1116 |
{ |
1117 |
return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
|
1118 |
} |
1119 |
|
1120 |
/* Called after interrupt disabled field update in config space,
|
1121 |
* assert/deassert interrupts if necessary.
|
1122 |
* Gets original interrupt disable bit value (before update). */
|
1123 |
static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) |
1124 |
{ |
1125 |
int i, disabled = pci_irq_disabled(d);
|
1126 |
if (disabled == was_irq_disabled)
|
1127 |
return;
|
1128 |
for (i = 0; i < PCI_NUM_PINS; ++i) { |
1129 |
int state = pci_irq_state(d, i);
|
1130 |
pci_change_irq_level(d, i, disabled ? -state : state); |
1131 |
} |
1132 |
} |
1133 |
|
1134 |
uint32_t pci_default_read_config(PCIDevice *d, |
1135 |
uint32_t address, int len)
|
1136 |
{ |
1137 |
uint32_t val = 0;
|
1138 |
|
1139 |
memcpy(&val, d->config + address, len); |
1140 |
return le32_to_cpu(val);
|
1141 |
} |
1142 |
|
1143 |
void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) |
1144 |
{ |
1145 |
int i, was_irq_disabled = pci_irq_disabled(d);
|
1146 |
|
1147 |
for (i = 0; i < l; val >>= 8, ++i) { |
1148 |
uint8_t wmask = d->wmask[addr + i]; |
1149 |
uint8_t w1cmask = d->w1cmask[addr + i]; |
1150 |
assert(!(wmask & w1cmask)); |
1151 |
d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); |
1152 |
d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
|
1153 |
} |
1154 |
if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || |
1155 |
ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
|
1156 |
ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
|
1157 |
range_covers_byte(addr, l, PCI_COMMAND)) |
1158 |
pci_update_mappings(d); |
1159 |
|
1160 |
if (range_covers_byte(addr, l, PCI_COMMAND)) {
|
1161 |
pci_update_irq_disabled(d, was_irq_disabled); |
1162 |
memory_region_set_enabled(&d->bus_master_enable_region, |
1163 |
pci_get_word(d->config + PCI_COMMAND) |
1164 |
& PCI_COMMAND_MASTER); |
1165 |
} |
1166 |
|
1167 |
msi_write_config(d, addr, val, l); |
1168 |
msix_write_config(d, addr, val, l); |
1169 |
} |
1170 |
|
1171 |
/***********************************************************/
|
1172 |
/* generic PCI irq support */
|
1173 |
|
1174 |
/* 0 <= irq_num <= 3. level must be 0 or 1 */
|
1175 |
static void pci_set_irq(void *opaque, int irq_num, int level) |
1176 |
{ |
1177 |
PCIDevice *pci_dev = opaque; |
1178 |
int change;
|
1179 |
|
1180 |
change = level - pci_irq_state(pci_dev, irq_num); |
1181 |
if (!change)
|
1182 |
return;
|
1183 |
|
1184 |
pci_set_irq_state(pci_dev, irq_num, level); |
1185 |
pci_update_irq_status(pci_dev); |
1186 |
if (pci_irq_disabled(pci_dev))
|
1187 |
return;
|
1188 |
pci_change_irq_level(pci_dev, irq_num, change); |
1189 |
} |
1190 |
|
1191 |
/* Special hooks used by device assignment */
|
1192 |
void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
|
1193 |
{ |
1194 |
assert(pci_bus_is_root(bus)); |
1195 |
bus->route_intx_to_irq = route_intx_to_irq; |
1196 |
} |
1197 |
|
1198 |
PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
|
1199 |
{ |
1200 |
PCIBus *bus; |
1201 |
|
1202 |
do {
|
1203 |
bus = dev->bus; |
1204 |
pin = bus->map_irq(dev, pin); |
1205 |
dev = bus->parent_dev; |
1206 |
} while (dev);
|
1207 |
|
1208 |
if (!bus->route_intx_to_irq) {
|
1209 |
error_report("PCI: Bug - unimplemented PCI INTx routing (%s)",
|
1210 |
object_get_typename(OBJECT(bus->qbus.parent))); |
1211 |
return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; |
1212 |
} |
1213 |
|
1214 |
return bus->route_intx_to_irq(bus->irq_opaque, pin);
|
1215 |
} |
1216 |
|
1217 |
bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new)
|
1218 |
{ |
1219 |
return old->mode != new->mode || old->irq != new->irq;
|
1220 |
} |
1221 |
|
1222 |
void pci_bus_fire_intx_routing_notifier(PCIBus *bus)
|
1223 |
{ |
1224 |
PCIDevice *dev; |
1225 |
PCIBus *sec; |
1226 |
int i;
|
1227 |
|
1228 |
for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
1229 |
dev = bus->devices[i]; |
1230 |
if (dev && dev->intx_routing_notifier) {
|
1231 |
dev->intx_routing_notifier(dev); |
1232 |
} |
1233 |
} |
1234 |
|
1235 |
QLIST_FOREACH(sec, &bus->child, sibling) { |
1236 |
pci_bus_fire_intx_routing_notifier(sec); |
1237 |
} |
1238 |
} |
1239 |
|
1240 |
void pci_device_set_intx_routing_notifier(PCIDevice *dev,
|
1241 |
PCIINTxRoutingNotifier notifier) |
1242 |
{ |
1243 |
dev->intx_routing_notifier = notifier; |
1244 |
} |
1245 |
|
1246 |
/*
|
1247 |
* PCI-to-PCI bridge specification
|
1248 |
* 9.1: Interrupt routing. Table 9-1
|
1249 |
*
|
1250 |
* the PCI Express Base Specification, Revision 2.1
|
1251 |
* 2.2.8.1: INTx interrutp signaling - Rules
|
1252 |
* the Implementation Note
|
1253 |
* Table 2-20
|
1254 |
*/
|
1255 |
/*
|
1256 |
* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
|
1257 |
* 0-origin unlike PCI interrupt pin register.
|
1258 |
*/
|
1259 |
int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) |
1260 |
{ |
1261 |
return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
|
1262 |
} |
1263 |
|
1264 |
/***********************************************************/
|
1265 |
/* monitor info on PCI */
|
1266 |
|
1267 |
typedef struct { |
1268 |
uint16_t class; |
1269 |
const char *desc; |
1270 |
const char *fw_name; |
1271 |
uint16_t fw_ign_bits; |
1272 |
} pci_class_desc; |
1273 |
|
1274 |
static const pci_class_desc pci_class_descriptions[] = |
1275 |
{ |
1276 |
{ 0x0001, "VGA controller", "display"}, |
1277 |
{ 0x0100, "SCSI controller", "scsi"}, |
1278 |
{ 0x0101, "IDE controller", "ide"}, |
1279 |
{ 0x0102, "Floppy controller", "fdc"}, |
1280 |
{ 0x0103, "IPI controller", "ipi"}, |
1281 |
{ 0x0104, "RAID controller", "raid"}, |
1282 |
{ 0x0106, "SATA controller"}, |
1283 |
{ 0x0107, "SAS controller"}, |
1284 |
{ 0x0180, "Storage controller"}, |
1285 |
{ 0x0200, "Ethernet controller", "ethernet"}, |
1286 |
{ 0x0201, "Token Ring controller", "token-ring"}, |
1287 |
{ 0x0202, "FDDI controller", "fddi"}, |
1288 |
{ 0x0203, "ATM controller", "atm"}, |
1289 |
{ 0x0280, "Network controller"}, |
1290 |
{ 0x0300, "VGA controller", "display", 0x00ff}, |
1291 |
{ 0x0301, "XGA controller"}, |
1292 |
{ 0x0302, "3D controller"}, |
1293 |
{ 0x0380, "Display controller"}, |
1294 |
{ 0x0400, "Video controller", "video"}, |
1295 |
{ 0x0401, "Audio controller", "sound"}, |
1296 |
{ 0x0402, "Phone"}, |
1297 |
{ 0x0403, "Audio controller", "sound"}, |
1298 |
{ 0x0480, "Multimedia controller"}, |
1299 |
{ 0x0500, "RAM controller", "memory"}, |
1300 |
{ 0x0501, "Flash controller", "flash"}, |
1301 |
{ 0x0580, "Memory controller"}, |
1302 |
{ 0x0600, "Host bridge", "host"}, |
1303 |
{ 0x0601, "ISA bridge", "isa"}, |
1304 |
{ 0x0602, "EISA bridge", "eisa"}, |
1305 |
{ 0x0603, "MC bridge", "mca"}, |
1306 |
{ 0x0604, "PCI bridge", "pci"}, |
1307 |
{ 0x0605, "PCMCIA bridge", "pcmcia"}, |
1308 |
{ 0x0606, "NUBUS bridge", "nubus"}, |
1309 |
{ 0x0607, "CARDBUS bridge", "cardbus"}, |
1310 |
{ 0x0608, "RACEWAY bridge"}, |
1311 |
{ 0x0680, "Bridge"}, |
1312 |
{ 0x0700, "Serial port", "serial"}, |
1313 |
{ 0x0701, "Parallel port", "parallel"}, |
1314 |
{ 0x0800, "Interrupt controller", "interrupt-controller"}, |
1315 |
{ 0x0801, "DMA controller", "dma-controller"}, |
1316 |
{ 0x0802, "Timer", "timer"}, |
1317 |
{ 0x0803, "RTC", "rtc"}, |
1318 |
{ 0x0900, "Keyboard", "keyboard"}, |
1319 |
{ 0x0901, "Pen", "pen"}, |
1320 |
{ 0x0902, "Mouse", "mouse"}, |
1321 |
{ 0x0A00, "Dock station", "dock", 0x00ff}, |
1322 |
{ 0x0B00, "i386 cpu", "cpu", 0x00ff}, |
1323 |
{ 0x0c00, "Fireware contorller", "fireware"}, |
1324 |
{ 0x0c01, "Access bus controller", "access-bus"}, |
1325 |
{ 0x0c02, "SSA controller", "ssa"}, |
1326 |
{ 0x0c03, "USB controller", "usb"}, |
1327 |
{ 0x0c04, "Fibre channel controller", "fibre-channel"}, |
1328 |
{ 0x0c05, "SMBus"}, |
1329 |
{ 0, NULL} |
1330 |
}; |
1331 |
|
1332 |
static void pci_for_each_device_under_bus(PCIBus *bus, |
1333 |
void (*fn)(PCIBus *b, PCIDevice *d,
|
1334 |
void *opaque),
|
1335 |
void *opaque)
|
1336 |
{ |
1337 |
PCIDevice *d; |
1338 |
int devfn;
|
1339 |
|
1340 |
for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
1341 |
d = bus->devices[devfn]; |
1342 |
if (d) {
|
1343 |
fn(bus, d, opaque); |
1344 |
} |
1345 |
} |
1346 |
} |
1347 |
|
1348 |
void pci_for_each_device(PCIBus *bus, int bus_num, |
1349 |
void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), |
1350 |
void *opaque)
|
1351 |
{ |
1352 |
bus = pci_find_bus_nr(bus, bus_num); |
1353 |
|
1354 |
if (bus) {
|
1355 |
pci_for_each_device_under_bus(bus, fn, opaque); |
1356 |
} |
1357 |
} |
1358 |
|
1359 |
static const pci_class_desc *get_class_desc(int class) |
1360 |
{ |
1361 |
const pci_class_desc *desc;
|
1362 |
|
1363 |
desc = pci_class_descriptions; |
1364 |
while (desc->desc && class != desc->class) {
|
1365 |
desc++; |
1366 |
} |
1367 |
|
1368 |
return desc;
|
1369 |
} |
1370 |
|
1371 |
static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); |
1372 |
|
1373 |
static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) |
1374 |
{ |
1375 |
PciMemoryRegionList *head = NULL, *cur_item = NULL; |
1376 |
int i;
|
1377 |
|
1378 |
for (i = 0; i < PCI_NUM_REGIONS; i++) { |
1379 |
const PCIIORegion *r = &dev->io_regions[i];
|
1380 |
PciMemoryRegionList *region; |
1381 |
|
1382 |
if (!r->size) {
|
1383 |
continue;
|
1384 |
} |
1385 |
|
1386 |
region = g_malloc0(sizeof(*region));
|
1387 |
region->value = g_malloc0(sizeof(*region->value));
|
1388 |
|
1389 |
if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
|
1390 |
region->value->type = g_strdup("io");
|
1391 |
} else {
|
1392 |
region->value->type = g_strdup("memory");
|
1393 |
region->value->has_prefetch = true;
|
1394 |
region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); |
1395 |
region->value->has_mem_type_64 = true;
|
1396 |
region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); |
1397 |
} |
1398 |
|
1399 |
region->value->bar = i; |
1400 |
region->value->address = r->addr; |
1401 |
region->value->size = r->size; |
1402 |
|
1403 |
/* XXX: waiting for the qapi to support GSList */
|
1404 |
if (!cur_item) {
|
1405 |
head = cur_item = region; |
1406 |
} else {
|
1407 |
cur_item->next = region; |
1408 |
cur_item = region; |
1409 |
} |
1410 |
} |
1411 |
|
1412 |
return head;
|
1413 |
} |
1414 |
|
1415 |
static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
|
1416 |
int bus_num)
|
1417 |
{ |
1418 |
PciBridgeInfo *info; |
1419 |
|
1420 |
info = g_malloc0(sizeof(*info));
|
1421 |
|
1422 |
info->bus.number = dev->config[PCI_PRIMARY_BUS]; |
1423 |
info->bus.secondary = dev->config[PCI_SECONDARY_BUS]; |
1424 |
info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS]; |
1425 |
|
1426 |
info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range));
|
1427 |
info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); |
1428 |
info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); |
1429 |
|
1430 |
info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range));
|
1431 |
info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); |
1432 |
info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); |
1433 |
|
1434 |
info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range));
|
1435 |
info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); |
1436 |
info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); |
1437 |
|
1438 |
if (dev->config[PCI_SECONDARY_BUS] != 0) { |
1439 |
PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); |
1440 |
if (child_bus) {
|
1441 |
info->has_devices = true;
|
1442 |
info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); |
1443 |
} |
1444 |
} |
1445 |
|
1446 |
return info;
|
1447 |
} |
1448 |
|
1449 |
static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
|
1450 |
int bus_num)
|
1451 |
{ |
1452 |
const pci_class_desc *desc;
|
1453 |
PciDeviceInfo *info; |
1454 |
uint8_t type; |
1455 |
int class;
|
1456 |
|
1457 |
info = g_malloc0(sizeof(*info));
|
1458 |
info->bus = bus_num; |
1459 |
info->slot = PCI_SLOT(dev->devfn); |
1460 |
info->function = PCI_FUNC(dev->devfn); |
1461 |
|
1462 |
class = pci_get_word(dev->config + PCI_CLASS_DEVICE); |
1463 |
info->class_info.class = class; |
1464 |
desc = get_class_desc(class); |
1465 |
if (desc->desc) {
|
1466 |
info->class_info.has_desc = true;
|
1467 |
info->class_info.desc = g_strdup(desc->desc); |
1468 |
} |
1469 |
|
1470 |
info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID); |
1471 |
info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID); |
1472 |
info->regions = qmp_query_pci_regions(dev); |
1473 |
info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
|
1474 |
|
1475 |
if (dev->config[PCI_INTERRUPT_PIN] != 0) { |
1476 |
info->has_irq = true;
|
1477 |
info->irq = dev->config[PCI_INTERRUPT_LINE]; |
1478 |
} |
1479 |
|
1480 |
type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
1481 |
if (type == PCI_HEADER_TYPE_BRIDGE) {
|
1482 |
info->has_pci_bridge = true;
|
1483 |
info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); |
1484 |
} |
1485 |
|
1486 |
return info;
|
1487 |
} |
1488 |
|
1489 |
static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) |
1490 |
{ |
1491 |
PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; |
1492 |
PCIDevice *dev; |
1493 |
int devfn;
|
1494 |
|
1495 |
for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
1496 |
dev = bus->devices[devfn]; |
1497 |
if (dev) {
|
1498 |
info = g_malloc0(sizeof(*info));
|
1499 |
info->value = qmp_query_pci_device(dev, bus, bus_num); |
1500 |
|
1501 |
/* XXX: waiting for the qapi to support GSList */
|
1502 |
if (!cur_item) {
|
1503 |
head = cur_item = info; |
1504 |
} else {
|
1505 |
cur_item->next = info; |
1506 |
cur_item = info; |
1507 |
} |
1508 |
} |
1509 |
} |
1510 |
|
1511 |
return head;
|
1512 |
} |
1513 |
|
1514 |
static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) |
1515 |
{ |
1516 |
PciInfo *info = NULL;
|
1517 |
|
1518 |
bus = pci_find_bus_nr(bus, bus_num); |
1519 |
if (bus) {
|
1520 |
info = g_malloc0(sizeof(*info));
|
1521 |
info->bus = bus_num; |
1522 |
info->devices = qmp_query_pci_devices(bus, bus_num); |
1523 |
} |
1524 |
|
1525 |
return info;
|
1526 |
} |
1527 |
|
1528 |
PciInfoList *qmp_query_pci(Error **errp) |
1529 |
{ |
1530 |
PciInfoList *info, *head = NULL, *cur_item = NULL; |
1531 |
struct PCIHostBus *host;
|
1532 |
|
1533 |
QLIST_FOREACH(host, &host_buses, next) { |
1534 |
info = g_malloc0(sizeof(*info));
|
1535 |
info->value = qmp_query_pci_bus(host->bus, 0);
|
1536 |
|
1537 |
/* XXX: waiting for the qapi to support GSList */
|
1538 |
if (!cur_item) {
|
1539 |
head = cur_item = info; |
1540 |
} else {
|
1541 |
cur_item->next = info; |
1542 |
cur_item = info; |
1543 |
} |
1544 |
} |
1545 |
|
1546 |
return head;
|
1547 |
} |
1548 |
|
1549 |
static const char * const pci_nic_models[] = { |
1550 |
"ne2k_pci",
|
1551 |
"i82551",
|
1552 |
"i82557b",
|
1553 |
"i82559er",
|
1554 |
"rtl8139",
|
1555 |
"e1000",
|
1556 |
"pcnet",
|
1557 |
"virtio",
|
1558 |
NULL
|
1559 |
}; |
1560 |
|
1561 |
static const char * const pci_nic_names[] = { |
1562 |
"ne2k_pci",
|
1563 |
"i82551",
|
1564 |
"i82557b",
|
1565 |
"i82559er",
|
1566 |
"rtl8139",
|
1567 |
"e1000",
|
1568 |
"pcnet",
|
1569 |
"virtio-net-pci",
|
1570 |
NULL
|
1571 |
}; |
1572 |
|
1573 |
/* Initialize a PCI NIC. */
|
1574 |
/* FIXME callers should check for failure, but don't */
|
1575 |
PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model, |
1576 |
const char *default_devaddr) |
1577 |
{ |
1578 |
const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
1579 |
PCIBus *bus; |
1580 |
int devfn;
|
1581 |
PCIDevice *pci_dev; |
1582 |
DeviceState *dev; |
1583 |
int i;
|
1584 |
|
1585 |
i = qemu_find_nic_model(nd, pci_nic_models, default_model); |
1586 |
if (i < 0) |
1587 |
return NULL; |
1588 |
|
1589 |
bus = pci_get_bus_devfn(&devfn, devaddr); |
1590 |
if (!bus) {
|
1591 |
error_report("Invalid PCI device address %s for device %s",
|
1592 |
devaddr, pci_nic_names[i]); |
1593 |
return NULL; |
1594 |
} |
1595 |
|
1596 |
pci_dev = pci_create(bus, devfn, pci_nic_names[i]); |
1597 |
dev = &pci_dev->qdev; |
1598 |
qdev_set_nic_properties(dev, nd); |
1599 |
if (qdev_init(dev) < 0) |
1600 |
return NULL; |
1601 |
return pci_dev;
|
1602 |
} |
1603 |
|
1604 |
PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model, |
1605 |
const char *default_devaddr) |
1606 |
{ |
1607 |
PCIDevice *res; |
1608 |
|
1609 |
if (qemu_show_nic_models(nd->model, pci_nic_models))
|
1610 |
exit(0);
|
1611 |
|
1612 |
res = pci_nic_init(nd, default_model, default_devaddr); |
1613 |
if (!res)
|
1614 |
exit(1);
|
1615 |
return res;
|
1616 |
} |
1617 |
|
1618 |
PCIDevice *pci_vga_init(PCIBus *bus) |
1619 |
{ |
1620 |
switch (vga_interface_type) {
|
1621 |
case VGA_CIRRUS:
|
1622 |
return pci_create_simple(bus, -1, "cirrus-vga"); |
1623 |
case VGA_QXL:
|
1624 |
return pci_create_simple(bus, -1, "qxl-vga"); |
1625 |
case VGA_STD:
|
1626 |
return pci_create_simple(bus, -1, "VGA"); |
1627 |
case VGA_VMWARE:
|
1628 |
return pci_create_simple(bus, -1, "vmware-svga"); |
1629 |
case VGA_NONE:
|
1630 |
default: /* Other non-PCI types. Checking for unsupported types is already |
1631 |
done in vl.c. */
|
1632 |
return NULL; |
1633 |
} |
1634 |
} |
1635 |
|
1636 |
/* Whether a given bus number is in range of the secondary
|
1637 |
* bus of the given bridge device. */
|
1638 |
static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) |
1639 |
{ |
1640 |
return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
|
1641 |
PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
|
1642 |
dev->config[PCI_SECONDARY_BUS] < bus_num && |
1643 |
bus_num <= dev->config[PCI_SUBORDINATE_BUS]; |
1644 |
} |
1645 |
|
1646 |
static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) |
1647 |
{ |
1648 |
PCIBus *sec; |
1649 |
|
1650 |
if (!bus) {
|
1651 |
return NULL; |
1652 |
} |
1653 |
|
1654 |
if (pci_bus_num(bus) == bus_num) {
|
1655 |
return bus;
|
1656 |
} |
1657 |
|
1658 |
/* Consider all bus numbers in range for the host pci bridge. */
|
1659 |
if (!pci_bus_is_root(bus) &&
|
1660 |
!pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { |
1661 |
return NULL; |
1662 |
} |
1663 |
|
1664 |
/* try child bus */
|
1665 |
for (; bus; bus = sec) {
|
1666 |
QLIST_FOREACH(sec, &bus->child, sibling) { |
1667 |
assert(!pci_bus_is_root(sec)); |
1668 |
if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
|
1669 |
return sec;
|
1670 |
} |
1671 |
if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
|
1672 |
break;
|
1673 |
} |
1674 |
} |
1675 |
} |
1676 |
|
1677 |
return NULL; |
1678 |
} |
1679 |
|
1680 |
PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
|
1681 |
{ |
1682 |
bus = pci_find_bus_nr(bus, bus_num); |
1683 |
|
1684 |
if (!bus)
|
1685 |
return NULL; |
1686 |
|
1687 |
return bus->devices[devfn];
|
1688 |
} |
1689 |
|
1690 |
static int pci_qdev_init(DeviceState *qdev) |
1691 |
{ |
1692 |
PCIDevice *pci_dev = (PCIDevice *)qdev; |
1693 |
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); |
1694 |
PCIBus *bus; |
1695 |
int rc;
|
1696 |
bool is_default_rom;
|
1697 |
|
1698 |
/* initialize cap_present for pci_is_express() and pci_config_size() */
|
1699 |
if (pc->is_express) {
|
1700 |
pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; |
1701 |
} |
1702 |
|
1703 |
bus = PCI_BUS(qdev_get_parent_bus(qdev)); |
1704 |
pci_dev = do_pci_register_device(pci_dev, bus, |
1705 |
object_get_typename(OBJECT(qdev)), |
1706 |
pci_dev->devfn); |
1707 |
if (pci_dev == NULL) |
1708 |
return -1; |
1709 |
if (qdev->hotplugged && pc->no_hotplug) {
|
1710 |
qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(pci_dev))); |
1711 |
do_pci_unregister_device(pci_dev); |
1712 |
return -1; |
1713 |
} |
1714 |
if (pc->init) {
|
1715 |
rc = pc->init(pci_dev); |
1716 |
if (rc != 0) { |
1717 |
do_pci_unregister_device(pci_dev); |
1718 |
return rc;
|
1719 |
} |
1720 |
} |
1721 |
|
1722 |
/* rom loading */
|
1723 |
is_default_rom = false;
|
1724 |
if (pci_dev->romfile == NULL && pc->romfile != NULL) { |
1725 |
pci_dev->romfile = g_strdup(pc->romfile); |
1726 |
is_default_rom = true;
|
1727 |
} |
1728 |
pci_add_option_rom(pci_dev, is_default_rom); |
1729 |
|
1730 |
if (bus->hotplug) {
|
1731 |
/* Let buses differentiate between hotplug and when device is
|
1732 |
* enabled during qemu machine creation. */
|
1733 |
rc = bus->hotplug(bus->hotplug_qdev, pci_dev, |
1734 |
qdev->hotplugged ? PCI_HOTPLUG_ENABLED: |
1735 |
PCI_COLDPLUG_ENABLED); |
1736 |
if (rc != 0) { |
1737 |
int r = pci_unregister_device(&pci_dev->qdev);
|
1738 |
assert(!r); |
1739 |
return rc;
|
1740 |
} |
1741 |
} |
1742 |
return 0; |
1743 |
} |
1744 |
|
1745 |
static int pci_unplug_device(DeviceState *qdev) |
1746 |
{ |
1747 |
PCIDevice *dev = PCI_DEVICE(qdev); |
1748 |
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); |
1749 |
|
1750 |
if (pc->no_hotplug) {
|
1751 |
qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(dev))); |
1752 |
return -1; |
1753 |
} |
1754 |
return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
|
1755 |
PCI_HOTPLUG_DISABLED); |
1756 |
} |
1757 |
|
1758 |
PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
1759 |
const char *name) |
1760 |
{ |
1761 |
DeviceState *dev; |
1762 |
|
1763 |
dev = qdev_create(&bus->qbus, name); |
1764 |
qdev_prop_set_int32(dev, "addr", devfn);
|
1765 |
qdev_prop_set_bit(dev, "multifunction", multifunction);
|
1766 |
return PCI_DEVICE(dev);
|
1767 |
} |
1768 |
|
1769 |
PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
|
1770 |
bool multifunction,
|
1771 |
const char *name) |
1772 |
{ |
1773 |
PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); |
1774 |
qdev_init_nofail(&dev->qdev); |
1775 |
return dev;
|
1776 |
} |
1777 |
|
1778 |
PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) |
1779 |
{ |
1780 |
return pci_create_multifunction(bus, devfn, false, name); |
1781 |
} |
1782 |
|
1783 |
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) |
1784 |
{ |
1785 |
return pci_create_simple_multifunction(bus, devfn, false, name); |
1786 |
} |
1787 |
|
1788 |
static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
|
1789 |
{ |
1790 |
int offset = PCI_CONFIG_HEADER_SIZE;
|
1791 |
int i;
|
1792 |
for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) {
|
1793 |
if (pdev->used[i])
|
1794 |
offset = i + 1;
|
1795 |
else if (i - offset + 1 == size) |
1796 |
return offset;
|
1797 |
} |
1798 |
return 0; |
1799 |
} |
1800 |
|
1801 |
static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
|
1802 |
uint8_t *prev_p) |
1803 |
{ |
1804 |
uint8_t next, prev; |
1805 |
|
1806 |
if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
|
1807 |
return 0; |
1808 |
|
1809 |
for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
|
1810 |
prev = next + PCI_CAP_LIST_NEXT) |
1811 |
if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
|
1812 |
break;
|
1813 |
|
1814 |
if (prev_p)
|
1815 |
*prev_p = prev; |
1816 |
return next;
|
1817 |
} |
1818 |
|
1819 |
static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
|
1820 |
{ |
1821 |
uint8_t next, prev, found = 0;
|
1822 |
|
1823 |
if (!(pdev->used[offset])) {
|
1824 |
return 0; |
1825 |
} |
1826 |
|
1827 |
assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); |
1828 |
|
1829 |
for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
|
1830 |
prev = next + PCI_CAP_LIST_NEXT) { |
1831 |
if (next <= offset && next > found) {
|
1832 |
found = next; |
1833 |
} |
1834 |
} |
1835 |
return found;
|
1836 |
} |
1837 |
|
1838 |
/* Patch the PCI vendor and device ids in a PCI rom image if necessary.
|
1839 |
This is needed for an option rom which is used for more than one device. */
|
1840 |
static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) |
1841 |
{ |
1842 |
uint16_t vendor_id; |
1843 |
uint16_t device_id; |
1844 |
uint16_t rom_vendor_id; |
1845 |
uint16_t rom_device_id; |
1846 |
uint16_t rom_magic; |
1847 |
uint16_t pcir_offset; |
1848 |
uint8_t checksum; |
1849 |
|
1850 |
/* Words in rom data are little endian (like in PCI configuration),
|
1851 |
so they can be read / written with pci_get_word / pci_set_word. */
|
1852 |
|
1853 |
/* Only a valid rom will be patched. */
|
1854 |
rom_magic = pci_get_word(ptr); |
1855 |
if (rom_magic != 0xaa55) { |
1856 |
PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
|
1857 |
return;
|
1858 |
} |
1859 |
pcir_offset = pci_get_word(ptr + 0x18);
|
1860 |
if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) { |
1861 |
PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
|
1862 |
return;
|
1863 |
} |
1864 |
|
1865 |
vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); |
1866 |
device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); |
1867 |
rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
|
1868 |
rom_device_id = pci_get_word(ptr + pcir_offset + 6);
|
1869 |
|
1870 |
PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
|
1871 |
vendor_id, device_id, rom_vendor_id, rom_device_id); |
1872 |
|
1873 |
checksum = ptr[6];
|
1874 |
|
1875 |
if (vendor_id != rom_vendor_id) {
|
1876 |
/* Patch vendor id and checksum (at offset 6 for etherboot roms). */
|
1877 |
checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
|
1878 |
checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
|
1879 |
PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); |
1880 |
ptr[6] = checksum;
|
1881 |
pci_set_word(ptr + pcir_offset + 4, vendor_id);
|
1882 |
} |
1883 |
|
1884 |
if (device_id != rom_device_id) {
|
1885 |
/* Patch device id and checksum (at offset 6 for etherboot roms). */
|
1886 |
checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
|
1887 |
checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
|
1888 |
PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum); |
1889 |
ptr[6] = checksum;
|
1890 |
pci_set_word(ptr + pcir_offset + 6, device_id);
|
1891 |
} |
1892 |
} |
1893 |
|
1894 |
/* Add an option rom for the device */
|
1895 |
static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom) |
1896 |
{ |
1897 |
int size;
|
1898 |
char *path;
|
1899 |
void *ptr;
|
1900 |
char name[32]; |
1901 |
const VMStateDescription *vmsd;
|
1902 |
|
1903 |
if (!pdev->romfile)
|
1904 |
return 0; |
1905 |
if (strlen(pdev->romfile) == 0) |
1906 |
return 0; |
1907 |
|
1908 |
if (!pdev->rom_bar) {
|
1909 |
/*
|
1910 |
* Load rom via fw_cfg instead of creating a rom bar,
|
1911 |
* for 0.11 compatibility.
|
1912 |
*/
|
1913 |
int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
|
1914 |
if (class == 0x0300) { |
1915 |
rom_add_vga(pdev->romfile); |
1916 |
} else {
|
1917 |
rom_add_option(pdev->romfile, -1);
|
1918 |
} |
1919 |
return 0; |
1920 |
} |
1921 |
|
1922 |
path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); |
1923 |
if (path == NULL) { |
1924 |
path = g_strdup(pdev->romfile); |
1925 |
} |
1926 |
|
1927 |
size = get_image_size(path); |
1928 |
if (size < 0) { |
1929 |
error_report("%s: failed to find romfile \"%s\"",
|
1930 |
__func__, pdev->romfile); |
1931 |
g_free(path); |
1932 |
return -1; |
1933 |
} else if (size == 0) { |
1934 |
error_report("%s: ignoring empty romfile \"%s\"",
|
1935 |
__func__, pdev->romfile); |
1936 |
g_free(path); |
1937 |
return -1; |
1938 |
} |
1939 |
if (size & (size - 1)) { |
1940 |
size = 1 << qemu_fls(size);
|
1941 |
} |
1942 |
|
1943 |
vmsd = qdev_get_vmsd(DEVICE(pdev)); |
1944 |
|
1945 |
if (vmsd) {
|
1946 |
snprintf(name, sizeof(name), "%s.rom", vmsd->name); |
1947 |
} else {
|
1948 |
snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); |
1949 |
} |
1950 |
pdev->has_rom = true;
|
1951 |
memory_region_init_ram(&pdev->rom, name, size); |
1952 |
vmstate_register_ram(&pdev->rom, &pdev->qdev); |
1953 |
ptr = memory_region_get_ram_ptr(&pdev->rom); |
1954 |
load_image(path, ptr); |
1955 |
g_free(path); |
1956 |
|
1957 |
if (is_default_rom) {
|
1958 |
/* Only the default rom images will be patched (if needed). */
|
1959 |
pci_patch_ids(pdev, ptr, size); |
1960 |
} |
1961 |
|
1962 |
pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
|
1963 |
|
1964 |
return 0; |
1965 |
} |
1966 |
|
1967 |
static void pci_del_option_rom(PCIDevice *pdev) |
1968 |
{ |
1969 |
if (!pdev->has_rom)
|
1970 |
return;
|
1971 |
|
1972 |
vmstate_unregister_ram(&pdev->rom, &pdev->qdev); |
1973 |
memory_region_destroy(&pdev->rom); |
1974 |
pdev->has_rom = false;
|
1975 |
} |
1976 |
|
1977 |
/*
|
1978 |
* if !offset
|
1979 |
* Reserve space and add capability to the linked list in pci config space
|
1980 |
*
|
1981 |
* if offset = 0,
|
1982 |
* Find and reserve space and add capability to the linked list
|
1983 |
* in pci config space */
|
1984 |
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
|
1985 |
uint8_t offset, uint8_t size) |
1986 |
{ |
1987 |
uint8_t *config; |
1988 |
int i, overlapping_cap;
|
1989 |
|
1990 |
if (!offset) {
|
1991 |
offset = pci_find_space(pdev, size); |
1992 |
if (!offset) {
|
1993 |
return -ENOSPC;
|
1994 |
} |
1995 |
} else {
|
1996 |
/* Verify that capabilities don't overlap. Note: device assignment
|
1997 |
* depends on this check to verify that the device is not broken.
|
1998 |
* Should never trigger for emulated devices, but it's helpful
|
1999 |
* for debugging these. */
|
2000 |
for (i = offset; i < offset + size; i++) {
|
2001 |
overlapping_cap = pci_find_capability_at_offset(pdev, i); |
2002 |
if (overlapping_cap) {
|
2003 |
fprintf(stderr, "ERROR: %04x:%02x:%02x.%x "
|
2004 |
"Attempt to add PCI capability %x at offset "
|
2005 |
"%x overlaps existing capability %x at offset %x\n",
|
2006 |
pci_find_domain(pdev->bus), pci_bus_num(pdev->bus), |
2007 |
PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), |
2008 |
cap_id, offset, overlapping_cap, i); |
2009 |
return -EINVAL;
|
2010 |
} |
2011 |
} |
2012 |
} |
2013 |
|
2014 |
config = pdev->config + offset; |
2015 |
config[PCI_CAP_LIST_ID] = cap_id; |
2016 |
config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; |
2017 |
pdev->config[PCI_CAPABILITY_LIST] = offset; |
2018 |
pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; |
2019 |
memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); |
2020 |
/* Make capability read-only by default */
|
2021 |
memset(pdev->wmask + offset, 0, size);
|
2022 |
/* Check capability by default */
|
2023 |
memset(pdev->cmask + offset, 0xFF, size);
|
2024 |
return offset;
|
2025 |
} |
2026 |
|
2027 |
/* Unlink capability from the pci config space. */
|
2028 |
void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
2029 |
{ |
2030 |
uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); |
2031 |
if (!offset)
|
2032 |
return;
|
2033 |
pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; |
2034 |
/* Make capability writable again */
|
2035 |
memset(pdev->wmask + offset, 0xff, size);
|
2036 |
memset(pdev->w1cmask + offset, 0, size);
|
2037 |
/* Clear cmask as device-specific registers can't be checked */
|
2038 |
memset(pdev->cmask + offset, 0, size);
|
2039 |
memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); |
2040 |
|
2041 |
if (!pdev->config[PCI_CAPABILITY_LIST])
|
2042 |
pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; |
2043 |
} |
2044 |
|
2045 |
uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) |
2046 |
{ |
2047 |
return pci_find_capability_list(pdev, cap_id, NULL); |
2048 |
} |
2049 |
|
2050 |
static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) |
2051 |
{ |
2052 |
PCIDevice *d = (PCIDevice *)dev; |
2053 |
const pci_class_desc *desc;
|
2054 |
char ctxt[64]; |
2055 |
PCIIORegion *r; |
2056 |
int i, class;
|
2057 |
|
2058 |
class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
2059 |
desc = pci_class_descriptions; |
2060 |
while (desc->desc && class != desc->class)
|
2061 |
desc++; |
2062 |
if (desc->desc) {
|
2063 |
snprintf(ctxt, sizeof(ctxt), "%s", desc->desc); |
2064 |
} else {
|
2065 |
snprintf(ctxt, sizeof(ctxt), "Class %04x", class); |
2066 |
} |
2067 |
|
2068 |
monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
|
2069 |
"pci id %04x:%04x (sub %04x:%04x)\n",
|
2070 |
indent, "", ctxt, pci_bus_num(d->bus),
|
2071 |
PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), |
2072 |
pci_get_word(d->config + PCI_VENDOR_ID), |
2073 |
pci_get_word(d->config + PCI_DEVICE_ID), |
2074 |
pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), |
2075 |
pci_get_word(d->config + PCI_SUBSYSTEM_ID)); |
2076 |
for (i = 0; i < PCI_NUM_REGIONS; i++) { |
2077 |
r = &d->io_regions[i]; |
2078 |
if (!r->size)
|
2079 |
continue;
|
2080 |
monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
|
2081 |
" [0x%"FMT_PCIBUS"]\n", |
2082 |
indent, "",
|
2083 |
i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem", |
2084 |
r->addr, r->addr + r->size - 1);
|
2085 |
} |
2086 |
} |
2087 |
|
2088 |
static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) |
2089 |
{ |
2090 |
PCIDevice *d = (PCIDevice *)dev; |
2091 |
const char *name = NULL; |
2092 |
const pci_class_desc *desc = pci_class_descriptions;
|
2093 |
int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
|
2094 |
|
2095 |
while (desc->desc &&
|
2096 |
(class & ~desc->fw_ign_bits) != |
2097 |
(desc->class & ~desc->fw_ign_bits)) { |
2098 |
desc++; |
2099 |
} |
2100 |
|
2101 |
if (desc->desc) {
|
2102 |
name = desc->fw_name; |
2103 |
} |
2104 |
|
2105 |
if (name) {
|
2106 |
pstrcpy(buf, len, name); |
2107 |
} else {
|
2108 |
snprintf(buf, len, "pci%04x,%04x",
|
2109 |
pci_get_word(d->config + PCI_VENDOR_ID), |
2110 |
pci_get_word(d->config + PCI_DEVICE_ID)); |
2111 |
} |
2112 |
|
2113 |
return buf;
|
2114 |
} |
2115 |
|
2116 |
static char *pcibus_get_fw_dev_path(DeviceState *dev) |
2117 |
{ |
2118 |
PCIDevice *d = (PCIDevice *)dev; |
2119 |
char path[50], name[33]; |
2120 |
int off;
|
2121 |
|
2122 |
off = snprintf(path, sizeof(path), "%s@%x", |
2123 |
pci_dev_fw_name(dev, name, sizeof name),
|
2124 |
PCI_SLOT(d->devfn)); |
2125 |
if (PCI_FUNC(d->devfn))
|
2126 |
snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn)); |
2127 |
return g_strdup(path);
|
2128 |
} |
2129 |
|
2130 |
static char *pcibus_get_dev_path(DeviceState *dev) |
2131 |
{ |
2132 |
PCIDevice *d = container_of(dev, PCIDevice, qdev); |
2133 |
PCIDevice *t; |
2134 |
int slot_depth;
|
2135 |
/* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
|
2136 |
* 00 is added here to make this format compatible with
|
2137 |
* domain:Bus:Slot.Func for systems without nested PCI bridges.
|
2138 |
* Slot.Function list specifies the slot and function numbers for all
|
2139 |
* devices on the path from root to the specific device. */
|
2140 |
char domain[] = "DDDD:00"; |
2141 |
char slot[] = ":SS.F"; |
2142 |
int domain_len = sizeof domain - 1 /* For '\0' */; |
2143 |
int slot_len = sizeof slot - 1 /* For '\0' */; |
2144 |
int path_len;
|
2145 |
char *path, *p;
|
2146 |
int s;
|
2147 |
|
2148 |
/* Calculate # of slots on path between device and root. */;
|
2149 |
slot_depth = 0;
|
2150 |
for (t = d; t; t = t->bus->parent_dev) {
|
2151 |
++slot_depth; |
2152 |
} |
2153 |
|
2154 |
path_len = domain_len + slot_len * slot_depth; |
2155 |
|
2156 |
/* Allocate memory, fill in the terminating null byte. */
|
2157 |
path = g_malloc(path_len + 1 /* For '\0' */); |
2158 |
path[path_len] = '\0';
|
2159 |
|
2160 |
/* First field is the domain. */
|
2161 |
s = snprintf(domain, sizeof domain, "%04x:00", pci_find_domain(d->bus)); |
2162 |
assert(s == domain_len); |
2163 |
memcpy(path, domain, domain_len); |
2164 |
|
2165 |
/* Fill in slot numbers. We walk up from device to root, so need to print
|
2166 |
* them in the reverse order, last to first. */
|
2167 |
p = path + path_len; |
2168 |
for (t = d; t; t = t->bus->parent_dev) {
|
2169 |
p -= slot_len; |
2170 |
s = snprintf(slot, sizeof slot, ":%02x.%x", |
2171 |
PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); |
2172 |
assert(s == slot_len); |
2173 |
memcpy(p, slot, slot_len); |
2174 |
} |
2175 |
|
2176 |
return path;
|
2177 |
} |
2178 |
|
2179 |
static int pci_qdev_find_recursive(PCIBus *bus, |
2180 |
const char *id, PCIDevice **pdev) |
2181 |
{ |
2182 |
DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); |
2183 |
if (!qdev) {
|
2184 |
return -ENODEV;
|
2185 |
} |
2186 |
|
2187 |
/* roughly check if given qdev is pci device */
|
2188 |
if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
|
2189 |
*pdev = PCI_DEVICE(qdev); |
2190 |
return 0; |
2191 |
} |
2192 |
return -EINVAL;
|
2193 |
} |
2194 |
|
2195 |
int pci_qdev_find_device(const char *id, PCIDevice **pdev) |
2196 |
{ |
2197 |
struct PCIHostBus *host;
|
2198 |
int rc = -ENODEV;
|
2199 |
|
2200 |
QLIST_FOREACH(host, &host_buses, next) { |
2201 |
int tmp = pci_qdev_find_recursive(host->bus, id, pdev);
|
2202 |
if (!tmp) {
|
2203 |
rc = 0;
|
2204 |
break;
|
2205 |
} |
2206 |
if (tmp != -ENODEV) {
|
2207 |
rc = tmp; |
2208 |
} |
2209 |
} |
2210 |
|
2211 |
return rc;
|
2212 |
} |
2213 |
|
2214 |
MemoryRegion *pci_address_space(PCIDevice *dev) |
2215 |
{ |
2216 |
return dev->bus->address_space_mem;
|
2217 |
} |
2218 |
|
2219 |
MemoryRegion *pci_address_space_io(PCIDevice *dev) |
2220 |
{ |
2221 |
return dev->bus->address_space_io;
|
2222 |
} |
2223 |
|
2224 |
static void pci_device_class_init(ObjectClass *klass, void *data) |
2225 |
{ |
2226 |
DeviceClass *k = DEVICE_CLASS(klass); |
2227 |
k->init = pci_qdev_init; |
2228 |
k->unplug = pci_unplug_device; |
2229 |
k->exit = pci_unregister_device; |
2230 |
k->bus_type = TYPE_PCI_BUS; |
2231 |
k->props = pci_props; |
2232 |
} |
2233 |
|
2234 |
void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) |
2235 |
{ |
2236 |
bus->iommu_fn = fn; |
2237 |
bus->iommu_opaque = opaque; |
2238 |
} |
2239 |
|
2240 |
static const TypeInfo pci_device_type_info = { |
2241 |
.name = TYPE_PCI_DEVICE, |
2242 |
.parent = TYPE_DEVICE, |
2243 |
.instance_size = sizeof(PCIDevice),
|
2244 |
.abstract = true,
|
2245 |
.class_size = sizeof(PCIDeviceClass),
|
2246 |
.class_init = pci_device_class_init, |
2247 |
}; |
2248 |
|
2249 |
static void pci_register_types(void) |
2250 |
{ |
2251 |
type_register_static(&pci_bus_info); |
2252 |
type_register_static(&pcie_bus_info); |
2253 |
type_register_static(&pci_device_type_info); |
2254 |
} |
2255 |
|
2256 |
type_init(pci_register_types) |