Revision e023e832 target-s390x/translate.c

b/target-s390x/translate.c
2 2
 *  S/390 translation
3 3
 *
4 4
 *  Copyright (c) 2009 Ulrich Hecht
5
 *  Copyright (c) 2010 Alexander Graf
5 6
 *
6 7
 * This library is free software; you can redistribute it and/or
7 8
 * modify it under the terms of the GNU Lesser General Public
......
16 17
 * You should have received a copy of the GNU Lesser General Public
17 18
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 19
 */
20
#include <stdarg.h>
21
#include <stdlib.h>
22
#include <stdio.h>
23
#include <string.h>
24
#include <inttypes.h>
25

  
26
/* #define DEBUG_ILLEGAL_INSTRUCTIONS */
27
/* #define DEBUG_INLINE_BRANCHES */
28
#define S390X_DEBUG_DISAS
29
/* #define S390X_DEBUG_DISAS_VERBOSE */
30

  
31
#ifdef S390X_DEBUG_DISAS_VERBOSE
32
#  define LOG_DISAS(...) qemu_log(__VA_ARGS__)
33
#else
34
#  define LOG_DISAS(...) do { } while (0)
35
#endif
19 36

  
20 37
#include "cpu.h"
21 38
#include "exec-all.h"
......
23 40
#include "tcg-op.h"
24 41
#include "qemu-log.h"
25 42

  
43
/* global register indexes */
44
static TCGv_ptr cpu_env;
45

  
46
#include "gen-icount.h"
47
#include "helpers.h"
48
#define GEN_HELPER 1
49
#include "helpers.h"
50

  
51
typedef struct DisasContext DisasContext;
52
struct DisasContext {
53
    uint64_t pc;
54
    int is_jmp;
55
    enum cc_op cc_op;
56
    struct TranslationBlock *tb;
57
};
58

  
59
#define DISAS_EXCP 4
60

  
61
static void gen_op_calc_cc(DisasContext *s);
62

  
63
#ifdef DEBUG_INLINE_BRANCHES
64
static uint64_t inline_branch_hit[CC_OP_MAX];
65
static uint64_t inline_branch_miss[CC_OP_MAX];
66
#endif
67

  
68
static inline void debug_insn(uint64_t insn)
69
{
70
    LOG_DISAS("insn: 0x%" PRIx64 "\n", insn);
71
}
72

  
73
static inline uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
74
{
75
    if (!(s->tb->flags & FLAG_MASK_64)) {
76
        if (s->tb->flags & FLAG_MASK_32) {
77
            return pc | 0x80000000;
78
        }
79
    }
80
    return pc;
81
}
82

  
26 83
void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
27 84
                    int flags)
28 85
{
29 86
    int i;
87

  
30 88
    for (i = 0; i < 16; i++) {
31
        cpu_fprintf(f, "R%02d=%016lx", i, env->regs[i]);
89
        cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
32 90
        if ((i % 4) == 3) {
33 91
            cpu_fprintf(f, "\n");
34 92
        } else {
35 93
            cpu_fprintf(f, " ");
36 94
        }
37 95
    }
96

  
38 97
    for (i = 0; i < 16; i++) {
39 98
        cpu_fprintf(f, "F%02d=%016" PRIx64, i, *(uint64_t *)&env->fregs[i]);
40 99
        if ((i % 4) == 3) {
......
43 102
            cpu_fprintf(f, " ");
44 103
        }
45 104
    }
46
    cpu_fprintf(f, "PSW=mask %016lx addr %016lx cc %02x\n", env->psw.mask, env->psw.addr, env->cc);
105

  
106
    cpu_fprintf(f, "\n");
107

  
108
#ifndef CONFIG_USER_ONLY
109
    for (i = 0; i < 16; i++) {
110
        cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
111
        if ((i % 4) == 3) {
112
            cpu_fprintf(f, "\n");
113
        } else {
114
            cpu_fprintf(f, " ");
115
        }
116
    }
117
#endif
118

  
119
    cpu_fprintf(f, "\n");
120

  
121
    if (env->cc_op > 3) {
122
        cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
123
                    env->psw.mask, env->psw.addr, cc_name(env->cc_op));
124
    } else {
125
        cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
126
                    env->psw.mask, env->psw.addr, env->cc_op);
127
    }
128

  
129
#ifdef DEBUG_INLINE_BRANCHES
130
    for (i = 0; i < CC_OP_MAX; i++) {
131
        cpu_fprintf(f, "  %15s = %10ld\t%10ld\n", cc_name(i),
132
                    inline_branch_miss[i], inline_branch_hit[i]);
133
    }
134
#endif
47 135
}
48 136

  
137
static TCGv_i64 psw_addr;
138
static TCGv_i64 psw_mask;
139

  
140
static TCGv_i32 cc_op;
141
static TCGv_i64 cc_src;
142
static TCGv_i64 cc_dst;
143
static TCGv_i64 cc_vr;
144

  
145
static char cpu_reg_names[10*3 + 6*4];
146
static TCGv_i64 regs[16];
147

  
148
static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
149

  
49 150
void s390x_translate_init(void)
50 151
{
152
    int i;
153
    size_t cpu_reg_names_size = sizeof(cpu_reg_names);
154
    char *p;
155

  
156
    cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
157
    psw_addr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, psw.addr),
158
                                      "psw_addr");
159
    psw_mask = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, psw.mask),
160
                                      "psw_mask");
161

  
162
    cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, cc_op),
163
                                   "cc_op");
164
    cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, cc_src),
165
                                    "cc_src");
166
    cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, cc_dst),
167
                                    "cc_dst");
168
    cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, cc_vr),
169
                                   "cc_vr");
170

  
171
    p = cpu_reg_names;
172
    for (i = 0; i < 16; i++) {
173
        snprintf(p, cpu_reg_names_size, "r%d", i);
174
        regs[i] = tcg_global_mem_new(TCG_AREG0,
175
                                     offsetof(CPUState, regs[i]), p);
176
        p += (i < 10) ? 3 : 4;
177
        cpu_reg_names_size -= (i < 10) ? 3 : 4;
178
    }
51 179
}
52 180

  
53
void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
181
static inline TCGv_i64 load_reg(int reg)
54 182
{
183
    TCGv_i64 r = tcg_temp_new_i64();
184
    tcg_gen_mov_i64(r, regs[reg]);
185
    return r;
55 186
}
56 187

  
57
void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
188
static inline TCGv_i64 load_freg(int reg)
58 189
{
190
    TCGv_i64 r = tcg_temp_new_i64();
191
    tcg_gen_ld_i64(r, cpu_env, offsetof(CPUState, fregs[reg].d));
192
    return r;
59 193
}
60 194

  
61
void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
195
static inline TCGv_i32 load_freg32(int reg)
62 196
{
63
    env->psw.addr = gen_opc_pc[pc_pos];
197
    TCGv_i32 r = tcg_temp_new_i32();
198
    tcg_gen_ld_i32(r, cpu_env, offsetof(CPUState, fregs[reg].l.upper));
199
    return r;
200
}
201

  
202
static inline TCGv_i32 load_reg32(int reg)
203
{
204
    TCGv_i32 r = tcg_temp_new_i32();
205
    tcg_gen_trunc_i64_i32(r, regs[reg]);
206
    return r;
207
}
208

  
209
static inline TCGv_i64 load_reg32_i64(int reg)
210
{
211
    TCGv_i64 r = tcg_temp_new_i64();
212
    tcg_gen_ext32s_i64(r, regs[reg]);
213
    return r;
214
}
215

  
216
static inline void store_reg(int reg, TCGv_i64 v)
217
{
218
    tcg_gen_mov_i64(regs[reg], v);
219
}
220

  
221
static inline void store_freg(int reg, TCGv_i64 v)
222
{
223
    tcg_gen_st_i64(v, cpu_env, offsetof(CPUState, fregs[reg].d));
224
}
225

  
226
static inline void store_reg32(int reg, TCGv_i32 v)
227
{
228
#if HOST_LONG_BITS == 32
229
    tcg_gen_mov_i32(TCGV_LOW(regs[reg]), v);
230
#else
231
    TCGv_i64 tmp = tcg_temp_new_i64();
232
    tcg_gen_extu_i32_i64(tmp, v);
233
    /* 32 bit register writes keep the upper half */
234
    tcg_gen_deposit_i64(regs[reg], regs[reg], tmp, 0, 32);
235
    tcg_temp_free_i64(tmp);
236
#endif
237
}
238

  
239
static inline void store_reg32_i64(int reg, TCGv_i64 v)
240
{
241
    /* 32 bit register writes keep the upper half */
242
#if HOST_LONG_BITS == 32
243
    tcg_gen_mov_i32(TCGV_LOW(regs[reg]), TCGV_LOW(v));
244
#else
245
    tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
246
#endif
247
}
248

  
249
static inline void store_reg16(int reg, TCGv_i32 v)
250
{
251
    TCGv_i64 tmp = tcg_temp_new_i64();
252
    tcg_gen_extu_i32_i64(tmp, v);
253
    /* 16 bit register writes keep the upper bytes */
254
    tcg_gen_deposit_i64(regs[reg], regs[reg], tmp, 0, 16);
255
    tcg_temp_free_i64(tmp);
256
}
257

  
258
static inline void store_reg8(int reg, TCGv_i64 v)
259
{
260
    /* 8 bit register writes keep the upper bytes */
261
    tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 8);
262
}
263

  
264
static inline void store_freg32(int reg, TCGv_i32 v)
265
{
266
    tcg_gen_st_i32(v, cpu_env, offsetof(CPUState, fregs[reg].l.upper));
267
}
268

  
269
static inline void update_psw_addr(DisasContext *s)
270
{
271
    /* psw.addr */
272
    tcg_gen_movi_i64(psw_addr, s->pc);
273
}
274

  
275
static inline void potential_page_fault(DisasContext *s)
276
{
277
#ifndef CONFIG_USER_ONLY
278
    update_psw_addr(s);
279
    gen_op_calc_cc(s);
280
#endif
281
}
282

  
283
static inline uint64_t ld_code2(uint64_t pc)
284
{
285
    return (uint64_t)lduw_code(pc);
286
}
287

  
288
static inline uint64_t ld_code4(uint64_t pc)
289
{
290
    return (uint64_t)ldl_code(pc);
291
}
292

  
293
static inline uint64_t ld_code6(uint64_t pc)
294
{
295
    uint64_t opc;
296
    opc = (uint64_t)lduw_code(pc) << 32;
297
    opc |= (uint64_t)(uint32_t)ldl_code(pc+2);
298
    return opc;
299
}
300

  
301
static inline int get_mem_index(DisasContext *s)
302
{
303
    switch (s->tb->flags & FLAG_MASK_ASC) {
304
    case PSW_ASC_PRIMARY >> 32:
305
        return 0;
306
    case PSW_ASC_SECONDARY >> 32:
307
        return 1;
308
    case PSW_ASC_HOME >> 32:
309
        return 2;
310
    default:
311
        tcg_abort();
312
        break;
313
    }
314
}
315

  
316
static inline void gen_debug(DisasContext *s)
317
{
318
    TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
319
    update_psw_addr(s);
320
    gen_op_calc_cc(s);
321
    gen_helper_exception(tmp);
322
    tcg_temp_free_i32(tmp);
323
    s->is_jmp = DISAS_EXCP;
324
}
325

  
326
#ifdef CONFIG_USER_ONLY
327

  
328
static void gen_illegal_opcode(DisasContext *s, int ilc)
329
{
330
    TCGv_i32 tmp = tcg_const_i32(EXCP_SPEC);
331
    update_psw_addr(s);
332
    gen_op_calc_cc(s);
333
    gen_helper_exception(tmp);
334
    tcg_temp_free_i32(tmp);
335
    s->is_jmp = DISAS_EXCP;
336
}
337

  
338
#else /* CONFIG_USER_ONLY */
339

  
340
static void debug_print_inst(DisasContext *s, int ilc)
341
{
342
#ifdef DEBUG_ILLEGAL_INSTRUCTIONS
343
    uint64_t inst = 0;
344

  
345
    switch (ilc & 3) {
346
    case 1:
347
        inst = ld_code2(s->pc);
348
        break;
349
    case 2:
350
        inst = ld_code4(s->pc);
351
        break;
352
    case 3:
353
        inst = ld_code6(s->pc);
354
        break;
355
    }
356

  
357
    fprintf(stderr, "Illegal instruction [%d at %016" PRIx64 "]: 0x%016"
358
            PRIx64 "\n", ilc, s->pc, inst);
359
#endif
360
}
361

  
362
static void gen_program_exception(DisasContext *s, int ilc, int code)
363
{
364
    TCGv_i32 tmp;
365

  
366
    debug_print_inst(s, ilc);
367

  
368
    /* remember what pgm exeption this was */
369
    tmp = tcg_const_i32(code);
370
    tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, int_pgm_code));
371
    tcg_temp_free_i32(tmp);
372

  
373
    tmp = tcg_const_i32(ilc);
374
    tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, int_pgm_ilc));
375
    tcg_temp_free_i32(tmp);
376

  
377
    /* advance past instruction */
378
    s->pc += (ilc * 2);
379
    update_psw_addr(s);
380

  
381
    /* save off cc */
382
    gen_op_calc_cc(s);
383

  
384
    /* trigger exception */
385
    tmp = tcg_const_i32(EXCP_PGM);
386
    gen_helper_exception(tmp);
387
    tcg_temp_free_i32(tmp);
388

  
389
    /* end TB here */
390
    s->is_jmp = DISAS_EXCP;
391
}
392

  
393

  
394
static void gen_illegal_opcode(DisasContext *s, int ilc)
395
{
396
    gen_program_exception(s, ilc, PGM_SPECIFICATION);
397
}
398

  
399
static void gen_privileged_exception(DisasContext *s, int ilc)
400
{
401
    gen_program_exception(s, ilc, PGM_PRIVILEGED);
402
}
403

  
404
static void check_privileged(DisasContext *s, int ilc)
405
{
406
    if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
407
        gen_privileged_exception(s, ilc);
408
    }
409
}
410

  
411
#endif /* CONFIG_USER_ONLY */
412

  
413
static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
414
{
415
    TCGv_i64 tmp;
416

  
417
    /* 31-bitify the immediate part; register contents are dealt with below */
418
    if (!(s->tb->flags & FLAG_MASK_64)) {
419
        d2 &= 0x7fffffffUL;
420
    }
421

  
422
    if (x2) {
423
        if (d2) {
424
            tmp = tcg_const_i64(d2);
425
            tcg_gen_add_i64(tmp, tmp, regs[x2]);
426
        } else {
427
            tmp = load_reg(x2);
428
        }
429
        if (b2) {
430
            tcg_gen_add_i64(tmp, tmp, regs[b2]);
431
        }
432
    } else if (b2) {
433
        if (d2) {
434
            tmp = tcg_const_i64(d2);
435
            tcg_gen_add_i64(tmp, tmp, regs[b2]);
436
        } else {
437
            tmp = load_reg(b2);
438
        }
439
    } else {
440
        tmp = tcg_const_i64(d2);
441
    }
442

  
443
    /* 31-bit mode mask if there are values loaded from registers */
444
    if (!(s->tb->flags & FLAG_MASK_64) && (x2 || b2)) {
445
        tcg_gen_andi_i64(tmp, tmp, 0x7fffffffUL);
446
    }
447

  
448
    return tmp;
449
}
450

  
451
static void gen_op_movi_cc(DisasContext *s, uint32_t val)
452
{
453
    s->cc_op = CC_OP_CONST0 + val;
454
}
455

  
456
static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst)
457
{
458
    tcg_gen_discard_i64(cc_src);
459
    tcg_gen_mov_i64(cc_dst, dst);
460
    tcg_gen_discard_i64(cc_vr);
461
    s->cc_op = op;
462
}
463

  
464
static void gen_op_update1_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 dst)
465
{
466
    tcg_gen_discard_i64(cc_src);
467
    tcg_gen_extu_i32_i64(cc_dst, dst);
468
    tcg_gen_discard_i64(cc_vr);
469
    s->cc_op = op;
470
}
471

  
472
static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
473
                                  TCGv_i64 dst)
474
{
475
    tcg_gen_mov_i64(cc_src, src);
476
    tcg_gen_mov_i64(cc_dst, dst);
477
    tcg_gen_discard_i64(cc_vr);
478
    s->cc_op = op;
479
}
480

  
481
static void gen_op_update2_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 src,
482
                                  TCGv_i32 dst)
483
{
484
    tcg_gen_extu_i32_i64(cc_src, src);
485
    tcg_gen_extu_i32_i64(cc_dst, dst);
486
    tcg_gen_discard_i64(cc_vr);
487
    s->cc_op = op;
488
}
489

  
490
static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
491
                                  TCGv_i64 dst, TCGv_i64 vr)
492
{
493
    tcg_gen_mov_i64(cc_src, src);
494
    tcg_gen_mov_i64(cc_dst, dst);
495
    tcg_gen_mov_i64(cc_vr, vr);
496
    s->cc_op = op;
497
}
498

  
499
static void gen_op_update3_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 src,
500
                                  TCGv_i32 dst, TCGv_i32 vr)
501
{
502
    tcg_gen_extu_i32_i64(cc_src, src);
503
    tcg_gen_extu_i32_i64(cc_dst, dst);
504
    tcg_gen_extu_i32_i64(cc_vr, vr);
505
    s->cc_op = op;
506
}
507

  
508
static inline void set_cc_nz_u32(DisasContext *s, TCGv_i32 val)
509
{
510
    gen_op_update1_cc_i32(s, CC_OP_NZ, val);
511
}
512

  
513
static inline void set_cc_nz_u64(DisasContext *s, TCGv_i64 val)
514
{
515
    gen_op_update1_cc_i64(s, CC_OP_NZ, val);
516
}
517

  
518
static inline void cmp_32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
519
                          enum cc_op cond)
520
{
521
    gen_op_update2_cc_i32(s, cond, v1, v2);
522
}
523

  
524
static inline void cmp_64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
525
                          enum cc_op cond)
526
{
527
    gen_op_update2_cc_i64(s, cond, v1, v2);
528
}
529

  
530
static inline void cmp_s32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
531
{
532
    cmp_32(s, v1, v2, CC_OP_LTGT_32);
533
}
534

  
535
static inline void cmp_u32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
536
{
537
    cmp_32(s, v1, v2, CC_OP_LTUGTU_32);
538
}
539

  
540
static inline void cmp_s32c(DisasContext *s, TCGv_i32 v1, int32_t v2)
541
{
542
    /* XXX optimize for the constant? put it in s? */
543
    TCGv_i32 tmp = tcg_const_i32(v2);
544
    cmp_32(s, v1, tmp, CC_OP_LTGT_32);
545
    tcg_temp_free_i32(tmp);
546
}
547

  
548
static inline void cmp_u32c(DisasContext *s, TCGv_i32 v1, uint32_t v2)
549
{
550
    TCGv_i32 tmp = tcg_const_i32(v2);
551
    cmp_32(s, v1, tmp, CC_OP_LTUGTU_32);
552
    tcg_temp_free_i32(tmp);
553
}
554

  
555
static inline void cmp_s64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
556
{
557
    cmp_64(s, v1, v2, CC_OP_LTGT_64);
558
}
559

  
560
static inline void cmp_u64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
561
{
562
    cmp_64(s, v1, v2, CC_OP_LTUGTU_64);
563
}
564

  
565
static inline void cmp_s64c(DisasContext *s, TCGv_i64 v1, int64_t v2)
566
{
567
    TCGv_i64 tmp = tcg_const_i64(v2);
568
    cmp_s64(s, v1, tmp);
569
    tcg_temp_free_i64(tmp);
570
}
571

  
572
static inline void cmp_u64c(DisasContext *s, TCGv_i64 v1, uint64_t v2)
573
{
574
    TCGv_i64 tmp = tcg_const_i64(v2);
575
    cmp_u64(s, v1, tmp);
576
    tcg_temp_free_i64(tmp);
577
}
578

  
579
static inline void set_cc_s32(DisasContext *s, TCGv_i32 val)
580
{
581
    gen_op_update1_cc_i32(s, CC_OP_LTGT0_32, val);
582
}
583

  
584
static inline void set_cc_s64(DisasContext *s, TCGv_i64 val)
585
{
586
    gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, val);
587
}
588

  
589
static void set_cc_add64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2, TCGv_i64 vr)
590
{
591
    gen_op_update3_cc_i64(s, CC_OP_ADD_64, v1, v2, vr);
592
}
593

  
594
static void set_cc_addu64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
595
                          TCGv_i64 vr)
596
{
597
    gen_op_update3_cc_i64(s, CC_OP_ADDU_64, v1, v2, vr);
598
}
599

  
600
static void set_cc_sub64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2, TCGv_i64 vr)
601
{
602
    gen_op_update3_cc_i64(s, CC_OP_SUB_64, v1, v2, vr);
603
}
604

  
605
static void set_cc_subu64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
606
                          TCGv_i64 vr)
607
{
608
    gen_op_update3_cc_i64(s, CC_OP_SUBU_64, v1, v2, vr);
609
}
610

  
611
static void set_cc_abs64(DisasContext *s, TCGv_i64 v1)
612
{
613
    gen_op_update1_cc_i64(s, CC_OP_ABS_64, v1);
614
}
615

  
616
static void set_cc_nabs64(DisasContext *s, TCGv_i64 v1)
617
{
618
    gen_op_update1_cc_i64(s, CC_OP_NABS_64, v1);
619
}
620

  
621
static void set_cc_add32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2, TCGv_i32 vr)
622
{
623
    gen_op_update3_cc_i32(s, CC_OP_ADD_32, v1, v2, vr);
624
}
625

  
626
static void set_cc_addu32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
627
                          TCGv_i32 vr)
628
{
629
    gen_op_update3_cc_i32(s, CC_OP_ADDU_32, v1, v2, vr);
630
}
631

  
632
static void set_cc_sub32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2, TCGv_i32 vr)
633
{
634
    gen_op_update3_cc_i32(s, CC_OP_SUB_32, v1, v2, vr);
635
}
636

  
637
static void set_cc_subu32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
638
                          TCGv_i32 vr)
639
{
640
    gen_op_update3_cc_i32(s, CC_OP_SUBU_32, v1, v2, vr);
641
}
642

  
643
static void set_cc_abs32(DisasContext *s, TCGv_i32 v1)
644
{
645
    gen_op_update1_cc_i32(s, CC_OP_ABS_32, v1);
646
}
647

  
648
static void set_cc_nabs32(DisasContext *s, TCGv_i32 v1)
649
{
650
    gen_op_update1_cc_i32(s, CC_OP_NABS_32, v1);
651
}
652

  
653
static void set_cc_comp32(DisasContext *s, TCGv_i32 v1)
654
{
655
    gen_op_update1_cc_i32(s, CC_OP_COMP_32, v1);
656
}
657

  
658
static void set_cc_comp64(DisasContext *s, TCGv_i64 v1)
659
{
660
    gen_op_update1_cc_i64(s, CC_OP_COMP_64, v1);
661
}
662

  
663
static void set_cc_icm(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
664
{
665
    gen_op_update2_cc_i32(s, CC_OP_ICM, v1, v2);
666
}
667

  
668
static void set_cc_cmp_f32_i64(DisasContext *s, TCGv_i32 v1, TCGv_i64 v2)
669
{
670
    tcg_gen_extu_i32_i64(cc_src, v1);
671
    tcg_gen_mov_i64(cc_dst, v2);
672
    tcg_gen_discard_i64(cc_vr);
673
    s->cc_op = CC_OP_LTGT_F32;
674
}
675

  
676
static void set_cc_nz_f32(DisasContext *s, TCGv_i32 v1)
677
{
678
    gen_op_update1_cc_i32(s, CC_OP_NZ_F32, v1);
679
}
680

  
681
static inline void set_cc_nz_f64(DisasContext *s, TCGv_i64 v1)
682
{
683
    gen_op_update1_cc_i64(s, CC_OP_NZ_F64, v1);
684
}
685

  
686
/* CC value is in env->cc_op */
687
static inline void set_cc_static(DisasContext *s)
688
{
689
    tcg_gen_discard_i64(cc_src);
690
    tcg_gen_discard_i64(cc_dst);
691
    tcg_gen_discard_i64(cc_vr);
692
    s->cc_op = CC_OP_STATIC;
693
}
694

  
695
static inline void gen_op_set_cc_op(DisasContext *s)
696
{
697
    if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) {
698
        tcg_gen_movi_i32(cc_op, s->cc_op);
699
    }
700
}
701

  
702
static inline void gen_update_cc_op(DisasContext *s)
703
{
704
    gen_op_set_cc_op(s);
705
}
706

  
707
/* calculates cc into cc_op */
708
static void gen_op_calc_cc(DisasContext *s)
709
{
710
    TCGv_i32 local_cc_op = tcg_const_i32(s->cc_op);
711
    TCGv_i64 dummy = tcg_const_i64(0);
712

  
713
    switch (s->cc_op) {
714
    case CC_OP_CONST0:
715
    case CC_OP_CONST1:
716
    case CC_OP_CONST2:
717
    case CC_OP_CONST3:
718
        /* s->cc_op is the cc value */
719
        tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
720
        break;
721
    case CC_OP_STATIC:
722
        /* env->cc_op already is the cc value */
723
        break;
724
    case CC_OP_NZ:
725
    case CC_OP_ABS_64:
726
    case CC_OP_NABS_64:
727
    case CC_OP_ABS_32:
728
    case CC_OP_NABS_32:
729
    case CC_OP_LTGT0_32:
730
    case CC_OP_LTGT0_64:
731
    case CC_OP_COMP_32:
732
    case CC_OP_COMP_64:
733
    case CC_OP_NZ_F32:
734
    case CC_OP_NZ_F64:
735
        /* 1 argument */
736
        gen_helper_calc_cc(cc_op, local_cc_op, dummy, cc_dst, dummy);
737
        break;
738
    case CC_OP_ICM:
739
    case CC_OP_LTGT_32:
740
    case CC_OP_LTGT_64:
741
    case CC_OP_LTUGTU_32:
742
    case CC_OP_LTUGTU_64:
743
    case CC_OP_TM_32:
744
    case CC_OP_TM_64:
745
    case CC_OP_LTGT_F32:
746
    case CC_OP_LTGT_F64:
747
    case CC_OP_SLAG:
748
        /* 2 arguments */
749
        gen_helper_calc_cc(cc_op, local_cc_op, cc_src, cc_dst, dummy);
750
        break;
751
    case CC_OP_ADD_64:
752
    case CC_OP_ADDU_64:
753
    case CC_OP_SUB_64:
754
    case CC_OP_SUBU_64:
755
    case CC_OP_ADD_32:
756
    case CC_OP_ADDU_32:
757
    case CC_OP_SUB_32:
758
    case CC_OP_SUBU_32:
759
        /* 3 arguments */
760
        gen_helper_calc_cc(cc_op, local_cc_op, cc_src, cc_dst, cc_vr);
761
        break;
762
    case CC_OP_DYNAMIC:
763
        /* unknown operation - assume 3 arguments and cc_op in env */
764
        gen_helper_calc_cc(cc_op, cc_op, cc_src, cc_dst, cc_vr);
765
        break;
766
    default:
767
        tcg_abort();
768
    }
769

  
770
    tcg_temp_free_i32(local_cc_op);
771

  
772
    /* We now have cc in cc_op as constant */
773
    set_cc_static(s);
774
}
775

  
776
static inline void decode_rr(DisasContext *s, uint64_t insn, int *r1, int *r2)
777
{
778
    debug_insn(insn);
779

  
780
    *r1 = (insn >> 4) & 0xf;
781
    *r2 = insn & 0xf;
782
}
783

  
784
static inline TCGv_i64 decode_rx(DisasContext *s, uint64_t insn, int *r1,
785
                                 int *x2, int *b2, int *d2)
786
{
787
    debug_insn(insn);
788

  
789
    *r1 = (insn >> 20) & 0xf;
790
    *x2 = (insn >> 16) & 0xf;
791
    *b2 = (insn >> 12) & 0xf;
792
    *d2 = insn & 0xfff;
793

  
794
    return get_address(s, *x2, *b2, *d2);
795
}
796

  
797
static inline void decode_rs(DisasContext *s, uint64_t insn, int *r1, int *r3,
798
                             int *b2, int *d2)
799
{
800
    debug_insn(insn);
801

  
802
    *r1 = (insn >> 20) & 0xf;
803
    /* aka m3 */
804
    *r3 = (insn >> 16) & 0xf;
805
    *b2 = (insn >> 12) & 0xf;
806
    *d2 = insn & 0xfff;
807
}
808

  
809
static inline TCGv_i64 decode_si(DisasContext *s, uint64_t insn, int *i2,
810
                                 int *b1, int *d1)
811
{
812
    debug_insn(insn);
813

  
814
    *i2 = (insn >> 16) & 0xff;
815
    *b1 = (insn >> 12) & 0xf;
816
    *d1 = insn & 0xfff;
817

  
818
    return get_address(s, 0, *b1, *d1);
819
}
820

  
821
static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong pc)
822
{
823
    TranslationBlock *tb;
824

  
825
    gen_update_cc_op(s);
826

  
827
    tb = s->tb;
828
    /* NOTE: we handle the case where the TB spans two pages here */
829
    if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
830
        (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK))  {
831
        /* jump to same page: we can use a direct jump */
832
        tcg_gen_goto_tb(tb_num);
833
        tcg_gen_movi_i64(psw_addr, pc);
834
        tcg_gen_exit_tb((long)tb + tb_num);
835
    } else {
836
        /* jump to another page: currently not optimized */
837
        tcg_gen_movi_i64(psw_addr, pc);
838
        tcg_gen_exit_tb(0);
839
    }
840
}
841

  
842
static inline void account_noninline_branch(DisasContext *s, int cc_op)
843
{
844
#ifdef DEBUG_INLINE_BRANCHES
845
    inline_branch_miss[cc_op]++;
846
#endif
847
}
848

  
849
static inline void account_inline_branch(DisasContext *s)
850
{
851
#ifdef DEBUG_INLINE_BRANCHES
852
    inline_branch_hit[s->cc_op]++;
853
#endif
854
}
855

  
856
static void gen_jcc(DisasContext *s, uint32_t mask, int skip)
857
{
858
    TCGv_i32 tmp, tmp2, r;
859
    TCGv_i64 tmp64;
860
    int old_cc_op;
861

  
862
    switch (s->cc_op) {
863
    case CC_OP_LTGT0_32:
864
        tmp = tcg_temp_new_i32();
865
        tcg_gen_trunc_i64_i32(tmp, cc_dst);
866
        switch (mask) {
867
        case 0x8 | 0x4: /* dst <= 0 */
868
            tcg_gen_brcondi_i32(TCG_COND_GT, tmp, 0, skip);
869
            break;
870
        case 0x8 | 0x2: /* dst >= 0 */
871
            tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, skip);
872
            break;
873
        case 0x8: /* dst == 0 */
874
            tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, skip);
875
            break;
876
        case 0x7: /* dst != 0 */
877
        case 0x6: /* dst != 0 */
878
            tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, skip);
879
            break;
880
        case 0x4: /* dst < 0 */
881
            tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, skip);
882
            break;
883
        case 0x2: /* dst > 0 */
884
            tcg_gen_brcondi_i32(TCG_COND_LE, tmp, 0, skip);
885
            break;
886
        default:
887
            tcg_temp_free_i32(tmp);
888
            goto do_dynamic;
889
        }
890
        account_inline_branch(s);
891
        tcg_temp_free_i32(tmp);
892
        break;
893
    case CC_OP_LTGT0_64:
894
        switch (mask) {
895
        case 0x8 | 0x4: /* dst <= 0 */
896
            tcg_gen_brcondi_i64(TCG_COND_GT, cc_dst, 0, skip);
897
            break;
898
        case 0x8 | 0x2: /* dst >= 0 */
899
            tcg_gen_brcondi_i64(TCG_COND_LT, cc_dst, 0, skip);
900
            break;
901
        case 0x8: /* dst == 0 */
902
            tcg_gen_brcondi_i64(TCG_COND_NE, cc_dst, 0, skip);
903
            break;
904
        case 0x7: /* dst != 0 */
905
        case 0x6: /* dst != 0 */
906
            tcg_gen_brcondi_i64(TCG_COND_EQ, cc_dst, 0, skip);
907
            break;
908
        case 0x4: /* dst < 0 */
909
            tcg_gen_brcondi_i64(TCG_COND_GE, cc_dst, 0, skip);
910
            break;
911
        case 0x2: /* dst > 0 */
912
            tcg_gen_brcondi_i64(TCG_COND_LE, cc_dst, 0, skip);
913
            break;
914
        default:
915
            goto do_dynamic;
916
        }
917
        account_inline_branch(s);
918
        break;
919
    case CC_OP_LTGT_32:
920
        tmp = tcg_temp_new_i32();
921
        tmp2 = tcg_temp_new_i32();
922
        tcg_gen_trunc_i64_i32(tmp, cc_src);
923
        tcg_gen_trunc_i64_i32(tmp2, cc_dst);
924
        switch (mask) {
925
        case 0x8 | 0x4: /* src <= dst */
926
            tcg_gen_brcond_i32(TCG_COND_GT, tmp, tmp2, skip);
927
            break;
928
        case 0x8 | 0x2: /* src >= dst */
929
            tcg_gen_brcond_i32(TCG_COND_LT, tmp, tmp2, skip);
930
            break;
931
        case 0x8: /* src == dst */
932
            tcg_gen_brcond_i32(TCG_COND_NE, tmp, tmp2, skip);
933
            break;
934
        case 0x7: /* src != dst */
935
        case 0x6: /* src != dst */
936
            tcg_gen_brcond_i32(TCG_COND_EQ, tmp, tmp2, skip);
937
            break;
938
        case 0x4: /* src < dst */
939
            tcg_gen_brcond_i32(TCG_COND_GE, tmp, tmp2, skip);
940
            break;
941
        case 0x2: /* src > dst */
942
            tcg_gen_brcond_i32(TCG_COND_LE, tmp, tmp2, skip);
943
            break;
944
        default:
945
            tcg_temp_free_i32(tmp);
946
            tcg_temp_free_i32(tmp2);
947
            goto do_dynamic;
948
        }
949
        account_inline_branch(s);
950
        tcg_temp_free_i32(tmp);
951
        tcg_temp_free_i32(tmp2);
952
        break;
953
    case CC_OP_LTGT_64:
954
        switch (mask) {
955
        case 0x8 | 0x4: /* src <= dst */
956
            tcg_gen_brcond_i64(TCG_COND_GT, cc_src, cc_dst, skip);
957
            break;
958
        case 0x8 | 0x2: /* src >= dst */
959
            tcg_gen_brcond_i64(TCG_COND_LT, cc_src, cc_dst, skip);
960
            break;
961
        case 0x8: /* src == dst */
962
            tcg_gen_brcond_i64(TCG_COND_NE, cc_src, cc_dst, skip);
963
            break;
964
        case 0x7: /* src != dst */
965
        case 0x6: /* src != dst */
966
            tcg_gen_brcond_i64(TCG_COND_EQ, cc_src, cc_dst, skip);
967
            break;
968
        case 0x4: /* src < dst */
969
            tcg_gen_brcond_i64(TCG_COND_GE, cc_src, cc_dst, skip);
970
            break;
971
        case 0x2: /* src > dst */
972
            tcg_gen_brcond_i64(TCG_COND_LE, cc_src, cc_dst, skip);
973
            break;
974
        default:
975
            goto do_dynamic;
976
        }
977
        account_inline_branch(s);
978
        break;
979
    case CC_OP_LTUGTU_32:
980
        tmp = tcg_temp_new_i32();
981
        tmp2 = tcg_temp_new_i32();
982
        tcg_gen_trunc_i64_i32(tmp, cc_src);
983
        tcg_gen_trunc_i64_i32(tmp2, cc_dst);
984
        switch (mask) {
985
        case 0x8 | 0x4: /* src <= dst */
986
            tcg_gen_brcond_i32(TCG_COND_GTU, tmp, tmp2, skip);
987
            break;
988
        case 0x8 | 0x2: /* src >= dst */
989
            tcg_gen_brcond_i32(TCG_COND_LTU, tmp, tmp2, skip);
990
            break;
991
        case 0x8: /* src == dst */
992
            tcg_gen_brcond_i32(TCG_COND_NE, tmp, tmp2, skip);
993
            break;
994
        case 0x7: /* src != dst */
995
        case 0x6: /* src != dst */
996
            tcg_gen_brcond_i32(TCG_COND_EQ, tmp, tmp2, skip);
997
            break;
998
        case 0x4: /* src < dst */
999
            tcg_gen_brcond_i32(TCG_COND_GEU, tmp, tmp2, skip);
1000
            break;
1001
        case 0x2: /* src > dst */
1002
            tcg_gen_brcond_i32(TCG_COND_LEU, tmp, tmp2, skip);
1003
            break;
1004
        default:
1005
            tcg_temp_free_i32(tmp);
1006
            tcg_temp_free_i32(tmp2);
1007
            goto do_dynamic;
1008
        }
1009
        account_inline_branch(s);
1010
        tcg_temp_free_i32(tmp);
1011
        tcg_temp_free_i32(tmp2);
1012
        break;
1013
    case CC_OP_LTUGTU_64:
1014
        switch (mask) {
1015
        case 0x8 | 0x4: /* src <= dst */
1016
            tcg_gen_brcond_i64(TCG_COND_GTU, cc_src, cc_dst, skip);
1017
            break;
1018
        case 0x8 | 0x2: /* src >= dst */
1019
            tcg_gen_brcond_i64(TCG_COND_LTU, cc_src, cc_dst, skip);
1020
            break;
1021
        case 0x8: /* src == dst */
1022
            tcg_gen_brcond_i64(TCG_COND_NE, cc_src, cc_dst, skip);
1023
            break;
1024
        case 0x7: /* src != dst */
1025
        case 0x6: /* src != dst */
1026
            tcg_gen_brcond_i64(TCG_COND_EQ, cc_src, cc_dst, skip);
1027
            break;
1028
        case 0x4: /* src < dst */
1029
            tcg_gen_brcond_i64(TCG_COND_GEU, cc_src, cc_dst, skip);
1030
            break;
1031
        case 0x2: /* src > dst */
1032
            tcg_gen_brcond_i64(TCG_COND_LEU, cc_src, cc_dst, skip);
1033
            break;
1034
        default:
1035
            goto do_dynamic;
1036
        }
1037
        account_inline_branch(s);
1038
        break;
1039
    case CC_OP_NZ:
1040
        switch (mask) {
1041
        /* dst == 0 || dst != 0 */
1042
        case 0x8 | 0x4:
1043
        case 0x8 | 0x4 | 0x2:
1044
        case 0x8 | 0x4 | 0x2 | 0x1:
1045
        case 0x8 | 0x4 | 0x1:
1046
            break;
1047
        /* dst == 0 */
1048
        case 0x8:
1049
        case 0x8 | 0x2:
1050
        case 0x8 | 0x2 | 0x1:
1051
        case 0x8 | 0x1:
1052
            tcg_gen_brcondi_i64(TCG_COND_NE, cc_dst, 0, skip);
1053
            break;
1054
        /* dst != 0 */
1055
        case 0x4:
1056
        case 0x4 | 0x2:
1057
        case 0x4 | 0x2 | 0x1:
1058
        case 0x4 | 0x1:
1059
            tcg_gen_brcondi_i64(TCG_COND_EQ, cc_dst, 0, skip);
1060
            break;
1061
        default:
1062
            goto do_dynamic;
1063
        }
1064
        account_inline_branch(s);
1065
        break;
1066
    case CC_OP_TM_32:
1067
        tmp = tcg_temp_new_i32();
1068
        tmp2 = tcg_temp_new_i32();
1069

  
1070
        tcg_gen_trunc_i64_i32(tmp, cc_src);
1071
        tcg_gen_trunc_i64_i32(tmp2, cc_dst);
1072
        tcg_gen_and_i32(tmp, tmp, tmp2);
1073
        switch (mask) {
1074
        case 0x8: /* val & mask == 0 */
1075
            tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, skip);
1076
            break;
1077
        case 0x4 | 0x2 | 0x1: /* val & mask != 0 */
1078
            tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, skip);
1079
            break;
1080
        default:
1081
            goto do_dynamic;
1082
        }
1083
        tcg_temp_free_i32(tmp);
1084
        account_inline_branch(s);
1085
        break;
1086
    case CC_OP_TM_64:
1087
        tmp64 = tcg_temp_new_i64();
1088

  
1089
        tcg_gen_and_i64(tmp64, cc_src, cc_dst);
1090
        switch (mask) {
1091
        case 0x8: /* val & mask == 0 */
1092
            tcg_gen_brcondi_i64(TCG_COND_NE, tmp64, 0, skip);
1093
            break;
1094
        case 0x4 | 0x2 | 0x1: /* val & mask != 0 */
1095
            tcg_gen_brcondi_i64(TCG_COND_EQ, tmp64, 0, skip);
1096
            break;
1097
        default:
1098
            goto do_dynamic;
1099
        }
1100
        tcg_temp_free_i64(tmp64);
1101
        account_inline_branch(s);
1102
        break;
1103
    case CC_OP_ICM:
1104
        switch (mask) {
1105
        case 0x8: /* val == 0 */
1106
            tcg_gen_brcondi_i64(TCG_COND_NE, cc_dst, 0, skip);
1107
            break;
1108
        case 0x4 | 0x2 | 0x1: /* val != 0 */
1109
        case 0x4 | 0x2: /* val != 0 */
1110
            tcg_gen_brcondi_i64(TCG_COND_EQ, cc_dst, 0, skip);
1111
            break;
1112
        default:
1113
            goto do_dynamic;
1114
        }
1115
        account_inline_branch(s);
1116
        break;
1117
    case CC_OP_STATIC:
1118
        old_cc_op = s->cc_op;
1119
        goto do_dynamic_nocccalc;
1120
    case CC_OP_DYNAMIC:
1121
    default:
1122
do_dynamic:
1123
        old_cc_op = s->cc_op;
1124
        /* calculate cc value */
1125
        gen_op_calc_cc(s);
1126

  
1127
do_dynamic_nocccalc:
1128
        /* jump based on cc */
1129
        account_noninline_branch(s, old_cc_op);
1130

  
1131
        switch (mask) {
1132
        case 0x8 | 0x4 | 0x2 | 0x1:
1133
            /* always true */
1134
            break;
1135
        case 0x8 | 0x4 | 0x2: /* cc != 3 */
1136
            tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 3, skip);
1137
            break;
1138
        case 0x8 | 0x4 | 0x1: /* cc != 2 */
1139
            tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 2, skip);
1140
            break;
1141
        case 0x8 | 0x2 | 0x1: /* cc != 1 */
1142
            tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 1, skip);
1143
            break;
1144
        case 0x8 | 0x2: /* cc == 0 || cc == 2 */
1145
            tmp = tcg_temp_new_i32();
1146
            tcg_gen_andi_i32(tmp, cc_op, 1);
1147
            tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, skip);
1148
            tcg_temp_free_i32(tmp);
1149
            break;
1150
        case 0x8 | 0x4: /* cc < 2 */
1151
            tcg_gen_brcondi_i32(TCG_COND_GEU, cc_op, 2, skip);
1152
            break;
1153
        case 0x8: /* cc == 0 */
1154
            tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 0, skip);
1155
            break;
1156
        case 0x4 | 0x2 | 0x1: /* cc != 0 */
1157
            tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 0, skip);
1158
            break;
1159
        case 0x4 | 0x1: /* cc == 1 || cc == 3 */
1160
            tmp = tcg_temp_new_i32();
1161
            tcg_gen_andi_i32(tmp, cc_op, 1);
1162
            tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, skip);
1163
            tcg_temp_free_i32(tmp);
1164
            break;
1165
        case 0x4: /* cc == 1 */
1166
            tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 1, skip);
1167
            break;
1168
        case 0x2 | 0x1: /* cc > 1 */
1169
            tcg_gen_brcondi_i32(TCG_COND_LEU, cc_op, 1, skip);
1170
            break;
1171
        case 0x2: /* cc == 2 */
1172
            tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 2, skip);
1173
            break;
1174
        case 0x1: /* cc == 3 */
1175
            tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 3, skip);
1176
            break;
1177
        default: /* cc is masked by something else */
1178
            tmp = tcg_const_i32(3);
1179
            /* 3 - cc */
1180
            tcg_gen_sub_i32(tmp, tmp, cc_op);
1181
            tmp2 = tcg_const_i32(1);
1182
            /* 1 << (3 - cc) */
1183
            tcg_gen_shl_i32(tmp2, tmp2, tmp);
1184
            r = tcg_const_i32(mask);
1185
            /* mask & (1 << (3 - cc)) */
1186
            tcg_gen_and_i32(r, r, tmp2);
1187
            tcg_temp_free_i32(tmp);
1188
            tcg_temp_free_i32(tmp2);
1189

  
1190
            tcg_gen_brcondi_i32(TCG_COND_EQ, r, 0, skip);
1191
            tcg_temp_free_i32(r);
1192
            break;
1193
        }
1194
        break;
1195
    }
1196
}
1197

  
1198
static void gen_bcr(DisasContext *s, uint32_t mask, TCGv_i64 target,
1199
                    uint64_t offset)
1200
{
1201
    int skip;
1202

  
1203
    if (mask == 0xf) {
1204
        /* unconditional */
1205
        tcg_gen_mov_i64(psw_addr, target);
1206
        tcg_gen_exit_tb(0);
1207
    } else if (mask == 0) {
1208
        /* ignore cc and never match */
1209
        gen_goto_tb(s, 0, offset + 2);
1210
    } else {
1211
        TCGv_i64 new_addr = tcg_temp_local_new_i64();
1212

  
1213
        tcg_gen_mov_i64(new_addr, target);
1214
        skip = gen_new_label();
1215
        gen_jcc(s, mask, skip);
1216
        tcg_gen_mov_i64(psw_addr, new_addr);
1217
        tcg_temp_free_i64(new_addr);
1218
        tcg_gen_exit_tb(0);
1219
        gen_set_label(skip);
1220
        tcg_temp_free_i64(new_addr);
1221
        gen_goto_tb(s, 1, offset + 2);
1222
    }
1223
}
1224

  
1225
static void gen_brc(uint32_t mask, DisasContext *s, int32_t offset)
1226
{
1227
    int skip;
1228

  
1229
    if (mask == 0xf) {
1230
        /* unconditional */
1231
        gen_goto_tb(s, 0, s->pc + offset);
1232
    } else if (mask == 0) {
1233
        /* ignore cc and never match */
1234
        gen_goto_tb(s, 0, s->pc + 4);
1235
    } else {
1236
        skip = gen_new_label();
1237
        gen_jcc(s, mask, skip);
1238
        gen_goto_tb(s, 0, s->pc + offset);
1239
        gen_set_label(skip);
1240
        gen_goto_tb(s, 1, s->pc + 4);
1241
    }
1242
    s->is_jmp = DISAS_TB_JUMP;
1243
}
1244

  
1245
static void gen_op_mvc(DisasContext *s, int l, TCGv_i64 s1, TCGv_i64 s2)
1246
{
1247
    TCGv_i64 tmp, tmp2;
1248
    int i;
1249
    int l_memset = gen_new_label();
1250
    int l_out = gen_new_label();
1251
    TCGv_i64 dest = tcg_temp_local_new_i64();
1252
    TCGv_i64 src = tcg_temp_local_new_i64();
1253
    TCGv_i32 vl;
1254

  
1255
    /* Find out if we should use the inline version of mvc */
1256
    switch (l) {
1257
    case 0:
1258
    case 1:
1259
    case 2:
1260
    case 3:
1261
    case 4:
1262
    case 5:
1263
    case 6:
1264
    case 7:
1265
    case 11:
1266
    case 15:
1267
        /* use inline */
1268
        break;
1269
    default:
1270
        /* Fall back to helper */
1271
        vl = tcg_const_i32(l);
1272
        potential_page_fault(s);
1273
        gen_helper_mvc(vl, s1, s2);
1274
        tcg_temp_free_i32(vl);
1275
        return;
1276
    }
1277

  
1278
    tcg_gen_mov_i64(dest, s1);
1279
    tcg_gen_mov_i64(src, s2);
1280

  
1281
    if (!(s->tb->flags & FLAG_MASK_64)) {
1282
        /* XXX what if we overflow while moving? */
1283
        tcg_gen_andi_i64(dest, dest, 0x7fffffffUL);
1284
        tcg_gen_andi_i64(src, src, 0x7fffffffUL);
1285
    }
1286

  
1287
    tmp = tcg_temp_new_i64();
1288
    tcg_gen_addi_i64(tmp, src, 1);
1289
    tcg_gen_brcond_i64(TCG_COND_EQ, dest, tmp, l_memset);
1290
    tcg_temp_free_i64(tmp);
1291

  
1292
    switch (l) {
1293
    case 0:
1294
        tmp = tcg_temp_new_i64();
1295

  
1296
        tcg_gen_qemu_ld8u(tmp, src, get_mem_index(s));
1297
        tcg_gen_qemu_st8(tmp, dest, get_mem_index(s));
1298

  
1299
        tcg_temp_free_i64(tmp);
1300
        break;
1301
    case 1:
1302
        tmp = tcg_temp_new_i64();
1303

  
1304
        tcg_gen_qemu_ld16u(tmp, src, get_mem_index(s));
1305
        tcg_gen_qemu_st16(tmp, dest, get_mem_index(s));
1306

  
1307
        tcg_temp_free_i64(tmp);
1308
        break;
1309
    case 3:
1310
        tmp = tcg_temp_new_i64();
1311

  
1312
        tcg_gen_qemu_ld32u(tmp, src, get_mem_index(s));
1313
        tcg_gen_qemu_st32(tmp, dest, get_mem_index(s));
1314

  
1315
        tcg_temp_free_i64(tmp);
1316
        break;
1317
    case 4:
1318
        tmp = tcg_temp_new_i64();
1319
        tmp2 = tcg_temp_new_i64();
1320

  
1321
        tcg_gen_qemu_ld32u(tmp, src, get_mem_index(s));
1322
        tcg_gen_addi_i64(src, src, 4);
1323
        tcg_gen_qemu_ld8u(tmp2, src, get_mem_index(s));
1324
        tcg_gen_qemu_st32(tmp, dest, get_mem_index(s));
1325
        tcg_gen_addi_i64(dest, dest, 4);
1326
        tcg_gen_qemu_st8(tmp2, dest, get_mem_index(s));
1327

  
1328
        tcg_temp_free_i64(tmp);
1329
        tcg_temp_free_i64(tmp2);
1330
        break;
1331
    case 7:
1332
        tmp = tcg_temp_new_i64();
1333

  
1334
        tcg_gen_qemu_ld64(tmp, src, get_mem_index(s));
1335
        tcg_gen_qemu_st64(tmp, dest, get_mem_index(s));
1336

  
1337
        tcg_temp_free_i64(tmp);
1338
        break;
1339
    default:
1340
        /* The inline version can become too big for too uneven numbers, only
1341
           use it on known good lengths */
1342
        tmp = tcg_temp_new_i64();
1343
        tmp2 = tcg_const_i64(8);
1344
        for (i = 0; (i + 7) <= l; i += 8) {
1345
            tcg_gen_qemu_ld64(tmp, src, get_mem_index(s));
1346
            tcg_gen_qemu_st64(tmp, dest, get_mem_index(s));
1347

  
1348
            tcg_gen_add_i64(src, src, tmp2);
1349
            tcg_gen_add_i64(dest, dest, tmp2);
1350
        }
1351

  
1352
        tcg_temp_free_i64(tmp2);
1353
        tmp2 = tcg_const_i64(1);
1354

  
1355
        for (; i <= l; i++) {
1356
            tcg_gen_qemu_ld8u(tmp, src, get_mem_index(s));
1357
            tcg_gen_qemu_st8(tmp, dest, get_mem_index(s));
1358

  
1359
            tcg_gen_add_i64(src, src, tmp2);
1360
            tcg_gen_add_i64(dest, dest, tmp2);
1361
        }
1362

  
1363
        tcg_temp_free_i64(tmp2);
1364
        tcg_temp_free_i64(tmp);
1365
        break;
1366
    }
1367

  
1368
    tcg_gen_br(l_out);
1369

  
1370
    gen_set_label(l_memset);
1371
    /* memset case (dest == (src + 1)) */
1372

  
1373
    tmp = tcg_temp_new_i64();
1374
    tmp2 = tcg_temp_new_i64();
1375
    /* fill tmp with the byte */
1376
    tcg_gen_qemu_ld8u(tmp, src, get_mem_index(s));
1377
    tcg_gen_shli_i64(tmp2, tmp, 8);
1378
    tcg_gen_or_i64(tmp, tmp, tmp2);
1379
    tcg_gen_shli_i64(tmp2, tmp, 16);
1380
    tcg_gen_or_i64(tmp, tmp, tmp2);
1381
    tcg_gen_shli_i64(tmp2, tmp, 32);
1382
    tcg_gen_or_i64(tmp, tmp, tmp2);
1383
    tcg_temp_free_i64(tmp2);
1384

  
1385
    tmp2 = tcg_const_i64(8);
1386

  
1387
    for (i = 0; (i + 7) <= l; i += 8) {
1388
        tcg_gen_qemu_st64(tmp, dest, get_mem_index(s));
1389
        tcg_gen_addi_i64(dest, dest, 8);
1390
    }
1391

  
1392
    tcg_temp_free_i64(tmp2);
1393
    tmp2 = tcg_const_i64(1);
1394

  
1395
    for (; i <= l; i++) {
1396
        tcg_gen_qemu_st8(tmp, dest, get_mem_index(s));
1397
        tcg_gen_addi_i64(dest, dest, 1);
1398
    }
1399

  
1400
    tcg_temp_free_i64(tmp2);
1401
    tcg_temp_free_i64(tmp);
1402

  
1403
    gen_set_label(l_out);
1404

  
1405
    tcg_temp_free(dest);
1406
    tcg_temp_free(src);
1407
}
1408

  
1409
static void gen_op_clc(DisasContext *s, int l, TCGv_i64 s1, TCGv_i64 s2)
1410
{
1411
    TCGv_i64 tmp;
1412
    TCGv_i64 tmp2;
1413
    TCGv_i32 vl;
1414

  
1415
    /* check for simple 32bit or 64bit match */
1416
    switch (l) {
1417
    case 0:
1418
        tmp = tcg_temp_new_i64();
1419
        tmp2 = tcg_temp_new_i64();
1420

  
1421
        tcg_gen_qemu_ld8u(tmp, s1, get_mem_index(s));
1422
        tcg_gen_qemu_ld8u(tmp2, s2, get_mem_index(s));
1423
        cmp_u64(s, tmp, tmp2);
1424

  
1425
        tcg_temp_free_i64(tmp);
1426
        tcg_temp_free_i64(tmp2);
1427
        return;
1428
    case 1:
1429
        tmp = tcg_temp_new_i64();
1430
        tmp2 = tcg_temp_new_i64();
1431

  
1432
        tcg_gen_qemu_ld16u(tmp, s1, get_mem_index(s));
1433
        tcg_gen_qemu_ld16u(tmp2, s2, get_mem_index(s));
1434
        cmp_u64(s, tmp, tmp2);
1435

  
1436
        tcg_temp_free_i64(tmp);
1437
        tcg_temp_free_i64(tmp2);
1438
        return;
1439
    case 3:
1440
        tmp = tcg_temp_new_i64();
1441
        tmp2 = tcg_temp_new_i64();
1442

  
1443
        tcg_gen_qemu_ld32u(tmp, s1, get_mem_index(s));
1444
        tcg_gen_qemu_ld32u(tmp2, s2, get_mem_index(s));
1445
        cmp_u64(s, tmp, tmp2);
1446

  
1447
        tcg_temp_free_i64(tmp);
1448
        tcg_temp_free_i64(tmp2);
1449
        return;
1450
    case 7:
1451
        tmp = tcg_temp_new_i64();
1452
        tmp2 = tcg_temp_new_i64();
1453

  
1454
        tcg_gen_qemu_ld64(tmp, s1, get_mem_index(s));
1455
        tcg_gen_qemu_ld64(tmp2, s2, get_mem_index(s));
1456
        cmp_u64(s, tmp, tmp2);
1457

  
1458
        tcg_temp_free_i64(tmp);
1459
        tcg_temp_free_i64(tmp2);
1460
        return;
1461
    }
1462

  
1463
    potential_page_fault(s);
1464
    vl = tcg_const_i32(l);
1465
    gen_helper_clc(cc_op, vl, s1, s2);
1466
    tcg_temp_free_i32(vl);
1467
    set_cc_static(s);
1468
}
1469

  
1470
static void disas_e3(DisasContext* s, int op, int r1, int x2, int b2, int d2)
1471
{
1472
    TCGv_i64 addr, tmp, tmp2, tmp3, tmp4;
1473
    TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
1474

  
1475
    LOG_DISAS("disas_e3: op 0x%x r1 %d x2 %d b2 %d d2 %d\n",
1476
              op, r1, x2, b2, d2);
1477
    addr = get_address(s, x2, b2, d2);
1478
    switch (op) {
1479
    case 0x2: /* LTG R1,D2(X2,B2) [RXY] */
1480
    case 0x4: /* lg r1,d2(x2,b2) */
... This diff was truncated because it exceeds the maximum size that can be displayed.

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