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1
/*
2
 *  S/390 translation
3
 *
4
 *  Copyright (c) 2009 Ulrich Hecht
5
 *  Copyright (c) 2010 Alexander Graf
6
 *
7
 * This library is free software; you can redistribute it and/or
8
 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
20
#include <stdarg.h>
21
#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
25

    
26
/* #define DEBUG_ILLEGAL_INSTRUCTIONS */
27
/* #define DEBUG_INLINE_BRANCHES */
28
#define S390X_DEBUG_DISAS
29
/* #define S390X_DEBUG_DISAS_VERBOSE */
30

    
31
#ifdef S390X_DEBUG_DISAS_VERBOSE
32
#  define LOG_DISAS(...) qemu_log(__VA_ARGS__)
33
#else
34
#  define LOG_DISAS(...) do { } while (0)
35
#endif
36

    
37
#include "cpu.h"
38
#include "exec-all.h"
39
#include "disas.h"
40
#include "tcg-op.h"
41
#include "qemu-log.h"
42

    
43
/* global register indexes */
44
static TCGv_ptr cpu_env;
45

    
46
#include "gen-icount.h"
47
#include "helpers.h"
48
#define GEN_HELPER 1
49
#include "helpers.h"
50

    
51
typedef struct DisasContext DisasContext;
52
struct DisasContext {
53
    uint64_t pc;
54
    int is_jmp;
55
    enum cc_op cc_op;
56
    struct TranslationBlock *tb;
57
};
58

    
59
#define DISAS_EXCP 4
60

    
61
static void gen_op_calc_cc(DisasContext *s);
62

    
63
#ifdef DEBUG_INLINE_BRANCHES
64
static uint64_t inline_branch_hit[CC_OP_MAX];
65
static uint64_t inline_branch_miss[CC_OP_MAX];
66
#endif
67

    
68
static inline void debug_insn(uint64_t insn)
69
{
70
    LOG_DISAS("insn: 0x%" PRIx64 "\n", insn);
71
}
72

    
73
static inline uint64_t pc_to_link_info(DisasContext *s, uint64_t pc)
74
{
75
    if (!(s->tb->flags & FLAG_MASK_64)) {
76
        if (s->tb->flags & FLAG_MASK_32) {
77
            return pc | 0x80000000;
78
        }
79
    }
80
    return pc;
81
}
82

    
83
void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
84
                    int flags)
85
{
86
    int i;
87

    
88
    for (i = 0; i < 16; i++) {
89
        cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]);
90
        if ((i % 4) == 3) {
91
            cpu_fprintf(f, "\n");
92
        } else {
93
            cpu_fprintf(f, " ");
94
        }
95
    }
96

    
97
    for (i = 0; i < 16; i++) {
98
        cpu_fprintf(f, "F%02d=%016" PRIx64, i, *(uint64_t *)&env->fregs[i]);
99
        if ((i % 4) == 3) {
100
            cpu_fprintf(f, "\n");
101
        } else {
102
            cpu_fprintf(f, " ");
103
        }
104
    }
105

    
106
    cpu_fprintf(f, "\n");
107

    
108
#ifndef CONFIG_USER_ONLY
109
    for (i = 0; i < 16; i++) {
110
        cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]);
111
        if ((i % 4) == 3) {
112
            cpu_fprintf(f, "\n");
113
        } else {
114
            cpu_fprintf(f, " ");
115
        }
116
    }
117
#endif
118

    
119
    cpu_fprintf(f, "\n");
120

    
121
    if (env->cc_op > 3) {
122
        cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n",
123
                    env->psw.mask, env->psw.addr, cc_name(env->cc_op));
124
    } else {
125
        cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n",
126
                    env->psw.mask, env->psw.addr, env->cc_op);
127
    }
128

    
129
#ifdef DEBUG_INLINE_BRANCHES
130
    for (i = 0; i < CC_OP_MAX; i++) {
131
        cpu_fprintf(f, "  %15s = %10ld\t%10ld\n", cc_name(i),
132
                    inline_branch_miss[i], inline_branch_hit[i]);
133
    }
134
#endif
135
}
136

    
137
static TCGv_i64 psw_addr;
138
static TCGv_i64 psw_mask;
139

    
140
static TCGv_i32 cc_op;
141
static TCGv_i64 cc_src;
142
static TCGv_i64 cc_dst;
143
static TCGv_i64 cc_vr;
144

    
145
static char cpu_reg_names[10*3 + 6*4];
146
static TCGv_i64 regs[16];
147

    
148
static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
149

    
150
void s390x_translate_init(void)
151
{
152
    int i;
153
    size_t cpu_reg_names_size = sizeof(cpu_reg_names);
154
    char *p;
155

    
156
    cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
157
    psw_addr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, psw.addr),
158
                                      "psw_addr");
159
    psw_mask = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, psw.mask),
160
                                      "psw_mask");
161

    
162
    cc_op = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, cc_op),
163
                                   "cc_op");
164
    cc_src = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, cc_src),
165
                                    "cc_src");
166
    cc_dst = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, cc_dst),
167
                                    "cc_dst");
168
    cc_vr = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUState, cc_vr),
169
                                   "cc_vr");
170

    
171
    p = cpu_reg_names;
172
    for (i = 0; i < 16; i++) {
173
        snprintf(p, cpu_reg_names_size, "r%d", i);
174
        regs[i] = tcg_global_mem_new(TCG_AREG0,
175
                                     offsetof(CPUState, regs[i]), p);
176
        p += (i < 10) ? 3 : 4;
177
        cpu_reg_names_size -= (i < 10) ? 3 : 4;
178
    }
179
}
180

    
181
static inline TCGv_i64 load_reg(int reg)
182
{
183
    TCGv_i64 r = tcg_temp_new_i64();
184
    tcg_gen_mov_i64(r, regs[reg]);
185
    return r;
186
}
187

    
188
static inline TCGv_i64 load_freg(int reg)
189
{
190
    TCGv_i64 r = tcg_temp_new_i64();
191
    tcg_gen_ld_i64(r, cpu_env, offsetof(CPUState, fregs[reg].d));
192
    return r;
193
}
194

    
195
static inline TCGv_i32 load_freg32(int reg)
196
{
197
    TCGv_i32 r = tcg_temp_new_i32();
198
    tcg_gen_ld_i32(r, cpu_env, offsetof(CPUState, fregs[reg].l.upper));
199
    return r;
200
}
201

    
202
static inline TCGv_i32 load_reg32(int reg)
203
{
204
    TCGv_i32 r = tcg_temp_new_i32();
205
    tcg_gen_trunc_i64_i32(r, regs[reg]);
206
    return r;
207
}
208

    
209
static inline TCGv_i64 load_reg32_i64(int reg)
210
{
211
    TCGv_i64 r = tcg_temp_new_i64();
212
    tcg_gen_ext32s_i64(r, regs[reg]);
213
    return r;
214
}
215

    
216
static inline void store_reg(int reg, TCGv_i64 v)
217
{
218
    tcg_gen_mov_i64(regs[reg], v);
219
}
220

    
221
static inline void store_freg(int reg, TCGv_i64 v)
222
{
223
    tcg_gen_st_i64(v, cpu_env, offsetof(CPUState, fregs[reg].d));
224
}
225

    
226
static inline void store_reg32(int reg, TCGv_i32 v)
227
{
228
#if HOST_LONG_BITS == 32
229
    tcg_gen_mov_i32(TCGV_LOW(regs[reg]), v);
230
#else
231
    TCGv_i64 tmp = tcg_temp_new_i64();
232
    tcg_gen_extu_i32_i64(tmp, v);
233
    /* 32 bit register writes keep the upper half */
234
    tcg_gen_deposit_i64(regs[reg], regs[reg], tmp, 0, 32);
235
    tcg_temp_free_i64(tmp);
236
#endif
237
}
238

    
239
static inline void store_reg32_i64(int reg, TCGv_i64 v)
240
{
241
    /* 32 bit register writes keep the upper half */
242
#if HOST_LONG_BITS == 32
243
    tcg_gen_mov_i32(TCGV_LOW(regs[reg]), TCGV_LOW(v));
244
#else
245
    tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32);
246
#endif
247
}
248

    
249
static inline void store_reg16(int reg, TCGv_i32 v)
250
{
251
    TCGv_i64 tmp = tcg_temp_new_i64();
252
    tcg_gen_extu_i32_i64(tmp, v);
253
    /* 16 bit register writes keep the upper bytes */
254
    tcg_gen_deposit_i64(regs[reg], regs[reg], tmp, 0, 16);
255
    tcg_temp_free_i64(tmp);
256
}
257

    
258
static inline void store_reg8(int reg, TCGv_i64 v)
259
{
260
    /* 8 bit register writes keep the upper bytes */
261
    tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 8);
262
}
263

    
264
static inline void store_freg32(int reg, TCGv_i32 v)
265
{
266
    tcg_gen_st_i32(v, cpu_env, offsetof(CPUState, fregs[reg].l.upper));
267
}
268

    
269
static inline void update_psw_addr(DisasContext *s)
270
{
271
    /* psw.addr */
272
    tcg_gen_movi_i64(psw_addr, s->pc);
273
}
274

    
275
static inline void potential_page_fault(DisasContext *s)
276
{
277
#ifndef CONFIG_USER_ONLY
278
    update_psw_addr(s);
279
    gen_op_calc_cc(s);
280
#endif
281
}
282

    
283
static inline uint64_t ld_code2(uint64_t pc)
284
{
285
    return (uint64_t)lduw_code(pc);
286
}
287

    
288
static inline uint64_t ld_code4(uint64_t pc)
289
{
290
    return (uint64_t)ldl_code(pc);
291
}
292

    
293
static inline uint64_t ld_code6(uint64_t pc)
294
{
295
    uint64_t opc;
296
    opc = (uint64_t)lduw_code(pc) << 32;
297
    opc |= (uint64_t)(uint32_t)ldl_code(pc+2);
298
    return opc;
299
}
300

    
301
static inline int get_mem_index(DisasContext *s)
302
{
303
    switch (s->tb->flags & FLAG_MASK_ASC) {
304
    case PSW_ASC_PRIMARY >> 32:
305
        return 0;
306
    case PSW_ASC_SECONDARY >> 32:
307
        return 1;
308
    case PSW_ASC_HOME >> 32:
309
        return 2;
310
    default:
311
        tcg_abort();
312
        break;
313
    }
314
}
315

    
316
static inline void gen_debug(DisasContext *s)
317
{
318
    TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
319
    update_psw_addr(s);
320
    gen_op_calc_cc(s);
321
    gen_helper_exception(tmp);
322
    tcg_temp_free_i32(tmp);
323
    s->is_jmp = DISAS_EXCP;
324
}
325

    
326
#ifdef CONFIG_USER_ONLY
327

    
328
static void gen_illegal_opcode(DisasContext *s, int ilc)
329
{
330
    TCGv_i32 tmp = tcg_const_i32(EXCP_SPEC);
331
    update_psw_addr(s);
332
    gen_op_calc_cc(s);
333
    gen_helper_exception(tmp);
334
    tcg_temp_free_i32(tmp);
335
    s->is_jmp = DISAS_EXCP;
336
}
337

    
338
#else /* CONFIG_USER_ONLY */
339

    
340
static void debug_print_inst(DisasContext *s, int ilc)
341
{
342
#ifdef DEBUG_ILLEGAL_INSTRUCTIONS
343
    uint64_t inst = 0;
344

    
345
    switch (ilc & 3) {
346
    case 1:
347
        inst = ld_code2(s->pc);
348
        break;
349
    case 2:
350
        inst = ld_code4(s->pc);
351
        break;
352
    case 3:
353
        inst = ld_code6(s->pc);
354
        break;
355
    }
356

    
357
    fprintf(stderr, "Illegal instruction [%d at %016" PRIx64 "]: 0x%016"
358
            PRIx64 "\n", ilc, s->pc, inst);
359
#endif
360
}
361

    
362
static void gen_program_exception(DisasContext *s, int ilc, int code)
363
{
364
    TCGv_i32 tmp;
365

    
366
    debug_print_inst(s, ilc);
367

    
368
    /* remember what pgm exeption this was */
369
    tmp = tcg_const_i32(code);
370
    tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, int_pgm_code));
371
    tcg_temp_free_i32(tmp);
372

    
373
    tmp = tcg_const_i32(ilc);
374
    tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, int_pgm_ilc));
375
    tcg_temp_free_i32(tmp);
376

    
377
    /* advance past instruction */
378
    s->pc += (ilc * 2);
379
    update_psw_addr(s);
380

    
381
    /* save off cc */
382
    gen_op_calc_cc(s);
383

    
384
    /* trigger exception */
385
    tmp = tcg_const_i32(EXCP_PGM);
386
    gen_helper_exception(tmp);
387
    tcg_temp_free_i32(tmp);
388

    
389
    /* end TB here */
390
    s->is_jmp = DISAS_EXCP;
391
}
392

    
393

    
394
static void gen_illegal_opcode(DisasContext *s, int ilc)
395
{
396
    gen_program_exception(s, ilc, PGM_SPECIFICATION);
397
}
398

    
399
static void gen_privileged_exception(DisasContext *s, int ilc)
400
{
401
    gen_program_exception(s, ilc, PGM_PRIVILEGED);
402
}
403

    
404
static void check_privileged(DisasContext *s, int ilc)
405
{
406
    if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
407
        gen_privileged_exception(s, ilc);
408
    }
409
}
410

    
411
#endif /* CONFIG_USER_ONLY */
412

    
413
static TCGv_i64 get_address(DisasContext *s, int x2, int b2, int d2)
414
{
415
    TCGv_i64 tmp;
416

    
417
    /* 31-bitify the immediate part; register contents are dealt with below */
418
    if (!(s->tb->flags & FLAG_MASK_64)) {
419
        d2 &= 0x7fffffffUL;
420
    }
421

    
422
    if (x2) {
423
        if (d2) {
424
            tmp = tcg_const_i64(d2);
425
            tcg_gen_add_i64(tmp, tmp, regs[x2]);
426
        } else {
427
            tmp = load_reg(x2);
428
        }
429
        if (b2) {
430
            tcg_gen_add_i64(tmp, tmp, regs[b2]);
431
        }
432
    } else if (b2) {
433
        if (d2) {
434
            tmp = tcg_const_i64(d2);
435
            tcg_gen_add_i64(tmp, tmp, regs[b2]);
436
        } else {
437
            tmp = load_reg(b2);
438
        }
439
    } else {
440
        tmp = tcg_const_i64(d2);
441
    }
442

    
443
    /* 31-bit mode mask if there are values loaded from registers */
444
    if (!(s->tb->flags & FLAG_MASK_64) && (x2 || b2)) {
445
        tcg_gen_andi_i64(tmp, tmp, 0x7fffffffUL);
446
    }
447

    
448
    return tmp;
449
}
450

    
451
static void gen_op_movi_cc(DisasContext *s, uint32_t val)
452
{
453
    s->cc_op = CC_OP_CONST0 + val;
454
}
455

    
456
static void gen_op_update1_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 dst)
457
{
458
    tcg_gen_discard_i64(cc_src);
459
    tcg_gen_mov_i64(cc_dst, dst);
460
    tcg_gen_discard_i64(cc_vr);
461
    s->cc_op = op;
462
}
463

    
464
static void gen_op_update1_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 dst)
465
{
466
    tcg_gen_discard_i64(cc_src);
467
    tcg_gen_extu_i32_i64(cc_dst, dst);
468
    tcg_gen_discard_i64(cc_vr);
469
    s->cc_op = op;
470
}
471

    
472
static void gen_op_update2_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
473
                                  TCGv_i64 dst)
474
{
475
    tcg_gen_mov_i64(cc_src, src);
476
    tcg_gen_mov_i64(cc_dst, dst);
477
    tcg_gen_discard_i64(cc_vr);
478
    s->cc_op = op;
479
}
480

    
481
static void gen_op_update2_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 src,
482
                                  TCGv_i32 dst)
483
{
484
    tcg_gen_extu_i32_i64(cc_src, src);
485
    tcg_gen_extu_i32_i64(cc_dst, dst);
486
    tcg_gen_discard_i64(cc_vr);
487
    s->cc_op = op;
488
}
489

    
490
static void gen_op_update3_cc_i64(DisasContext *s, enum cc_op op, TCGv_i64 src,
491
                                  TCGv_i64 dst, TCGv_i64 vr)
492
{
493
    tcg_gen_mov_i64(cc_src, src);
494
    tcg_gen_mov_i64(cc_dst, dst);
495
    tcg_gen_mov_i64(cc_vr, vr);
496
    s->cc_op = op;
497
}
498

    
499
static void gen_op_update3_cc_i32(DisasContext *s, enum cc_op op, TCGv_i32 src,
500
                                  TCGv_i32 dst, TCGv_i32 vr)
501
{
502
    tcg_gen_extu_i32_i64(cc_src, src);
503
    tcg_gen_extu_i32_i64(cc_dst, dst);
504
    tcg_gen_extu_i32_i64(cc_vr, vr);
505
    s->cc_op = op;
506
}
507

    
508
static inline void set_cc_nz_u32(DisasContext *s, TCGv_i32 val)
509
{
510
    gen_op_update1_cc_i32(s, CC_OP_NZ, val);
511
}
512

    
513
static inline void set_cc_nz_u64(DisasContext *s, TCGv_i64 val)
514
{
515
    gen_op_update1_cc_i64(s, CC_OP_NZ, val);
516
}
517

    
518
static inline void cmp_32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
519
                          enum cc_op cond)
520
{
521
    gen_op_update2_cc_i32(s, cond, v1, v2);
522
}
523

    
524
static inline void cmp_64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
525
                          enum cc_op cond)
526
{
527
    gen_op_update2_cc_i64(s, cond, v1, v2);
528
}
529

    
530
static inline void cmp_s32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
531
{
532
    cmp_32(s, v1, v2, CC_OP_LTGT_32);
533
}
534

    
535
static inline void cmp_u32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
536
{
537
    cmp_32(s, v1, v2, CC_OP_LTUGTU_32);
538
}
539

    
540
static inline void cmp_s32c(DisasContext *s, TCGv_i32 v1, int32_t v2)
541
{
542
    /* XXX optimize for the constant? put it in s? */
543
    TCGv_i32 tmp = tcg_const_i32(v2);
544
    cmp_32(s, v1, tmp, CC_OP_LTGT_32);
545
    tcg_temp_free_i32(tmp);
546
}
547

    
548
static inline void cmp_u32c(DisasContext *s, TCGv_i32 v1, uint32_t v2)
549
{
550
    TCGv_i32 tmp = tcg_const_i32(v2);
551
    cmp_32(s, v1, tmp, CC_OP_LTUGTU_32);
552
    tcg_temp_free_i32(tmp);
553
}
554

    
555
static inline void cmp_s64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
556
{
557
    cmp_64(s, v1, v2, CC_OP_LTGT_64);
558
}
559

    
560
static inline void cmp_u64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2)
561
{
562
    cmp_64(s, v1, v2, CC_OP_LTUGTU_64);
563
}
564

    
565
static inline void cmp_s64c(DisasContext *s, TCGv_i64 v1, int64_t v2)
566
{
567
    TCGv_i64 tmp = tcg_const_i64(v2);
568
    cmp_s64(s, v1, tmp);
569
    tcg_temp_free_i64(tmp);
570
}
571

    
572
static inline void cmp_u64c(DisasContext *s, TCGv_i64 v1, uint64_t v2)
573
{
574
    TCGv_i64 tmp = tcg_const_i64(v2);
575
    cmp_u64(s, v1, tmp);
576
    tcg_temp_free_i64(tmp);
577
}
578

    
579
static inline void set_cc_s32(DisasContext *s, TCGv_i32 val)
580
{
581
    gen_op_update1_cc_i32(s, CC_OP_LTGT0_32, val);
582
}
583

    
584
static inline void set_cc_s64(DisasContext *s, TCGv_i64 val)
585
{
586
    gen_op_update1_cc_i64(s, CC_OP_LTGT0_64, val);
587
}
588

    
589
static void set_cc_add64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2, TCGv_i64 vr)
590
{
591
    gen_op_update3_cc_i64(s, CC_OP_ADD_64, v1, v2, vr);
592
}
593

    
594
static void set_cc_addu64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
595
                          TCGv_i64 vr)
596
{
597
    gen_op_update3_cc_i64(s, CC_OP_ADDU_64, v1, v2, vr);
598
}
599

    
600
static void set_cc_sub64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2, TCGv_i64 vr)
601
{
602
    gen_op_update3_cc_i64(s, CC_OP_SUB_64, v1, v2, vr);
603
}
604

    
605
static void set_cc_subu64(DisasContext *s, TCGv_i64 v1, TCGv_i64 v2,
606
                          TCGv_i64 vr)
607
{
608
    gen_op_update3_cc_i64(s, CC_OP_SUBU_64, v1, v2, vr);
609
}
610

    
611
static void set_cc_abs64(DisasContext *s, TCGv_i64 v1)
612
{
613
    gen_op_update1_cc_i64(s, CC_OP_ABS_64, v1);
614
}
615

    
616
static void set_cc_nabs64(DisasContext *s, TCGv_i64 v1)
617
{
618
    gen_op_update1_cc_i64(s, CC_OP_NABS_64, v1);
619
}
620

    
621
static void set_cc_add32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2, TCGv_i32 vr)
622
{
623
    gen_op_update3_cc_i32(s, CC_OP_ADD_32, v1, v2, vr);
624
}
625

    
626
static void set_cc_addu32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
627
                          TCGv_i32 vr)
628
{
629
    gen_op_update3_cc_i32(s, CC_OP_ADDU_32, v1, v2, vr);
630
}
631

    
632
static void set_cc_sub32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2, TCGv_i32 vr)
633
{
634
    gen_op_update3_cc_i32(s, CC_OP_SUB_32, v1, v2, vr);
635
}
636

    
637
static void set_cc_subu32(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2,
638
                          TCGv_i32 vr)
639
{
640
    gen_op_update3_cc_i32(s, CC_OP_SUBU_32, v1, v2, vr);
641
}
642

    
643
static void set_cc_abs32(DisasContext *s, TCGv_i32 v1)
644
{
645
    gen_op_update1_cc_i32(s, CC_OP_ABS_32, v1);
646
}
647

    
648
static void set_cc_nabs32(DisasContext *s, TCGv_i32 v1)
649
{
650
    gen_op_update1_cc_i32(s, CC_OP_NABS_32, v1);
651
}
652

    
653
static void set_cc_comp32(DisasContext *s, TCGv_i32 v1)
654
{
655
    gen_op_update1_cc_i32(s, CC_OP_COMP_32, v1);
656
}
657

    
658
static void set_cc_comp64(DisasContext *s, TCGv_i64 v1)
659
{
660
    gen_op_update1_cc_i64(s, CC_OP_COMP_64, v1);
661
}
662

    
663
static void set_cc_icm(DisasContext *s, TCGv_i32 v1, TCGv_i32 v2)
664
{
665
    gen_op_update2_cc_i32(s, CC_OP_ICM, v1, v2);
666
}
667

    
668
static void set_cc_cmp_f32_i64(DisasContext *s, TCGv_i32 v1, TCGv_i64 v2)
669
{
670
    tcg_gen_extu_i32_i64(cc_src, v1);
671
    tcg_gen_mov_i64(cc_dst, v2);
672
    tcg_gen_discard_i64(cc_vr);
673
    s->cc_op = CC_OP_LTGT_F32;
674
}
675

    
676
static void set_cc_nz_f32(DisasContext *s, TCGv_i32 v1)
677
{
678
    gen_op_update1_cc_i32(s, CC_OP_NZ_F32, v1);
679
}
680

    
681
static inline void set_cc_nz_f64(DisasContext *s, TCGv_i64 v1)
682
{
683
    gen_op_update1_cc_i64(s, CC_OP_NZ_F64, v1);
684
}
685

    
686
/* CC value is in env->cc_op */
687
static inline void set_cc_static(DisasContext *s)
688
{
689
    tcg_gen_discard_i64(cc_src);
690
    tcg_gen_discard_i64(cc_dst);
691
    tcg_gen_discard_i64(cc_vr);
692
    s->cc_op = CC_OP_STATIC;
693
}
694

    
695
static inline void gen_op_set_cc_op(DisasContext *s)
696
{
697
    if (s->cc_op != CC_OP_DYNAMIC && s->cc_op != CC_OP_STATIC) {
698
        tcg_gen_movi_i32(cc_op, s->cc_op);
699
    }
700
}
701

    
702
static inline void gen_update_cc_op(DisasContext *s)
703
{
704
    gen_op_set_cc_op(s);
705
}
706

    
707
/* calculates cc into cc_op */
708
static void gen_op_calc_cc(DisasContext *s)
709
{
710
    TCGv_i32 local_cc_op = tcg_const_i32(s->cc_op);
711
    TCGv_i64 dummy = tcg_const_i64(0);
712

    
713
    switch (s->cc_op) {
714
    case CC_OP_CONST0:
715
    case CC_OP_CONST1:
716
    case CC_OP_CONST2:
717
    case CC_OP_CONST3:
718
        /* s->cc_op is the cc value */
719
        tcg_gen_movi_i32(cc_op, s->cc_op - CC_OP_CONST0);
720
        break;
721
    case CC_OP_STATIC:
722
        /* env->cc_op already is the cc value */
723
        break;
724
    case CC_OP_NZ:
725
    case CC_OP_ABS_64:
726
    case CC_OP_NABS_64:
727
    case CC_OP_ABS_32:
728
    case CC_OP_NABS_32:
729
    case CC_OP_LTGT0_32:
730
    case CC_OP_LTGT0_64:
731
    case CC_OP_COMP_32:
732
    case CC_OP_COMP_64:
733
    case CC_OP_NZ_F32:
734
    case CC_OP_NZ_F64:
735
        /* 1 argument */
736
        gen_helper_calc_cc(cc_op, local_cc_op, dummy, cc_dst, dummy);
737
        break;
738
    case CC_OP_ICM:
739
    case CC_OP_LTGT_32:
740
    case CC_OP_LTGT_64:
741
    case CC_OP_LTUGTU_32:
742
    case CC_OP_LTUGTU_64:
743
    case CC_OP_TM_32:
744
    case CC_OP_TM_64:
745
    case CC_OP_LTGT_F32:
746
    case CC_OP_LTGT_F64:
747
    case CC_OP_SLAG:
748
        /* 2 arguments */
749
        gen_helper_calc_cc(cc_op, local_cc_op, cc_src, cc_dst, dummy);
750
        break;
751
    case CC_OP_ADD_64:
752
    case CC_OP_ADDU_64:
753
    case CC_OP_SUB_64:
754
    case CC_OP_SUBU_64:
755
    case CC_OP_ADD_32:
756
    case CC_OP_ADDU_32:
757
    case CC_OP_SUB_32:
758
    case CC_OP_SUBU_32:
759
        /* 3 arguments */
760
        gen_helper_calc_cc(cc_op, local_cc_op, cc_src, cc_dst, cc_vr);
761
        break;
762
    case CC_OP_DYNAMIC:
763
        /* unknown operation - assume 3 arguments and cc_op in env */
764
        gen_helper_calc_cc(cc_op, cc_op, cc_src, cc_dst, cc_vr);
765
        break;
766
    default:
767
        tcg_abort();
768
    }
769

    
770
    tcg_temp_free_i32(local_cc_op);
771

    
772
    /* We now have cc in cc_op as constant */
773
    set_cc_static(s);
774
}
775

    
776
static inline void decode_rr(DisasContext *s, uint64_t insn, int *r1, int *r2)
777
{
778
    debug_insn(insn);
779

    
780
    *r1 = (insn >> 4) & 0xf;
781
    *r2 = insn & 0xf;
782
}
783

    
784
static inline TCGv_i64 decode_rx(DisasContext *s, uint64_t insn, int *r1,
785
                                 int *x2, int *b2, int *d2)
786
{
787
    debug_insn(insn);
788

    
789
    *r1 = (insn >> 20) & 0xf;
790
    *x2 = (insn >> 16) & 0xf;
791
    *b2 = (insn >> 12) & 0xf;
792
    *d2 = insn & 0xfff;
793

    
794
    return get_address(s, *x2, *b2, *d2);
795
}
796

    
797
static inline void decode_rs(DisasContext *s, uint64_t insn, int *r1, int *r3,
798
                             int *b2, int *d2)
799
{
800
    debug_insn(insn);
801

    
802
    *r1 = (insn >> 20) & 0xf;
803
    /* aka m3 */
804
    *r3 = (insn >> 16) & 0xf;
805
    *b2 = (insn >> 12) & 0xf;
806
    *d2 = insn & 0xfff;
807
}
808

    
809
static inline TCGv_i64 decode_si(DisasContext *s, uint64_t insn, int *i2,
810
                                 int *b1, int *d1)
811
{
812
    debug_insn(insn);
813

    
814
    *i2 = (insn >> 16) & 0xff;
815
    *b1 = (insn >> 12) & 0xf;
816
    *d1 = insn & 0xfff;
817

    
818
    return get_address(s, 0, *b1, *d1);
819
}
820

    
821
static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong pc)
822
{
823
    TranslationBlock *tb;
824

    
825
    gen_update_cc_op(s);
826

    
827
    tb = s->tb;
828
    /* NOTE: we handle the case where the TB spans two pages here */
829
    if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
830
        (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK))  {
831
        /* jump to same page: we can use a direct jump */
832
        tcg_gen_goto_tb(tb_num);
833
        tcg_gen_movi_i64(psw_addr, pc);
834
        tcg_gen_exit_tb((long)tb + tb_num);
835
    } else {
836
        /* jump to another page: currently not optimized */
837
        tcg_gen_movi_i64(psw_addr, pc);
838
        tcg_gen_exit_tb(0);
839
    }
840
}
841

    
842
static inline void account_noninline_branch(DisasContext *s, int cc_op)
843
{
844
#ifdef DEBUG_INLINE_BRANCHES
845
    inline_branch_miss[cc_op]++;
846
#endif
847
}
848

    
849
static inline void account_inline_branch(DisasContext *s)
850
{
851
#ifdef DEBUG_INLINE_BRANCHES
852
    inline_branch_hit[s->cc_op]++;
853
#endif
854
}
855

    
856
static void gen_jcc(DisasContext *s, uint32_t mask, int skip)
857
{
858
    TCGv_i32 tmp, tmp2, r;
859
    TCGv_i64 tmp64;
860
    int old_cc_op;
861

    
862
    switch (s->cc_op) {
863
    case CC_OP_LTGT0_32:
864
        tmp = tcg_temp_new_i32();
865
        tcg_gen_trunc_i64_i32(tmp, cc_dst);
866
        switch (mask) {
867
        case 0x8 | 0x4: /* dst <= 0 */
868
            tcg_gen_brcondi_i32(TCG_COND_GT, tmp, 0, skip);
869
            break;
870
        case 0x8 | 0x2: /* dst >= 0 */
871
            tcg_gen_brcondi_i32(TCG_COND_LT, tmp, 0, skip);
872
            break;
873
        case 0x8: /* dst == 0 */
874
            tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, skip);
875
            break;
876
        case 0x7: /* dst != 0 */
877
        case 0x6: /* dst != 0 */
878
            tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, skip);
879
            break;
880
        case 0x4: /* dst < 0 */
881
            tcg_gen_brcondi_i32(TCG_COND_GE, tmp, 0, skip);
882
            break;
883
        case 0x2: /* dst > 0 */
884
            tcg_gen_brcondi_i32(TCG_COND_LE, tmp, 0, skip);
885
            break;
886
        default:
887
            tcg_temp_free_i32(tmp);
888
            goto do_dynamic;
889
        }
890
        account_inline_branch(s);
891
        tcg_temp_free_i32(tmp);
892
        break;
893
    case CC_OP_LTGT0_64:
894
        switch (mask) {
895
        case 0x8 | 0x4: /* dst <= 0 */
896
            tcg_gen_brcondi_i64(TCG_COND_GT, cc_dst, 0, skip);
897
            break;
898
        case 0x8 | 0x2: /* dst >= 0 */
899
            tcg_gen_brcondi_i64(TCG_COND_LT, cc_dst, 0, skip);
900
            break;
901
        case 0x8: /* dst == 0 */
902
            tcg_gen_brcondi_i64(TCG_COND_NE, cc_dst, 0, skip);
903
            break;
904
        case 0x7: /* dst != 0 */
905
        case 0x6: /* dst != 0 */
906
            tcg_gen_brcondi_i64(TCG_COND_EQ, cc_dst, 0, skip);
907
            break;
908
        case 0x4: /* dst < 0 */
909
            tcg_gen_brcondi_i64(TCG_COND_GE, cc_dst, 0, skip);
910
            break;
911
        case 0x2: /* dst > 0 */
912
            tcg_gen_brcondi_i64(TCG_COND_LE, cc_dst, 0, skip);
913
            break;
914
        default:
915
            goto do_dynamic;
916
        }
917
        account_inline_branch(s);
918
        break;
919
    case CC_OP_LTGT_32:
920
        tmp = tcg_temp_new_i32();
921
        tmp2 = tcg_temp_new_i32();
922
        tcg_gen_trunc_i64_i32(tmp, cc_src);
923
        tcg_gen_trunc_i64_i32(tmp2, cc_dst);
924
        switch (mask) {
925
        case 0x8 | 0x4: /* src <= dst */
926
            tcg_gen_brcond_i32(TCG_COND_GT, tmp, tmp2, skip);
927
            break;
928
        case 0x8 | 0x2: /* src >= dst */
929
            tcg_gen_brcond_i32(TCG_COND_LT, tmp, tmp2, skip);
930
            break;
931
        case 0x8: /* src == dst */
932
            tcg_gen_brcond_i32(TCG_COND_NE, tmp, tmp2, skip);
933
            break;
934
        case 0x7: /* src != dst */
935
        case 0x6: /* src != dst */
936
            tcg_gen_brcond_i32(TCG_COND_EQ, tmp, tmp2, skip);
937
            break;
938
        case 0x4: /* src < dst */
939
            tcg_gen_brcond_i32(TCG_COND_GE, tmp, tmp2, skip);
940
            break;
941
        case 0x2: /* src > dst */
942
            tcg_gen_brcond_i32(TCG_COND_LE, tmp, tmp2, skip);
943
            break;
944
        default:
945
            tcg_temp_free_i32(tmp);
946
            tcg_temp_free_i32(tmp2);
947
            goto do_dynamic;
948
        }
949
        account_inline_branch(s);
950
        tcg_temp_free_i32(tmp);
951
        tcg_temp_free_i32(tmp2);
952
        break;
953
    case CC_OP_LTGT_64:
954
        switch (mask) {
955
        case 0x8 | 0x4: /* src <= dst */
956
            tcg_gen_brcond_i64(TCG_COND_GT, cc_src, cc_dst, skip);
957
            break;
958
        case 0x8 | 0x2: /* src >= dst */
959
            tcg_gen_brcond_i64(TCG_COND_LT, cc_src, cc_dst, skip);
960
            break;
961
        case 0x8: /* src == dst */
962
            tcg_gen_brcond_i64(TCG_COND_NE, cc_src, cc_dst, skip);
963
            break;
964
        case 0x7: /* src != dst */
965
        case 0x6: /* src != dst */
966
            tcg_gen_brcond_i64(TCG_COND_EQ, cc_src, cc_dst, skip);
967
            break;
968
        case 0x4: /* src < dst */
969
            tcg_gen_brcond_i64(TCG_COND_GE, cc_src, cc_dst, skip);
970
            break;
971
        case 0x2: /* src > dst */
972
            tcg_gen_brcond_i64(TCG_COND_LE, cc_src, cc_dst, skip);
973
            break;
974
        default:
975
            goto do_dynamic;
976
        }
977
        account_inline_branch(s);
978
        break;
979
    case CC_OP_LTUGTU_32:
980
        tmp = tcg_temp_new_i32();
981
        tmp2 = tcg_temp_new_i32();
982
        tcg_gen_trunc_i64_i32(tmp, cc_src);
983
        tcg_gen_trunc_i64_i32(tmp2, cc_dst);
984
        switch (mask) {
985
        case 0x8 | 0x4: /* src <= dst */
986
            tcg_gen_brcond_i32(TCG_COND_GTU, tmp, tmp2, skip);
987
            break;
988
        case 0x8 | 0x2: /* src >= dst */
989
            tcg_gen_brcond_i32(TCG_COND_LTU, tmp, tmp2, skip);
990
            break;
991
        case 0x8: /* src == dst */
992
            tcg_gen_brcond_i32(TCG_COND_NE, tmp, tmp2, skip);
993
            break;
994
        case 0x7: /* src != dst */
995
        case 0x6: /* src != dst */
996
            tcg_gen_brcond_i32(TCG_COND_EQ, tmp, tmp2, skip);
997
            break;
998
        case 0x4: /* src < dst */
999
            tcg_gen_brcond_i32(TCG_COND_GEU, tmp, tmp2, skip);
1000
            break;
1001
        case 0x2: /* src > dst */
1002
            tcg_gen_brcond_i32(TCG_COND_LEU, tmp, tmp2, skip);
1003
            break;
1004
        default:
1005
            tcg_temp_free_i32(tmp);
1006
            tcg_temp_free_i32(tmp2);
1007
            goto do_dynamic;
1008
        }
1009
        account_inline_branch(s);
1010
        tcg_temp_free_i32(tmp);
1011
        tcg_temp_free_i32(tmp2);
1012
        break;
1013
    case CC_OP_LTUGTU_64:
1014
        switch (mask) {
1015
        case 0x8 | 0x4: /* src <= dst */
1016
            tcg_gen_brcond_i64(TCG_COND_GTU, cc_src, cc_dst, skip);
1017
            break;
1018
        case 0x8 | 0x2: /* src >= dst */
1019
            tcg_gen_brcond_i64(TCG_COND_LTU, cc_src, cc_dst, skip);
1020
            break;
1021
        case 0x8: /* src == dst */
1022
            tcg_gen_brcond_i64(TCG_COND_NE, cc_src, cc_dst, skip);
1023
            break;
1024
        case 0x7: /* src != dst */
1025
        case 0x6: /* src != dst */
1026
            tcg_gen_brcond_i64(TCG_COND_EQ, cc_src, cc_dst, skip);
1027
            break;
1028
        case 0x4: /* src < dst */
1029
            tcg_gen_brcond_i64(TCG_COND_GEU, cc_src, cc_dst, skip);
1030
            break;
1031
        case 0x2: /* src > dst */
1032
            tcg_gen_brcond_i64(TCG_COND_LEU, cc_src, cc_dst, skip);
1033
            break;
1034
        default:
1035
            goto do_dynamic;
1036
        }
1037
        account_inline_branch(s);
1038
        break;
1039
    case CC_OP_NZ:
1040
        switch (mask) {
1041
        /* dst == 0 || dst != 0 */
1042
        case 0x8 | 0x4:
1043
        case 0x8 | 0x4 | 0x2:
1044
        case 0x8 | 0x4 | 0x2 | 0x1:
1045
        case 0x8 | 0x4 | 0x1:
1046
            break;
1047
        /* dst == 0 */
1048
        case 0x8:
1049
        case 0x8 | 0x2:
1050
        case 0x8 | 0x2 | 0x1:
1051
        case 0x8 | 0x1:
1052
            tcg_gen_brcondi_i64(TCG_COND_NE, cc_dst, 0, skip);
1053
            break;
1054
        /* dst != 0 */
1055
        case 0x4:
1056
        case 0x4 | 0x2:
1057
        case 0x4 | 0x2 | 0x1:
1058
        case 0x4 | 0x1:
1059
            tcg_gen_brcondi_i64(TCG_COND_EQ, cc_dst, 0, skip);
1060
            break;
1061
        default:
1062
            goto do_dynamic;
1063
        }
1064
        account_inline_branch(s);
1065
        break;
1066
    case CC_OP_TM_32:
1067
        tmp = tcg_temp_new_i32();
1068
        tmp2 = tcg_temp_new_i32();
1069

    
1070
        tcg_gen_trunc_i64_i32(tmp, cc_src);
1071
        tcg_gen_trunc_i64_i32(tmp2, cc_dst);
1072
        tcg_gen_and_i32(tmp, tmp, tmp2);
1073
        switch (mask) {
1074
        case 0x8: /* val & mask == 0 */
1075
            tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, skip);
1076
            break;
1077
        case 0x4 | 0x2 | 0x1: /* val & mask != 0 */
1078
            tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, skip);
1079
            break;
1080
        default:
1081
            goto do_dynamic;
1082
        }
1083
        tcg_temp_free_i32(tmp);
1084
        account_inline_branch(s);
1085
        break;
1086
    case CC_OP_TM_64:
1087
        tmp64 = tcg_temp_new_i64();
1088

    
1089
        tcg_gen_and_i64(tmp64, cc_src, cc_dst);
1090
        switch (mask) {
1091
        case 0x8: /* val & mask == 0 */
1092
            tcg_gen_brcondi_i64(TCG_COND_NE, tmp64, 0, skip);
1093
            break;
1094
        case 0x4 | 0x2 | 0x1: /* val & mask != 0 */
1095
            tcg_gen_brcondi_i64(TCG_COND_EQ, tmp64, 0, skip);
1096
            break;
1097
        default:
1098
            goto do_dynamic;
1099
        }
1100
        tcg_temp_free_i64(tmp64);
1101
        account_inline_branch(s);
1102
        break;
1103
    case CC_OP_ICM:
1104
        switch (mask) {
1105
        case 0x8: /* val == 0 */
1106
            tcg_gen_brcondi_i64(TCG_COND_NE, cc_dst, 0, skip);
1107
            break;
1108
        case 0x4 | 0x2 | 0x1: /* val != 0 */
1109
        case 0x4 | 0x2: /* val != 0 */
1110
            tcg_gen_brcondi_i64(TCG_COND_EQ, cc_dst, 0, skip);
1111
            break;
1112
        default:
1113
            goto do_dynamic;
1114
        }
1115
        account_inline_branch(s);
1116
        break;
1117
    case CC_OP_STATIC:
1118
        old_cc_op = s->cc_op;
1119
        goto do_dynamic_nocccalc;
1120
    case CC_OP_DYNAMIC:
1121
    default:
1122
do_dynamic:
1123
        old_cc_op = s->cc_op;
1124
        /* calculate cc value */
1125
        gen_op_calc_cc(s);
1126

    
1127
do_dynamic_nocccalc:
1128
        /* jump based on cc */
1129
        account_noninline_branch(s, old_cc_op);
1130

    
1131
        switch (mask) {
1132
        case 0x8 | 0x4 | 0x2 | 0x1:
1133
            /* always true */
1134
            break;
1135
        case 0x8 | 0x4 | 0x2: /* cc != 3 */
1136
            tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 3, skip);
1137
            break;
1138
        case 0x8 | 0x4 | 0x1: /* cc != 2 */
1139
            tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 2, skip);
1140
            break;
1141
        case 0x8 | 0x2 | 0x1: /* cc != 1 */
1142
            tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 1, skip);
1143
            break;
1144
        case 0x8 | 0x2: /* cc == 0 || cc == 2 */
1145
            tmp = tcg_temp_new_i32();
1146
            tcg_gen_andi_i32(tmp, cc_op, 1);
1147
            tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, skip);
1148
            tcg_temp_free_i32(tmp);
1149
            break;
1150
        case 0x8 | 0x4: /* cc < 2 */
1151
            tcg_gen_brcondi_i32(TCG_COND_GEU, cc_op, 2, skip);
1152
            break;
1153
        case 0x8: /* cc == 0 */
1154
            tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 0, skip);
1155
            break;
1156
        case 0x4 | 0x2 | 0x1: /* cc != 0 */
1157
            tcg_gen_brcondi_i32(TCG_COND_EQ, cc_op, 0, skip);
1158
            break;
1159
        case 0x4 | 0x1: /* cc == 1 || cc == 3 */
1160
            tmp = tcg_temp_new_i32();
1161
            tcg_gen_andi_i32(tmp, cc_op, 1);
1162
            tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, skip);
1163
            tcg_temp_free_i32(tmp);
1164
            break;
1165
        case 0x4: /* cc == 1 */
1166
            tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 1, skip);
1167
            break;
1168
        case 0x2 | 0x1: /* cc > 1 */
1169
            tcg_gen_brcondi_i32(TCG_COND_LEU, cc_op, 1, skip);
1170
            break;
1171
        case 0x2: /* cc == 2 */
1172
            tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 2, skip);
1173
            break;
1174
        case 0x1: /* cc == 3 */
1175
            tcg_gen_brcondi_i32(TCG_COND_NE, cc_op, 3, skip);
1176
            break;
1177
        default: /* cc is masked by something else */
1178
            tmp = tcg_const_i32(3);
1179
            /* 3 - cc */
1180
            tcg_gen_sub_i32(tmp, tmp, cc_op);
1181
            tmp2 = tcg_const_i32(1);
1182
            /* 1 << (3 - cc) */
1183
            tcg_gen_shl_i32(tmp2, tmp2, tmp);
1184
            r = tcg_const_i32(mask);
1185
            /* mask & (1 << (3 - cc)) */
1186
            tcg_gen_and_i32(r, r, tmp2);
1187
            tcg_temp_free_i32(tmp);
1188
            tcg_temp_free_i32(tmp2);
1189

    
1190
            tcg_gen_brcondi_i32(TCG_COND_EQ, r, 0, skip);
1191
            tcg_temp_free_i32(r);
1192
            break;
1193
        }
1194
        break;
1195
    }
1196
}
1197

    
1198
static void gen_bcr(DisasContext *s, uint32_t mask, TCGv_i64 target,
1199
                    uint64_t offset)
1200
{
1201
    int skip;
1202

    
1203
    if (mask == 0xf) {
1204
        /* unconditional */
1205
        tcg_gen_mov_i64(psw_addr, target);
1206
        tcg_gen_exit_tb(0);
1207
    } else if (mask == 0) {
1208
        /* ignore cc and never match */
1209
        gen_goto_tb(s, 0, offset + 2);
1210
    } else {
1211
        TCGv_i64 new_addr = tcg_temp_local_new_i64();
1212

    
1213
        tcg_gen_mov_i64(new_addr, target);
1214
        skip = gen_new_label();
1215
        gen_jcc(s, mask, skip);
1216
        tcg_gen_mov_i64(psw_addr, new_addr);
1217
        tcg_temp_free_i64(new_addr);
1218
        tcg_gen_exit_tb(0);
1219
        gen_set_label(skip);
1220
        tcg_temp_free_i64(new_addr);
1221
        gen_goto_tb(s, 1, offset + 2);
1222
    }
1223
}
1224

    
1225
static void gen_brc(uint32_t mask, DisasContext *s, int32_t offset)
1226
{
1227
    int skip;
1228

    
1229
    if (mask == 0xf) {
1230
        /* unconditional */
1231
        gen_goto_tb(s, 0, s->pc + offset);
1232
    } else if (mask == 0) {
1233
        /* ignore cc and never match */
1234
        gen_goto_tb(s, 0, s->pc + 4);
1235
    } else {
1236
        skip = gen_new_label();
1237
        gen_jcc(s, mask, skip);
1238
        gen_goto_tb(s, 0, s->pc + offset);
1239
        gen_set_label(skip);
1240
        gen_goto_tb(s, 1, s->pc + 4);
1241
    }
1242
    s->is_jmp = DISAS_TB_JUMP;
1243
}
1244

    
1245
static void gen_op_mvc(DisasContext *s, int l, TCGv_i64 s1, TCGv_i64 s2)
1246
{
1247
    TCGv_i64 tmp, tmp2;
1248
    int i;
1249
    int l_memset = gen_new_label();
1250
    int l_out = gen_new_label();
1251
    TCGv_i64 dest = tcg_temp_local_new_i64();
1252
    TCGv_i64 src = tcg_temp_local_new_i64();
1253
    TCGv_i32 vl;
1254

    
1255
    /* Find out if we should use the inline version of mvc */
1256
    switch (l) {
1257
    case 0:
1258
    case 1:
1259
    case 2:
1260
    case 3:
1261
    case 4:
1262
    case 5:
1263
    case 6:
1264
    case 7:
1265
    case 11:
1266
    case 15:
1267
        /* use inline */
1268
        break;
1269
    default:
1270
        /* Fall back to helper */
1271
        vl = tcg_const_i32(l);
1272
        potential_page_fault(s);
1273
        gen_helper_mvc(vl, s1, s2);
1274
        tcg_temp_free_i32(vl);
1275
        return;
1276
    }
1277

    
1278
    tcg_gen_mov_i64(dest, s1);
1279
    tcg_gen_mov_i64(src, s2);
1280

    
1281
    if (!(s->tb->flags & FLAG_MASK_64)) {
1282
        /* XXX what if we overflow while moving? */
1283
        tcg_gen_andi_i64(dest, dest, 0x7fffffffUL);
1284
        tcg_gen_andi_i64(src, src, 0x7fffffffUL);
1285
    }
1286

    
1287
    tmp = tcg_temp_new_i64();
1288
    tcg_gen_addi_i64(tmp, src, 1);
1289
    tcg_gen_brcond_i64(TCG_COND_EQ, dest, tmp, l_memset);
1290
    tcg_temp_free_i64(tmp);
1291

    
1292
    switch (l) {
1293
    case 0:
1294
        tmp = tcg_temp_new_i64();
1295

    
1296
        tcg_gen_qemu_ld8u(tmp, src, get_mem_index(s));
1297
        tcg_gen_qemu_st8(tmp, dest, get_mem_index(s));
1298

    
1299
        tcg_temp_free_i64(tmp);
1300
        break;
1301
    case 1:
1302
        tmp = tcg_temp_new_i64();
1303

    
1304
        tcg_gen_qemu_ld16u(tmp, src, get_mem_index(s));
1305
        tcg_gen_qemu_st16(tmp, dest, get_mem_index(s));
1306

    
1307
        tcg_temp_free_i64(tmp);
1308
        break;
1309
    case 3:
1310
        tmp = tcg_temp_new_i64();
1311

    
1312
        tcg_gen_qemu_ld32u(tmp, src, get_mem_index(s));
1313
        tcg_gen_qemu_st32(tmp, dest, get_mem_index(s));
1314

    
1315
        tcg_temp_free_i64(tmp);
1316
        break;
1317
    case 4:
1318
        tmp = tcg_temp_new_i64();
1319
        tmp2 = tcg_temp_new_i64();
1320

    
1321
        tcg_gen_qemu_ld32u(tmp, src, get_mem_index(s));
1322
        tcg_gen_addi_i64(src, src, 4);
1323
        tcg_gen_qemu_ld8u(tmp2, src, get_mem_index(s));
1324
        tcg_gen_qemu_st32(tmp, dest, get_mem_index(s));
1325
        tcg_gen_addi_i64(dest, dest, 4);
1326
        tcg_gen_qemu_st8(tmp2, dest, get_mem_index(s));
1327

    
1328
        tcg_temp_free_i64(tmp);
1329
        tcg_temp_free_i64(tmp2);
1330
        break;
1331
    case 7:
1332
        tmp = tcg_temp_new_i64();
1333

    
1334
        tcg_gen_qemu_ld64(tmp, src, get_mem_index(s));
1335
        tcg_gen_qemu_st64(tmp, dest, get_mem_index(s));
1336

    
1337
        tcg_temp_free_i64(tmp);
1338
        break;
1339
    default:
1340
        /* The inline version can become too big for too uneven numbers, only
1341
           use it on known good lengths */
1342
        tmp = tcg_temp_new_i64();
1343
        tmp2 = tcg_const_i64(8);
1344
        for (i = 0; (i + 7) <= l; i += 8) {
1345
            tcg_gen_qemu_ld64(tmp, src, get_mem_index(s));
1346
            tcg_gen_qemu_st64(tmp, dest, get_mem_index(s));
1347

    
1348
            tcg_gen_add_i64(src, src, tmp2);
1349
            tcg_gen_add_i64(dest, dest, tmp2);
1350
        }
1351

    
1352
        tcg_temp_free_i64(tmp2);
1353
        tmp2 = tcg_const_i64(1);
1354

    
1355
        for (; i <= l; i++) {
1356
            tcg_gen_qemu_ld8u(tmp, src, get_mem_index(s));
1357
            tcg_gen_qemu_st8(tmp, dest, get_mem_index(s));
1358

    
1359
            tcg_gen_add_i64(src, src, tmp2);
1360
            tcg_gen_add_i64(dest, dest, tmp2);
1361
        }
1362

    
1363
        tcg_temp_free_i64(tmp2);
1364
        tcg_temp_free_i64(tmp);
1365
        break;
1366
    }
1367

    
1368
    tcg_gen_br(l_out);
1369

    
1370
    gen_set_label(l_memset);
1371
    /* memset case (dest == (src + 1)) */
1372

    
1373
    tmp = tcg_temp_new_i64();
1374
    tmp2 = tcg_temp_new_i64();
1375
    /* fill tmp with the byte */
1376
    tcg_gen_qemu_ld8u(tmp, src, get_mem_index(s));
1377
    tcg_gen_shli_i64(tmp2, tmp, 8);
1378
    tcg_gen_or_i64(tmp, tmp, tmp2);
1379
    tcg_gen_shli_i64(tmp2, tmp, 16);
1380
    tcg_gen_or_i64(tmp, tmp, tmp2);
1381
    tcg_gen_shli_i64(tmp2, tmp, 32);
1382
    tcg_gen_or_i64(tmp, tmp, tmp2);
1383
    tcg_temp_free_i64(tmp2);
1384

    
1385
    tmp2 = tcg_const_i64(8);
1386

    
1387
    for (i = 0; (i + 7) <= l; i += 8) {
1388
        tcg_gen_qemu_st64(tmp, dest, get_mem_index(s));
1389
        tcg_gen_addi_i64(dest, dest, 8);
1390
    }
1391

    
1392
    tcg_temp_free_i64(tmp2);
1393
    tmp2 = tcg_const_i64(1);
1394

    
1395
    for (; i <= l; i++) {
1396
        tcg_gen_qemu_st8(tmp, dest, get_mem_index(s));
1397
        tcg_gen_addi_i64(dest, dest, 1);
1398
    }
1399

    
1400
    tcg_temp_free_i64(tmp2);
1401
    tcg_temp_free_i64(tmp);
1402

    
1403
    gen_set_label(l_out);
1404

    
1405
    tcg_temp_free(dest);
1406
    tcg_temp_free(src);
1407
}
1408

    
1409
static void gen_op_clc(DisasContext *s, int l, TCGv_i64 s1, TCGv_i64 s2)
1410
{
1411
    TCGv_i64 tmp;
1412
    TCGv_i64 tmp2;
1413
    TCGv_i32 vl;
1414

    
1415
    /* check for simple 32bit or 64bit match */
1416
    switch (l) {
1417
    case 0:
1418
        tmp = tcg_temp_new_i64();
1419
        tmp2 = tcg_temp_new_i64();
1420

    
1421
        tcg_gen_qemu_ld8u(tmp, s1, get_mem_index(s));
1422
        tcg_gen_qemu_ld8u(tmp2, s2, get_mem_index(s));
1423
        cmp_u64(s, tmp, tmp2);
1424

    
1425
        tcg_temp_free_i64(tmp);
1426
        tcg_temp_free_i64(tmp2);
1427
        return;
1428
    case 1:
1429
        tmp = tcg_temp_new_i64();
1430
        tmp2 = tcg_temp_new_i64();
1431

    
1432
        tcg_gen_qemu_ld16u(tmp, s1, get_mem_index(s));
1433
        tcg_gen_qemu_ld16u(tmp2, s2, get_mem_index(s));
1434
        cmp_u64(s, tmp, tmp2);
1435

    
1436
        tcg_temp_free_i64(tmp);
1437
        tcg_temp_free_i64(tmp2);
1438
        return;
1439
    case 3:
1440
        tmp = tcg_temp_new_i64();
1441
        tmp2 = tcg_temp_new_i64();
1442

    
1443
        tcg_gen_qemu_ld32u(tmp, s1, get_mem_index(s));
1444
        tcg_gen_qemu_ld32u(tmp2, s2, get_mem_index(s));
1445
        cmp_u64(s, tmp, tmp2);
1446

    
1447
        tcg_temp_free_i64(tmp);
1448
        tcg_temp_free_i64(tmp2);
1449
        return;
1450
    case 7:
1451
        tmp = tcg_temp_new_i64();
1452
        tmp2 = tcg_temp_new_i64();
1453

    
1454
        tcg_gen_qemu_ld64(tmp, s1, get_mem_index(s));
1455
        tcg_gen_qemu_ld64(tmp2, s2, get_mem_index(s));
1456
        cmp_u64(s, tmp, tmp2);
1457

    
1458
        tcg_temp_free_i64(tmp);
1459
        tcg_temp_free_i64(tmp2);
1460
        return;
1461
    }
1462

    
1463
    potential_page_fault(s);
1464
    vl = tcg_const_i32(l);
1465
    gen_helper_clc(cc_op, vl, s1, s2);
1466
    tcg_temp_free_i32(vl);
1467
    set_cc_static(s);
1468
}
1469

    
1470
static void disas_e3(DisasContext* s, int op, int r1, int x2, int b2, int d2)
1471
{
1472
    TCGv_i64 addr, tmp, tmp2, tmp3, tmp4;
1473
    TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
1474

    
1475
    LOG_DISAS("disas_e3: op 0x%x r1 %d x2 %d b2 %d d2 %d\n",
1476
              op, r1, x2, b2, d2);
1477
    addr = get_address(s, x2, b2, d2);
1478
    switch (op) {
1479
    case 0x2: /* LTG R1,D2(X2,B2) [RXY] */
1480
    case 0x4: /* lg r1,d2(x2,b2) */
1481
        tcg_gen_qemu_ld64(regs[r1], addr, get_mem_index(s));
1482
        if (op == 0x2) {
1483
            set_cc_s64(s, regs[r1]);
1484
        }
1485
        break;
1486
    case 0x12: /* LT R1,D2(X2,B2) [RXY] */
1487
        tmp2 = tcg_temp_new_i64();
1488
        tmp32_1 = tcg_temp_new_i32();
1489
        tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
1490
        tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
1491
        store_reg32(r1, tmp32_1);
1492
        set_cc_s32(s, tmp32_1);
1493
        tcg_temp_free_i64(tmp2);
1494
        tcg_temp_free_i32(tmp32_1);
1495
        break;
1496
    case 0xc: /* MSG      R1,D2(X2,B2)     [RXY] */
1497
    case 0x1c: /* MSGF     R1,D2(X2,B2)     [RXY] */
1498
        tmp2 = tcg_temp_new_i64();
1499
        if (op == 0xc) {
1500
            tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1501
        } else {
1502
            tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
1503
        }
1504
        tcg_gen_mul_i64(regs[r1], regs[r1], tmp2);
1505
        tcg_temp_free_i64(tmp2);
1506
        break;
1507
    case 0xd: /* DSG      R1,D2(X2,B2)     [RXY] */
1508
    case 0x1d: /* DSGF      R1,D2(X2,B2)     [RXY] */
1509
        tmp2 = tcg_temp_new_i64();
1510
        if (op == 0x1d) {
1511
            tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
1512
        } else {
1513
            tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1514
        }
1515
        tmp4 = load_reg(r1 + 1);
1516
        tmp3 = tcg_temp_new_i64();
1517
        tcg_gen_div_i64(tmp3, tmp4, tmp2);
1518
        store_reg(r1 + 1, tmp3);
1519
        tcg_gen_rem_i64(tmp3, tmp4, tmp2);
1520
        store_reg(r1, tmp3);
1521
        tcg_temp_free_i64(tmp2);
1522
        tcg_temp_free_i64(tmp3);
1523
        tcg_temp_free_i64(tmp4);
1524
        break;
1525
    case 0x8: /* AG      R1,D2(X2,B2)     [RXY] */
1526
    case 0xa: /* ALG      R1,D2(X2,B2)     [RXY] */
1527
    case 0x18: /* AGF       R1,D2(X2,B2)     [RXY] */
1528
    case 0x1a: /* ALGF      R1,D2(X2,B2)     [RXY] */
1529
        if (op == 0x1a) {
1530
            tmp2 = tcg_temp_new_i64();
1531
            tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1532
        } else if (op == 0x18) {
1533
            tmp2 = tcg_temp_new_i64();
1534
            tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
1535
        } else {
1536
            tmp2 = tcg_temp_new_i64();
1537
            tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1538
        }
1539
        tmp4 = load_reg(r1);
1540
        tmp3 = tcg_temp_new_i64();
1541
        tcg_gen_add_i64(tmp3, tmp4, tmp2);
1542
        store_reg(r1, tmp3);
1543
        switch (op) {
1544
        case 0x8:
1545
        case 0x18:
1546
            set_cc_add64(s, tmp4, tmp2, tmp3);
1547
            break;
1548
        case 0xa:
1549
        case 0x1a:
1550
            set_cc_addu64(s, tmp4, tmp2, tmp3);
1551
            break;
1552
        default:
1553
            tcg_abort();
1554
        }
1555
        tcg_temp_free_i64(tmp2);
1556
        tcg_temp_free_i64(tmp3);
1557
        tcg_temp_free_i64(tmp4);
1558
        break;
1559
    case 0x9: /* SG      R1,D2(X2,B2)     [RXY] */
1560
    case 0xb: /* SLG      R1,D2(X2,B2)     [RXY] */
1561
    case 0x19: /* SGF      R1,D2(X2,B2)     [RXY] */
1562
    case 0x1b: /* SLGF     R1,D2(X2,B2)     [RXY] */
1563
        tmp2 = tcg_temp_new_i64();
1564
        if (op == 0x19) {
1565
            tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
1566
        } else if (op == 0x1b) {
1567
            tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1568
        } else {
1569
            tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1570
        }
1571
        tmp4 = load_reg(r1);
1572
        tmp3 = tcg_temp_new_i64();
1573
        tcg_gen_sub_i64(tmp3, tmp4, tmp2);
1574
        store_reg(r1, tmp3);
1575
        switch (op) {
1576
        case 0x9:
1577
        case 0x19:
1578
            set_cc_sub64(s, tmp4, tmp2, tmp3);
1579
            break;
1580
        case 0xb:
1581
        case 0x1b:
1582
            set_cc_subu64(s, tmp4, tmp2, tmp3);
1583
            break;
1584
        default:
1585
            tcg_abort();
1586
        }
1587
        tcg_temp_free_i64(tmp2);
1588
        tcg_temp_free_i64(tmp3);
1589
        tcg_temp_free_i64(tmp4);
1590
        break;
1591
    case 0xf: /* LRVG     R1,D2(X2,B2)     [RXE] */
1592
        tmp2 = tcg_temp_new_i64();
1593
        tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1594
        tcg_gen_bswap64_i64(tmp2, tmp2);
1595
        store_reg(r1, tmp2);
1596
        tcg_temp_free_i64(tmp2);
1597
        break;
1598
    case 0x14: /* LGF      R1,D2(X2,B2)     [RXY] */
1599
    case 0x16: /* LLGF      R1,D2(X2,B2)     [RXY] */
1600
        tmp2 = tcg_temp_new_i64();
1601
        tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1602
        if (op == 0x14) {
1603
            tcg_gen_ext32s_i64(tmp2, tmp2);
1604
        }
1605
        store_reg(r1, tmp2);
1606
        tcg_temp_free_i64(tmp2);
1607
        break;
1608
    case 0x15: /* LGH     R1,D2(X2,B2)     [RXY] */
1609
        tmp2 = tcg_temp_new_i64();
1610
        tcg_gen_qemu_ld16s(tmp2, addr, get_mem_index(s));
1611
        store_reg(r1, tmp2);
1612
        tcg_temp_free_i64(tmp2);
1613
        break;
1614
    case 0x17: /* LLGT      R1,D2(X2,B2)     [RXY] */
1615
        tmp2 = tcg_temp_new_i64();
1616
        tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1617
        tcg_gen_andi_i64(tmp2, tmp2, 0x7fffffffULL);
1618
        store_reg(r1, tmp2);
1619
        tcg_temp_free_i64(tmp2);
1620
        break;
1621
    case 0x1e: /* LRV R1,D2(X2,B2) [RXY] */
1622
        tmp2 = tcg_temp_new_i64();
1623
        tmp32_1 = tcg_temp_new_i32();
1624
        tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1625
        tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
1626
        tcg_temp_free_i64(tmp2);
1627
        tcg_gen_bswap32_i32(tmp32_1, tmp32_1);
1628
        store_reg32(r1, tmp32_1);
1629
        tcg_temp_free_i32(tmp32_1);
1630
        break;
1631
    case 0x1f: /* LRVH R1,D2(X2,B2) [RXY] */
1632
        tmp2 = tcg_temp_new_i64();
1633
        tmp32_1 = tcg_temp_new_i32();
1634
        tcg_gen_qemu_ld16u(tmp2, addr, get_mem_index(s));
1635
        tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
1636
        tcg_temp_free_i64(tmp2);
1637
        tcg_gen_bswap16_i32(tmp32_1, tmp32_1);
1638
        store_reg16(r1, tmp32_1);
1639
        tcg_temp_free_i32(tmp32_1);
1640
        break;
1641
    case 0x20: /* CG      R1,D2(X2,B2)     [RXY] */
1642
    case 0x21: /* CLG      R1,D2(X2,B2) */
1643
    case 0x30: /* CGF       R1,D2(X2,B2)     [RXY] */
1644
    case 0x31: /* CLGF      R1,D2(X2,B2)     [RXY] */
1645
        tmp2 = tcg_temp_new_i64();
1646
        switch (op) {
1647
        case 0x20:
1648
        case 0x21:
1649
            tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1650
            break;
1651
        case 0x30:
1652
            tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
1653
            break;
1654
        case 0x31:
1655
            tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1656
            break;
1657
        default:
1658
            tcg_abort();
1659
        }
1660
        switch (op) {
1661
        case 0x20:
1662
        case 0x30:
1663
            cmp_s64(s, regs[r1], tmp2);
1664
            break;
1665
        case 0x21:
1666
        case 0x31:
1667
            cmp_u64(s, regs[r1], tmp2);
1668
            break;
1669
        default:
1670
            tcg_abort();
1671
        }
1672
        tcg_temp_free_i64(tmp2);
1673
        break;
1674
    case 0x24: /* stg r1, d2(x2,b2) */
1675
        tcg_gen_qemu_st64(regs[r1], addr, get_mem_index(s));
1676
        break;
1677
    case 0x3e: /* STRV R1,D2(X2,B2) [RXY] */
1678
        tmp32_1 = load_reg32(r1);
1679
        tmp2 = tcg_temp_new_i64();
1680
        tcg_gen_bswap32_i32(tmp32_1, tmp32_1);
1681
        tcg_gen_extu_i32_i64(tmp2, tmp32_1);
1682
        tcg_temp_free_i32(tmp32_1);
1683
        tcg_gen_qemu_st32(tmp2, addr, get_mem_index(s));
1684
        tcg_temp_free_i64(tmp2);
1685
        break;
1686
    case 0x50: /* STY  R1,D2(X2,B2) [RXY] */
1687
        tmp32_1 = load_reg32(r1);
1688
        tmp2 = tcg_temp_new_i64();
1689
        tcg_gen_extu_i32_i64(tmp2, tmp32_1);
1690
        tcg_temp_free_i32(tmp32_1);
1691
        tcg_gen_qemu_st32(tmp2, addr, get_mem_index(s));
1692
        tcg_temp_free_i64(tmp2);
1693
        break;
1694
    case 0x57: /* XY R1,D2(X2,B2) [RXY] */
1695
        tmp32_1 = load_reg32(r1);
1696
        tmp32_2 = tcg_temp_new_i32();
1697
        tmp2 = tcg_temp_new_i64();
1698
        tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1699
        tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
1700
        tcg_temp_free_i64(tmp2);
1701
        tcg_gen_xor_i32(tmp32_2, tmp32_1, tmp32_2);
1702
        store_reg32(r1, tmp32_2);
1703
        set_cc_nz_u32(s, tmp32_2);
1704
        tcg_temp_free_i32(tmp32_1);
1705
        tcg_temp_free_i32(tmp32_2);
1706
        break;
1707
    case 0x58: /* LY R1,D2(X2,B2) [RXY] */
1708
        tmp3 = tcg_temp_new_i64();
1709
        tcg_gen_qemu_ld32u(tmp3, addr, get_mem_index(s));
1710
        store_reg32_i64(r1, tmp3);
1711
        tcg_temp_free_i64(tmp3);
1712
        break;
1713
    case 0x5a: /* AY R1,D2(X2,B2) [RXY] */
1714
    case 0x5b: /* SY R1,D2(X2,B2) [RXY] */
1715
        tmp32_1 = load_reg32(r1);
1716
        tmp32_2 = tcg_temp_new_i32();
1717
        tmp32_3 = tcg_temp_new_i32();
1718
        tmp2 = tcg_temp_new_i64();
1719
        tcg_gen_qemu_ld32s(tmp2, addr, get_mem_index(s));
1720
        tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
1721
        tcg_temp_free_i64(tmp2);
1722
        switch (op) {
1723
        case 0x5a:
1724
            tcg_gen_add_i32(tmp32_3, tmp32_1, tmp32_2);
1725
            break;
1726
        case 0x5b:
1727
            tcg_gen_sub_i32(tmp32_3, tmp32_1, tmp32_2);
1728
            break;
1729
        default:
1730
            tcg_abort();
1731
        }
1732
        store_reg32(r1, tmp32_3);
1733
        switch (op) {
1734
        case 0x5a:
1735
            set_cc_add32(s, tmp32_1, tmp32_2, tmp32_3);
1736
            break;
1737
        case 0x5b:
1738
            set_cc_sub32(s, tmp32_1, tmp32_2, tmp32_3);
1739
            break;
1740
        default:
1741
            tcg_abort();
1742
        }
1743
        tcg_temp_free_i32(tmp32_1);
1744
        tcg_temp_free_i32(tmp32_2);
1745
        tcg_temp_free_i32(tmp32_3);
1746
        break;
1747
    case 0x71: /* LAY R1,D2(X2,B2) [RXY] */
1748
        store_reg(r1, addr);
1749
        break;
1750
    case 0x72: /* STCY R1,D2(X2,B2) [RXY] */
1751
        tmp32_1 = load_reg32(r1);
1752
        tmp2 = tcg_temp_new_i64();
1753
        tcg_gen_ext_i32_i64(tmp2, tmp32_1);
1754
        tcg_gen_qemu_st8(tmp2, addr, get_mem_index(s));
1755
        tcg_temp_free_i32(tmp32_1);
1756
        tcg_temp_free_i64(tmp2);
1757
        break;
1758
    case 0x73: /* ICY R1,D2(X2,B2) [RXY] */
1759
        tmp3 = tcg_temp_new_i64();
1760
        tcg_gen_qemu_ld8u(tmp3, addr, get_mem_index(s));
1761
        store_reg8(r1, tmp3);
1762
        tcg_temp_free_i64(tmp3);
1763
        break;
1764
    case 0x76: /* LB R1,D2(X2,B2) [RXY] */
1765
    case 0x77: /* LGB R1,D2(X2,B2) [RXY] */
1766
        tmp2 = tcg_temp_new_i64();
1767
        tcg_gen_qemu_ld8s(tmp2, addr, get_mem_index(s));
1768
        switch (op) {
1769
        case 0x76:
1770
            tcg_gen_ext8s_i64(tmp2, tmp2);
1771
            store_reg32_i64(r1, tmp2);
1772
            break;
1773
        case 0x77:
1774
            tcg_gen_ext8s_i64(tmp2, tmp2);
1775
            store_reg(r1, tmp2);
1776
            break;
1777
        default:
1778
            tcg_abort();
1779
        }
1780
        tcg_temp_free_i64(tmp2);
1781
        break;
1782
    case 0x78: /* LHY R1,D2(X2,B2) [RXY] */
1783
        tmp2 = tcg_temp_new_i64();
1784
        tcg_gen_qemu_ld16s(tmp2, addr, get_mem_index(s));
1785
        store_reg32_i64(r1, tmp2);
1786
        tcg_temp_free_i64(tmp2);
1787
        break;
1788
    case 0x80: /* NG      R1,D2(X2,B2)     [RXY] */
1789
    case 0x81: /* OG      R1,D2(X2,B2)     [RXY] */
1790
    case 0x82: /* XG      R1,D2(X2,B2)     [RXY] */
1791
        tmp3 = tcg_temp_new_i64();
1792
        tcg_gen_qemu_ld64(tmp3, addr, get_mem_index(s));
1793
        switch (op) {
1794
        case 0x80:
1795
            tcg_gen_and_i64(regs[r1], regs[r1], tmp3);
1796
            break;
1797
        case 0x81:
1798
            tcg_gen_or_i64(regs[r1], regs[r1], tmp3);
1799
            break;
1800
        case 0x82:
1801
            tcg_gen_xor_i64(regs[r1], regs[r1], tmp3);
1802
            break;
1803
        default:
1804
            tcg_abort();
1805
        }
1806
        set_cc_nz_u64(s, regs[r1]);
1807
        tcg_temp_free_i64(tmp3);
1808
        break;
1809
    case 0x86: /* MLG      R1,D2(X2,B2)     [RXY] */
1810
        tmp2 = tcg_temp_new_i64();
1811
        tmp32_1 = tcg_const_i32(r1);
1812
        tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1813
        gen_helper_mlg(tmp32_1, tmp2);
1814
        tcg_temp_free_i64(tmp2);
1815
        tcg_temp_free_i32(tmp32_1);
1816
        break;
1817
    case 0x87: /* DLG      R1,D2(X2,B2)     [RXY] */
1818
        tmp2 = tcg_temp_new_i64();
1819
        tmp32_1 = tcg_const_i32(r1);
1820
        tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1821
        gen_helper_dlg(tmp32_1, tmp2);
1822
        tcg_temp_free_i64(tmp2);
1823
        tcg_temp_free_i32(tmp32_1);
1824
        break;
1825
    case 0x88: /* ALCG      R1,D2(X2,B2)     [RXY] */
1826
        tmp2 = tcg_temp_new_i64();
1827
        tmp3 = tcg_temp_new_i64();
1828
        tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1829
        /* XXX possible optimization point */
1830
        gen_op_calc_cc(s);
1831
        tcg_gen_extu_i32_i64(tmp3, cc_op);
1832
        tcg_gen_shri_i64(tmp3, tmp3, 1);
1833
        tcg_gen_andi_i64(tmp3, tmp3, 1);
1834
        tcg_gen_add_i64(tmp3, tmp2, tmp3);
1835
        tcg_gen_add_i64(tmp3, regs[r1], tmp3);
1836
        store_reg(r1, tmp3);
1837
        set_cc_addu64(s, regs[r1], tmp2, tmp3);
1838
        tcg_temp_free_i64(tmp2);
1839
        tcg_temp_free_i64(tmp3);
1840
        break;
1841
    case 0x89: /* SLBG      R1,D2(X2,B2)     [RXY] */
1842
        tmp2 = tcg_temp_new_i64();
1843
        tmp32_1 = tcg_const_i32(r1);
1844
        tcg_gen_qemu_ld64(tmp2, addr, get_mem_index(s));
1845
        /* XXX possible optimization point */
1846
        gen_op_calc_cc(s);
1847
        gen_helper_slbg(cc_op, cc_op, tmp32_1, regs[r1], tmp2);
1848
        set_cc_static(s);
1849
        tcg_temp_free_i64(tmp2);
1850
        tcg_temp_free_i32(tmp32_1);
1851
        break;
1852
    case 0x90: /* LLGC      R1,D2(X2,B2)     [RXY] */
1853
        tcg_gen_qemu_ld8u(regs[r1], addr, get_mem_index(s));
1854
        break;
1855
    case 0x91: /* LLGH      R1,D2(X2,B2)     [RXY] */
1856
        tcg_gen_qemu_ld16u(regs[r1], addr, get_mem_index(s));
1857
        break;
1858
    case 0x94: /* LLC     R1,D2(X2,B2)     [RXY] */
1859
        tmp2 = tcg_temp_new_i64();
1860
        tcg_gen_qemu_ld8u(tmp2, addr, get_mem_index(s));
1861
        store_reg32_i64(r1, tmp2);
1862
        tcg_temp_free_i64(tmp2);
1863
        break;
1864
    case 0x95: /* LLH     R1,D2(X2,B2)     [RXY] */
1865
        tmp2 = tcg_temp_new_i64();
1866
        tcg_gen_qemu_ld16u(tmp2, addr, get_mem_index(s));
1867
        store_reg32_i64(r1, tmp2);
1868
        tcg_temp_free_i64(tmp2);
1869
        break;
1870
    case 0x96: /* ML      R1,D2(X2,B2)     [RXY] */
1871
        tmp2 = tcg_temp_new_i64();
1872
        tmp3 = load_reg((r1 + 1) & 15);
1873
        tcg_gen_ext32u_i64(tmp3, tmp3);
1874
        tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1875
        tcg_gen_mul_i64(tmp2, tmp2, tmp3);
1876
        store_reg32_i64((r1 + 1) & 15, tmp2);
1877
        tcg_gen_shri_i64(tmp2, tmp2, 32);
1878
        store_reg32_i64(r1, tmp2);
1879
        tcg_temp_free_i64(tmp2);
1880
        tcg_temp_free_i64(tmp3);
1881
        break;
1882
    case 0x97: /* DL     R1,D2(X2,B2)     [RXY] */
1883
        /* reg(r1) = reg(r1, r1+1) % ld32(addr) */
1884
        /* reg(r1+1) = reg(r1, r1+1) / ld32(addr) */
1885
        tmp = load_reg(r1);
1886
        tmp2 = tcg_temp_new_i64();
1887
        tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1888
        tmp3 = load_reg((r1 + 1) & 15);
1889
        tcg_gen_ext32u_i64(tmp2, tmp2);
1890
        tcg_gen_ext32u_i64(tmp3, tmp3);
1891
        tcg_gen_shli_i64(tmp, tmp, 32);
1892
        tcg_gen_or_i64(tmp, tmp, tmp3);
1893

    
1894
        tcg_gen_rem_i64(tmp3, tmp, tmp2);
1895
        tcg_gen_div_i64(tmp, tmp, tmp2);
1896
        store_reg32_i64((r1 + 1) & 15, tmp);
1897
        store_reg32_i64(r1, tmp3);
1898
        tcg_temp_free_i64(tmp);
1899
        tcg_temp_free_i64(tmp2);
1900
        tcg_temp_free_i64(tmp3);
1901
        break;
1902
    case 0x98: /* ALC     R1,D2(X2,B2)     [RXY] */
1903
        tmp2 = tcg_temp_new_i64();
1904
        tmp32_1 = load_reg32(r1);
1905
        tmp32_2 = tcg_temp_new_i32();
1906
        tmp32_3 = tcg_temp_new_i32();
1907
        tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1908
        tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
1909
        /* XXX possible optimization point */
1910
        gen_op_calc_cc(s);
1911
        gen_helper_addc_u32(tmp32_3, cc_op, tmp32_1, tmp32_2);
1912
        set_cc_addu32(s, tmp32_1, tmp32_2, tmp32_3);
1913
        store_reg32(r1, tmp32_3);
1914
        tcg_temp_free_i64(tmp2);
1915
        tcg_temp_free_i32(tmp32_1);
1916
        tcg_temp_free_i32(tmp32_2);
1917
        tcg_temp_free_i32(tmp32_3);
1918
        break;
1919
    case 0x99: /* SLB     R1,D2(X2,B2)     [RXY] */
1920
        tmp2 = tcg_temp_new_i64();
1921
        tmp32_1 = tcg_const_i32(r1);
1922
        tmp32_2 = tcg_temp_new_i32();
1923
        tcg_gen_qemu_ld32u(tmp2, addr, get_mem_index(s));
1924
        tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
1925
        /* XXX possible optimization point */
1926
        gen_op_calc_cc(s);
1927
        gen_helper_slb(cc_op, cc_op, tmp32_1, tmp32_2);
1928
        set_cc_static(s);
1929
        tcg_temp_free_i64(tmp2);
1930
        tcg_temp_free_i32(tmp32_1);
1931
        tcg_temp_free_i32(tmp32_2);
1932
        break;
1933
    default:
1934
        LOG_DISAS("illegal e3 operation 0x%x\n", op);
1935
        gen_illegal_opcode(s, 3);
1936
        break;
1937
    }
1938
    tcg_temp_free_i64(addr);
1939
}
1940

    
1941
#ifndef CONFIG_USER_ONLY
1942
static void disas_e5(DisasContext* s, uint64_t insn)
1943
{
1944
    TCGv_i64 tmp, tmp2;
1945
    int op = (insn >> 32) & 0xff;
1946

    
1947
    tmp = get_address(s, 0, (insn >> 28) & 0xf, (insn >> 16) & 0xfff);
1948
    tmp2 = get_address(s, 0, (insn >> 12) & 0xf, insn & 0xfff);
1949

    
1950
    LOG_DISAS("disas_e5: insn %" PRIx64 "\n", insn);
1951
    switch (op) {
1952
    case 0x01: /* TPROT    D1(B1),D2(B2)  [SSE] */
1953
        /* Test Protection */
1954
        potential_page_fault(s);
1955
        gen_helper_tprot(cc_op, tmp, tmp2);
1956
        set_cc_static(s);
1957
        break;
1958
    default:
1959
        LOG_DISAS("illegal e5 operation 0x%x\n", op);
1960
        gen_illegal_opcode(s, 3);
1961
        break;
1962
    }
1963

    
1964
    tcg_temp_free_i64(tmp);
1965
    tcg_temp_free_i64(tmp2);
1966
}
1967
#endif
1968

    
1969
static void disas_eb(DisasContext *s, int op, int r1, int r3, int b2, int d2)
1970
{
1971
    TCGv_i64 tmp, tmp2, tmp3, tmp4;
1972
    TCGv_i32 tmp32_1, tmp32_2;
1973
    int i, stm_len;
1974
    int ilc = 3;
1975

    
1976
    LOG_DISAS("disas_eb: op 0x%x r1 %d r3 %d b2 %d d2 0x%x\n",
1977
              op, r1, r3, b2, d2);
1978
    switch (op) {
1979
    case 0xc: /* SRLG     R1,R3,D2(B2)     [RSY] */
1980
    case 0xd: /* SLLG     R1,R3,D2(B2)     [RSY] */
1981
    case 0xa: /* SRAG     R1,R3,D2(B2)     [RSY] */
1982
    case 0xb: /* SLAG     R1,R3,D2(B2)     [RSY] */
1983
    case 0x1c: /* RLLG     R1,R3,D2(B2)     [RSY] */
1984
        if (b2) {
1985
            tmp = get_address(s, 0, b2, d2);
1986
            tcg_gen_andi_i64(tmp, tmp, 0x3f);
1987
        } else {
1988
            tmp = tcg_const_i64(d2 & 0x3f);
1989
        }
1990
        switch (op) {
1991
        case 0xc:
1992
            tcg_gen_shr_i64(regs[r1], regs[r3], tmp);
1993
            break;
1994
        case 0xd:
1995
            tcg_gen_shl_i64(regs[r1], regs[r3], tmp);
1996
            break;
1997
        case 0xa:
1998
            tcg_gen_sar_i64(regs[r1], regs[r3], tmp);
1999
            break;
2000
        case 0xb:
2001
            tmp2 = tcg_temp_new_i64();
2002
            tmp3 = tcg_temp_new_i64();
2003
            gen_op_update2_cc_i64(s, CC_OP_SLAG, regs[r3], tmp);
2004
            tcg_gen_shl_i64(tmp2, regs[r3], tmp);
2005
            /* override sign bit with source sign */
2006
            tcg_gen_andi_i64(tmp2, tmp2, ~0x8000000000000000ULL);
2007
            tcg_gen_andi_i64(tmp3, regs[r3], 0x8000000000000000ULL);
2008
            tcg_gen_or_i64(regs[r1], tmp2, tmp3);
2009
            tcg_temp_free_i64(tmp2);
2010
            tcg_temp_free_i64(tmp3);
2011
            break;
2012
        case 0x1c:
2013
            tcg_gen_rotl_i64(regs[r1], regs[r3], tmp);
2014
            break;
2015
        default:
2016
            tcg_abort();
2017
            break;
2018
        }
2019
        if (op == 0xa) {
2020
            set_cc_s64(s, regs[r1]);
2021
        }
2022
        tcg_temp_free_i64(tmp);
2023
        break;
2024
    case 0x1d: /* RLL    R1,R3,D2(B2)        [RSY] */
2025
        if (b2) {
2026
            tmp = get_address(s, 0, b2, d2);
2027
            tcg_gen_andi_i64(tmp, tmp, 0x3f);
2028
        } else {
2029
            tmp = tcg_const_i64(d2 & 0x3f);
2030
        }
2031
        tmp32_1 = tcg_temp_new_i32();
2032
        tmp32_2 = load_reg32(r3);
2033
        tcg_gen_trunc_i64_i32(tmp32_1, tmp);
2034
        switch (op) {
2035
        case 0x1d:
2036
            tcg_gen_rotl_i32(tmp32_1, tmp32_2, tmp32_1);
2037
            break;
2038
        default:
2039
            tcg_abort();
2040
            break;
2041
        }
2042
        store_reg32(r1, tmp32_1);
2043
        tcg_temp_free_i64(tmp);
2044
        tcg_temp_free_i32(tmp32_1);
2045
        tcg_temp_free_i32(tmp32_2);
2046
        break;
2047
    case 0x4:  /* LMG      R1,R3,D2(B2)     [RSE] */
2048
    case 0x24: /* STMG     R1,R3,D2(B2)     [RSE] */
2049
        stm_len = 8;
2050
        goto do_mh;
2051
    case 0x26: /* STMH     R1,R3,D2(B2)     [RSE] */
2052
    case 0x96: /* LMH      R1,R3,D2(B2)     [RSE] */
2053
        stm_len = 4;
2054
do_mh:
2055
        /* Apparently, unrolling lmg/stmg of any size gains performance -
2056
           even for very long ones... */
2057
        tmp = get_address(s, 0, b2, d2);
2058
        tmp3 = tcg_const_i64(stm_len);
2059
        tmp4 = tcg_const_i64(32);
2060
        for (i = r1;; i = (i + 1) % 16) {
2061
            switch (op) {
2062
            case 0x4:
2063
                tcg_gen_qemu_ld64(regs[i], tmp, get_mem_index(s));
2064
                break;
2065
            case 0x96:
2066
                tmp2 = tcg_temp_new_i64();
2067
#if HOST_LONG_BITS == 32
2068
                tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
2069
                tcg_gen_trunc_i64_i32(TCGV_HIGH(regs[i]), tmp2);
2070
#else
2071
                tmp2 = tcg_temp_new_i64();
2072
                tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
2073
                tcg_gen_shl_i64(tmp2, tmp2, 4);
2074
                tcg_gen_ext32u_i64(regs[i], regs[i]);
2075
                tcg_gen_or_i64(regs[i], regs[i], tmp2);
2076
#endif
2077
                tcg_temp_free_i64(tmp2);
2078
                break;
2079
            case 0x24:
2080
                tcg_gen_qemu_st64(regs[i], tmp, get_mem_index(s));
2081
                break;
2082
            case 0x26:
2083
                tmp2 = tcg_temp_new_i64();
2084
                tcg_gen_shr_i64(tmp2, regs[i], tmp4);
2085
                tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
2086
                tcg_temp_free_i64(tmp2);
2087
                break;
2088
            default:
2089
                tcg_abort();
2090
            }
2091
            if (i == r3) {
2092
                break;
2093
            }
2094
            tcg_gen_add_i64(tmp, tmp, tmp3);
2095
        }
2096
        tcg_temp_free_i64(tmp);
2097
        tcg_temp_free_i64(tmp4);
2098
        break;
2099
    case 0x2c: /* STCMH R1,M3,D2(B2) [RSY] */
2100
        tmp = get_address(s, 0, b2, d2);
2101
        tmp32_1 = tcg_const_i32(r1);
2102
        tmp32_2 = tcg_const_i32(r3);
2103
        potential_page_fault(s);
2104
        gen_helper_stcmh(tmp32_1, tmp, tmp32_2);
2105
        tcg_temp_free_i64(tmp);
2106
        tcg_temp_free_i32(tmp32_1);
2107
        tcg_temp_free_i32(tmp32_2);
2108
        break;
2109
#ifndef CONFIG_USER_ONLY
2110
    case 0x2f: /* LCTLG     R1,R3,D2(B2)     [RSE] */
2111
        /* Load Control */
2112
        check_privileged(s, ilc);
2113
        tmp = get_address(s, 0, b2, d2);
2114
        tmp32_1 = tcg_const_i32(r1);
2115
        tmp32_2 = tcg_const_i32(r3);
2116
        potential_page_fault(s);
2117
        gen_helper_lctlg(tmp32_1, tmp, tmp32_2);
2118
        tcg_temp_free_i64(tmp);
2119
        tcg_temp_free_i32(tmp32_1);
2120
        tcg_temp_free_i32(tmp32_2);
2121
        break;
2122
    case 0x25: /* STCTG     R1,R3,D2(B2)     [RSE] */
2123
        /* Store Control */
2124
        check_privileged(s, ilc);
2125
        tmp = get_address(s, 0, b2, d2);
2126
        tmp32_1 = tcg_const_i32(r1);
2127
        tmp32_2 = tcg_const_i32(r3);
2128
        potential_page_fault(s);
2129
        gen_helper_stctg(tmp32_1, tmp, tmp32_2);
2130
        tcg_temp_free_i64(tmp);
2131
        tcg_temp_free_i32(tmp32_1);
2132
        tcg_temp_free_i32(tmp32_2);
2133
        break;
2134
#endif
2135
    case 0x30: /* CSG     R1,R3,D2(B2)     [RSY] */
2136
        tmp = get_address(s, 0, b2, d2);
2137
        tmp32_1 = tcg_const_i32(r1);
2138
        tmp32_2 = tcg_const_i32(r3);
2139
        potential_page_fault(s);
2140
        /* XXX rewrite in tcg */
2141
        gen_helper_csg(cc_op, tmp32_1, tmp, tmp32_2);
2142
        set_cc_static(s);
2143
        tcg_temp_free_i64(tmp);
2144
        tcg_temp_free_i32(tmp32_1);
2145
        tcg_temp_free_i32(tmp32_2);
2146
        break;
2147
    case 0x3e: /* CDSG R1,R3,D2(B2) [RSY] */
2148
        tmp = get_address(s, 0, b2, d2);
2149
        tmp32_1 = tcg_const_i32(r1);
2150
        tmp32_2 = tcg_const_i32(r3);
2151
        potential_page_fault(s);
2152
        /* XXX rewrite in tcg */
2153
        gen_helper_cdsg(cc_op, tmp32_1, tmp, tmp32_2);
2154
        set_cc_static(s);
2155
        tcg_temp_free_i64(tmp);
2156
        tcg_temp_free_i32(tmp32_1);
2157
        tcg_temp_free_i32(tmp32_2);
2158
        break;
2159
    case 0x51: /* TMY D1(B1),I2 [SIY] */
2160
        tmp = get_address(s, 0, b2, d2); /* SIY -> this is the destination */
2161
        tmp2 = tcg_const_i64((r1 << 4) | r3);
2162
        tcg_gen_qemu_ld8u(tmp, tmp, get_mem_index(s));
2163
        /* yes, this is a 32 bit operation with 64 bit tcg registers, because
2164
           that incurs less conversions */
2165
        cmp_64(s, tmp, tmp2, CC_OP_TM_32);
2166
        tcg_temp_free_i64(tmp);
2167
        tcg_temp_free_i64(tmp2);
2168
        break;
2169
    case 0x52: /* MVIY D1(B1),I2 [SIY] */
2170
        tmp = get_address(s, 0, b2, d2); /* SIY -> this is the destination */
2171
        tmp2 = tcg_const_i64((r1 << 4) | r3);
2172
        tcg_gen_qemu_st8(tmp2, tmp, get_mem_index(s));
2173
        tcg_temp_free_i64(tmp);
2174
        tcg_temp_free_i64(tmp2);
2175
        break;
2176
    case 0x55: /* CLIY D1(B1),I2 [SIY] */
2177
        tmp3 = get_address(s, 0, b2, d2); /* SIY -> this is the 1st operand */
2178
        tmp = tcg_temp_new_i64();
2179
        tmp32_1 = tcg_temp_new_i32();
2180
        tcg_gen_qemu_ld8u(tmp, tmp3, get_mem_index(s));
2181
        tcg_gen_trunc_i64_i32(tmp32_1, tmp);
2182
        cmp_u32c(s, tmp32_1, (r1 << 4) | r3);
2183
        tcg_temp_free_i64(tmp);
2184
        tcg_temp_free_i64(tmp3);
2185
        tcg_temp_free_i32(tmp32_1);
2186
        break;
2187
    case 0x80: /* ICMH      R1,M3,D2(B2)     [RSY] */
2188
        tmp = get_address(s, 0, b2, d2);
2189
        tmp32_1 = tcg_const_i32(r1);
2190
        tmp32_2 = tcg_const_i32(r3);
2191
        potential_page_fault(s);
2192
        /* XXX split CC calculation out */
2193
        gen_helper_icmh(cc_op, tmp32_1, tmp, tmp32_2);
2194
        set_cc_static(s);
2195
        tcg_temp_free_i64(tmp);
2196
        tcg_temp_free_i32(tmp32_1);
2197
        tcg_temp_free_i32(tmp32_2);
2198
        break;
2199
    default:
2200
        LOG_DISAS("illegal eb operation 0x%x\n", op);
2201
        gen_illegal_opcode(s, ilc);
2202
        break;
2203
    }
2204
}
2205

    
2206
static void disas_ed(DisasContext *s, int op, int r1, int x2, int b2, int d2,
2207
                     int r1b)
2208
{
2209
    TCGv_i32 tmp_r1, tmp32;
2210
    TCGv_i64 addr, tmp;
2211
    addr = get_address(s, x2, b2, d2);
2212
    tmp_r1 = tcg_const_i32(r1);
2213
    switch (op) {
2214
    case 0x5: /* LXDB R1,D2(X2,B2) [RXE] */
2215
        potential_page_fault(s);
2216
        gen_helper_lxdb(tmp_r1, addr);
2217
        break;
2218
    case 0x9: /* CEB    R1,D2(X2,B2)       [RXE] */
2219
        tmp = tcg_temp_new_i64();
2220
        tmp32 = load_freg32(r1);
2221
        tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
2222
        set_cc_cmp_f32_i64(s, tmp32, tmp);
2223
        tcg_temp_free_i64(tmp);
2224
        tcg_temp_free_i32(tmp32);
2225
        break;
2226
    case 0xa: /* AEB    R1,D2(X2,B2)       [RXE] */
2227
        tmp = tcg_temp_new_i64();
2228
        tmp32 = tcg_temp_new_i32();
2229
        tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
2230
        tcg_gen_trunc_i64_i32(tmp32, tmp);
2231
        gen_helper_aeb(tmp_r1, tmp32);
2232
        tcg_temp_free_i64(tmp);
2233
        tcg_temp_free_i32(tmp32);
2234

    
2235
        tmp32 = load_freg32(r1);
2236
        set_cc_nz_f32(s, tmp32);
2237
        tcg_temp_free_i32(tmp32);
2238
        break;
2239
    case 0xb: /* SEB    R1,D2(X2,B2)       [RXE] */
2240
        tmp = tcg_temp_new_i64();
2241
        tmp32 = tcg_temp_new_i32();
2242
        tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
2243
        tcg_gen_trunc_i64_i32(tmp32, tmp);
2244
        gen_helper_seb(tmp_r1, tmp32);
2245
        tcg_temp_free_i64(tmp);
2246
        tcg_temp_free_i32(tmp32);
2247

    
2248
        tmp32 = load_freg32(r1);
2249
        set_cc_nz_f32(s, tmp32);
2250
        tcg_temp_free_i32(tmp32);
2251
        break;
2252
    case 0xd: /* DEB    R1,D2(X2,B2)       [RXE] */
2253
        tmp = tcg_temp_new_i64();
2254
        tmp32 = tcg_temp_new_i32();
2255
        tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
2256
        tcg_gen_trunc_i64_i32(tmp32, tmp);
2257
        gen_helper_deb(tmp_r1, tmp32);
2258
        tcg_temp_free_i64(tmp);
2259
        tcg_temp_free_i32(tmp32);
2260
        break;
2261
    case 0x10: /* TCEB   R1,D2(X2,B2)       [RXE] */
2262
        potential_page_fault(s);
2263
        gen_helper_tceb(cc_op, tmp_r1, addr);
2264
        set_cc_static(s);
2265
        break;
2266
    case 0x11: /* TCDB   R1,D2(X2,B2)       [RXE] */
2267
        potential_page_fault(s);
2268
        gen_helper_tcdb(cc_op, tmp_r1, addr);
2269
        set_cc_static(s);
2270
        break;
2271
    case 0x12: /* TCXB   R1,D2(X2,B2)       [RXE] */
2272
        potential_page_fault(s);
2273
        gen_helper_tcxb(cc_op, tmp_r1, addr);
2274
        set_cc_static(s);
2275
        break;
2276
    case 0x17: /* MEEB   R1,D2(X2,B2)       [RXE] */
2277
        tmp = tcg_temp_new_i64();
2278
        tmp32 = tcg_temp_new_i32();
2279
        tcg_gen_qemu_ld32u(tmp, addr, get_mem_index(s));
2280
        tcg_gen_trunc_i64_i32(tmp32, tmp);
2281
        gen_helper_meeb(tmp_r1, tmp32);
2282
        tcg_temp_free_i64(tmp);
2283
        tcg_temp_free_i32(tmp32);
2284
        break;
2285
    case 0x19: /* CDB    R1,D2(X2,B2)       [RXE] */
2286
        potential_page_fault(s);
2287
        gen_helper_cdb(cc_op, tmp_r1, addr);
2288
        set_cc_static(s);
2289
        break;
2290
    case 0x1a: /* ADB    R1,D2(X2,B2)       [RXE] */
2291
        potential_page_fault(s);
2292
        gen_helper_adb(cc_op, tmp_r1, addr);
2293
        set_cc_static(s);
2294
        break;
2295
    case 0x1b: /* SDB    R1,D2(X2,B2)       [RXE] */
2296
        potential_page_fault(s);
2297
        gen_helper_sdb(cc_op, tmp_r1, addr);
2298
        set_cc_static(s);
2299
        break;
2300
    case 0x1c: /* MDB    R1,D2(X2,B2)       [RXE] */
2301
        potential_page_fault(s);
2302
        gen_helper_mdb(tmp_r1, addr);
2303
        break;
2304
    case 0x1d: /* DDB    R1,D2(X2,B2)       [RXE] */
2305
        potential_page_fault(s);
2306
        gen_helper_ddb(tmp_r1, addr);
2307
        break;
2308
    case 0x1e: /* MADB  R1,R3,D2(X2,B2) [RXF] */
2309
        /* for RXF insns, r1 is R3 and r1b is R1 */
2310
        tmp32 = tcg_const_i32(r1b);
2311
        potential_page_fault(s);
2312
        gen_helper_madb(tmp32, addr, tmp_r1);
2313
        tcg_temp_free_i32(tmp32);
2314
        break;
2315
    default:
2316
        LOG_DISAS("illegal ed operation 0x%x\n", op);
2317
        gen_illegal_opcode(s, 3);
2318
        return;
2319
    }
2320
    tcg_temp_free_i32(tmp_r1);
2321
    tcg_temp_free_i64(addr);
2322
}
2323

    
2324
static void disas_a5(DisasContext *s, int op, int r1, int i2)
2325
{
2326
    TCGv_i64 tmp, tmp2;
2327
    TCGv_i32 tmp32;
2328
    LOG_DISAS("disas_a5: op 0x%x r1 %d i2 0x%x\n", op, r1, i2);
2329
    switch (op) {
2330
    case 0x0: /* IIHH     R1,I2     [RI] */
2331
        tmp = tcg_const_i64(i2);
2332
        tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 48, 16);
2333
        break;
2334
    case 0x1: /* IIHL     R1,I2     [RI] */
2335
        tmp = tcg_const_i64(i2);
2336
        tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 32, 16);
2337
        break;
2338
    case 0x2: /* IILH     R1,I2     [RI] */
2339
        tmp = tcg_const_i64(i2);
2340
        tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 16, 16);
2341
        break;
2342
    case 0x3: /* IILL     R1,I2     [RI] */
2343
        tmp = tcg_const_i64(i2);
2344
        tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 0, 16);
2345
        break;
2346
    case 0x4: /* NIHH     R1,I2     [RI] */
2347
    case 0x8: /* OIHH     R1,I2     [RI] */
2348
        tmp = load_reg(r1);
2349
        tmp32 = tcg_temp_new_i32();
2350
        switch (op) {
2351
        case 0x4:
2352
            tmp2 = tcg_const_i64((((uint64_t)i2) << 48)
2353
                               | 0x0000ffffffffffffULL);
2354
            tcg_gen_and_i64(tmp, tmp, tmp2);
2355
            break;
2356
        case 0x8:
2357
            tmp2 = tcg_const_i64(((uint64_t)i2) << 48);
2358
            tcg_gen_or_i64(tmp, tmp, tmp2);
2359
            break;
2360
        default:
2361
            tcg_abort();
2362
        }
2363
        store_reg(r1, tmp);
2364
        tcg_gen_shri_i64(tmp2, tmp, 48);
2365
        tcg_gen_trunc_i64_i32(tmp32, tmp2);
2366
        set_cc_nz_u32(s, tmp32);
2367
        tcg_temp_free_i64(tmp2);
2368
        tcg_temp_free_i32(tmp32);
2369
        break;
2370
    case 0x5: /* NIHL     R1,I2     [RI] */
2371
    case 0x9: /* OIHL     R1,I2     [RI] */
2372
        tmp = load_reg(r1);
2373
        tmp32 = tcg_temp_new_i32();
2374
        switch (op) {
2375
        case 0x5:
2376
            tmp2 = tcg_const_i64((((uint64_t)i2) << 32)
2377
                               | 0xffff0000ffffffffULL);
2378
            tcg_gen_and_i64(tmp, tmp, tmp2);
2379
            break;
2380
        case 0x9:
2381
            tmp2 = tcg_const_i64(((uint64_t)i2) << 32);
2382
            tcg_gen_or_i64(tmp, tmp, tmp2);
2383
            break;
2384
        default:
2385
            tcg_abort();
2386
        }
2387
        store_reg(r1, tmp);
2388
        tcg_gen_shri_i64(tmp2, tmp, 32);
2389
        tcg_gen_trunc_i64_i32(tmp32, tmp2);
2390
        tcg_gen_andi_i32(tmp32, tmp32, 0xffff);
2391
        set_cc_nz_u32(s, tmp32);
2392
        tcg_temp_free_i64(tmp2);
2393
        tcg_temp_free_i32(tmp32);
2394
        break;
2395
    case 0x6: /* NILH     R1,I2     [RI] */
2396
    case 0xa: /* OILH     R1,I2     [RI] */
2397
        tmp = load_reg(r1);
2398
        tmp32 = tcg_temp_new_i32();
2399
        switch (op) {
2400
        case 0x6:
2401
            tmp2 = tcg_const_i64((((uint64_t)i2) << 16)
2402
                               | 0xffffffff0000ffffULL);
2403
            tcg_gen_and_i64(tmp, tmp, tmp2);
2404
            break;
2405
        case 0xa:
2406
            tmp2 = tcg_const_i64(((uint64_t)i2) << 16);
2407
            tcg_gen_or_i64(tmp, tmp, tmp2);
2408
            break;
2409
        default:
2410
            tcg_abort();
2411
        }
2412
        store_reg(r1, tmp);
2413
        tcg_gen_shri_i64(tmp, tmp, 16);
2414
        tcg_gen_trunc_i64_i32(tmp32, tmp);
2415
        tcg_gen_andi_i32(tmp32, tmp32, 0xffff);
2416
        set_cc_nz_u32(s, tmp32);
2417
        tcg_temp_free_i64(tmp2);
2418
        tcg_temp_free_i32(tmp32);
2419
        break;
2420
    case 0x7: /* NILL     R1,I2     [RI] */
2421
    case 0xb: /* OILL     R1,I2     [RI] */
2422
        tmp = load_reg(r1);
2423
        tmp32 = tcg_temp_new_i32();
2424
        switch (op) {
2425
        case 0x7:
2426
            tmp2 = tcg_const_i64(i2 | 0xffffffffffff0000ULL);
2427
            tcg_gen_and_i64(tmp, tmp, tmp2);
2428
            break;
2429
        case 0xb:
2430
            tmp2 = tcg_const_i64(i2);
2431
            tcg_gen_or_i64(tmp, tmp, tmp2);
2432
            break;
2433
        default:
2434
            tcg_abort();
2435
        }
2436
        store_reg(r1, tmp);
2437
        tcg_gen_trunc_i64_i32(tmp32, tmp);
2438
        tcg_gen_andi_i32(tmp32, tmp32, 0xffff);
2439
        set_cc_nz_u32(s, tmp32);        /* signedness should not matter here */
2440
        tcg_temp_free_i64(tmp2);
2441
        tcg_temp_free_i32(tmp32);
2442
        break;
2443
    case 0xc: /* LLIHH     R1,I2     [RI] */
2444
        tmp = tcg_const_i64( ((uint64_t)i2) << 48 );
2445
        store_reg(r1, tmp);
2446
        break;
2447
    case 0xd: /* LLIHL     R1,I2     [RI] */
2448
        tmp = tcg_const_i64( ((uint64_t)i2) << 32 );
2449
        store_reg(r1, tmp);
2450
        break;
2451
    case 0xe: /* LLILH     R1,I2     [RI] */
2452
        tmp = tcg_const_i64( ((uint64_t)i2) << 16 );
2453
        store_reg(r1, tmp);
2454
        break;
2455
    case 0xf: /* LLILL     R1,I2     [RI] */
2456
        tmp = tcg_const_i64(i2);
2457
        store_reg(r1, tmp);
2458
        break;
2459
    default:
2460
        LOG_DISAS("illegal a5 operation 0x%x\n", op);
2461
        gen_illegal_opcode(s, 2);
2462
        return;
2463
    }
2464
    tcg_temp_free_i64(tmp);
2465
}
2466

    
2467
static void disas_a7(DisasContext *s, int op, int r1, int i2)
2468
{
2469
    TCGv_i64 tmp, tmp2;
2470
    TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
2471
    int l1;
2472

    
2473
    LOG_DISAS("disas_a7: op 0x%x r1 %d i2 0x%x\n", op, r1, i2);
2474
    switch (op) {
2475
    case 0x0: /* TMLH or TMH     R1,I2     [RI] */
2476
    case 0x1: /* TMLL or TML     R1,I2     [RI] */
2477
    case 0x2: /* TMHH     R1,I2     [RI] */
2478
    case 0x3: /* TMHL     R1,I2     [RI] */
2479
        tmp = load_reg(r1);
2480
        tmp2 = tcg_const_i64((uint16_t)i2);
2481
        switch (op) {
2482
        case 0x0:
2483
            tcg_gen_shri_i64(tmp, tmp, 16);
2484
            break;
2485
        case 0x1:
2486
            break;
2487
        case 0x2:
2488
            tcg_gen_shri_i64(tmp, tmp, 48);
2489
            break;
2490
        case 0x3:
2491
            tcg_gen_shri_i64(tmp, tmp, 32);
2492
            break;
2493
        }
2494
        tcg_gen_andi_i64(tmp, tmp, 0xffff);
2495
        cmp_64(s, tmp, tmp2, CC_OP_TM_64);
2496
        tcg_temp_free_i64(tmp);
2497
        tcg_temp_free_i64(tmp2);
2498
        break;
2499
    case 0x4: /* brc m1, i2 */
2500
        gen_brc(r1, s, i2 * 2LL);
2501
        return;
2502
    case 0x5: /* BRAS     R1,I2     [RI] */
2503
        tmp = tcg_const_i64(pc_to_link_info(s, s->pc + 4));
2504
        store_reg(r1, tmp);
2505
        tcg_temp_free_i64(tmp);
2506
        gen_goto_tb(s, 0, s->pc + i2 * 2LL);
2507
        s->is_jmp = DISAS_TB_JUMP;
2508
        break;
2509
    case 0x6: /* BRCT     R1,I2     [RI] */
2510
        tmp32_1 = load_reg32(r1);
2511
        tcg_gen_subi_i32(tmp32_1, tmp32_1, 1);
2512
        store_reg32(r1, tmp32_1);
2513
        gen_update_cc_op(s);
2514
        l1 = gen_new_label();
2515
        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp32_1, 0, l1);
2516
        gen_goto_tb(s, 0, s->pc + (i2 * 2LL));
2517
        gen_set_label(l1);
2518
        gen_goto_tb(s, 1, s->pc + 4);
2519
        s->is_jmp = DISAS_TB_JUMP;
2520
        tcg_temp_free_i32(tmp32_1);
2521
        break;
2522
    case 0x7: /* BRCTG     R1,I2     [RI] */
2523
        tmp = load_reg(r1);
2524
        tcg_gen_subi_i64(tmp, tmp, 1);
2525
        store_reg(r1, tmp);
2526
        gen_update_cc_op(s);
2527
        l1 = gen_new_label();
2528
        tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1);
2529
        gen_goto_tb(s, 0, s->pc + (i2 * 2LL));
2530
        gen_set_label(l1);
2531
        gen_goto_tb(s, 1, s->pc + 4);
2532
        s->is_jmp = DISAS_TB_JUMP;
2533
        tcg_temp_free_i64(tmp);
2534
        break;
2535
    case 0x8: /* lhi r1, i2 */
2536
        tmp32_1 = tcg_const_i32(i2);
2537
        store_reg32(r1, tmp32_1);
2538
        tcg_temp_free_i32(tmp32_1);
2539
        break;
2540
    case 0x9: /* lghi r1, i2 */
2541
        tmp = tcg_const_i64(i2);
2542
        store_reg(r1, tmp);
2543
        tcg_temp_free_i64(tmp);
2544
        break;
2545
    case 0xa: /* AHI     R1,I2     [RI] */
2546
        tmp32_1 = load_reg32(r1);
2547
        tmp32_2 = tcg_temp_new_i32();
2548
        tmp32_3 = tcg_const_i32(i2);
2549

    
2550
        if (i2 < 0) {
2551
            tcg_gen_subi_i32(tmp32_2, tmp32_1, -i2);
2552
        } else {
2553
            tcg_gen_add_i32(tmp32_2, tmp32_1, tmp32_3);
2554
        }
2555

    
2556
        store_reg32(r1, tmp32_2);
2557
        set_cc_add32(s, tmp32_1, tmp32_3, tmp32_2);
2558
        tcg_temp_free_i32(tmp32_1);
2559
        tcg_temp_free_i32(tmp32_2);
2560
        tcg_temp_free_i32(tmp32_3);
2561
        break;
2562
    case 0xb: /* aghi r1, i2 */
2563
        tmp = load_reg(r1);
2564
        tmp2 = tcg_const_i64(i2);
2565

    
2566
        if (i2 < 0) {
2567
            tcg_gen_subi_i64(regs[r1], tmp, -i2);
2568
        } else {
2569
            tcg_gen_add_i64(regs[r1], tmp, tmp2);
2570
        }
2571
        set_cc_add64(s, tmp, tmp2, regs[r1]);
2572
        tcg_temp_free_i64(tmp);
2573
        tcg_temp_free_i64(tmp2);
2574
        break;
2575
    case 0xc: /* MHI     R1,I2     [RI] */
2576
        tmp32_1 = load_reg32(r1);
2577
        tcg_gen_muli_i32(tmp32_1, tmp32_1, i2);
2578
        store_reg32(r1, tmp32_1);
2579
        tcg_temp_free_i32(tmp32_1);
2580
        break;
2581
    case 0xd: /* MGHI     R1,I2     [RI] */
2582
        tmp = load_reg(r1);
2583
        tcg_gen_muli_i64(tmp, tmp, i2);
2584
        store_reg(r1, tmp);
2585
        tcg_temp_free_i64(tmp);
2586
        break;
2587
    case 0xe: /* CHI     R1,I2     [RI] */
2588
        tmp32_1 = load_reg32(r1);
2589
        cmp_s32c(s, tmp32_1, i2);
2590
        tcg_temp_free_i32(tmp32_1);
2591
        break;
2592
    case 0xf: /* CGHI     R1,I2     [RI] */
2593
        tmp = load_reg(r1);
2594
        cmp_s64c(s, tmp, i2);
2595
        tcg_temp_free_i64(tmp);
2596
        break;
2597
    default:
2598
        LOG_DISAS("illegal a7 operation 0x%x\n", op);
2599
        gen_illegal_opcode(s, 2);
2600
        return;
2601
    }
2602
}
2603

    
2604
static void disas_b2(DisasContext *s, int op, uint32_t insn)
2605
{
2606
    TCGv_i64 tmp, tmp2, tmp3;
2607
    TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
2608
    int r1, r2;
2609
    int ilc = 2;
2610
#ifndef CONFIG_USER_ONLY
2611
    int r3, d2, b2;
2612
#endif
2613

    
2614
    r1 = (insn >> 4) & 0xf;
2615
    r2 = insn & 0xf;
2616

    
2617
    LOG_DISAS("disas_b2: op 0x%x r1 %d r2 %d\n", op, r1, r2);
2618

    
2619
    switch (op) {
2620
    case 0x22: /* IPM    R1               [RRE] */
2621
        tmp32_1 = tcg_const_i32(r1);
2622
        gen_op_calc_cc(s);
2623
        gen_helper_ipm(cc_op, tmp32_1);
2624
        tcg_temp_free_i32(tmp32_1);
2625
        break;
2626
    case 0x41: /* CKSM    R1,R2     [RRE] */
2627
        tmp32_1 = tcg_const_i32(r1);
2628
        tmp32_2 = tcg_const_i32(r2);
2629
        potential_page_fault(s);
2630
        gen_helper_cksm(tmp32_1, tmp32_2);
2631
        tcg_temp_free_i32(tmp32_1);
2632
        tcg_temp_free_i32(tmp32_2);
2633
        gen_op_movi_cc(s, 0);
2634
        break;
2635
    case 0x4e: /* SAR     R1,R2     [RRE] */
2636
        tmp32_1 = load_reg32(r2);
2637
        tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, aregs[r1]));
2638
        tcg_temp_free_i32(tmp32_1);
2639
        break;
2640
    case 0x4f: /* EAR     R1,R2     [RRE] */
2641
        tmp32_1 = tcg_temp_new_i32();
2642
        tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, aregs[r2]));
2643
        store_reg32(r1, tmp32_1);
2644
        tcg_temp_free_i32(tmp32_1);
2645
        break;
2646
    case 0x52: /* MSR     R1,R2     [RRE] */
2647
        tmp32_1 = load_reg32(r1);
2648
        tmp32_2 = load_reg32(r2);
2649
        tcg_gen_mul_i32(tmp32_1, tmp32_1, tmp32_2);
2650
        store_reg32(r1, tmp32_1);
2651
        tcg_temp_free_i32(tmp32_1);
2652
        tcg_temp_free_i32(tmp32_2);
2653
        break;
2654
    case 0x54: /* MVPG     R1,R2     [RRE] */
2655
        tmp = load_reg(0);
2656
        tmp2 = load_reg(r1);
2657
        tmp3 = load_reg(r2);
2658
        potential_page_fault(s);
2659
        gen_helper_mvpg(tmp, tmp2, tmp3);
2660
        tcg_temp_free_i64(tmp);
2661
        tcg_temp_free_i64(tmp2);
2662
        tcg_temp_free_i64(tmp3);
2663
        /* XXX check CCO bit and set CC accordingly */
2664
        gen_op_movi_cc(s, 0);
2665
        break;
2666
    case 0x55: /* MVST     R1,R2     [RRE] */
2667
        tmp32_1 = load_reg32(0);
2668
        tmp32_2 = tcg_const_i32(r1);
2669
        tmp32_3 = tcg_const_i32(r2);
2670
        potential_page_fault(s);
2671
        gen_helper_mvst(tmp32_1, tmp32_2, tmp32_3);
2672
        tcg_temp_free_i32(tmp32_1);
2673
        tcg_temp_free_i32(tmp32_2);
2674
        tcg_temp_free_i32(tmp32_3);
2675
        gen_op_movi_cc(s, 1);
2676
        break;
2677
    case 0x5d: /* CLST     R1,R2     [RRE] */
2678
        tmp32_1 = load_reg32(0);
2679
        tmp32_2 = tcg_const_i32(r1);
2680
        tmp32_3 = tcg_const_i32(r2);
2681
        potential_page_fault(s);
2682
        gen_helper_clst(cc_op, tmp32_1, tmp32_2, tmp32_3);
2683
        set_cc_static(s);
2684
        tcg_temp_free_i32(tmp32_1);
2685
        tcg_temp_free_i32(tmp32_2);
2686
        tcg_temp_free_i32(tmp32_3);
2687
        break;
2688
    case 0x5e: /* SRST     R1,R2     [RRE] */
2689
        tmp32_1 = load_reg32(0);
2690
        tmp32_2 = tcg_const_i32(r1);
2691
        tmp32_3 = tcg_const_i32(r2);
2692
        potential_page_fault(s);
2693
        gen_helper_srst(cc_op, tmp32_1, tmp32_2, tmp32_3);
2694
        set_cc_static(s);
2695
        tcg_temp_free_i32(tmp32_1);
2696
        tcg_temp_free_i32(tmp32_2);
2697
        tcg_temp_free_i32(tmp32_3);
2698
        break;
2699

    
2700
#ifndef CONFIG_USER_ONLY
2701
    case 0x02: /* STIDP     D2(B2)     [S] */
2702
        /* Store CPU ID */
2703
        check_privileged(s, ilc);
2704
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
2705
        tmp = get_address(s, 0, b2, d2);
2706
        potential_page_fault(s);
2707
        gen_helper_stidp(tmp);
2708
        tcg_temp_free_i64(tmp);
2709
        break;
2710
    case 0x04: /* SCK       D2(B2)     [S] */
2711
        /* Set Clock */
2712
        check_privileged(s, ilc);
2713
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
2714
        tmp = get_address(s, 0, b2, d2);
2715
        potential_page_fault(s);
2716
        gen_helper_sck(cc_op, tmp);
2717
        set_cc_static(s);
2718
        tcg_temp_free_i64(tmp);
2719
        break;
2720
    case 0x05: /* STCK     D2(B2)     [S] */
2721
        /* Store Clock */
2722
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
2723
        tmp = get_address(s, 0, b2, d2);
2724
        potential_page_fault(s);
2725
        gen_helper_stck(cc_op, tmp);
2726
        set_cc_static(s);
2727
        tcg_temp_free_i64(tmp);
2728
        break;
2729
    case 0x06: /* SCKC     D2(B2)     [S] */
2730
        /* Set Clock Comparator */
2731
        check_privileged(s, ilc);
2732
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
2733
        tmp = get_address(s, 0, b2, d2);
2734
        potential_page_fault(s);
2735
        gen_helper_sckc(tmp);
2736
        tcg_temp_free_i64(tmp);
2737
        break;
2738
    case 0x07: /* STCKC    D2(B2)     [S] */
2739
        /* Store Clock Comparator */
2740
        check_privileged(s, ilc);
2741
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
2742
        tmp = get_address(s, 0, b2, d2);
2743
        potential_page_fault(s);
2744
        gen_helper_stckc(tmp);
2745
        tcg_temp_free_i64(tmp);
2746
        break;
2747
    case 0x08: /* SPT      D2(B2)     [S] */
2748
        /* Set CPU Timer */
2749
        check_privileged(s, ilc);
2750
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
2751
        tmp = get_address(s, 0, b2, d2);
2752
        potential_page_fault(s);
2753
        gen_helper_spt(tmp);
2754
        tcg_temp_free_i64(tmp);
2755
        break;
2756
    case 0x09: /* STPT     D2(B2)     [S] */
2757
        /* Store CPU Timer */
2758
        check_privileged(s, ilc);
2759
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
2760
        tmp = get_address(s, 0, b2, d2);
2761
        potential_page_fault(s);
2762
        gen_helper_stpt(tmp);
2763
        tcg_temp_free_i64(tmp);
2764
        break;
2765
    case 0x0a: /* SPKA     D2(B2)     [S] */
2766
        /* Set PSW Key from Address */
2767
        check_privileged(s, ilc);
2768
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
2769
        tmp = get_address(s, 0, b2, d2);
2770
        tmp2 = tcg_temp_new_i64();
2771
        tcg_gen_andi_i64(tmp2, psw_mask, ~PSW_MASK_KEY);
2772
        tcg_gen_shli_i64(tmp, tmp, PSW_SHIFT_KEY - 4);
2773
        tcg_gen_or_i64(psw_mask, tmp2, tmp);
2774
        tcg_temp_free_i64(tmp2);
2775
        tcg_temp_free_i64(tmp);
2776
        break;
2777
    case 0x0d: /* PTLB                [S] */
2778
        /* Purge TLB */
2779
        check_privileged(s, ilc);
2780
        gen_helper_ptlb();
2781
        break;
2782
    case 0x10: /* SPX      D2(B2)     [S] */
2783
        /* Set Prefix Register */
2784
        check_privileged(s, ilc);
2785
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
2786
        tmp = get_address(s, 0, b2, d2);
2787
        potential_page_fault(s);
2788
        gen_helper_spx(tmp);
2789
        tcg_temp_free_i64(tmp);
2790
        break;
2791
    case 0x11: /* STPX     D2(B2)     [S] */
2792
        /* Store Prefix */
2793
        check_privileged(s, ilc);
2794
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
2795
        tmp = get_address(s, 0, b2, d2);
2796
        tmp2 = tcg_temp_new_i64();
2797
        tcg_gen_ld_i64(tmp2, cpu_env, offsetof(CPUState, psa));
2798
        tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
2799
        tcg_temp_free_i64(tmp);
2800
        tcg_temp_free_i64(tmp2);
2801
        break;
2802
    case 0x12: /* STAP     D2(B2)     [S] */
2803
        /* Store CPU Address */
2804
        check_privileged(s, ilc);
2805
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
2806
        tmp = get_address(s, 0, b2, d2);
2807
        tmp2 = tcg_temp_new_i64();
2808
        tmp32_1 = tcg_temp_new_i32();
2809
        tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, cpu_num));
2810
        tcg_gen_extu_i32_i64(tmp2, tmp32_1);
2811
        tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
2812
        tcg_temp_free_i64(tmp);
2813
        tcg_temp_free_i64(tmp2);
2814
        tcg_temp_free_i32(tmp32_1);
2815
        break;
2816
    case 0x21: /* IPTE     R1,R2      [RRE] */
2817
        /* Invalidate PTE */
2818
        check_privileged(s, ilc);
2819
        r1 = (insn >> 4) & 0xf;
2820
        r2 = insn & 0xf;
2821
        tmp = load_reg(r1);
2822
        tmp2 = load_reg(r2);
2823
        gen_helper_ipte(tmp, tmp2);
2824
        tcg_temp_free_i64(tmp);
2825
        tcg_temp_free_i64(tmp2);
2826
        break;
2827
    case 0x29: /* ISKE     R1,R2      [RRE] */
2828
        /* Insert Storage Key Extended */
2829
        check_privileged(s, ilc);
2830
        r1 = (insn >> 4) & 0xf;
2831
        r2 = insn & 0xf;
2832
        tmp = load_reg(r2);
2833
        tmp2 = tcg_temp_new_i64();
2834
        gen_helper_iske(tmp2, tmp);
2835
        store_reg(r1, tmp2);
2836
        tcg_temp_free_i64(tmp);
2837
        tcg_temp_free_i64(tmp2);
2838
        break;
2839
    case 0x2a: /* RRBE     R1,R2      [RRE] */
2840
        /* Set Storage Key Extended */
2841
        check_privileged(s, ilc);
2842
        r1 = (insn >> 4) & 0xf;
2843
        r2 = insn & 0xf;
2844
        tmp32_1 = load_reg32(r1);
2845
        tmp = load_reg(r2);
2846
        gen_helper_rrbe(cc_op, tmp32_1, tmp);
2847
        set_cc_static(s);
2848
        tcg_temp_free_i32(tmp32_1);
2849
        tcg_temp_free_i64(tmp);
2850
        break;
2851
    case 0x2b: /* SSKE     R1,R2      [RRE] */
2852
        /* Set Storage Key Extended */
2853
        check_privileged(s, ilc);
2854
        r1 = (insn >> 4) & 0xf;
2855
        r2 = insn & 0xf;
2856
        tmp32_1 = load_reg32(r1);
2857
        tmp = load_reg(r2);
2858
        gen_helper_sske(tmp32_1, tmp);
2859
        tcg_temp_free_i32(tmp32_1);
2860
        tcg_temp_free_i64(tmp);
2861
        break;
2862
    case 0x34: /* STCH ? */
2863
        /* Store Subchannel */
2864
        check_privileged(s, ilc);
2865
        gen_op_movi_cc(s, 3);
2866
        break;
2867
    case 0x46: /* STURA    R1,R2      [RRE] */
2868
        /* Store Using Real Address */
2869
        check_privileged(s, ilc);
2870
        r1 = (insn >> 4) & 0xf;
2871
        r2 = insn & 0xf;
2872
        tmp32_1 = load_reg32(r1);
2873
        tmp = load_reg(r2);
2874
        potential_page_fault(s);
2875
        gen_helper_stura(tmp, tmp32_1);
2876
        tcg_temp_free_i32(tmp32_1);
2877
        tcg_temp_free_i64(tmp);
2878
        break;
2879
    case 0x50: /* CSP      R1,R2      [RRE] */
2880
        /* Compare And Swap And Purge */
2881
        check_privileged(s, ilc);
2882
        r1 = (insn >> 4) & 0xf;
2883
        r2 = insn & 0xf;
2884
        tmp32_1 = tcg_const_i32(r1);
2885
        tmp32_2 = tcg_const_i32(r2);
2886
        gen_helper_csp(cc_op, tmp32_1, tmp32_2);
2887
        set_cc_static(s);
2888
        tcg_temp_free_i32(tmp32_1);
2889
        tcg_temp_free_i32(tmp32_2);
2890
        break;
2891
    case 0x5f: /* CHSC ? */
2892
        /* Channel Subsystem Call */
2893
        check_privileged(s, ilc);
2894
        gen_op_movi_cc(s, 3);
2895
        break;
2896
    case 0x78: /* STCKE    D2(B2)     [S] */
2897
        /* Store Clock Extended */
2898
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
2899
        tmp = get_address(s, 0, b2, d2);
2900
        potential_page_fault(s);
2901
        gen_helper_stcke(cc_op, tmp);
2902
        set_cc_static(s);
2903
        tcg_temp_free_i64(tmp);
2904
        break;
2905
    case 0x79: /* SACF    D2(B2)     [S] */
2906
        /* Store Clock Extended */
2907
        check_privileged(s, ilc);
2908
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
2909
        tmp = get_address(s, 0, b2, d2);
2910
        potential_page_fault(s);
2911
        gen_helper_sacf(tmp);
2912
        tcg_temp_free_i64(tmp);
2913
        /* addressing mode has changed, so end the block */
2914
        s->pc += ilc * 2;
2915
        update_psw_addr(s);
2916
        s->is_jmp = DISAS_EXCP;
2917
        break;
2918
    case 0x7d: /* STSI     D2,(B2)     [S] */
2919
        check_privileged(s, ilc);
2920
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
2921
        tmp = get_address(s, 0, b2, d2);
2922
        tmp32_1 = load_reg32(0);
2923
        tmp32_2 = load_reg32(1);
2924
        potential_page_fault(s);
2925
        gen_helper_stsi(cc_op, tmp, tmp32_1, tmp32_2);
2926
        set_cc_static(s);
2927
        tcg_temp_free_i64(tmp);
2928
        tcg_temp_free_i32(tmp32_1);
2929
        tcg_temp_free_i32(tmp32_2);
2930
        break;
2931
    case 0x9d: /* LFPC      D2(B2)   [S] */
2932
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
2933
        tmp = get_address(s, 0, b2, d2);
2934
        tmp2 = tcg_temp_new_i64();
2935
        tmp32_1 = tcg_temp_new_i32();
2936
        tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
2937
        tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
2938
        tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, fpc));
2939
        tcg_temp_free_i64(tmp);
2940
        tcg_temp_free_i64(tmp2);
2941
        tcg_temp_free_i32(tmp32_1);
2942
        break;
2943
    case 0xb1: /* STFL     D2(B2)     [S] */
2944
        /* Store Facility List (CPU features) at 200 */
2945
        check_privileged(s, ilc);
2946
        tmp2 = tcg_const_i64(0xc0000000);
2947
        tmp = tcg_const_i64(200);
2948
        tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
2949
        tcg_temp_free_i64(tmp2);
2950
        tcg_temp_free_i64(tmp);
2951
        break;
2952
    case 0xb2: /* LPSWE    D2(B2)     [S] */
2953
        /* Load PSW Extended */
2954
        check_privileged(s, ilc);
2955
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
2956
        tmp = get_address(s, 0, b2, d2);
2957
        tmp2 = tcg_temp_new_i64();
2958
        tmp3 = tcg_temp_new_i64();
2959
        tcg_gen_qemu_ld64(tmp2, tmp, get_mem_index(s));
2960
        tcg_gen_addi_i64(tmp, tmp, 8);
2961
        tcg_gen_qemu_ld64(tmp3, tmp, get_mem_index(s));
2962
        gen_helper_load_psw(tmp2, tmp3);
2963
        /* we need to keep cc_op intact */
2964
        s->is_jmp = DISAS_JUMP;
2965
        tcg_temp_free_i64(tmp);
2966
        break;
2967
    case 0x20: /* SERVC     R1,R2     [RRE] */
2968
        /* SCLP Service call (PV hypercall) */
2969
        check_privileged(s, ilc);
2970
        potential_page_fault(s);
2971
        tmp32_1 = load_reg32(r2);
2972
        tmp = load_reg(r1);
2973
        gen_helper_servc(cc_op, tmp32_1, tmp);
2974
        set_cc_static(s);
2975
        tcg_temp_free_i32(tmp32_1);
2976
        tcg_temp_free_i64(tmp);
2977
        break;
2978
#endif
2979
    default:
2980
        LOG_DISAS("illegal b2 operation 0x%x\n", op);
2981
        gen_illegal_opcode(s, ilc);
2982
        break;
2983
    }
2984
}
2985

    
2986
static void disas_b3(DisasContext *s, int op, int m3, int r1, int r2)
2987
{
2988
    TCGv_i64 tmp;
2989
    TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
2990
    LOG_DISAS("disas_b3: op 0x%x m3 0x%x r1 %d r2 %d\n", op, m3, r1, r2);
2991
#define FP_HELPER(i) \
2992
    tmp32_1 = tcg_const_i32(r1); \
2993
    tmp32_2 = tcg_const_i32(r2); \
2994
    gen_helper_ ## i (tmp32_1, tmp32_2); \
2995
    tcg_temp_free_i32(tmp32_1); \
2996
    tcg_temp_free_i32(tmp32_2);
2997

    
2998
#define FP_HELPER_CC(i) \
2999
    tmp32_1 = tcg_const_i32(r1); \
3000
    tmp32_2 = tcg_const_i32(r2); \
3001
    gen_helper_ ## i (cc_op, tmp32_1, tmp32_2); \
3002
    set_cc_static(s); \
3003
    tcg_temp_free_i32(tmp32_1); \
3004
    tcg_temp_free_i32(tmp32_2);
3005

    
3006
    switch (op) {
3007
    case 0x0: /* LPEBR       R1,R2             [RRE] */
3008
        FP_HELPER_CC(lpebr);
3009
        break;
3010
    case 0x2: /* LTEBR       R1,R2             [RRE] */
3011
        FP_HELPER_CC(ltebr);
3012
        break;
3013
    case 0x3: /* LCEBR       R1,R2             [RRE] */
3014
        FP_HELPER_CC(lcebr);
3015
        break;
3016
    case 0x4: /* LDEBR       R1,R2             [RRE] */
3017
        FP_HELPER(ldebr);
3018
        break;
3019
    case 0x5: /* LXDBR       R1,R2             [RRE] */
3020
        FP_HELPER(lxdbr);
3021
        break;
3022
    case 0x9: /* CEBR        R1,R2             [RRE] */
3023
        FP_HELPER_CC(cebr);
3024
        break;
3025
    case 0xa: /* AEBR        R1,R2             [RRE] */
3026
        FP_HELPER_CC(aebr);
3027
        break;
3028
    case 0xb: /* SEBR        R1,R2             [RRE] */
3029
        FP_HELPER_CC(sebr);
3030
        break;
3031
    case 0xd: /* DEBR        R1,R2             [RRE] */
3032
        FP_HELPER(debr);
3033
        break;
3034
    case 0x10: /* LPDBR       R1,R2             [RRE] */
3035
        FP_HELPER_CC(lpdbr);
3036
        break;
3037
    case 0x12: /* LTDBR       R1,R2             [RRE] */
3038
        FP_HELPER_CC(ltdbr);
3039
        break;
3040
    case 0x13: /* LCDBR       R1,R2             [RRE] */
3041
        FP_HELPER_CC(lcdbr);
3042
        break;
3043
    case 0x15: /* SQBDR       R1,R2             [RRE] */
3044
        FP_HELPER(sqdbr);
3045
        break;
3046
    case 0x17: /* MEEBR       R1,R2             [RRE] */
3047
        FP_HELPER(meebr);
3048
        break;
3049
    case 0x19: /* CDBR        R1,R2             [RRE] */
3050
        FP_HELPER_CC(cdbr);
3051
        break;
3052
    case 0x1a: /* ADBR        R1,R2             [RRE] */
3053
        FP_HELPER_CC(adbr);
3054
        break;
3055
    case 0x1b: /* SDBR        R1,R2             [RRE] */
3056
        FP_HELPER_CC(sdbr);
3057
        break;
3058
    case 0x1c: /* MDBR        R1,R2             [RRE] */
3059
        FP_HELPER(mdbr);
3060
        break;
3061
    case 0x1d: /* DDBR        R1,R2             [RRE] */
3062
        FP_HELPER(ddbr);
3063
        break;
3064
    case 0xe: /* MAEBR  R1,R3,R2 [RRF] */
3065
    case 0x1e: /* MADBR R1,R3,R2 [RRF] */
3066
    case 0x1f: /* MSDBR R1,R3,R2 [RRF] */
3067
        /* for RRF insns, m3 is R1, r1 is R3, and r2 is R2 */
3068
        tmp32_1 = tcg_const_i32(m3);
3069
        tmp32_2 = tcg_const_i32(r2);
3070
        tmp32_3 = tcg_const_i32(r1);
3071
        switch (op) {
3072
        case 0xe:
3073
            gen_helper_maebr(tmp32_1, tmp32_3, tmp32_2);
3074
            break;
3075
        case 0x1e:
3076
            gen_helper_madbr(tmp32_1, tmp32_3, tmp32_2);
3077
            break;
3078
        case 0x1f:
3079
            gen_helper_msdbr(tmp32_1, tmp32_3, tmp32_2);
3080
            break;
3081
        default:
3082
            tcg_abort();
3083
        }
3084
        tcg_temp_free_i32(tmp32_1);
3085
        tcg_temp_free_i32(tmp32_2);
3086
        tcg_temp_free_i32(tmp32_3);
3087
        break;
3088
    case 0x40: /* LPXBR       R1,R2             [RRE] */
3089
        FP_HELPER_CC(lpxbr);
3090
        break;
3091
    case 0x42: /* LTXBR       R1,R2             [RRE] */
3092
        FP_HELPER_CC(ltxbr);
3093
        break;
3094
    case 0x43: /* LCXBR       R1,R2             [RRE] */
3095
        FP_HELPER_CC(lcxbr);
3096
        break;
3097
    case 0x44: /* LEDBR       R1,R2             [RRE] */
3098
        FP_HELPER(ledbr);
3099
        break;
3100
    case 0x45: /* LDXBR       R1,R2             [RRE] */
3101
        FP_HELPER(ldxbr);
3102
        break;
3103
    case 0x46: /* LEXBR       R1,R2             [RRE] */
3104
        FP_HELPER(lexbr);
3105
        break;
3106
    case 0x49: /* CXBR        R1,R2             [RRE] */
3107
        FP_HELPER_CC(cxbr);
3108
        break;
3109
    case 0x4a: /* AXBR        R1,R2             [RRE] */
3110
        FP_HELPER_CC(axbr);
3111
        break;
3112
    case 0x4b: /* SXBR        R1,R2             [RRE] */
3113
        FP_HELPER_CC(sxbr);
3114
        break;
3115
    case 0x4c: /* MXBR        R1,R2             [RRE] */
3116
        FP_HELPER(mxbr);
3117
        break;
3118
    case 0x4d: /* DXBR        R1,R2             [RRE] */
3119
        FP_HELPER(dxbr);
3120
        break;
3121
    case 0x65: /* LXR         R1,R2             [RRE] */
3122
        tmp = load_freg(r2);
3123
        store_freg(r1, tmp);
3124
        tcg_temp_free_i64(tmp);
3125
        tmp = load_freg(r2 + 2);
3126
        store_freg(r1 + 2, tmp);
3127
        tcg_temp_free_i64(tmp);
3128
        break;
3129
    case 0x74: /* LZER        R1                [RRE] */
3130
        tmp32_1 = tcg_const_i32(r1);
3131
        gen_helper_lzer(tmp32_1);
3132
        tcg_temp_free_i32(tmp32_1);
3133
        break;
3134
    case 0x75: /* LZDR        R1                [RRE] */
3135
        tmp32_1 = tcg_const_i32(r1);
3136
        gen_helper_lzdr(tmp32_1);
3137
        tcg_temp_free_i32(tmp32_1);
3138
        break;
3139
    case 0x76: /* LZXR        R1                [RRE] */
3140
        tmp32_1 = tcg_const_i32(r1);
3141
        gen_helper_lzxr(tmp32_1);
3142
        tcg_temp_free_i32(tmp32_1);
3143
        break;
3144
    case 0x84: /* SFPC        R1                [RRE] */
3145
        tmp32_1 = load_reg32(r1);
3146
        tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, fpc));
3147
        tcg_temp_free_i32(tmp32_1);
3148
        break;
3149
    case 0x8c: /* EFPC        R1                [RRE] */
3150
        tmp32_1 = tcg_temp_new_i32();
3151
        tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, fpc));
3152
        store_reg32(r1, tmp32_1);
3153
        tcg_temp_free_i32(tmp32_1);
3154
        break;
3155
    case 0x94: /* CEFBR       R1,R2             [RRE] */
3156
    case 0x95: /* CDFBR       R1,R2             [RRE] */
3157
    case 0x96: /* CXFBR       R1,R2             [RRE] */
3158
        tmp32_1 = tcg_const_i32(r1);
3159
        tmp32_2 = load_reg32(r2);
3160
        switch (op) {
3161
        case 0x94:
3162
            gen_helper_cefbr(tmp32_1, tmp32_2);
3163
            break;
3164
        case 0x95:
3165
            gen_helper_cdfbr(tmp32_1, tmp32_2);
3166
            break;
3167
        case 0x96:
3168
            gen_helper_cxfbr(tmp32_1, tmp32_2);
3169
            break;
3170
        default:
3171
            tcg_abort();
3172
        }
3173
        tcg_temp_free_i32(tmp32_1);
3174
        tcg_temp_free_i32(tmp32_2);
3175
        break;
3176
    case 0x98: /* CFEBR       R1,R2             [RRE] */
3177
    case 0x99: /* CFDBR              R1,R2             [RRE] */
3178
    case 0x9a: /* CFXBR       R1,R2             [RRE] */
3179
        tmp32_1 = tcg_const_i32(r1);
3180
        tmp32_2 = tcg_const_i32(r2);
3181
        tmp32_3 = tcg_const_i32(m3);
3182
        switch (op) {
3183
        case 0x98:
3184
            gen_helper_cfebr(cc_op, tmp32_1, tmp32_2, tmp32_3);
3185
            break;
3186
        case 0x99:
3187
            gen_helper_cfdbr(cc_op, tmp32_1, tmp32_2, tmp32_3);
3188
            break;
3189
        case 0x9a:
3190
            gen_helper_cfxbr(cc_op, tmp32_1, tmp32_2, tmp32_3);
3191
            break;
3192
        default:
3193
            tcg_abort();
3194
        }
3195
        set_cc_static(s);
3196
        tcg_temp_free_i32(tmp32_1);
3197
        tcg_temp_free_i32(tmp32_2);
3198
        tcg_temp_free_i32(tmp32_3);
3199
        break;
3200
    case 0xa4: /* CEGBR       R1,R2             [RRE] */
3201
    case 0xa5: /* CDGBR       R1,R2             [RRE] */
3202
        tmp32_1 = tcg_const_i32(r1);
3203
        tmp = load_reg(r2);
3204
        switch (op) {
3205
        case 0xa4:
3206
            gen_helper_cegbr(tmp32_1, tmp);
3207
            break;
3208
        case 0xa5:
3209
            gen_helper_cdgbr(tmp32_1, tmp);
3210
            break;
3211
        default:
3212
            tcg_abort();
3213
        }
3214
        tcg_temp_free_i32(tmp32_1);
3215
        tcg_temp_free_i64(tmp);
3216
        break;
3217
    case 0xa6: /* CXGBR       R1,R2             [RRE] */
3218
        tmp32_1 = tcg_const_i32(r1);
3219
        tmp = load_reg(r2);
3220
        gen_helper_cxgbr(tmp32_1, tmp);
3221
        tcg_temp_free_i32(tmp32_1);
3222
        tcg_temp_free_i64(tmp);
3223
        break;
3224
    case 0xa8: /* CGEBR       R1,R2             [RRE] */
3225
        tmp32_1 = tcg_const_i32(r1);
3226
        tmp32_2 = tcg_const_i32(r2);
3227
        tmp32_3 = tcg_const_i32(m3);
3228
        gen_helper_cgebr(cc_op, tmp32_1, tmp32_2, tmp32_3);
3229
        set_cc_static(s);
3230
        tcg_temp_free_i32(tmp32_1);
3231
        tcg_temp_free_i32(tmp32_2);
3232
        tcg_temp_free_i32(tmp32_3);
3233
        break;
3234
    case 0xa9: /* CGDBR       R1,R2             [RRE] */
3235
        tmp32_1 = tcg_const_i32(r1);
3236
        tmp32_2 = tcg_const_i32(r2);
3237
        tmp32_3 = tcg_const_i32(m3);
3238
        gen_helper_cgdbr(cc_op, tmp32_1, tmp32_2, tmp32_3);
3239
        set_cc_static(s);
3240
        tcg_temp_free_i32(tmp32_1);
3241
        tcg_temp_free_i32(tmp32_2);
3242
        tcg_temp_free_i32(tmp32_3);
3243
        break;
3244
    case 0xaa: /* CGXBR       R1,R2             [RRE] */
3245
        tmp32_1 = tcg_const_i32(r1);
3246
        tmp32_2 = tcg_const_i32(r2);
3247
        tmp32_3 = tcg_const_i32(m3);
3248
        gen_helper_cgxbr(cc_op, tmp32_1, tmp32_2, tmp32_3);
3249
        set_cc_static(s);
3250
        tcg_temp_free_i32(tmp32_1);
3251
        tcg_temp_free_i32(tmp32_2);
3252
        tcg_temp_free_i32(tmp32_3);
3253
        break;
3254
    default:
3255
        LOG_DISAS("illegal b3 operation 0x%x\n", op);
3256
        gen_illegal_opcode(s, 2);
3257
        break;
3258
    }
3259

    
3260
#undef FP_HELPER_CC
3261
#undef FP_HELPER
3262
}
3263

    
3264
static void disas_b9(DisasContext *s, int op, int r1, int r2)
3265
{
3266
    TCGv_i64 tmp, tmp2, tmp3;
3267
    TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
3268

    
3269
    LOG_DISAS("disas_b9: op 0x%x r1 %d r2 %d\n", op, r1, r2);
3270
    switch (op) {
3271
    case 0x0: /* LPGR     R1,R2     [RRE] */
3272
    case 0x1: /* LNGR     R1,R2     [RRE] */
3273
    case 0x2: /* LTGR R1,R2 [RRE] */
3274
    case 0x3: /* LCGR     R1,R2     [RRE] */
3275
    case 0x10: /* LPGFR R1,R2 [RRE] */
3276
    case 0x11: /* LNFGR     R1,R2     [RRE] */
3277
    case 0x12: /* LTGFR R1,R2 [RRE] */
3278
    case 0x13: /* LCGFR    R1,R2     [RRE] */
3279
        if (op & 0x10) {
3280
            tmp = load_reg32_i64(r2);
3281
        } else {
3282
            tmp = load_reg(r2);
3283
        }
3284
        switch (op & 0xf) {
3285
        case 0x0: /* LP?GR */
3286
            set_cc_abs64(s, tmp);
3287
            gen_helper_abs_i64(tmp, tmp);
3288
            store_reg(r1, tmp);
3289
            break;
3290
        case 0x1: /* LN?GR */
3291
            set_cc_nabs64(s, tmp);
3292
            gen_helper_nabs_i64(tmp, tmp);
3293
            store_reg(r1, tmp);
3294
            break;
3295
        case 0x2: /* LT?GR */
3296
            if (r1 != r2) {
3297
                store_reg(r1, tmp);
3298
            }
3299
            set_cc_s64(s, tmp);
3300
            break;
3301
        case 0x3: /* LC?GR */
3302
            tcg_gen_neg_i64(regs[r1], tmp);
3303
            set_cc_comp64(s, regs[r1]);
3304
            break;
3305
        }
3306
        tcg_temp_free_i64(tmp);
3307
        break;
3308
    case 0x4: /* LGR R1,R2 [RRE] */
3309
        store_reg(r1, regs[r2]);
3310
        break;
3311
    case 0x6: /* LGBR R1,R2 [RRE] */
3312
        tmp2 = load_reg(r2);
3313
        tcg_gen_ext8s_i64(tmp2, tmp2);
3314
        store_reg(r1, tmp2);
3315
        tcg_temp_free_i64(tmp2);
3316
        break;
3317
    case 0x8: /* AGR     R1,R2     [RRE] */
3318
    case 0xa: /* ALGR     R1,R2     [RRE] */
3319
        tmp = load_reg(r1);
3320
        tmp2 = load_reg(r2);
3321
        tmp3 = tcg_temp_new_i64();
3322
        tcg_gen_add_i64(tmp3, tmp, tmp2);
3323
        store_reg(r1, tmp3);
3324
        switch (op) {
3325
        case 0x8:
3326
            set_cc_add64(s, tmp, tmp2, tmp3);
3327
            break;
3328
        case 0xa:
3329
            set_cc_addu64(s, tmp, tmp2, tmp3);
3330
            break;
3331
        default:
3332
            tcg_abort();
3333
        }
3334
        tcg_temp_free_i64(tmp);
3335
        tcg_temp_free_i64(tmp2);
3336
        tcg_temp_free_i64(tmp3);
3337
        break;
3338
    case 0x9: /* SGR     R1,R2     [RRE] */
3339
    case 0xb: /* SLGR     R1,R2     [RRE] */
3340
    case 0x1b: /* SLGFR     R1,R2     [RRE] */
3341
    case 0x19: /* SGFR     R1,R2     [RRE] */
3342
        tmp = load_reg(r1);
3343
        switch (op) {
3344
        case 0x1b:
3345
            tmp32_1 = load_reg32(r2);
3346
            tmp2 = tcg_temp_new_i64();
3347
            tcg_gen_extu_i32_i64(tmp2, tmp32_1);
3348
            tcg_temp_free_i32(tmp32_1);
3349
            break;
3350
        case 0x19:
3351
            tmp32_1 = load_reg32(r2);
3352
            tmp2 = tcg_temp_new_i64();
3353
            tcg_gen_ext_i32_i64(tmp2, tmp32_1);
3354
            tcg_temp_free_i32(tmp32_1);
3355
            break;
3356
        default:
3357
            tmp2 = load_reg(r2);
3358
            break;
3359
        }
3360
        tmp3 = tcg_temp_new_i64();
3361
        tcg_gen_sub_i64(tmp3, tmp, tmp2);
3362
        store_reg(r1, tmp3);
3363
        switch (op) {
3364
        case 0x9:
3365
        case 0x19:
3366
            set_cc_sub64(s, tmp, tmp2, tmp3);
3367
            break;
3368
        case 0xb:
3369
        case 0x1b:
3370
            set_cc_subu64(s, tmp, tmp2, tmp3);
3371
            break;
3372
        default:
3373
            tcg_abort();
3374
        }
3375
        tcg_temp_free_i64(tmp);
3376
        tcg_temp_free_i64(tmp2);
3377
        tcg_temp_free_i64(tmp3);
3378
        break;
3379
    case 0xc: /* MSGR      R1,R2     [RRE] */
3380
    case 0x1c: /* MSGFR      R1,R2     [RRE] */
3381
        tmp = load_reg(r1);
3382
        tmp2 = load_reg(r2);
3383
        if (op == 0x1c) {
3384
            tcg_gen_ext32s_i64(tmp2, tmp2);
3385
        }
3386
        tcg_gen_mul_i64(tmp, tmp, tmp2);
3387
        store_reg(r1, tmp);
3388
        tcg_temp_free_i64(tmp);
3389
        tcg_temp_free_i64(tmp2);
3390
        break;
3391
    case 0xd: /* DSGR      R1,R2     [RRE] */
3392
    case 0x1d: /* DSGFR      R1,R2     [RRE] */
3393
        tmp = load_reg(r1 + 1);
3394
        if (op == 0xd) {
3395
            tmp2 = load_reg(r2);
3396
        } else {
3397
            tmp32_1 = load_reg32(r2);
3398
            tmp2 = tcg_temp_new_i64();
3399
            tcg_gen_ext_i32_i64(tmp2, tmp32_1);
3400
            tcg_temp_free_i32(tmp32_1);
3401
        }
3402
        tmp3 = tcg_temp_new_i64();
3403
        tcg_gen_div_i64(tmp3, tmp, tmp2);
3404
        store_reg(r1 + 1, tmp3);
3405
        tcg_gen_rem_i64(tmp3, tmp, tmp2);
3406
        store_reg(r1, tmp3);
3407
        tcg_temp_free_i64(tmp);
3408
        tcg_temp_free_i64(tmp2);
3409
        tcg_temp_free_i64(tmp3);
3410
        break;
3411
    case 0x14: /* LGFR     R1,R2     [RRE] */
3412
        tmp32_1 = load_reg32(r2);
3413
        tmp = tcg_temp_new_i64();
3414
        tcg_gen_ext_i32_i64(tmp, tmp32_1);
3415
        store_reg(r1, tmp);
3416
        tcg_temp_free_i32(tmp32_1);
3417
        tcg_temp_free_i64(tmp);
3418
        break;
3419
    case 0x16: /* LLGFR      R1,R2     [RRE] */
3420
        tmp32_1 = load_reg32(r2);
3421
        tmp = tcg_temp_new_i64();
3422
        tcg_gen_extu_i32_i64(tmp, tmp32_1);
3423
        store_reg(r1, tmp);
3424
        tcg_temp_free_i32(tmp32_1);
3425
        tcg_temp_free_i64(tmp);
3426
        break;
3427
    case 0x17: /* LLGTR      R1,R2     [RRE] */
3428
        tmp32_1 = load_reg32(r2);
3429
        tmp = tcg_temp_new_i64();
3430
        tcg_gen_andi_i32(tmp32_1, tmp32_1, 0x7fffffffUL);
3431
        tcg_gen_extu_i32_i64(tmp, tmp32_1);
3432
        store_reg(r1, tmp);
3433
        tcg_temp_free_i32(tmp32_1);
3434
        tcg_temp_free_i64(tmp);
3435
        break;
3436
    case 0x18: /* AGFR     R1,R2     [RRE] */
3437
    case 0x1a: /* ALGFR     R1,R2     [RRE] */
3438
        tmp32_1 = load_reg32(r2);
3439
        tmp2 = tcg_temp_new_i64();
3440
        if (op == 0x18) {
3441
            tcg_gen_ext_i32_i64(tmp2, tmp32_1);
3442
        } else {
3443
            tcg_gen_extu_i32_i64(tmp2, tmp32_1);
3444
        }
3445
        tcg_temp_free_i32(tmp32_1);
3446
        tmp = load_reg(r1);
3447
        tmp3 = tcg_temp_new_i64();
3448
        tcg_gen_add_i64(tmp3, tmp, tmp2);
3449
        store_reg(r1, tmp3);
3450
        if (op == 0x18) {
3451
            set_cc_add64(s, tmp, tmp2, tmp3);
3452
        } else {
3453
            set_cc_addu64(s, tmp, tmp2, tmp3);
3454
        }
3455
        tcg_temp_free_i64(tmp);
3456
        tcg_temp_free_i64(tmp2);
3457
        tcg_temp_free_i64(tmp3);
3458
        break;
3459
    case 0x1f: /* LRVR     R1,R2     [RRE] */
3460
        tmp32_1 = load_reg32(r2);
3461
        tcg_gen_bswap32_i32(tmp32_1, tmp32_1);
3462
        store_reg32(r1, tmp32_1);
3463
        tcg_temp_free_i32(tmp32_1);
3464
        break;
3465
    case 0x20: /* CGR      R1,R2     [RRE] */
3466
    case 0x30: /* CGFR     R1,R2     [RRE] */
3467
        tmp2 = load_reg(r2);
3468
        if (op == 0x30) {
3469
            tcg_gen_ext32s_i64(tmp2, tmp2);
3470
        }
3471
        tmp = load_reg(r1);
3472
        cmp_s64(s, tmp, tmp2);
3473
        tcg_temp_free_i64(tmp);
3474
        tcg_temp_free_i64(tmp2);
3475
        break;
3476
    case 0x21: /* CLGR     R1,R2     [RRE] */
3477
    case 0x31: /* CLGFR    R1,R2     [RRE] */
3478
        tmp2 = load_reg(r2);
3479
        if (op == 0x31) {
3480
            tcg_gen_ext32u_i64(tmp2, tmp2);
3481
        }
3482
        tmp = load_reg(r1);
3483
        cmp_u64(s, tmp, tmp2);
3484
        tcg_temp_free_i64(tmp);
3485
        tcg_temp_free_i64(tmp2);
3486
        break;
3487
    case 0x26: /* LBR R1,R2 [RRE] */
3488
        tmp32_1 = load_reg32(r2);
3489
        tcg_gen_ext8s_i32(tmp32_1, tmp32_1);
3490
        store_reg32(r1, tmp32_1);
3491
        tcg_temp_free_i32(tmp32_1);
3492
        break;
3493
    case 0x27: /* LHR R1,R2 [RRE] */
3494
        tmp32_1 = load_reg32(r2);
3495
        tcg_gen_ext16s_i32(tmp32_1, tmp32_1);
3496
        store_reg32(r1, tmp32_1);
3497
        tcg_temp_free_i32(tmp32_1);
3498
        break;
3499
    case 0x80: /* NGR R1,R2 [RRE] */
3500
    case 0x81: /* OGR R1,R2 [RRE] */
3501
    case 0x82: /* XGR R1,R2 [RRE] */
3502
        tmp = load_reg(r1);
3503
        tmp2 = load_reg(r2);
3504
        switch (op) {
3505
        case 0x80:
3506
            tcg_gen_and_i64(tmp, tmp, tmp2);
3507
            break;
3508
        case 0x81:
3509
            tcg_gen_or_i64(tmp, tmp, tmp2);
3510
            break;
3511
        case 0x82:
3512
            tcg_gen_xor_i64(tmp, tmp, tmp2);
3513
            break;
3514
        default:
3515
            tcg_abort();
3516
        }
3517
        store_reg(r1, tmp);
3518
        set_cc_nz_u64(s, tmp);
3519
        tcg_temp_free_i64(tmp);
3520
        tcg_temp_free_i64(tmp2);
3521
        break;
3522
    case 0x83: /* FLOGR R1,R2 [RRE] */
3523
        tmp = load_reg(r2);
3524
        tmp32_1 = tcg_const_i32(r1);
3525
        gen_helper_flogr(cc_op, tmp32_1, tmp);
3526
        set_cc_static(s);
3527
        tcg_temp_free_i64(tmp);
3528
        tcg_temp_free_i32(tmp32_1);
3529
        break;
3530
    case 0x84: /* LLGCR R1,R2 [RRE] */
3531
        tmp = load_reg(r2);
3532
        tcg_gen_andi_i64(tmp, tmp, 0xff);
3533
        store_reg(r1, tmp);
3534
        tcg_temp_free_i64(tmp);
3535
        break;
3536
    case 0x85: /* LLGHR R1,R2 [RRE] */
3537
        tmp = load_reg(r2);
3538
        tcg_gen_andi_i64(tmp, tmp, 0xffff);
3539
        store_reg(r1, tmp);
3540
        tcg_temp_free_i64(tmp);
3541
        break;
3542
    case 0x87: /* DLGR      R1,R2     [RRE] */
3543
        tmp32_1 = tcg_const_i32(r1);
3544
        tmp = load_reg(r2);
3545
        gen_helper_dlg(tmp32_1, tmp);
3546
        tcg_temp_free_i64(tmp);
3547
        tcg_temp_free_i32(tmp32_1);
3548
        break;
3549
    case 0x88: /* ALCGR     R1,R2     [RRE] */
3550
        tmp = load_reg(r1);
3551
        tmp2 = load_reg(r2);
3552
        tmp3 = tcg_temp_new_i64();
3553
        gen_op_calc_cc(s);
3554
        tcg_gen_extu_i32_i64(tmp3, cc_op);
3555
        tcg_gen_shri_i64(tmp3, tmp3, 1);
3556
        tcg_gen_andi_i64(tmp3, tmp3, 1);
3557
        tcg_gen_add_i64(tmp3, tmp2, tmp3);
3558
        tcg_gen_add_i64(tmp3, tmp, tmp3);
3559
        store_reg(r1, tmp3);
3560
        set_cc_addu64(s, tmp, tmp2, tmp3);
3561
        tcg_temp_free_i64(tmp);
3562
        tcg_temp_free_i64(tmp2);
3563
        tcg_temp_free_i64(tmp3);
3564
        break;
3565
    case 0x89: /* SLBGR   R1,R2     [RRE] */
3566
        tmp = load_reg(r1);
3567
        tmp2 = load_reg(r2);
3568
        tmp32_1 = tcg_const_i32(r1);
3569
        gen_op_calc_cc(s);
3570
        gen_helper_slbg(cc_op, cc_op, tmp32_1, tmp, tmp2);
3571
        set_cc_static(s);
3572
        tcg_temp_free_i64(tmp);
3573
        tcg_temp_free_i64(tmp2);
3574
        tcg_temp_free_i32(tmp32_1);
3575
        break;
3576
    case 0x94: /* LLCR R1,R2 [RRE] */
3577
        tmp32_1 = load_reg32(r2);
3578
        tcg_gen_andi_i32(tmp32_1, tmp32_1, 0xff);
3579
        store_reg32(r1, tmp32_1);
3580
        tcg_temp_free_i32(tmp32_1);
3581
        break;
3582
    case 0x95: /* LLHR R1,R2 [RRE] */
3583
        tmp32_1 = load_reg32(r2);
3584
        tcg_gen_andi_i32(tmp32_1, tmp32_1, 0xffff);
3585
        store_reg32(r1, tmp32_1);
3586
        tcg_temp_free_i32(tmp32_1);
3587
        break;
3588
    case 0x96: /* MLR     R1,R2     [RRE] */
3589
        /* reg(r1, r1+1) = reg(r1+1) * reg(r2) */
3590
        tmp2 = load_reg(r2);
3591
        tmp3 = load_reg((r1 + 1) & 15);
3592
        tcg_gen_ext32u_i64(tmp2, tmp2);
3593
        tcg_gen_ext32u_i64(tmp3, tmp3);
3594
        tcg_gen_mul_i64(tmp2, tmp2, tmp3);
3595
        store_reg32_i64((r1 + 1) & 15, tmp2);
3596
        tcg_gen_shri_i64(tmp2, tmp2, 32);
3597
        store_reg32_i64(r1, tmp2);
3598
        tcg_temp_free_i64(tmp2);
3599
        tcg_temp_free_i64(tmp3);
3600
        break;
3601
    case 0x97: /* DLR     R1,R2     [RRE] */
3602
        /* reg(r1) = reg(r1, r1+1) % reg(r2) */
3603
        /* reg(r1+1) = reg(r1, r1+1) / reg(r2) */
3604
        tmp = load_reg(r1);
3605
        tmp2 = load_reg(r2);
3606
        tmp3 = load_reg((r1 + 1) & 15);
3607
        tcg_gen_ext32u_i64(tmp2, tmp2);
3608
        tcg_gen_ext32u_i64(tmp3, tmp3);
3609
        tcg_gen_shli_i64(tmp, tmp, 32);
3610
        tcg_gen_or_i64(tmp, tmp, tmp3);
3611

    
3612
        tcg_gen_rem_i64(tmp3, tmp, tmp2);
3613
        tcg_gen_div_i64(tmp, tmp, tmp2);
3614
        store_reg32_i64((r1 + 1) & 15, tmp);
3615
        store_reg32_i64(r1, tmp3);
3616
        tcg_temp_free_i64(tmp);
3617
        tcg_temp_free_i64(tmp2);
3618
        tcg_temp_free_i64(tmp3);
3619
        break;
3620
    case 0x98: /* ALCR    R1,R2     [RRE] */
3621
        tmp32_1 = load_reg32(r1);
3622
        tmp32_2 = load_reg32(r2);
3623
        tmp32_3 = tcg_temp_new_i32();
3624
        /* XXX possible optimization point */
3625
        gen_op_calc_cc(s);
3626
        gen_helper_addc_u32(tmp32_3, cc_op, tmp32_1, tmp32_2);
3627
        set_cc_addu32(s, tmp32_1, tmp32_2, tmp32_3);
3628
        store_reg32(r1, tmp32_3);
3629
        tcg_temp_free_i32(tmp32_1);
3630
        tcg_temp_free_i32(tmp32_2);
3631
        tcg_temp_free_i32(tmp32_3);
3632
        break;
3633
    case 0x99: /* SLBR    R1,R2     [RRE] */
3634
        tmp32_1 = load_reg32(r2);
3635
        tmp32_2 = tcg_const_i32(r1);
3636
        gen_op_calc_cc(s);
3637
        gen_helper_slb(cc_op, cc_op, tmp32_2, tmp32_1);
3638
        set_cc_static(s);
3639
        tcg_temp_free_i32(tmp32_1);
3640
        tcg_temp_free_i32(tmp32_2);
3641
        break;
3642
    default:
3643
        LOG_DISAS("illegal b9 operation 0x%x\n", op);
3644
        gen_illegal_opcode(s, 2);
3645
        break;
3646
    }
3647
}
3648

    
3649
static void disas_c0(DisasContext *s, int op, int r1, int i2)
3650
{
3651
    TCGv_i64 tmp;
3652
    TCGv_i32 tmp32_1, tmp32_2;
3653
    uint64_t target = s->pc + i2 * 2LL;
3654
    int l1;
3655

    
3656
    LOG_DISAS("disas_c0: op 0x%x r1 %d i2 %d\n", op, r1, i2);
3657

    
3658
    switch (op) {
3659
    case 0: /* larl r1, i2 */
3660
        tmp = tcg_const_i64(target);
3661
        store_reg(r1, tmp);
3662
        tcg_temp_free_i64(tmp);
3663
        break;
3664
    case 0x1: /* LGFI R1,I2 [RIL] */
3665
        tmp = tcg_const_i64((int64_t)i2);
3666
        store_reg(r1, tmp);
3667
        tcg_temp_free_i64(tmp);
3668
        break;
3669
    case 0x4: /* BRCL     M1,I2     [RIL] */
3670
        /* m1 & (1 << (3 - cc)) */
3671
        tmp32_1 = tcg_const_i32(3);
3672
        tmp32_2 = tcg_const_i32(1);
3673
        gen_op_calc_cc(s);
3674
        tcg_gen_sub_i32(tmp32_1, tmp32_1, cc_op);
3675
        tcg_gen_shl_i32(tmp32_2, tmp32_2, tmp32_1);
3676
        tcg_temp_free_i32(tmp32_1);
3677
        tmp32_1 = tcg_const_i32(r1); /* m1 == r1 */
3678
        tcg_gen_and_i32(tmp32_1, tmp32_1, tmp32_2);
3679
        l1 = gen_new_label();
3680
        tcg_gen_brcondi_i32(TCG_COND_EQ, tmp32_1, 0, l1);
3681
        gen_goto_tb(s, 0, target);
3682
        gen_set_label(l1);
3683
        gen_goto_tb(s, 1, s->pc + 6);
3684
        s->is_jmp = DISAS_TB_JUMP;
3685
        tcg_temp_free_i32(tmp32_1);
3686
        tcg_temp_free_i32(tmp32_2);
3687
        break;
3688
    case 0x5: /* brasl r1, i2 */
3689
        tmp = tcg_const_i64(pc_to_link_info(s, s->pc + 6));
3690
        store_reg(r1, tmp);
3691
        tcg_temp_free_i64(tmp);
3692
        gen_goto_tb(s, 0, target);
3693
        s->is_jmp = DISAS_TB_JUMP;
3694
        break;
3695
    case 0x7: /* XILF R1,I2 [RIL] */
3696
    case 0xb: /* NILF R1,I2 [RIL] */
3697
    case 0xd: /* OILF R1,I2 [RIL] */
3698
        tmp32_1 = load_reg32(r1);
3699
        switch (op) {
3700
        case 0x7:
3701
            tcg_gen_xori_i32(tmp32_1, tmp32_1, (uint32_t)i2);
3702
            break;
3703
        case 0xb:
3704
            tcg_gen_andi_i32(tmp32_1, tmp32_1, (uint32_t)i2);
3705
            break;
3706
        case 0xd:
3707
            tcg_gen_ori_i32(tmp32_1, tmp32_1, (uint32_t)i2);
3708
            break;
3709
        default:
3710
            tcg_abort();
3711
        }
3712
        store_reg32(r1, tmp32_1);
3713
        set_cc_nz_u32(s, tmp32_1);
3714
        tcg_temp_free_i32(tmp32_1);
3715
        break;
3716
    case 0x9: /* IILF R1,I2 [RIL] */
3717
        tmp32_1 = tcg_const_i32((uint32_t)i2);
3718
        store_reg32(r1, tmp32_1);
3719
        tcg_temp_free_i32(tmp32_1);
3720
        break;
3721
    case 0xa: /* NIHF R1,I2 [RIL] */
3722
        tmp = load_reg(r1);
3723
        tmp32_1 = tcg_temp_new_i32();
3724
        tcg_gen_andi_i64(tmp, tmp, (((uint64_t)((uint32_t)i2)) << 32)
3725
                                   | 0xffffffffULL);
3726
        store_reg(r1, tmp);
3727
        tcg_gen_shri_i64(tmp, tmp, 32);
3728
        tcg_gen_trunc_i64_i32(tmp32_1, tmp);
3729
        set_cc_nz_u32(s, tmp32_1);
3730
        tcg_temp_free_i64(tmp);
3731
        tcg_temp_free_i32(tmp32_1);
3732
        break;
3733
    case 0xe: /* LLIHF R1,I2 [RIL] */
3734
        tmp = tcg_const_i64(((uint64_t)(uint32_t)i2) << 32);
3735
        store_reg(r1, tmp);
3736
        tcg_temp_free_i64(tmp);
3737
        break;
3738
    case 0xf: /* LLILF R1,I2 [RIL] */
3739
        tmp = tcg_const_i64((uint32_t)i2);
3740
        store_reg(r1, tmp);
3741
        tcg_temp_free_i64(tmp);
3742
        break;
3743
    default:
3744
        LOG_DISAS("illegal c0 operation 0x%x\n", op);
3745
        gen_illegal_opcode(s, 3);
3746
        break;
3747
    }
3748
}
3749

    
3750
static void disas_c2(DisasContext *s, int op, int r1, int i2)
3751
{
3752
    TCGv_i64 tmp, tmp2, tmp3;
3753
    TCGv_i32 tmp32_1, tmp32_2, tmp32_3;
3754

    
3755
    switch (op) {
3756
    case 0x4: /* SLGFI R1,I2 [RIL] */
3757
    case 0xa: /* ALGFI R1,I2 [RIL] */
3758
        tmp = load_reg(r1);
3759
        tmp2 = tcg_const_i64((uint64_t)(uint32_t)i2);
3760
        tmp3 = tcg_temp_new_i64();
3761
        switch (op) {
3762
        case 0x4:
3763
            tcg_gen_sub_i64(tmp3, tmp, tmp2);
3764
            set_cc_subu64(s, tmp, tmp2, tmp3);
3765
            break;
3766
        case 0xa:
3767
            tcg_gen_add_i64(tmp3, tmp, tmp2);
3768
            set_cc_addu64(s, tmp, tmp2, tmp3);
3769
            break;
3770
        default:
3771
            tcg_abort();
3772
        }
3773
        store_reg(r1, tmp3);
3774
        tcg_temp_free_i64(tmp);
3775
        tcg_temp_free_i64(tmp2);
3776
        tcg_temp_free_i64(tmp3);
3777
        break;
3778
    case 0x5: /* SLFI R1,I2 [RIL] */
3779
    case 0xb: /* ALFI R1,I2 [RIL] */
3780
        tmp32_1 = load_reg32(r1);
3781
        tmp32_2 = tcg_const_i32(i2);
3782
        tmp32_3 = tcg_temp_new_i32();
3783
        switch (op) {
3784
        case 0x5:
3785
            tcg_gen_sub_i32(tmp32_3, tmp32_1, tmp32_2);
3786
            set_cc_subu32(s, tmp32_1, tmp32_2, tmp32_3);
3787
            break;
3788
        case 0xb:
3789
            tcg_gen_add_i32(tmp32_3, tmp32_1, tmp32_2);
3790
            set_cc_addu32(s, tmp32_1, tmp32_2, tmp32_3);
3791
            break;
3792
        default:
3793
            tcg_abort();
3794
        }
3795
        store_reg32(r1, tmp32_3);
3796
        tcg_temp_free_i32(tmp32_1);
3797
        tcg_temp_free_i32(tmp32_2);
3798
        tcg_temp_free_i32(tmp32_3);
3799
        break;
3800
    case 0xc: /* CGFI R1,I2 [RIL] */
3801
        tmp = load_reg(r1);
3802
        cmp_s64c(s, tmp, (int64_t)i2);
3803
        tcg_temp_free_i64(tmp);
3804
        break;
3805
    case 0xe: /* CLGFI R1,I2 [RIL] */
3806
        tmp = load_reg(r1);
3807
        cmp_u64c(s, tmp, (uint64_t)(uint32_t)i2);
3808
        tcg_temp_free_i64(tmp);
3809
        break;
3810
    case 0xd: /* CFI R1,I2 [RIL] */
3811
        tmp32_1 = load_reg32(r1);
3812
        cmp_s32c(s, tmp32_1, i2);
3813
        tcg_temp_free_i32(tmp32_1);
3814
        break;
3815
    case 0xf: /* CLFI R1,I2 [RIL] */
3816
        tmp32_1 = load_reg32(r1);
3817
        cmp_u32c(s, tmp32_1, i2);
3818
        tcg_temp_free_i32(tmp32_1);
3819
        break;
3820
    default:
3821
        LOG_DISAS("illegal c2 operation 0x%x\n", op);
3822
        gen_illegal_opcode(s, 3);
3823
        break;
3824
    }
3825
}
3826

    
3827
static void gen_and_or_xor_i32(int opc, TCGv_i32 tmp, TCGv_i32 tmp2)
3828
{
3829
    switch (opc & 0xf) {
3830
    case 0x4:
3831
        tcg_gen_and_i32(tmp, tmp, tmp2);
3832
        break;
3833
    case 0x6:
3834
        tcg_gen_or_i32(tmp, tmp, tmp2);
3835
        break;
3836
    case 0x7:
3837
        tcg_gen_xor_i32(tmp, tmp, tmp2);
3838
        break;
3839
    default:
3840
        tcg_abort();
3841
    }
3842
}
3843

    
3844
static void disas_s390_insn(DisasContext *s)
3845
{
3846
    TCGv_i64 tmp, tmp2, tmp3, tmp4;
3847
    TCGv_i32 tmp32_1, tmp32_2, tmp32_3, tmp32_4;
3848
    unsigned char opc;
3849
    uint64_t insn;
3850
    int op, r1, r2, r3, d1, d2, x2, b1, b2, i, i2, r1b;
3851
    TCGv_i32 vl;
3852
    int ilc;
3853
    int l1;
3854

    
3855
    opc = ldub_code(s->pc);
3856
    LOG_DISAS("opc 0x%x\n", opc);
3857

    
3858
    ilc = get_ilc(opc);
3859

    
3860
    switch (opc) {
3861
#ifndef CONFIG_USER_ONLY
3862
    case 0x01: /* SAM */
3863
        insn = ld_code2(s->pc);
3864
        /* set addressing mode, but we only do 64bit anyways */
3865
        break;
3866
#endif
3867
    case 0x6: /* BCTR     R1,R2     [RR] */
3868
        insn = ld_code2(s->pc);
3869
        decode_rr(s, insn, &r1, &r2);
3870
        tmp32_1 = load_reg32(r1);
3871
        tcg_gen_subi_i32(tmp32_1, tmp32_1, 1);
3872
        store_reg32(r1, tmp32_1);
3873

    
3874
        if (r2) {
3875
            gen_update_cc_op(s);
3876
            l1 = gen_new_label();
3877
            tcg_gen_brcondi_i32(TCG_COND_NE, tmp32_1, 0, l1);
3878

    
3879
            /* not taking the branch, jump to after the instruction */
3880
            gen_goto_tb(s, 0, s->pc + 2);
3881
            gen_set_label(l1);
3882

    
3883
            /* take the branch, move R2 into psw.addr */
3884
            tmp32_1 = load_reg32(r2);
3885
            tmp = tcg_temp_new_i64();
3886
            tcg_gen_extu_i32_i64(tmp, tmp32_1);
3887
            tcg_gen_mov_i64(psw_addr, tmp);
3888
            s->is_jmp = DISAS_JUMP;
3889
            tcg_temp_free_i32(tmp32_1);
3890
            tcg_temp_free_i64(tmp);
3891
        }
3892
        break;
3893
    case 0x7: /* BCR    M1,R2     [RR] */
3894
        insn = ld_code2(s->pc);
3895
        decode_rr(s, insn, &r1, &r2);
3896
        if (r2) {
3897
            tmp = load_reg(r2);
3898
            gen_bcr(s, r1, tmp, s->pc);
3899
            tcg_temp_free_i64(tmp);
3900
            s->is_jmp = DISAS_TB_JUMP;
3901
        } else {
3902
            /* XXX: "serialization and checkpoint-synchronization function"? */
3903
        }
3904
        break;
3905
    case 0xa: /* SVC    I         [RR] */
3906
        insn = ld_code2(s->pc);
3907
        debug_insn(insn);
3908
        i = insn & 0xff;
3909
        update_psw_addr(s);
3910
        gen_op_calc_cc(s);
3911
        tmp32_1 = tcg_const_i32(i);
3912
        tmp32_2 = tcg_const_i32(ilc * 2);
3913
        tmp32_3 = tcg_const_i32(EXCP_SVC);
3914
        tcg_gen_st_i32(tmp32_1, cpu_env, offsetof(CPUState, int_svc_code));
3915
        tcg_gen_st_i32(tmp32_2, cpu_env, offsetof(CPUState, int_svc_ilc));
3916
        gen_helper_exception(tmp32_3);
3917
        s->is_jmp = DISAS_EXCP;
3918
        tcg_temp_free_i32(tmp32_1);
3919
        tcg_temp_free_i32(tmp32_2);
3920
        tcg_temp_free_i32(tmp32_3);
3921
        break;
3922
    case 0xd: /* BASR   R1,R2     [RR] */
3923
        insn = ld_code2(s->pc);
3924
        decode_rr(s, insn, &r1, &r2);
3925
        tmp = tcg_const_i64(pc_to_link_info(s, s->pc + 2));
3926
        store_reg(r1, tmp);
3927
        if (r2) {
3928
            tmp2 = load_reg(r2);
3929
            tcg_gen_mov_i64(psw_addr, tmp2);
3930
            tcg_temp_free_i64(tmp2);
3931
            s->is_jmp = DISAS_JUMP;
3932
        }
3933
        tcg_temp_free_i64(tmp);
3934
        break;
3935
    case 0xe: /* MVCL   R1,R2     [RR] */
3936
        insn = ld_code2(s->pc);
3937
        decode_rr(s, insn, &r1, &r2);
3938
        tmp32_1 = tcg_const_i32(r1);
3939
        tmp32_2 = tcg_const_i32(r2);
3940
        potential_page_fault(s);
3941
        gen_helper_mvcl(cc_op, tmp32_1, tmp32_2);
3942
        set_cc_static(s);
3943
        tcg_temp_free_i32(tmp32_1);
3944
        tcg_temp_free_i32(tmp32_2);
3945
        break;
3946
    case 0x10: /* LPR    R1,R2     [RR] */
3947
        insn = ld_code2(s->pc);
3948
        decode_rr(s, insn, &r1, &r2);
3949
        tmp32_1 = load_reg32(r2);
3950
        set_cc_abs32(s, tmp32_1);
3951
        gen_helper_abs_i32(tmp32_1, tmp32_1);
3952
        store_reg32(r1, tmp32_1);
3953
        tcg_temp_free_i32(tmp32_1);
3954
        break;
3955
    case 0x11: /* LNR    R1,R2     [RR] */
3956
        insn = ld_code2(s->pc);
3957
        decode_rr(s, insn, &r1, &r2);
3958
        tmp32_1 = load_reg32(r2);
3959
        set_cc_nabs32(s, tmp32_1);
3960
        gen_helper_nabs_i32(tmp32_1, tmp32_1);
3961
        store_reg32(r1, tmp32_1);
3962
        tcg_temp_free_i32(tmp32_1);
3963
        break;
3964
    case 0x12: /* LTR    R1,R2     [RR] */
3965
        insn = ld_code2(s->pc);
3966
        decode_rr(s, insn, &r1, &r2);
3967
        tmp32_1 = load_reg32(r2);
3968
        if (r1 != r2) {
3969
            store_reg32(r1, tmp32_1);
3970
        }
3971
        set_cc_s32(s, tmp32_1);
3972
        tcg_temp_free_i32(tmp32_1);
3973
        break;
3974
    case 0x13: /* LCR    R1,R2     [RR] */
3975
        insn = ld_code2(s->pc);
3976
        decode_rr(s, insn, &r1, &r2);
3977
        tmp32_1 = load_reg32(r2);
3978
        tcg_gen_neg_i32(tmp32_1, tmp32_1);
3979
        store_reg32(r1, tmp32_1);
3980
        set_cc_comp32(s, tmp32_1);
3981
        tcg_temp_free_i32(tmp32_1);
3982
        break;
3983
    case 0x14: /* NR     R1,R2     [RR] */
3984
    case 0x16: /* OR     R1,R2     [RR] */
3985
    case 0x17: /* XR     R1,R2     [RR] */
3986
        insn = ld_code2(s->pc);
3987
        decode_rr(s, insn, &r1, &r2);
3988
        tmp32_2 = load_reg32(r2);
3989
        tmp32_1 = load_reg32(r1);
3990
        gen_and_or_xor_i32(opc, tmp32_1, tmp32_2);
3991
        store_reg32(r1, tmp32_1);
3992
        set_cc_nz_u32(s, tmp32_1);
3993
        tcg_temp_free_i32(tmp32_1);
3994
        tcg_temp_free_i32(tmp32_2);
3995
        break;
3996
    case 0x18: /* LR     R1,R2     [RR] */
3997
        insn = ld_code2(s->pc);
3998
        decode_rr(s, insn, &r1, &r2);
3999
        tmp32_1 = load_reg32(r2);
4000
        store_reg32(r1, tmp32_1);
4001
        tcg_temp_free_i32(tmp32_1);
4002
        break;
4003
    case 0x15: /* CLR    R1,R2     [RR] */
4004
    case 0x19: /* CR     R1,R2     [RR] */
4005
        insn = ld_code2(s->pc);
4006
        decode_rr(s, insn, &r1, &r2);
4007
        tmp32_1 = load_reg32(r1);
4008
        tmp32_2 = load_reg32(r2);
4009
        if (opc == 0x15) {
4010
            cmp_u32(s, tmp32_1, tmp32_2);
4011
        } else {
4012
            cmp_s32(s, tmp32_1, tmp32_2);
4013
        }
4014
        tcg_temp_free_i32(tmp32_1);
4015
        tcg_temp_free_i32(tmp32_2);
4016
        break;
4017
    case 0x1a: /* AR     R1,R2     [RR] */
4018
    case 0x1e: /* ALR    R1,R2     [RR] */
4019
        insn = ld_code2(s->pc);
4020
        decode_rr(s, insn, &r1, &r2);
4021
        tmp32_1 = load_reg32(r1);
4022
        tmp32_2 = load_reg32(r2);
4023
        tmp32_3 = tcg_temp_new_i32();
4024
        tcg_gen_add_i32(tmp32_3, tmp32_1, tmp32_2);
4025
        store_reg32(r1, tmp32_3);
4026
        if (opc == 0x1a) {
4027
            set_cc_add32(s, tmp32_1, tmp32_2, tmp32_3);
4028
        } else {
4029
            set_cc_addu32(s, tmp32_1, tmp32_2, tmp32_3);
4030
        }
4031
        tcg_temp_free_i32(tmp32_1);
4032
        tcg_temp_free_i32(tmp32_2);
4033
        tcg_temp_free_i32(tmp32_3);
4034
        break;
4035
    case 0x1b: /* SR     R1,R2     [RR] */
4036
    case 0x1f: /* SLR    R1,R2     [RR] */
4037
        insn = ld_code2(s->pc);
4038
        decode_rr(s, insn, &r1, &r2);
4039
        tmp32_1 = load_reg32(r1);
4040
        tmp32_2 = load_reg32(r2);
4041
        tmp32_3 = tcg_temp_new_i32();
4042
        tcg_gen_sub_i32(tmp32_3, tmp32_1, tmp32_2);
4043
        store_reg32(r1, tmp32_3);
4044
        if (opc == 0x1b) {
4045
            set_cc_sub32(s, tmp32_1, tmp32_2, tmp32_3);
4046
        } else {
4047
            set_cc_subu32(s, tmp32_1, tmp32_2, tmp32_3);
4048
        }
4049
        tcg_temp_free_i32(tmp32_1);
4050
        tcg_temp_free_i32(tmp32_2);
4051
        tcg_temp_free_i32(tmp32_3);
4052
        break;
4053
    case 0x1c: /* MR     R1,R2     [RR] */
4054
        /* reg(r1, r1+1) = reg(r1+1) * reg(r2) */
4055
        insn = ld_code2(s->pc);
4056
        decode_rr(s, insn, &r1, &r2);
4057
        tmp2 = load_reg(r2);
4058
        tmp3 = load_reg((r1 + 1) & 15);
4059
        tcg_gen_ext32s_i64(tmp2, tmp2);
4060
        tcg_gen_ext32s_i64(tmp3, tmp3);
4061
        tcg_gen_mul_i64(tmp2, tmp2, tmp3);
4062
        store_reg32_i64((r1 + 1) & 15, tmp2);
4063
        tcg_gen_shri_i64(tmp2, tmp2, 32);
4064
        store_reg32_i64(r1, tmp2);
4065
        tcg_temp_free_i64(tmp2);
4066
        tcg_temp_free_i64(tmp3);
4067
        break;
4068
    case 0x1d: /* DR     R1,R2               [RR] */
4069
        insn = ld_code2(s->pc);
4070
        decode_rr(s, insn, &r1, &r2);
4071
        tmp32_1 = load_reg32(r1);
4072
        tmp32_2 = load_reg32(r1 + 1);
4073
        tmp32_3 = load_reg32(r2);
4074

    
4075
        tmp = tcg_temp_new_i64(); /* dividend */
4076
        tmp2 = tcg_temp_new_i64(); /* divisor */
4077
        tmp3 = tcg_temp_new_i64();
4078

    
4079
        /* dividend is r(r1 << 32) | r(r1 + 1) */
4080
        tcg_gen_extu_i32_i64(tmp, tmp32_1);
4081
        tcg_gen_extu_i32_i64(tmp2, tmp32_2);
4082
        tcg_gen_shli_i64(tmp, tmp, 32);
4083
        tcg_gen_or_i64(tmp, tmp, tmp2);
4084

    
4085
        /* divisor is r(r2) */
4086
        tcg_gen_ext_i32_i64(tmp2, tmp32_3);
4087

    
4088
        tcg_gen_div_i64(tmp3, tmp, tmp2);
4089
        tcg_gen_rem_i64(tmp, tmp, tmp2);
4090

    
4091
        tcg_gen_trunc_i64_i32(tmp32_1, tmp);
4092
        tcg_gen_trunc_i64_i32(tmp32_2, tmp3);
4093

    
4094
        store_reg32(r1, tmp32_1); /* remainder */
4095
        store_reg32(r1 + 1, tmp32_2); /* quotient */
4096
        tcg_temp_free_i32(tmp32_1);
4097
        tcg_temp_free_i32(tmp32_2);
4098
        tcg_temp_free_i32(tmp32_3);
4099
        tcg_temp_free_i64(tmp);
4100
        tcg_temp_free_i64(tmp2);
4101
        tcg_temp_free_i64(tmp3);
4102
        break;
4103
    case 0x28: /* LDR    R1,R2               [RR] */
4104
        insn = ld_code2(s->pc);
4105
        decode_rr(s, insn, &r1, &r2);
4106
        tmp = load_freg(r2);
4107
        store_freg(r1, tmp);
4108
        tcg_temp_free_i64(tmp);
4109
        break;
4110
    case 0x38: /* LER    R1,R2               [RR] */
4111
        insn = ld_code2(s->pc);
4112
        decode_rr(s, insn, &r1, &r2);
4113
        tmp32_1 = load_freg32(r2);
4114
        store_freg32(r1, tmp32_1);
4115
        tcg_temp_free_i32(tmp32_1);
4116
        break;
4117
    case 0x40: /* STH    R1,D2(X2,B2)     [RX] */
4118
        insn = ld_code4(s->pc);
4119
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4120
        tmp2 = load_reg(r1);
4121
        tcg_gen_qemu_st16(tmp2, tmp, get_mem_index(s));
4122
        tcg_temp_free_i64(tmp);
4123
        tcg_temp_free_i64(tmp2);
4124
        break;
4125
    case 0x41:        /* la */
4126
        insn = ld_code4(s->pc);
4127
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4128
        store_reg(r1, tmp); /* FIXME: 31/24-bit addressing */
4129
        tcg_temp_free_i64(tmp);
4130
        break;
4131
    case 0x42: /* STC    R1,D2(X2,B2)     [RX] */
4132
        insn = ld_code4(s->pc);
4133
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4134
        tmp2 = load_reg(r1);
4135
        tcg_gen_qemu_st8(tmp2, tmp, get_mem_index(s));
4136
        tcg_temp_free_i64(tmp);
4137
        tcg_temp_free_i64(tmp2);
4138
        break;
4139
    case 0x43: /* IC     R1,D2(X2,B2)     [RX] */
4140
        insn = ld_code4(s->pc);
4141
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4142
        tmp2 = tcg_temp_new_i64();
4143
        tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s));
4144
        store_reg8(r1, tmp2);
4145
        tcg_temp_free_i64(tmp);
4146
        tcg_temp_free_i64(tmp2);
4147
        break;
4148
    case 0x44: /* EX     R1,D2(X2,B2)     [RX] */
4149
        insn = ld_code4(s->pc);
4150
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4151
        tmp2 = load_reg(r1);
4152
        tmp3 = tcg_const_i64(s->pc + 4);
4153
        update_psw_addr(s);
4154
        gen_op_calc_cc(s);
4155
        gen_helper_ex(cc_op, cc_op, tmp2, tmp, tmp3);
4156
        set_cc_static(s);
4157
        tcg_temp_free_i64(tmp);
4158
        tcg_temp_free_i64(tmp2);
4159
        tcg_temp_free_i64(tmp3);
4160
        break;
4161
    case 0x46: /* BCT    R1,D2(X2,B2)     [RX] */
4162
        insn = ld_code4(s->pc);
4163
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4164
        tcg_temp_free_i64(tmp);
4165

    
4166
        tmp32_1 = load_reg32(r1);
4167
        tcg_gen_subi_i32(tmp32_1, tmp32_1, 1);
4168
        store_reg32(r1, tmp32_1);
4169

    
4170
        gen_update_cc_op(s);
4171
        l1 = gen_new_label();
4172
        tcg_gen_brcondi_i32(TCG_COND_NE, tmp32_1, 0, l1);
4173

    
4174
        /* not taking the branch, jump to after the instruction */
4175
        gen_goto_tb(s, 0, s->pc + 4);
4176
        gen_set_label(l1);
4177

    
4178
        /* take the branch, move R2 into psw.addr */
4179
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4180
        tcg_gen_mov_i64(psw_addr, tmp);
4181
        s->is_jmp = DISAS_JUMP;
4182
        tcg_temp_free_i32(tmp32_1);
4183
        tcg_temp_free_i64(tmp);
4184
        break;
4185
    case 0x47: /* BC     M1,D2(X2,B2)     [RX] */
4186
        insn = ld_code4(s->pc);
4187
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4188
        gen_bcr(s, r1, tmp, s->pc + 4);
4189
        tcg_temp_free_i64(tmp);
4190
        s->is_jmp = DISAS_TB_JUMP;
4191
        break;
4192
    case 0x48: /* LH     R1,D2(X2,B2)     [RX] */
4193
        insn = ld_code4(s->pc);
4194
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4195
        tmp2 = tcg_temp_new_i64();
4196
        tcg_gen_qemu_ld16s(tmp2, tmp, get_mem_index(s));
4197
        store_reg32_i64(r1, tmp2);
4198
        tcg_temp_free_i64(tmp);
4199
        tcg_temp_free_i64(tmp2);
4200
        break;
4201
    case 0x49: /* CH     R1,D2(X2,B2)     [RX] */
4202
        insn = ld_code4(s->pc);
4203
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4204
        tmp32_1 = load_reg32(r1);
4205
        tmp32_2 = tcg_temp_new_i32();
4206
        tmp2 = tcg_temp_new_i64();
4207
        tcg_gen_qemu_ld16s(tmp2, tmp, get_mem_index(s));
4208
        tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
4209
        cmp_s32(s, tmp32_1, tmp32_2);
4210
        tcg_temp_free_i32(tmp32_1);
4211
        tcg_temp_free_i32(tmp32_2);
4212
        tcg_temp_free_i64(tmp);
4213
        tcg_temp_free_i64(tmp2);
4214
        break;
4215
    case 0x4a: /* AH     R1,D2(X2,B2)     [RX] */
4216
    case 0x4b: /* SH     R1,D2(X2,B2)     [RX] */
4217
    case 0x4c: /* MH     R1,D2(X2,B2)     [RX] */
4218
        insn = ld_code4(s->pc);
4219
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4220
        tmp2 = tcg_temp_new_i64();
4221
        tmp32_1 = load_reg32(r1);
4222
        tmp32_2 = tcg_temp_new_i32();
4223
        tmp32_3 = tcg_temp_new_i32();
4224

    
4225
        tcg_gen_qemu_ld16s(tmp2, tmp, get_mem_index(s));
4226
        tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
4227
        switch (opc) {
4228
        case 0x4a:
4229
            tcg_gen_add_i32(tmp32_3, tmp32_1, tmp32_2);
4230
            set_cc_add32(s, tmp32_1, tmp32_2, tmp32_3);
4231
            break;
4232
        case 0x4b:
4233
            tcg_gen_sub_i32(tmp32_3, tmp32_1, tmp32_2);
4234
            set_cc_sub32(s, tmp32_1, tmp32_2, tmp32_3);
4235
            break;
4236
        case 0x4c:
4237
            tcg_gen_mul_i32(tmp32_3, tmp32_1, tmp32_2);
4238
            break;
4239
        default:
4240
            tcg_abort();
4241
        }
4242
        store_reg32(r1, tmp32_3);
4243

    
4244
        tcg_temp_free_i32(tmp32_1);
4245
        tcg_temp_free_i32(tmp32_2);
4246
        tcg_temp_free_i32(tmp32_3);
4247
        tcg_temp_free_i64(tmp);
4248
        tcg_temp_free_i64(tmp2);
4249
        break;
4250
    case 0x4d: /* BAS    R1,D2(X2,B2)     [RX] */
4251
        insn = ld_code4(s->pc);
4252
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4253
        tmp2 = tcg_const_i64(pc_to_link_info(s, s->pc + 4));
4254
        store_reg(r1, tmp2);
4255
        tcg_gen_mov_i64(psw_addr, tmp);
4256
        tcg_temp_free_i64(tmp);
4257
        tcg_temp_free_i64(tmp2);
4258
        s->is_jmp = DISAS_JUMP;
4259
        break;
4260
    case 0x4e: /* CVD    R1,D2(X2,B2)     [RX] */
4261
        insn = ld_code4(s->pc);
4262
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4263
        tmp2 = tcg_temp_new_i64();
4264
        tmp32_1 = tcg_temp_new_i32();
4265
        tcg_gen_trunc_i64_i32(tmp32_1, regs[r1]);
4266
        gen_helper_cvd(tmp2, tmp32_1);
4267
        tcg_gen_qemu_st64(tmp2, tmp, get_mem_index(s));
4268
        tcg_temp_free_i64(tmp);
4269
        tcg_temp_free_i64(tmp2);
4270
        tcg_temp_free_i32(tmp32_1);
4271
        break;
4272
    case 0x50: /* st r1, d2(x2, b2) */
4273
        insn = ld_code4(s->pc);
4274
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4275
        tmp2 = load_reg(r1);
4276
        tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
4277
        tcg_temp_free_i64(tmp);
4278
        tcg_temp_free_i64(tmp2);
4279
        break;
4280
    case 0x55: /* CL     R1,D2(X2,B2)     [RX] */
4281
        insn = ld_code4(s->pc);
4282
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4283
        tmp2 = tcg_temp_new_i64();
4284
        tmp32_1 = tcg_temp_new_i32();
4285
        tmp32_2 = load_reg32(r1);
4286
        tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
4287
        tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
4288
        cmp_u32(s, tmp32_2, tmp32_1);
4289
        tcg_temp_free_i64(tmp);
4290
        tcg_temp_free_i64(tmp2);
4291
        tcg_temp_free_i32(tmp32_1);
4292
        tcg_temp_free_i32(tmp32_2);
4293
        break;
4294
    case 0x54: /* N      R1,D2(X2,B2)     [RX] */
4295
    case 0x56: /* O      R1,D2(X2,B2)     [RX] */
4296
    case 0x57: /* X      R1,D2(X2,B2)     [RX] */
4297
        insn = ld_code4(s->pc);
4298
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4299
        tmp2 = tcg_temp_new_i64();
4300
        tmp32_1 = load_reg32(r1);
4301
        tmp32_2 = tcg_temp_new_i32();
4302
        tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
4303
        tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
4304
        gen_and_or_xor_i32(opc, tmp32_1, tmp32_2);
4305
        store_reg32(r1, tmp32_1);
4306
        set_cc_nz_u32(s, tmp32_1);
4307
        tcg_temp_free_i64(tmp);
4308
        tcg_temp_free_i64(tmp2);
4309
        tcg_temp_free_i32(tmp32_1);
4310
        tcg_temp_free_i32(tmp32_2);
4311
        break;
4312
    case 0x58: /* l r1, d2(x2, b2) */
4313
        insn = ld_code4(s->pc);
4314
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4315
        tmp2 = tcg_temp_new_i64();
4316
        tmp32_1 = tcg_temp_new_i32();
4317
        tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
4318
        tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
4319
        store_reg32(r1, tmp32_1);
4320
        tcg_temp_free_i64(tmp);
4321
        tcg_temp_free_i64(tmp2);
4322
        tcg_temp_free_i32(tmp32_1);
4323
        break;
4324
    case 0x59: /* C      R1,D2(X2,B2)     [RX] */
4325
        insn = ld_code4(s->pc);
4326
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4327
        tmp2 = tcg_temp_new_i64();
4328
        tmp32_1 = tcg_temp_new_i32();
4329
        tmp32_2 = load_reg32(r1);
4330
        tcg_gen_qemu_ld32s(tmp2, tmp, get_mem_index(s));
4331
        tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
4332
        cmp_s32(s, tmp32_2, tmp32_1);
4333
        tcg_temp_free_i64(tmp);
4334
        tcg_temp_free_i64(tmp2);
4335
        tcg_temp_free_i32(tmp32_1);
4336
        tcg_temp_free_i32(tmp32_2);
4337
        break;
4338
    case 0x5a: /* A      R1,D2(X2,B2)     [RX] */
4339
    case 0x5b: /* S      R1,D2(X2,B2)     [RX] */
4340
    case 0x5e: /* AL     R1,D2(X2,B2)     [RX] */
4341
    case 0x5f: /* SL     R1,D2(X2,B2)     [RX] */
4342
        insn = ld_code4(s->pc);
4343
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4344
        tmp32_1 = load_reg32(r1);
4345
        tmp32_2 = tcg_temp_new_i32();
4346
        tmp32_3 = tcg_temp_new_i32();
4347
        tcg_gen_qemu_ld32s(tmp, tmp, get_mem_index(s));
4348
        tcg_gen_trunc_i64_i32(tmp32_2, tmp);
4349
        switch (opc) {
4350
        case 0x5a:
4351
        case 0x5e:
4352
            tcg_gen_add_i32(tmp32_3, tmp32_1, tmp32_2);
4353
            break;
4354
        case 0x5b:
4355
        case 0x5f:
4356
            tcg_gen_sub_i32(tmp32_3, tmp32_1, tmp32_2);
4357
            break;
4358
        default:
4359
            tcg_abort();
4360
        }
4361
        store_reg32(r1, tmp32_3);
4362
        switch (opc) {
4363
        case 0x5a:
4364
            set_cc_add32(s, tmp32_1, tmp32_2, tmp32_3);
4365
            break;
4366
        case 0x5e:
4367
            set_cc_addu32(s, tmp32_1, tmp32_2, tmp32_3);
4368
            break;
4369
        case 0x5b:
4370
            set_cc_sub32(s, tmp32_1, tmp32_2, tmp32_3);
4371
            break;
4372
        case 0x5f:
4373
            set_cc_subu32(s, tmp32_1, tmp32_2, tmp32_3);
4374
            break;
4375
        default:
4376
            tcg_abort();
4377
        }
4378
        tcg_temp_free_i64(tmp);
4379
        tcg_temp_free_i32(tmp32_1);
4380
        tcg_temp_free_i32(tmp32_2);
4381
        tcg_temp_free_i32(tmp32_3);
4382
        break;
4383
    case 0x5c: /* M      R1,D2(X2,B2)        [RX] */
4384
        /* reg(r1, r1+1) = reg(r1+1) * *(s32*)addr */
4385
        insn = ld_code4(s->pc);
4386
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4387
        tmp2 = tcg_temp_new_i64();
4388
        tcg_gen_qemu_ld32s(tmp2, tmp, get_mem_index(s));
4389
        tmp3 = load_reg((r1 + 1) & 15);
4390
        tcg_gen_ext32s_i64(tmp2, tmp2);
4391
        tcg_gen_ext32s_i64(tmp3, tmp3);
4392
        tcg_gen_mul_i64(tmp2, tmp2, tmp3);
4393
        store_reg32_i64((r1 + 1) & 15, tmp2);
4394
        tcg_gen_shri_i64(tmp2, tmp2, 32);
4395
        store_reg32_i64(r1, tmp2);
4396
        tcg_temp_free_i64(tmp);
4397
        tcg_temp_free_i64(tmp2);
4398
        tcg_temp_free_i64(tmp3);
4399
        break;
4400
    case 0x5d: /* D      R1,D2(X2,B2)        [RX] */
4401
        insn = ld_code4(s->pc);
4402
        tmp3 = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4403
        tmp32_1 = load_reg32(r1);
4404
        tmp32_2 = load_reg32(r1 + 1);
4405

    
4406
        tmp = tcg_temp_new_i64();
4407
        tmp2 = tcg_temp_new_i64();
4408

    
4409
        /* dividend is r(r1 << 32) | r(r1 + 1) */
4410
        tcg_gen_extu_i32_i64(tmp, tmp32_1);
4411
        tcg_gen_extu_i32_i64(tmp2, tmp32_2);
4412
        tcg_gen_shli_i64(tmp, tmp, 32);
4413
        tcg_gen_or_i64(tmp, tmp, tmp2);
4414

    
4415
        /* divisor is in memory */
4416
        tcg_gen_qemu_ld32s(tmp2, tmp3, get_mem_index(s));
4417

    
4418
        /* XXX divisor == 0 -> FixP divide exception */
4419

    
4420
        tcg_gen_div_i64(tmp3, tmp, tmp2);
4421
        tcg_gen_rem_i64(tmp, tmp, tmp2);
4422

    
4423
        tcg_gen_trunc_i64_i32(tmp32_1, tmp);
4424
        tcg_gen_trunc_i64_i32(tmp32_2, tmp3);
4425

    
4426
        store_reg32(r1, tmp32_1); /* remainder */
4427
        store_reg32(r1 + 1, tmp32_2); /* quotient */
4428
        tcg_temp_free_i32(tmp32_1);
4429
        tcg_temp_free_i32(tmp32_2);
4430
        tcg_temp_free_i64(tmp);
4431
        tcg_temp_free_i64(tmp2);
4432
        tcg_temp_free_i64(tmp3);
4433
        break;
4434
    case 0x60: /* STD    R1,D2(X2,B2)        [RX] */
4435
        insn = ld_code4(s->pc);
4436
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4437
        tmp2 = load_freg(r1);
4438
        tcg_gen_qemu_st64(tmp2, tmp, get_mem_index(s));
4439
        tcg_temp_free_i64(tmp);
4440
        tcg_temp_free_i64(tmp2);
4441
        break;
4442
    case 0x68: /* LD    R1,D2(X2,B2)        [RX] */
4443
        insn = ld_code4(s->pc);
4444
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4445
        tmp2 = tcg_temp_new_i64();
4446
        tcg_gen_qemu_ld64(tmp2, tmp, get_mem_index(s));
4447
        store_freg(r1, tmp2);
4448
        tcg_temp_free_i64(tmp);
4449
        tcg_temp_free_i64(tmp2);
4450
        break;
4451
    case 0x70: /* STE R1,D2(X2,B2) [RX] */
4452
        insn = ld_code4(s->pc);
4453
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4454
        tmp2 = tcg_temp_new_i64();
4455
        tmp32_1 = load_freg32(r1);
4456
        tcg_gen_extu_i32_i64(tmp2, tmp32_1);
4457
        tcg_gen_qemu_st32(tmp2, tmp, get_mem_index(s));
4458
        tcg_temp_free_i64(tmp);
4459
        tcg_temp_free_i64(tmp2);
4460
        tcg_temp_free_i32(tmp32_1);
4461
        break;
4462
    case 0x71: /* MS      R1,D2(X2,B2)     [RX] */
4463
        insn = ld_code4(s->pc);
4464
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4465
        tmp2 = tcg_temp_new_i64();
4466
        tmp32_1 = load_reg32(r1);
4467
        tmp32_2 = tcg_temp_new_i32();
4468
        tcg_gen_qemu_ld32s(tmp2, tmp, get_mem_index(s));
4469
        tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
4470
        tcg_gen_mul_i32(tmp32_1, tmp32_1, tmp32_2);
4471
        store_reg32(r1, tmp32_1);
4472
        tcg_temp_free_i64(tmp);
4473
        tcg_temp_free_i64(tmp2);
4474
        tcg_temp_free_i32(tmp32_1);
4475
        tcg_temp_free_i32(tmp32_2);
4476
        break;
4477
    case 0x78: /* LE     R1,D2(X2,B2)        [RX] */
4478
        insn = ld_code4(s->pc);
4479
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4480
        tmp2 = tcg_temp_new_i64();
4481
        tmp32_1 = tcg_temp_new_i32();
4482
        tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
4483
        tcg_gen_trunc_i64_i32(tmp32_1, tmp2);
4484
        store_freg32(r1, tmp32_1);
4485
        tcg_temp_free_i64(tmp);
4486
        tcg_temp_free_i64(tmp2);
4487
        tcg_temp_free_i32(tmp32_1);
4488
        break;
4489
#ifndef CONFIG_USER_ONLY
4490
    case 0x80: /* SSM      D2(B2)       [S] */
4491
        /* Set System Mask */
4492
        check_privileged(s, ilc);
4493
        insn = ld_code4(s->pc);
4494
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
4495
        tmp = get_address(s, 0, b2, d2);
4496
        tmp2 = tcg_temp_new_i64();
4497
        tmp3 = tcg_temp_new_i64();
4498
        tcg_gen_andi_i64(tmp3, psw_mask, ~0xff00000000000000ULL);
4499
        tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s));
4500
        tcg_gen_shli_i64(tmp2, tmp2, 56);
4501
        tcg_gen_or_i64(psw_mask, tmp3, tmp2);
4502
        tcg_temp_free_i64(tmp);
4503
        tcg_temp_free_i64(tmp2);
4504
        tcg_temp_free_i64(tmp3);
4505
        break;
4506
    case 0x82: /* LPSW     D2(B2)       [S] */
4507
        /* Load PSW */
4508
        check_privileged(s, ilc);
4509
        insn = ld_code4(s->pc);
4510
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
4511
        tmp = get_address(s, 0, b2, d2);
4512
        tmp2 = tcg_temp_new_i64();
4513
        tmp3 = tcg_temp_new_i64();
4514
        tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
4515
        tcg_gen_addi_i64(tmp, tmp, 4);
4516
        tcg_gen_qemu_ld32u(tmp3, tmp, get_mem_index(s));
4517
        gen_helper_load_psw(tmp2, tmp3);
4518
        tcg_temp_free_i64(tmp);
4519
        tcg_temp_free_i64(tmp2);
4520
        tcg_temp_free_i64(tmp3);
4521
        /* we need to keep cc_op intact */
4522
        s->is_jmp = DISAS_JUMP;
4523
        break;
4524
    case 0x83: /* DIAG     R1,R3,D2     [RS] */
4525
        /* Diagnose call (KVM hypercall) */
4526
        check_privileged(s, ilc);
4527
        potential_page_fault(s);
4528
        insn = ld_code4(s->pc);
4529
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
4530
        tmp32_1 = tcg_const_i32(insn & 0xfff);
4531
        tmp2 = load_reg(2);
4532
        tmp3 = load_reg(1);
4533
        gen_helper_diag(tmp2, tmp32_1, tmp2, tmp3);
4534
        store_reg(2, tmp2);
4535
        tcg_temp_free_i32(tmp32_1);
4536
        tcg_temp_free_i64(tmp2);
4537
        tcg_temp_free_i64(tmp3);
4538
        break;
4539
#endif
4540
    case 0x88: /* SRL    R1,D2(B2)        [RS] */
4541
    case 0x89: /* SLL    R1,D2(B2)        [RS] */
4542
    case 0x8a: /* SRA    R1,D2(B2)        [RS] */
4543
        insn = ld_code4(s->pc);
4544
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
4545
        tmp = get_address(s, 0, b2, d2);
4546
        tmp32_1 = load_reg32(r1);
4547
        tmp32_2 = tcg_temp_new_i32();
4548
        tcg_gen_trunc_i64_i32(tmp32_2, tmp);
4549
        tcg_gen_andi_i32(tmp32_2, tmp32_2, 0x3f);
4550
        switch (opc) {
4551
        case 0x88:
4552
            tcg_gen_shr_i32(tmp32_1, tmp32_1, tmp32_2);
4553
            break;
4554
        case 0x89:
4555
            tcg_gen_shl_i32(tmp32_1, tmp32_1, tmp32_2);
4556
            break;
4557
        case 0x8a:
4558
            tcg_gen_sar_i32(tmp32_1, tmp32_1, tmp32_2);
4559
            set_cc_s32(s, tmp32_1);
4560
            break;
4561
        default:
4562
            tcg_abort();
4563
        }
4564
        store_reg32(r1, tmp32_1);
4565
        tcg_temp_free_i64(tmp);
4566
        tcg_temp_free_i32(tmp32_1);
4567
        tcg_temp_free_i32(tmp32_2);
4568
        break;
4569
    case 0x8c: /* SRDL   R1,D2(B2)        [RS] */
4570
    case 0x8d: /* SLDL   R1,D2(B2)        [RS] */
4571
    case 0x8e: /* SRDA   R1,D2(B2)        [RS] */
4572
        insn = ld_code4(s->pc);
4573
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
4574
        tmp = get_address(s, 0, b2, d2); /* shift */
4575
        tmp2 = tcg_temp_new_i64();
4576
        tmp32_1 = load_reg32(r1);
4577
        tmp32_2 = load_reg32(r1 + 1);
4578
        tcg_gen_concat_i32_i64(tmp2, tmp32_2, tmp32_1); /* operand */
4579
        switch (opc) {
4580
        case 0x8c:
4581
            tcg_gen_shr_i64(tmp2, tmp2, tmp);
4582
            break;
4583
        case 0x8d:
4584
            tcg_gen_shl_i64(tmp2, tmp2, tmp);
4585
            break;
4586
        case 0x8e:
4587
            tcg_gen_sar_i64(tmp2, tmp2, tmp);
4588
            set_cc_s64(s, tmp2);
4589
            break;
4590
        }
4591
        tcg_gen_shri_i64(tmp, tmp2, 32);
4592
        tcg_gen_trunc_i64_i32(tmp32_1, tmp);
4593
        store_reg32(r1, tmp32_1);
4594
        tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
4595
        store_reg32(r1 + 1, tmp32_2);
4596
        break;
4597
    case 0x98: /* LM     R1,R3,D2(B2)     [RS] */
4598
    case 0x90: /* STM    R1,R3,D2(B2)     [RS] */
4599
        insn = ld_code4(s->pc);
4600
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
4601

    
4602
        tmp = get_address(s, 0, b2, d2);
4603
        tmp2 = tcg_temp_new_i64();
4604
        tmp3 = tcg_const_i64(4);
4605
        tmp4 = tcg_const_i64(0xffffffff00000000ULL);
4606
        for (i = r1;; i = (i + 1) % 16) {
4607
            if (opc == 0x98) {
4608
                tcg_gen_qemu_ld32u(tmp2, tmp, get_mem_index(s));
4609
                tcg_gen_and_i64(regs[i], regs[i], tmp4);
4610
                tcg_gen_or_i64(regs[i], regs[i], tmp2);
4611
            } else {
4612
                tcg_gen_qemu_st32(regs[i], tmp, get_mem_index(s));
4613
            }
4614
            if (i == r3) {
4615
                break;
4616
            }
4617
            tcg_gen_add_i64(tmp, tmp, tmp3);
4618
        }
4619
        tcg_temp_free_i64(tmp2);
4620
        tcg_temp_free_i64(tmp3);
4621
        tcg_temp_free_i64(tmp4);
4622
        break;
4623
    case 0x91: /* TM     D1(B1),I2        [SI] */
4624
        insn = ld_code4(s->pc);
4625
        tmp = decode_si(s, insn, &i2, &b1, &d1);
4626
        tmp2 = tcg_const_i64(i2);
4627
        tcg_gen_qemu_ld8u(tmp, tmp, get_mem_index(s));
4628
        cmp_64(s, tmp, tmp2, CC_OP_TM_32);
4629
        tcg_temp_free_i64(tmp);
4630
        tcg_temp_free_i64(tmp2);
4631
        break;
4632
    case 0x92: /* MVI    D1(B1),I2        [SI] */
4633
        insn = ld_code4(s->pc);
4634
        tmp = decode_si(s, insn, &i2, &b1, &d1);
4635
        tmp2 = tcg_const_i64(i2);
4636
        tcg_gen_qemu_st8(tmp2, tmp, get_mem_index(s));
4637
        tcg_temp_free_i64(tmp);
4638
        tcg_temp_free_i64(tmp2);
4639
        break;
4640
    case 0x94: /* NI     D1(B1),I2        [SI] */
4641
    case 0x96: /* OI     D1(B1),I2        [SI] */
4642
    case 0x97: /* XI     D1(B1),I2        [SI] */
4643
        insn = ld_code4(s->pc);
4644
        tmp = decode_si(s, insn, &i2, &b1, &d1);
4645
        tmp2 = tcg_temp_new_i64();
4646
        tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s));
4647
        switch (opc) {
4648
        case 0x94:
4649
            tcg_gen_andi_i64(tmp2, tmp2, i2);
4650
            break;
4651
        case 0x96:
4652
            tcg_gen_ori_i64(tmp2, tmp2, i2);
4653
            break;
4654
        case 0x97:
4655
            tcg_gen_xori_i64(tmp2, tmp2, i2);
4656
            break;
4657
        default:
4658
            tcg_abort();
4659
        }
4660
        tcg_gen_qemu_st8(tmp2, tmp, get_mem_index(s));
4661
        set_cc_nz_u64(s, tmp2);
4662
        tcg_temp_free_i64(tmp);
4663
        tcg_temp_free_i64(tmp2);
4664
        break;
4665
    case 0x95: /* CLI    D1(B1),I2        [SI] */
4666
        insn = ld_code4(s->pc);
4667
        tmp = decode_si(s, insn, &i2, &b1, &d1);
4668
        tmp2 = tcg_temp_new_i64();
4669
        tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s));
4670
        cmp_u64c(s, tmp2, i2);
4671
        tcg_temp_free_i64(tmp);
4672
        tcg_temp_free_i64(tmp2);
4673
        break;
4674
    case 0x9a: /* LAM      R1,R3,D2(B2)     [RS] */
4675
        insn = ld_code4(s->pc);
4676
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
4677
        tmp = get_address(s, 0, b2, d2);
4678
        tmp32_1 = tcg_const_i32(r1);
4679
        tmp32_2 = tcg_const_i32(r3);
4680
        potential_page_fault(s);
4681
        gen_helper_lam(tmp32_1, tmp, tmp32_2);
4682
        tcg_temp_free_i64(tmp);
4683
        tcg_temp_free_i32(tmp32_1);
4684
        tcg_temp_free_i32(tmp32_2);
4685
        break;
4686
    case 0x9b: /* STAM     R1,R3,D2(B2)     [RS] */
4687
        insn = ld_code4(s->pc);
4688
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
4689
        tmp = get_address(s, 0, b2, d2);
4690
        tmp32_1 = tcg_const_i32(r1);
4691
        tmp32_2 = tcg_const_i32(r3);
4692
        potential_page_fault(s);
4693
        gen_helper_stam(tmp32_1, tmp, tmp32_2);
4694
        tcg_temp_free_i64(tmp);
4695
        tcg_temp_free_i32(tmp32_1);
4696
        tcg_temp_free_i32(tmp32_2);
4697
        break;
4698
    case 0xa5:
4699
        insn = ld_code4(s->pc);
4700
        r1 = (insn >> 20) & 0xf;
4701
        op = (insn >> 16) & 0xf;
4702
        i2 = insn & 0xffff;
4703
        disas_a5(s, op, r1, i2);
4704
        break;
4705
    case 0xa7:
4706
        insn = ld_code4(s->pc);
4707
        r1 = (insn >> 20) & 0xf;
4708
        op = (insn >> 16) & 0xf;
4709
        i2 = (short)insn;
4710
        disas_a7(s, op, r1, i2);
4711
        break;
4712
    case 0xa8: /* MVCLE   R1,R3,D2(B2)     [RS] */
4713
        insn = ld_code4(s->pc);
4714
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
4715
        tmp = get_address(s, 0, b2, d2);
4716
        tmp32_1 = tcg_const_i32(r1);
4717
        tmp32_2 = tcg_const_i32(r3);
4718
        potential_page_fault(s);
4719
        gen_helper_mvcle(cc_op, tmp32_1, tmp, tmp32_2);
4720
        set_cc_static(s);
4721
        tcg_temp_free_i64(tmp);
4722
        tcg_temp_free_i32(tmp32_1);
4723
        tcg_temp_free_i32(tmp32_2);
4724
        break;
4725
    case 0xa9: /* CLCLE   R1,R3,D2(B2)     [RS] */
4726
        insn = ld_code4(s->pc);
4727
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
4728
        tmp = get_address(s, 0, b2, d2);
4729
        tmp32_1 = tcg_const_i32(r1);
4730
        tmp32_2 = tcg_const_i32(r3);
4731
        potential_page_fault(s);
4732
        gen_helper_clcle(cc_op, tmp32_1, tmp, tmp32_2);
4733
        set_cc_static(s);
4734
        tcg_temp_free_i64(tmp);
4735
        tcg_temp_free_i32(tmp32_1);
4736
        tcg_temp_free_i32(tmp32_2);
4737
        break;
4738
#ifndef CONFIG_USER_ONLY
4739
    case 0xac: /* STNSM   D1(B1),I2     [SI] */
4740
    case 0xad: /* STOSM   D1(B1),I2     [SI] */
4741
        check_privileged(s, ilc);
4742
        insn = ld_code4(s->pc);
4743
        tmp = decode_si(s, insn, &i2, &b1, &d1);
4744
        tmp2 = tcg_temp_new_i64();
4745
        tcg_gen_shri_i64(tmp2, psw_mask, 56);
4746
        tcg_gen_qemu_st8(tmp2, tmp, get_mem_index(s));
4747
        if (opc == 0xac) {
4748
            tcg_gen_andi_i64(psw_mask, psw_mask,
4749
                    ((uint64_t)i2 << 56) | 0x00ffffffffffffffULL);
4750
        } else {
4751
            tcg_gen_ori_i64(psw_mask, psw_mask, (uint64_t)i2 << 56);
4752
        }
4753
        tcg_temp_free_i64(tmp);
4754
        tcg_temp_free_i64(tmp2);
4755
        break;
4756
    case 0xae: /* SIGP   R1,R3,D2(B2)     [RS] */
4757
        check_privileged(s, ilc);
4758
        insn = ld_code4(s->pc);
4759
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
4760
        tmp = get_address(s, 0, b2, d2);
4761
        tmp2 = load_reg(r3);
4762
        tmp32_1 = tcg_const_i32(r1);
4763
        potential_page_fault(s);
4764
        gen_helper_sigp(cc_op, tmp, tmp32_1, tmp2);
4765
        set_cc_static(s);
4766
        tcg_temp_free_i64(tmp);
4767
        tcg_temp_free_i64(tmp2);
4768
        tcg_temp_free_i32(tmp32_1);
4769
        break;
4770
    case 0xb1: /* LRA    R1,D2(X2, B2)     [RX] */
4771
        check_privileged(s, ilc);
4772
        insn = ld_code4(s->pc);
4773
        tmp = decode_rx(s, insn, &r1, &x2, &b2, &d2);
4774
        tmp32_1 = tcg_const_i32(r1);
4775
        potential_page_fault(s);
4776
        gen_helper_lra(cc_op, tmp, tmp32_1);
4777
        set_cc_static(s);
4778
        tcg_temp_free_i64(tmp);
4779
        tcg_temp_free_i32(tmp32_1);
4780
        break;
4781
#endif
4782
    case 0xb2:
4783
        insn = ld_code4(s->pc);
4784
        op = (insn >> 16) & 0xff;
4785
        switch (op) {
4786
        case 0x9c: /* STFPC    D2(B2) [S] */
4787
            d2 = insn & 0xfff;
4788
            b2 = (insn >> 12) & 0xf;
4789
            tmp32_1 = tcg_temp_new_i32();
4790
            tmp = tcg_temp_new_i64();
4791
            tmp2 = get_address(s, 0, b2, d2);
4792
            tcg_gen_ld_i32(tmp32_1, cpu_env, offsetof(CPUState, fpc));
4793
            tcg_gen_extu_i32_i64(tmp, tmp32_1);
4794
            tcg_gen_qemu_st32(tmp, tmp2, get_mem_index(s));
4795
            tcg_temp_free_i32(tmp32_1);
4796
            tcg_temp_free_i64(tmp);
4797
            tcg_temp_free_i64(tmp2);
4798
            break;
4799
        default:
4800
            disas_b2(s, op, insn);
4801
            break;
4802
        }
4803
        break;
4804
    case 0xb3:
4805
        insn = ld_code4(s->pc);
4806
        op = (insn >> 16) & 0xff;
4807
        r3 = (insn >> 12) & 0xf; /* aka m3 */
4808
        r1 = (insn >> 4) & 0xf;
4809
        r2 = insn & 0xf;
4810
        disas_b3(s, op, r3, r1, r2);
4811
        break;
4812
#ifndef CONFIG_USER_ONLY
4813
    case 0xb6: /* STCTL     R1,R3,D2(B2)     [RS] */
4814
        /* Store Control */
4815
        check_privileged(s, ilc);
4816
        insn = ld_code4(s->pc);
4817
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
4818
        tmp = get_address(s, 0, b2, d2);
4819
        tmp32_1 = tcg_const_i32(r1);
4820
        tmp32_2 = tcg_const_i32(r3);
4821
        potential_page_fault(s);
4822
        gen_helper_stctl(tmp32_1, tmp, tmp32_2);
4823
        tcg_temp_free_i64(tmp);
4824
        tcg_temp_free_i32(tmp32_1);
4825
        tcg_temp_free_i32(tmp32_2);
4826
        break;
4827
    case 0xb7: /* LCTL      R1,R3,D2(B2)     [RS] */
4828
        /* Load Control */
4829
        check_privileged(s, ilc);
4830
        insn = ld_code4(s->pc);
4831
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
4832
        tmp = get_address(s, 0, b2, d2);
4833
        tmp32_1 = tcg_const_i32(r1);
4834
        tmp32_2 = tcg_const_i32(r3);
4835
        potential_page_fault(s);
4836
        gen_helper_lctl(tmp32_1, tmp, tmp32_2);
4837
        tcg_temp_free_i64(tmp);
4838
        tcg_temp_free_i32(tmp32_1);
4839
        tcg_temp_free_i32(tmp32_2);
4840
        break;
4841
#endif
4842
    case 0xb9:
4843
        insn = ld_code4(s->pc);
4844
        r1 = (insn >> 4) & 0xf;
4845
        r2 = insn & 0xf;
4846
        op = (insn >> 16) & 0xff;
4847
        disas_b9(s, op, r1, r2);
4848
        break;
4849
    case 0xba: /* CS     R1,R3,D2(B2)     [RS] */
4850
        insn = ld_code4(s->pc);
4851
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
4852
        tmp = get_address(s, 0, b2, d2);
4853
        tmp32_1 = tcg_const_i32(r1);
4854
        tmp32_2 = tcg_const_i32(r3);
4855
        potential_page_fault(s);
4856
        gen_helper_cs(cc_op, tmp32_1, tmp, tmp32_2);
4857
        set_cc_static(s);
4858
        tcg_temp_free_i64(tmp);
4859
        tcg_temp_free_i32(tmp32_1);
4860
        tcg_temp_free_i32(tmp32_2);
4861
        break;
4862
    case 0xbd: /* CLM    R1,M3,D2(B2)     [RS] */
4863
        insn = ld_code4(s->pc);
4864
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
4865
        tmp = get_address(s, 0, b2, d2);
4866
        tmp32_1 = load_reg32(r1);
4867
        tmp32_2 = tcg_const_i32(r3);
4868
        potential_page_fault(s);
4869
        gen_helper_clm(cc_op, tmp32_1, tmp32_2, tmp);
4870
        set_cc_static(s);
4871
        tcg_temp_free_i64(tmp);
4872
        tcg_temp_free_i32(tmp32_1);
4873
        tcg_temp_free_i32(tmp32_2);
4874
        break;
4875
    case 0xbe: /* STCM R1,M3,D2(B2) [RS] */
4876
        insn = ld_code4(s->pc);
4877
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
4878
        tmp = get_address(s, 0, b2, d2);
4879
        tmp32_1 = load_reg32(r1);
4880
        tmp32_2 = tcg_const_i32(r3);
4881
        potential_page_fault(s);
4882
        gen_helper_stcm(tmp32_1, tmp32_2, tmp);
4883
        tcg_temp_free_i64(tmp);
4884
        tcg_temp_free_i32(tmp32_1);
4885
        tcg_temp_free_i32(tmp32_2);
4886
        break;
4887
    case 0xbf: /* ICM    R1,M3,D2(B2)     [RS] */
4888
        insn = ld_code4(s->pc);
4889
        decode_rs(s, insn, &r1, &r3, &b2, &d2);
4890
        if (r3 == 15) {
4891
            /* effectively a 32-bit load */
4892
            tmp = get_address(s, 0, b2, d2);
4893
            tmp32_1 = tcg_temp_new_i32();
4894
            tmp32_2 = tcg_const_i32(r3);
4895
            tcg_gen_qemu_ld32u(tmp, tmp, get_mem_index(s));
4896
            store_reg32_i64(r1, tmp);
4897
            tcg_gen_trunc_i64_i32(tmp32_1, tmp);
4898
            set_cc_icm(s, tmp32_2, tmp32_1);
4899
            tcg_temp_free_i64(tmp);
4900
            tcg_temp_free_i32(tmp32_1);
4901
            tcg_temp_free_i32(tmp32_2);
4902
        } else if (r3) {
4903
            uint32_t mask = 0x00ffffffUL;
4904
            uint32_t shift = 24;
4905
            int m3 = r3;
4906
            tmp = get_address(s, 0, b2, d2);
4907
            tmp2 = tcg_temp_new_i64();
4908
            tmp32_1 = load_reg32(r1);
4909
            tmp32_2 = tcg_temp_new_i32();
4910
            tmp32_3 = tcg_const_i32(r3);
4911
            tmp32_4 = tcg_const_i32(0);
4912
            while (m3) {
4913
                if (m3 & 8) {
4914
                    tcg_gen_qemu_ld8u(tmp2, tmp, get_mem_index(s));
4915
                    tcg_gen_trunc_i64_i32(tmp32_2, tmp2);
4916
                    if (shift) {
4917
                        tcg_gen_shli_i32(tmp32_2, tmp32_2, shift);
4918
                    }
4919
                    tcg_gen_andi_i32(tmp32_1, tmp32_1, mask);
4920
                    tcg_gen_or_i32(tmp32_1, tmp32_1, tmp32_2);
4921
                    tcg_gen_or_i32(tmp32_4, tmp32_4, tmp32_2);
4922
                    tcg_gen_addi_i64(tmp, tmp, 1);
4923
                }
4924
                m3 = (m3 << 1) & 0xf;
4925
                mask = (mask >> 8) | 0xff000000UL;
4926
                shift -= 8;
4927
            }
4928
            store_reg32(r1, tmp32_1);
4929
            set_cc_icm(s, tmp32_3, tmp32_4);
4930
            tcg_temp_free_i64(tmp);
4931
            tcg_temp_free_i64(tmp2);
4932
            tcg_temp_free_i32(tmp32_1);
4933
            tcg_temp_free_i32(tmp32_2);
4934
            tcg_temp_free_i32(tmp32_3);
4935
            tcg_temp_free_i32(tmp32_4);
4936
        } else {
4937
            /* i.e. env->cc = 0 */
4938
            gen_op_movi_cc(s, 0);
4939
        }
4940
        break;
4941
    case 0xc0:
4942
    case 0xc2:
4943
        insn = ld_code6(s->pc);
4944
        r1 = (insn >> 36) & 0xf;
4945
        op = (insn >> 32) & 0xf;
4946
        i2 = (int)insn;
4947
        switch (opc) {
4948
        case 0xc0:
4949
            disas_c0(s, op, r1, i2);
4950
            break;
4951
        case 0xc2:
4952
            disas_c2(s, op, r1, i2);
4953
            break;
4954
        default:
4955
            tcg_abort();
4956
        }
4957
        break;
4958
    case 0xd2: /* MVC    D1(L,B1),D2(B2)         [SS] */
4959
    case 0xd4: /* NC     D1(L,B1),D2(B2)         [SS] */
4960
    case 0xd5: /* CLC    D1(L,B1),D2(B2)         [SS] */
4961
    case 0xd6: /* OC     D1(L,B1),D2(B2)         [SS] */
4962
    case 0xd7: /* XC     D1(L,B1),D2(B2)         [SS] */
4963
    case 0xdc: /* TR     D1(L,B1),D2(B2)         [SS] */
4964
    case 0xf3: /* UNPK   D1(L1,B1),D2(L2,B2)     [SS] */
4965
        insn = ld_code6(s->pc);
4966
        vl = tcg_const_i32((insn >> 32) & 0xff);
4967
        b1 = (insn >> 28) & 0xf;
4968
        b2 = (insn >> 12) & 0xf;
4969
        d1 = (insn >> 16) & 0xfff;
4970
        d2 = insn & 0xfff;
4971
        tmp = get_address(s, 0, b1, d1);
4972
        tmp2 = get_address(s, 0, b2, d2);
4973
        switch (opc) {
4974
        case 0xd2:
4975
            gen_op_mvc(s, (insn >> 32) & 0xff, tmp, tmp2);
4976
            break;
4977
        case 0xd4:
4978
            potential_page_fault(s);
4979
            gen_helper_nc(cc_op, vl, tmp, tmp2);
4980
            set_cc_static(s);
4981
            break;
4982
        case 0xd5:
4983
            gen_op_clc(s, (insn >> 32) & 0xff, tmp, tmp2);
4984
            break;
4985
        case 0xd6:
4986
            potential_page_fault(s);
4987
            gen_helper_oc(cc_op, vl, tmp, tmp2);
4988
            set_cc_static(s);
4989
            break;
4990
        case 0xd7:
4991
            potential_page_fault(s);
4992
            gen_helper_xc(cc_op, vl, tmp, tmp2);
4993
            set_cc_static(s);
4994
            break;
4995
        case 0xdc:
4996
            potential_page_fault(s);
4997
            gen_helper_tr(vl, tmp, tmp2);
4998
            set_cc_static(s);
4999
            break;
5000
        case 0xf3:
5001
            potential_page_fault(s);
5002
            gen_helper_unpk(vl, tmp, tmp2);
5003
            break;
5004
        default:
5005
            tcg_abort();
5006
        }
5007
        tcg_temp_free_i64(tmp);
5008
        tcg_temp_free_i64(tmp2);
5009
        break;
5010
#ifndef CONFIG_USER_ONLY
5011
    case 0xda: /* MVCP     D1(R1,B1),D2(B2),R3   [SS] */
5012
    case 0xdb: /* MVCS     D1(R1,B1),D2(B2),R3   [SS] */
5013
        check_privileged(s, ilc);
5014
        potential_page_fault(s);
5015
        insn = ld_code6(s->pc);
5016
        r1 = (insn >> 36) & 0xf;
5017
        r3 = (insn >> 32) & 0xf;
5018
        b1 = (insn >> 28) & 0xf;
5019
        d1 = (insn >> 16) & 0xfff;
5020
        b2 = (insn >> 12) & 0xf;
5021
        d2 = insn & 0xfff;
5022
        tmp = load_reg(r1);
5023
        /* XXX key in r3 */
5024
        tmp2 = get_address(s, 0, b1, d1);
5025
        tmp3 = get_address(s, 0, b2, d2);
5026
        if (opc == 0xda) {
5027
            gen_helper_mvcp(cc_op, tmp, tmp2, tmp3);
5028
        } else {
5029
            gen_helper_mvcs(cc_op, tmp, tmp2, tmp3);
5030
        }
5031
        set_cc_static(s);
5032
        tcg_temp_free_i64(tmp);
5033
        tcg_temp_free_i64(tmp2);
5034
        tcg_temp_free_i64(tmp3);
5035
        break;
5036
#endif
5037
    case 0xe3:
5038
        insn = ld_code6(s->pc);
5039
        debug_insn(insn);
5040
        op = insn & 0xff;
5041
        r1 = (insn >> 36) & 0xf;
5042
        x2 = (insn >> 32) & 0xf;
5043
        b2 = (insn >> 28) & 0xf;
5044
        d2 = ((